Multi-row pattern pin result matching method and chip testing machine

Abstract

The invention relates to a pin result matching method of a multi-line pattern and a chip testing machine, a testing unit extracts a matching microinstruction and an expected pattern in a pattern file, circularly multiplexes the multi-line expected pattern according to the matching microinstruction, obtains a pin matching result obtained by matching an output signal of a to-be-tested device, and sends the pin matching result to the chip testing machine; and the test unit sends a pin matching result to the communication board card when determining that the mode is the synchronous mode based on the mode setting parameter. The communication board card receives a pin matching result sent by each test unit in the test board card, converts the pin matching result according to the mapping parameters of the test units to obtain a site matching result of a corresponding site, judges that the pin matching result of the corresponding site is received according to a site identifier carried in the mapping parameters of the test units and the site matching result meets a matching completion condition, and if the matching completion condition is met, the communication board card receives the pin matching result of the corresponding site. Therefore, the test efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a pin result matching method for multi-row patterns and a chip testing machine. Background Technology

[0002] During the testing of the Device Under Test (DUT), the tester needs to match the sequence information output by the DUT and process whether the matching sequence is successful within a specified time. The operation ends upon success or timeout. This process constitutes one MatchLoop operation, and multiple MatchLoop operations can be supported within a single test item. Traditional tester matching methods rely on the test board to retrieve the corresponding target test vector (pattern) line by line from memory according to microinstructions. Furthermore, the number of DUTs that can be matched simultaneously within a single test item is limited by the number of channels on the test board, resulting in a limited number of DUTs that can be tested in parallel and low testing efficiency. Summary of the Invention

[0003] Therefore, it is necessary to provide a method for matching pin results of multi-line patterns and a chip testing machine that can improve testing efficiency in response to the above problems.

[0004] The first aspect of this application provides a method for matching pin results of multi-line patterns, including:

[0005] The host computer sends the pattern file and mode setting parameters to the test units in the test board, and sends the test unit mapping parameters to the communication board; wherein, the test unit mapping parameters represent the correspondence between the site associated with the test unit and the test unit channel in different test boards;

[0006] The test unit extracts the matching micro-instructions and expected pattern from the pattern file, and repeatedly reuses multiple lines of the expected pattern according to the matching micro-instructions to obtain the pin matching result obtained by matching the output signal of the device under test.

[0007] When the test unit determines that it is in synchronous mode based on the mode setting parameters, it sends the pin matching result to the communication board. In synchronous mode, the channel of the same test unit is connected to the pins of the device under test (DUT) of the same or different sites, and the pins of the DUT of the same site are connected to the channels of the same or different test units.

[0008] The communication board receives the pin matching results sent by each test unit in the test board, converts the pin matching results according to the test unit mapping parameters to obtain the site matching results of the corresponding site, and determines that the pin matching results of the corresponding site have been received according to the site identifier carried in the test unit mapping parameters. If the site matching results meet the matching completion conditions, the pin matching is completed.

[0009] The second aspect of this application provides a method for matching pin results of multi-line patterns, implemented based on a communication board, including:

[0010] Receive test unit mapping parameters sent by the host computer;

[0011] The test board receives pin matching results from each test unit. These results are obtained by extracting matching micro-instructions and a desired pattern from a pattern file, repeatedly using multiple lines of the desired pattern based on the matching micro-instructions, matching the output signal of the device under test (DUT), and sending it to the communication board in synchronous mode. In synchronous mode, channels of the same test unit connect to pins of DUTs at the same or different sites, and pins of DUTs at the same site connect to channels of the same or different test units. The test unit mapping parameters characterize the correspondence between sites associated with test units and test unit channels in different test boards.

[0012] The pin matching result is converted according to the test unit mapping parameters to obtain the site matching result of the corresponding site;

[0013] If the pin matching result of the corresponding site is received after determining the site identifier carried in the test unit mapping parameters, and the site matching result meets the matching completion condition, then the pin result matching is complete.

[0014] A third aspect of this application provides a chip testing machine, including a host computer, a test board, and a communication board. The test board includes multiple test units, each test unit is connected to the host computer through the communication board, and the channel of each test unit is connected to the pin of the device under test of the corresponding site. The chip testing machine performs pin result matching of multiple patterns according to the above method.

[0015] The above-described multi-line pattern pin result matching method and chip tester involve the host computer sending the pattern file and mode setting parameters to the test units on the test board, and sending the test unit mapping parameters to the communication board. The test units extract the matching micro-instructions and expected patterns from the pattern file, and repeatedly use multiple lines of the expected patterns according to the matching micro-instructions to obtain the pin matching results obtained by matching the output signals of the device under test. When the test unit determines that it is in synchronous mode based on the mode setting parameters, it sends the pin matching results to the communication board. The communication board receives the pin matching results sent by each test unit on the test board, converts the pin matching results according to the test unit mapping parameters to obtain the site matching results for the corresponding site, and determines whether the pin matching results for the corresponding site have been received based on the site identifier carried in the test unit mapping parameters. If the site matching results meet the matching completion conditions, the pin result matching is considered complete. The test unit uses matching micro-instructions to repeatedly reuse multiple lines of the expected pattern to obtain the pin matching result obtained by matching the output signal of the device under test. Compared with reading the expected pattern for matching every time during the matching process, the latency is effectively reduced. The communication board receives the pin matching results sent by each test unit, converts them into site matching results, and detects whether the pin matching is complete. It can support different test boards to match the device under test under one test item, expand the number of devices under test that can be tested in parallel, and improve test efficiency. Attached Figure Description

[0016] Figure 1 This is a flowchart of a method for matching pin results of multiple patterns in one embodiment;

[0017] Figure 2 This is a schematic diagram of the structure of the host computer, communication board, and test unit in one embodiment;

[0018] Figure 3 This is a schematic diagram illustrating the correspondence between the site associated with the test unit and the test unit channel in synchronous mode in one embodiment.

[0019] Figure 4 This is a schematic diagram illustrating the correspondence between the site associated with the test unit and the test unit channel in asynchronous mode in one embodiment.

[0020] Figure 5 This is a schematic diagram illustrating the matching of microinstructions in one embodiment;

[0021] Figure 6 This is a schematic diagram showing the correspondence between the communication board and each test board in one embodiment;

[0022] Figure 7 A flowchart of a method for matching pin results of multiple patterns in another embodiment;

[0023] Figure 8 This is a flowchart of a method for matching pin results of multiple patterns in another embodiment;

[0024] Figure 9 This is a flowchart of a method for matching pin results of multiple patterns in another embodiment. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application.

[0026] It is understood that the term "connection" in the following embodiments should be interpreted as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., transmit electrical signals or data to each other. It should also be understood that the terms "comprising / including" or "having," etc., specify the presence of the stated features, integrals, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integrals, steps, operations, components, parts, or combinations thereof.

[0027] In one embodiment, such as Figure 1 As shown, a method for matching pin results of multi-line patterns is provided, including:

[0028] Step S110: The host computer sends the pattern file and mode setting parameters to the test unit in the test board, and sends the test unit mapping parameters to the communication board.

[0029] The test unit mapping parameters represent the correspondence between the sites (stations) associated with test units on different test boards and the test unit channels. One site (station) corresponds to one device under test (DUT). The content of the pattern (vector) file will differ for different test items. The pattern file specifically includes row vectors, matching micro-instructions, and the desired pattern. It may also include the timing parameters corresponding to the matching micro-instructions (i.e., the timing information of the excitation pattern / desired pattern in the waveform output to the DUT). In addition, the pattern file may also include other types of micro-instructions (such as normal micro-instructions) as well as the corresponding desired pattern and the corresponding timing parameters. Matching micro-instructions and other types of micro-instructions can be in one or more groups to achieve one or more match operations or other corresponding operations.

[0030] The matching microinstructions can specifically include the MatchStart, MatchLoop, and EndMatch microinstructions. The operand of the MatchStart microinstruction (set from 1 to 16383, e.g., 8000) serves as the first-level loop count, and the operand of the MatchLoop microinstruction (set from 1 to 65535, e.g., 8) serves as the inner second-level loop count. One execution from MatchStart to MatchLoop, and the second-level loop from MatchLoop to EndMatch, constitutes one complete matching loop (MatchStart loop). The site identifier is the unique identifier for each site; each site corresponds to a Device Under Test (DUT), which can be a chip or other electronic device to be tested. For example... Figure 2 As shown, the test board 300 can specifically be a digital board, containing one or more test units 310. The test unit 310 can be a functional module built based on programmable logic chips such as FPGAs to perform multi-line pattern matching operations. The test board 300 may also include a PE (Pin Electronics) chip 400. Each channel of the test unit 310 is connected to a pin (pin or terminal) of the corresponding device under test (DUT) on the site via the corresponding PE chip 400. Each channel of the test unit 310 corresponds to a pin of the DUT. In this application, the pin matching result can also be understood as the channel matching result of the test unit. The mode setting parameters are used to indicate the operating mode of the test unit 310. The operating mode will vary depending on the connection relationship between the test unit 310 and the site. The pins that the test unit matches on the site for the DUT can be understood as matching terminals or matching pins.

[0031] Specifically, the operating modes include synchronous mode and asynchronous mode. In synchronous mode, channels of the same test unit 310 are connected to pins of the device under test (DUT) at the same or different sites, and pins of the DUT at the same site are connected to channels of the same or different test units. For example... Figure 3 The diagram illustrates two scenarios in synchronous mode. First, taking test unit 310, which includes units FE0 and FE1, as an example, unit FE0 can connect to pins 01 to 03 of the device under test (DUT0) on site 0, and pins 01 to 03 of the device under test (DUT1) on site 1. Unit FE1 can connect to pins 01 to 03 of the device under test (DUT2) on site 2, and pins 01 to 03 of the device under test (DUT3) on site 3. Second, pin 01 of the device under test (DUT0) on site 0 can be connected to unit FE0, and pin 02 of the device under test (DUT0) on site 0 can be connected to unit FE1. In asynchronous mode, test unit 310 and sites are in a one-to-one correspondence; pins of the devices under test (DUTs) on the same site are connected to channels of the same test unit 310. For example... Figure 4 As shown, taking the test unit 310, which includes units FE0 to FE3, as an example, unit FE0 corresponds to pins pin01 to pin03 of the device under test (DUT0) on site 0, unit FE1 corresponds to pins pin01 to pin03 of the device under test (DUT1) on site 1, unit FE2 corresponds to pins pin01 to pin03 of the device under test (DUT2) on site 2, and unit FE3 corresponds to pins pin01 to pin03 of the device under test (DUT3) on site 3.

[0032] After connecting the Device Under Test (DUT) on each site to the test unit 310 according to actual testing needs, the tester imports the corresponding pattern file to the host computer 100. The test unit mapping parameters include the required test board slot number, test unit number, and the correspondence between the site and the test unit channel. Based on these parameters, the system analyzes whether all pins of the DUT on each site are connected to the same test unit 310, and whether each site is connected to a different test unit 310. If this condition is met, it is considered asynchronous mode; otherwise, it is considered synchronous mode, and the corresponding mode setting parameters are obtained. Specifically, if the host computer 100's test board driver determines that the test board meets this condition, it is considered asynchronous mode; otherwise, it is considered synchronous mode, thus determining the mode setting parameters. When running the pattern file for the corresponding test item, all test units 310 in the test board 300 can either be in synchronous mode or all in asynchronous mode. For example, when running the pattern file for the current test item, all test units 310 in the test board 300 can be in asynchronous mode. When running the pattern file for the next test item, all test units 310 in the test board 300 can switch to synchronous mode. The host computer 100 communicates with the communication board 200 to send the test unit mapping parameters to the communication board 200, and to send the pattern file and mode setting parameters to each test unit 310 in the test board 300 through the communication board 200.

[0033] It should be noted that all pins mentioned in this application refer to the pins / pins of the device under test (DUT) that need to be matched. The pins that need to be matched are determined by the expected pattern in the pattern file and the pin information corresponding to the expected pattern. The pin information refers to the pin number of the pin on the DUT.

[0034] It should be noted that the site identifier is used to enable the site that needs to be matched. The site identifier can be resolved by the test board slot number, test unit number, and the correspondence between the site and the test unit channel. The site identifier can also be set separately on the host computer.

[0035] Specifically, step S110 includes: the host computer sending the pattern file to the storage module of the test unit, and sending the mode setting parameters to the mode register in the test unit; wherein, the test unit is configured to: read the mode setting parameters in the mode register to determine the working mode.

[0036] Continue to refer to Figure 2 The host computer 100 sends the test unit mapping parameters to the communication board 200, so that the communication board 200 knows the mapping relationship between the site used for this matching and each channel of each test unit 310 on the corresponding test board 300, and can thus determine whether each site has been successfully matched. By configuring the test unit mapping parameters on the communication board 200, the communication board 200 receives the pin matching results sent by each test unit 310, converts them into site matching results, and detects whether the pin matching is complete. This supports the joint matching of different test boards 300 (e.g., 4 or 8 test boards 300) under one test item, expanding the number of DUTs that can be tested in parallel.

[0037] The host computer 100 also configures the mode register in the test unit 310 by sending mode setting parameters through the communication board 200, for example, 1 for asynchronous mode and 0 for synchronous mode. It should be noted that multiple test units 310 within a single test board 300 can be configured in parallel synchronously to ensure that each test unit is in the same working mode. The host computer 100 also sends a pattern file to the storage module 311 of the test unit 310 through the communication board 200. The test unit 310 obtains the working mode according to the mode setting parameters in the mode register and calls the pattern file in the storage module 311 for a match operation. The storage module 311 can be RAM or other types of memory. In other embodiments, the host computer 100 can also send the mode setting parameters to the test unit 310 transparently through the communication board 200, and the test unit 310 directly determines the working mode.

[0038] Furthermore, before step S110, the method may further include: when the host computer carries matching microinstructions in the pattern file, determining the corresponding mode setting parameters according to the test unit mapping parameters and the pattern file.

[0039] The pattern file can be written by testers or users. When the host computer 100 detects that the pattern file contains a matching microinstruction (only one of the MatchStart, MatchLoop, and EndMatch microinstructions needs to be detected, for example, if the MatchStart microinstruction is detected), it combines the test unit mapping parameters containing the required test board slot number, test unit number, and the correspondence between the site and the test unit channel, and the pin information in the pattern file to determine whether all pins of the device under test (DUT) on each site are connected to the same test unit 310, and whether the test units 310 connected to each site are different. If this condition is met, it is considered to be in asynchronous mode; otherwise, it is considered to be in synchronous mode. This allows the determination of the mode setting parameters.

[0040] For example, the expected pattern in the pattern file corresponds to the DUT pin information to determine the corresponding test unit channel. Then, based on the correspondence between the test unit channel and the site, the correspondence between each test unit and its associated site is determined, thereby determining the mode setting parameters.

[0041] Step S120: The test unit extracts the matching micro-instructions and expected pattern from the pattern file, and repeatedly reuses multiple lines of expected pattern according to the matching micro-instructions to obtain the pin matching result obtained by matching the output signal of the device under test.

[0042] Specifically, the device under test (DUT) can output a signal based on a desired pattern; in other embodiments, it can also output a signal after power-on. After receiving the pattern file and mode setting parameters, the test unit 310 can extract the matching micro-instructions and the desired pattern from the pattern file and perform a matching operation after receiving a matching start command from the host computer 100. Specifically, the test unit 310 can configure the PE chip 400 by cyclically multiplexing multiple lines of the desired pattern according to the matching micro-instructions, receive the response pattern returned by the PE chip 400 after matching the output signal of the DUT with the desired pattern, and analyze the result to obtain the pin matching result of the DUT. In other embodiments, the test unit 310 can also include the matching function of the PE chip 400. For example, the PE chip 400 simply transmits the output signal of the DUT to the test unit 310, and the test unit 310 matches the output signal of the DUT with multiple lines of the desired pattern to obtain the pin matching result of the DUT.

[0043] In one embodiment, it should be noted that both the expected pattern and the response pattern belong to the narrow sense of pattern, i.e., test vector. The expected pattern can be a sequence of HHLLH (H represents the expected input high level, L represents the expected input low level, and X represents that the input level is not important). The expected pattern can also include VOH, i.e., the expected high level output of the device under test (DUT), and VOL, i.e., the expected low level output of the DUT. The response pattern can be a sequence of 01010 (or the comparison result between the DUT output signal and the expected pattern). This is only an explanation of the pattern; the expected pattern and response pattern can be represented in other ways without limitation. Of course, if the test unit performs other non-matching operations, it sends an excitation pattern to the DUT, which can be a sequence of 01010.

[0044] Specifically, the PE chip compares the output signal of the device under test (DUT) with the expected level (VOH, the expected high level of the DUT output, and VOL, the expected low level of the DUT output; VOH and VOL remain constant within a test item) in the expected pattern to obtain the response pattern (comparison result). The test unit samples the response pattern according to the timing parameter, and then performs a matching operation between the response pattern of each row and the expected pattern of the corresponding row to obtain the matching result. Specifically, if the expected pattern of the same row is H and the response pattern is 1, the match is successful; if the expected pattern of the same row is L and the response pattern is 0, the match is successful; if the expected pattern of the same row is H and the response pattern is 0, the match fails; if the expected pattern of the same row is L and the response pattern is 1, the match fails; if the expected pattern of the same row is X and the response pattern is 1 or 0, the match is successful.

[0045] In another embodiment, the desired pattern and desired levels (VOH, VOL) ​​are configured separately in a pattern file. The test unit configures VOH and VOL to the PE chip. The PE chip receives VOH and VOL, and the CA comparator and CB comparator in the PE chip compare VOH and VOL with the actual output level of the device under test (DUT) to obtain the comparison results CA value and CB value. The test unit samples the CA value and CB value according to the timing parameter setting. If the actual output level is higher than VOH, the CA value is 1, otherwise it is 0. If the actual output level is higher than VOL, the CB value is 1, otherwise it is 0. The response pattern is a combination of CA value and CB value, which is represented by three combinations: 01, 00, and 11. There is no combination form of 10. Furthermore, the matching of expected and response patterns in the same row is as follows: If the expected pattern is H and the response pattern is 11, the match is successful; if the response pattern is 01 or 00, the match fails. If the expected pattern is L and the response pattern is 00, the match is successful; if the response pattern is 11 or 10, the match fails. If the expected pattern is M (expected output intermediate state) and the response pattern is 01, the match is successful; if the response pattern is 00 or 11, the match fails. If the expected pattern is X (regardless of input level), and the response pattern is 11, 00, or 01, all matches are successful.

[0046] Furthermore, it should be noted that both the expected pattern and the response pattern belong to the narrow sense of pattern, i.e., test vector. The expected pattern can be the sequence information of HHLLMX (H represents the expected input high level, L represents the expected input low level, M represents the expected output intermediate state or expected output intermediate level, and X represents that the input level is not important). The expected pattern can also include VOH, i.e. the expected high level output of the device under test, and VOL, i.e. the expected low level output of the device under test. The response pattern can be the sequence information of 01010 (or the comparison result of the output signal of the device under test and the expected pattern, represented by 2 bits).

[0047] Taking the MatchStart, MatchLoop, and EndMatch micro-instructions as an example, the test unit 310 uses a two-level nested approach to cyclically call multiple lines of expected patterns to obtain the response patterns after matching with the output signals of the device under test (DUT). The response pattern represents the original comparison result of each pin. Based on the response pattern, the test unit 310 can determine which pins of the DUT matched successfully and which failed, thus converting this into the pin matching results of the DUT. Specifically, in the multiple lines from the MatchStart to the EndMatch micro-instructions, the expected pattern and the dummy can share a timing parameter. The test unit continuously samples multiple lines of response patterns based on the same timing parameter.

[0048] By using matching microinstructions to repeatedly reuse multiple rows of desired patterns, the latency is effectively reduced compared to reading the desired pattern for matching each time during the matching process. For ease of understanding, the following explanation will focus on the following scenario: the test unit 310 repeatedly reuses multiple rows of desired patterns according to the matching microinstructions to configure the PE chip 400, receives the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the desired pattern, and analyzes the pin matching results of the DUT for further explanation.

[0049] In one embodiment, the pattern file further includes row vectors and timing parameters corresponding to matching microinstructions, and step S120 includes steps 121 to 123.

[0050] Step 121: The test unit extracts the matching micro-instructions, row vectors, expected pattern and timing parameters from the pattern file in the storage module and sends them to the internal cache module for caching.

[0051] Specifically, such as Figure 2 As shown, the cache module 313 can be a FIFO (First In First Out) or other type of cache module. The microinstruction module 312 in the test unit 310 can extract the matching microinstruction, row vector, expected pattern and timing parameters corresponding to the matching microinstruction from the pattern file in the storage module 311, and send them to the cache module 313 for caching.

[0052] Step 122: The test unit reads the matching microinstruction, row vector, expected pattern and timing parameters from the cache module, and performs pattern configuration on the PE chip by cyclically reusing the expected pattern and timing parameters of multiple rows according to the order of the row vector and the matching microinstruction.

[0053] In this embodiment, the test unit 310 obtains the matching microinstructions, expected pattern, and timing parameters from the cache module 313 and caches them in the internal vector cache module 3141. The test unit 310 reads the matching microinstructions from the vector cache module 3141 in the order of row vectors and uses a two-level nested approach to cyclically call multiple rows of expected pattern and timing parameters in the vector cache module 3141. The test unit 310 configures the PE chip 400 according to the called multiple rows of expected pattern and timing parameters. Compared to the microinstruction module 312 issuing the expected pattern every time during the matching process, the latency is effectively reduced.

[0054] Specifically, the method of using a two-level nested loop to call the multi-line expected pattern and timing parameters in the vector cache module 3141 includes: using the operand of the MatchStart microinstruction as the first-level loop count and the operand of the MatchLoop microinstruction as the inner second-level loop count, and calling the multi-line expected pattern and corresponding timing parameters from the MatchStart microinstruction to the EndMatch microinstruction in the order of the row vector; the loop from the MatchStart microinstruction to the MatchLoop microinstruction is the first-level loop, and the loop from the MatchLoop microinstruction to the EndMatch microinstruction is the second-level loop.

[0055] like Figure 2 As shown, the test module 314 in the test unit 310 can read the matching microinstructions, row vectors, expected patterns and timing parameters from the cache module 313 and cache them in the internal vector cache module 3141. The multiple rows of expected patterns and timing parameters in the vector cache module 3141 are called in a two-level nested manner to configure the pattern of the PE chip 400.

[0056] Furthermore, in the test module 314, the vector cache module 3141 retrieves and caches the matching micro-instructions, expected patterns, and timing parameters from the cache module 313. By using the vector cache module 3141 to cache relevant data, data does not need to be repeatedly retrieved from the cache module 313 during the matching loop, thus avoiding impacting the matching loop efficiency. The vector read / write control module 3142 reads the matching micro-instructions from the vector cache module 3141 in the order of row vectors, and uses a two-level nested approach to cyclically call the multiple rows of expected patterns and timing parameters from the vector cache module 3141 and send them to the driver module 3143. The driver module 3143 performs pattern configuration on the PE chip 400 based on the received multiple rows of expected patterns and timing parameters. Alternatively, the vector read / write control module 3142 can cache the matching micro-instructions and expected patterns in internal RAM (the timing parameters do not change during the matching loop, so caching is not required), and use a two-level nested approach to cyclically call the multiple rows of expected patterns and timing parameters corresponding to the matching micro-instructions and send them to the driver module 3143.

[0057] The pattern file also contains pin information corresponding to the desired pattern. The pin information is stored from the storage module 311 into the cache module 313 along with the desired pattern, and then cached into the vector cache module 3141. The vector read / write control module 3142 sends multiple lines of desired pattern, pin information, and timing parameters to the driver module 3143. The driver module 3143 configures the PE chip 400 according to the pin information, so that the PE chip 400 compares the output signal of the corresponding pin with the desired pattern.

[0058] Step 123: The test unit receives the response pattern returned by the PE chip after comparing the output signal of the device under test with the expected pattern, and analyzes it to obtain the pin matching result of the device under test.

[0059] Specifically, refer to Figure 2 The pin matching result of the DUT can be obtained by receiving the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the expected pattern through the result statistics module 3144 in the test module 314, and analyzing it. For example, 0 and 1 can be used to represent the corresponding pin matching success and matching failure, respectively, and the pin matching result can be obtained by combining them.

[0060] Specifically, such as Figure 5As shown, the first column is a row vector, which can be understood as row numbers. The second column is a micro-instruction. Taking the matching of 5 pins of the device under test (DUT) as an example, the 5 columns on the right represent the expected pattern for pins 01, 02, 03, 04, and 05. Figure 5 It can be displayed on the host computer interface. The test module 314 configures the PE chip 400 according to the pattern of the row vector, repeatedly using the expected pattern and timing parameters of multiple rows according to the matching micro-instruction. It receives the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the expected pattern. If there is a pin matching failure, the matching loop continues, and the expected pattern of multiple rows is called again to configure the PE chip 400, until the matching loop reaches the first-level loop count (e.g., 8000 times). Figure 5 The expected pattern highlighted in red indicates that the corresponding pin failed to match after the matching loop reached the first-level loop count.

[0061] Understandably, please continue to refer to this. Figure 5 Taking pin03 as an example, the expected pattern of multiple rows is reused in a loop, specifically the expected pattern of multiple rows corresponding to rows 1216 to 1231, which are HLLHHHLM in sequence. From rows 1232 to 1236, five pins have no expected pattern configured, represented by a dummy. The purpose of executing the dummy in the second-level loop is to wait for the pin matching result of the previous first-level loop. It can be understood that in row 1237, the test unit 310 inputs an stimulus pattern of 1 to pin01 of the DUT.

[0062] When the test unit 310 is in asynchronous mode, after the test unit 310 executes a matching loop and obtains the pin matching result, if all pins are successfully matched, there is no need to continue the matching loop and the pin matching result can be determined; if there are pins that fail to match, the matching loop continues and the test unit 310 calls the expected pattern of multiple lines again to configure the pattern of the PE chip 400 until the matching loop reaches the first-level loop count, and the last obtained pin matching result is retained.

[0063] In one embodiment, after step S120, the method further includes: the test unit detects the last received response pattern when the first-level loop number is reached according to the matching micro-instruction, and stores the matching failure result data into the result storage device.

[0064] Specifically, such as Figure 2As shown, the result statistics module 3144 can send the matching failure result data and storage instruction to the matching failure cache module 317 based on the response pattern received when the matching micro-instruction detection reaches the first-level loop count. The matching failure result data includes the row vector of the matching failure, the matching pin information corresponding to the matching failure row vector, and the corresponding expected pattern and response pattern, where the matching pin information refers to the matching PIN number. The matching failure cache module 317 converts the matching failure result data according to the storage protocol according to the storage instruction and stores it into the result storage device 320.

[0065] The result statistics module 3144 receives the response pattern returned by the PE chip 400 and analyzes it to obtain the pin matching results. During this process, to filter invalid data during the matching loop, it also sends a storage instruction to the matching failure cache module 317. This instruction controls whether the matching failure cache module 317 performs a matching result storage operation on the result storage device 320, which can be DDR or other types of storage devices. For example, when the storage instruction is 1, the matching failure cache module 317 does not perform a storage operation; when the storage instruction is 0, the matching failure cache module 317 performs a storage operation. After receiving the pin matching results, when all pins are successfully matched, the result statistics module 3144 outputs a storage instruction of 0, controlling the matching failure cache module 317 to perform a successful matching result storage operation. Specifically, this can be done by setting the result storage device 320 to empty (or storing a successful matching flag) to indicate that all pins are successfully matched. When the matching loop reaches the first-level loop count, if there are still pins that have not been matched successfully, the result statistics module 3144 outputs a storage instruction of 0 and controls the matching failure cache module 317 to perform a matching failure result data storage. Specifically, it can store the matching failure vector row, as well as the corresponding expected pattern and response pattern, into the result storage device 320.

[0066] Step S130: When the test unit determines the mode to be synchronous based on the mode setting parameters, it sends the pin matching result to the communication board.

[0067] When the mode setting parameters determine that it is in synchronous mode, the test unit 310 sends the pin matching result to the communication board 200 after each matching loop. In this embodiment, as shown... Figure 2As shown, in synchronous mode, the result statistics module 3144 receives the matching micro-instructions and expected pattern sent by the vector read / write control module 3142, and receives the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the expected pattern. It analyzes and obtains the pin matching result of the DUT and sends it to the micro-instruction module 312. The micro-instruction module 312 sends the pin matching result obtained in each matching cycle to the communication board 200 through the uplink module 315. Specifically, when the matching cycle reaches the first-level cycle count, the micro-instruction module 312 also carries a "last" identifier in the uploaded pin matching result so that the communication board 200 can identify it as the last pin matching result after the first-level cycle count.

[0068] Step S140: The communication board receives the pin matching results sent by each test unit in the test board, converts the pin matching results according to the test unit mapping parameters to obtain the site matching results of the corresponding site, and determines that the pin matching results of the corresponding site have been received according to the site identifier carried in the test unit mapping parameters. If the site matching results meet the matching completion conditions, the pin matching is completed.

[0069] The matching completion condition is that each site successfully matches or the loop matching reaches the first-level loop count. For example... Figure 2 As shown, the communication board 200 can connect to various test units 310 in multiple test boards 300, and receive the pin matching results sent by each test unit 310. The communication board 200 converts the pin matching results based on the test unit mapping parameters to obtain the site matching results of the sites associated with each test unit 310. For example, by combining the test unit mapping parameters to analyze whether all pins of the corresponding site (i.e., the site associated with each test unit 310) are successfully matched, 1 indicates that all pins of the corresponding site are successfully matched (i.e., the site matching is successful), and 0 indicates that there are pin matching failures in the corresponding site (i.e., the site matching fails), thus obtaining the site matching results.

[0070] Based on the converted site matching results and the site identifiers carried in the test unit mapping parameters, the communication board 200 determines whether all site matching results corresponding to the site identifiers have been obtained after the first round of matching. It analyzes whether all sites corresponding to the site identifiers have successfully matched. If so, the pin matching is complete. If only some sites have successfully matched (all pins of the DUT on a site have successfully matched in the current matching cycle, then this site has successfully matched; if one pin fails, then this site has failed), the successfully matched site is recorded, and subsequent cycles will not check for successfully matched sites. If no site matching is successful in this cycle, the communication board 200 continues to wait for the next matching cycle (e.g., the second round, the third round, etc.) to report the pin matching results of the unsuccessful sites from the previous round and convert them into site matching results, until it receives the pin matching results carrying the last identifier reported by the test unit 310. After conversion by the communication board 200, these results become the final site matching results for the corresponding sites, and the pin matching is complete. Regardless of whether all sites ultimately match successfully, the matching operation based on the matching micro-instruction ends.

[0071] Furthermore, with Figure 3 For example, different test boards 300 have different slot numbers (e.g., 01 and 02 represent different slot numbers of different test boards 300). In one test board 300, FE0 is associated with pin01 of the device under test (DUT0) where site0 is located, and FE1 is associated with pin02 of the device under test (DUT0) where site0 is located. site0 is the site corresponding to the site identifier. The communication board 200 finally counts the matching results of site0, which includes the corresponding test board slot number, test unit number, and the matching results of pins 01 and 02 of DUT0. If both pins are successful, site0 is considered to be successfully matched. If both pins reach the first-level loop count together, it is considered to be a timeout and site0 is considered to be unsuccessful.

[0072] The communication board 200 may communicate with the corresponding test board 300 using one or more controllers. In one embodiment, such as... Figure 6As shown, the communication board 200 includes a first controller 210 and a second controller 220, which can be FPGAs or other types of controllers. The first controller 210 and the second controller 220 communicate with corresponding test boards 300. This can be achieved by dividing all test boards 300 into two equal parts, with the first controller 210 and the second controller 220 communicating with half of the test boards 300 respectively; or by dividing all test boards 300 into two parts of varying numbers as needed, with the first controller 210 and the second controller 220 communicating with a portion of the test boards 300 respectively.

[0073] After the first controller 210 and the second controller 220 detect that they have received all the pin matching results sent by all test units 310 in their respective test boards 300, and that the site matching results meet the matching completion conditions, based on the preset distribution map information, they send each other a matching result collection completion command. The distribution map information includes the test board slot number, the test unit number, and the correspondence between the test unit 310 and the site. This distribution map information can be pre-stored in the storage module of the communication board 200. Upon receiving the matching result collection completion command, the first controller 210 and the second controller 220 have completed the pin matching.

[0074] The host computer 100 sends test board driver to communication board 200 test unit mapping parameters, which include the test board slot number, test unit number, correspondence between test unit 310 and site, and correspondence between site and test unit channel. The test board slot number, test unit number, and correspondence between test unit 310 and site in the test unit mapping parameters are also used as distribution map information, which is used by the first controller 210 and the second controller 220 to determine whether the pin matching results sent by all test units 310 in the corresponding test board 300 have been received.

[0075] In one embodiment, such as Figure 7 As shown, after step S140, the method further includes steps S150 and S160.

[0076] Step S150: The communication board generates a verification command based on the converted pin matching result and sends it to the test unit.

[0077] Specifically, the converted pin matching result is obtained by converting the site matching result using the test unit mapping parameters. Alternatively, after the pin matching is completed, the first controller 210 and the second controller 220 may broadcast verification commands to the corresponding test board 300, instructing the test unit 310 in the test board 300 to set the status of the pins for which the device under test (DUT) failed to match.

[0078] Step S160: After receiving the verification command, the test unit sets the status of the pins of the device under test that failed to match according to the configured status flags. Setting the status of the pins of the device under test that failed to match includes setting the pins of the device under test to continue running the pattern, output high impedance, output low level, or output high level.

[0079] Specifically, after the pin matching is completed, the first controller 210 and the second controller 220 convert the successful and failed site matching results into transformed pin matching results (successful and failed pin matching results) based on the test unit mapping parameters and load them into the verification command for broadcast. The test unit 310, based on the pin matching results carried in the verification command, performs status setting for the failed pins according to the configured status flags. The status flags can be stored in the storage module 311 along with the pattern file. After receiving the verification command through the downlink module 316 and sending it to the micro-instruction module 312, the micro-instruction module 312 extracts the status flags from the storage module 311 and sends them to the test module 314 (specifically, it can be stored in the vector cache module 3141) to set the status of the pins that failed to match the device under test (DUT).

[0080] Furthermore, the pin matching results sent by the test unit to the communication board 200 only contain the concept of the test unit channel and do not have a corresponding relationship with the site. The communication board 200 binds the channel of the pin matching result to the corresponding site based on the site matching result of the test unit mapping parameters, and then converts it into a successful and unsuccessful pin matching result (i.e., the converted pin matching result, which contains the correspondence between the DUT matching pin and the site) based on the test unit mapping parameters and sends it to the corresponding test unit. The DUT pin of the successful site associated with the test unit is the successfully matched pin, and the DUT pin of the unsuccessful site associated with the test unit is the unsuccessful matched pin.

[0081] Furthermore, depending on the type of status flag, the method for setting the status of the pins that failed to match the device under test (DUT) will also vary. In this embodiment, there are four status flags: 2'b00 indicates that the failed pin continues to run the pattern; 2'b01 indicates that the failed pin is set to a high-impedance state, continuously outputting a high-impedance state or outputting 0; 2'b10 indicates that the failed pin runs drive 0 and outputs a low level; 2'b11 indicates that the failed pin runs drive 1 and outputs a high level. The first status flag indicates that the failed pin can be ignored and the pattern can continue to run. The latter three status flags indicate that the failed pin is configured to a corresponding locked state. The appropriate status flag can be selected according to the actual test needs to set the status of the pins that failed to match the DUT.

[0082] Furthermore, continue to refer to Figure 7 After step S150, the method may further include step S170: when the test unit detects that the number of matching completion loops executed by itself is inconsistent with the number of matching completion loops carried by the verification instruction, it outputs an alarm message.

[0083] The number of loop completions is defined as the number of loops at which a site matching corresponding to the site identifier is successfully matched, or the number of loops detected by the matching micro-instruction to have reached the first-level loop count. If a site matching corresponding to the site identifier is successful, the communication board 200 uses the number of loops detected when the site matching is successful as the number of loop completions. If the matching loop reaches the first-level loop count and a site matching still fails, the communication board 200 uses the first-level loop count as the number of loop completions. The communication board 200 broadcasts a verification instruction carrying the number of loop completions. The test unit 310 compares the number of loop completions carried in the verification instruction with the number of loop completions it has executed. If they do not match, an alarm message is output. The alarm message can be output in the form of audible and visual alarms, displaying setting information, sending an alarm signal to the host computer 100, or other methods, or a combination of multiple alarm methods.

[0084] Furthermore, after step S150, the method may further include: the communication board sending a continue execution instruction to the test unit.

[0085] The execution can be continued via a broadcast instruction from the first controller 210 to the corresponding test board 300, and the second controller 220 receiving the instruction from the first controller 210 and broadcasting it back to the corresponding test board 300. In the test unit 310, after the downlink module 316 receives the instruction and sends it to the micro-instruction module 312, the micro-instruction module 312 extracts the next micro-instruction from the pattern file, along with the corresponding pattern and timing parameters, for the next operation. If a matching micro-instruction may appear later in the pattern file, the test unit 310 performs another matching operation. For pins whose status was set in the current matching operation, matching can continue in the next matching operation. If the next micro-instruction in the pattern file is of another type, the test unit 310 performs the corresponding type of operation, and for pins whose status was set in the current matching operation, the set status is maintained.

[0086] In one embodiment, after step S140, the method may further include: when the cumulative number of verification commands issued by the communication board has not reached the set number of matching groups, sending a verification command and a continue execution command to the test unit; when the cumulative number of verification commands issued by the communication board reaches the set number of matching groups, sending a verification command and a continue execution command to the test unit and exiting the matching data collection state.

[0087] Similarly, the number of matching groups can be configured on the communication board 200 via the host computer 100, which serves as the basis for determining how many matching operations need to be performed. After each pin result matching is completed, the communication board 200 sends a verification command and a continue execution command to the test unit 310. That is, the sent verification command can represent the number of matching operations completed.

[0088] If the cumulative number of verification commands issued does not reach the set number of matching groups, the communication board 200 continues to issue verification commands and continue execution commands to the test unit 310. The test unit 310 sets the status of the pins of the device under test (DUT) that failed to match according to the configured status flags, and outputs an alarm message when it detects that the number of matching completion loops it has executed is inconsistent with the number of matching completion loops carried in the verification command. After receiving the continue execution command, the test unit 310 also extracts the next micro-instruction (which can be a matching micro-instruction or other types of micro-instruction) from the pattern file, as well as the corresponding pattern and corresponding timing parameters, for the next operation.

[0089] If the cumulative number of verification commands issued reaches the set number of matching groups, it indicates that all matching operations have been completed. The communication board 200 continues to issue verification commands and continue execution commands to the test unit 310 and exits the matching data collection state, meaning it no longer waits to receive site matching results. The test unit 310 sets the status of the pins of the device under test (DUT) that failed to match according to the configured status flags, and outputs an alarm message when it detects that the number of matching completion loops it has executed is inconsistent with the number of matching completion loops carried by the verification command. After receiving the continue execution command, the test unit 310 also extracts the next micro-instruction (other types of micro-instructions) from the pattern file, as well as the corresponding pattern and corresponding timing parameters, for the next operation.

[0090] In addition, after step S120, the method may further include: when the test unit determines the asynchronous mode based on the mode setting parameters and the pin result matching is completed, extracting the next micro-instruction and the corresponding pattern and timing parameters from the pattern file for the next operation.

[0091] When the test unit is in asynchronous mode, after the test unit 310 executes a matching loop and obtains the pin matching result, if all pins are successfully matched, there is no need to continue the matching loop and the pin matching result can be determined; if there are pins that fail to match, the matching loop continues, and the test unit 310 calls the expected pattern of multiple lines again to configure the pattern of the PE chip 400 until the matching loop reaches the first-level loop count, and retains the last obtained pin matching result.

[0092] The next microinstruction can be a matching microinstruction or other types of microinstructions. For example... Figure 2 As shown, in asynchronous mode, there is a one-to-one correspondence between test unit 310 and the site. Therefore, the pin matching result obtained after one matching loop can represent the corresponding site matching result. During the execution process from MatchStart to MatchLoop, if all channels of test unit 310 match successfully, or the matching loop reaches the first-level loop count (the last time), then the pin result matching in asynchronous mode is considered complete, that is, the matching operation based on the matching micro-instruction ends. Test unit 310 extracts the next micro-instruction (matching micro-instruction or other type of micro-instruction) from the pattern file, the corresponding pattern, and the corresponding timing parameters for the next operation.

[0093] It should be noted that in asynchronous mode, test unit 310 will also set the status of pins that fail to match the device under test (DUT), in a manner similar to that in synchronous mode, which will not be described in detail here.

[0094] In one embodiment, such as Figure 8 As shown, a method for matching pin results of multiple patterns is provided, implemented based on a communication board, including:

[0095] Step S210: Receive the test unit mapping parameters sent by the host computer.

[0096] Step S220: Receive the pin matching results sent by each test unit in the test board.

[0097] Specifically, the pin matching result is obtained by the test unit extracting the matching micro-instructions and expected pattern from the pattern file, repeatedly using multiple lines of the expected pattern according to the matching micro-instructions, matching the output signal of the device under test, and sending it to the communication board in synchronous mode. In synchronous mode, the channel of the same test unit is connected to the pins of the device under test of the same or different sites, and the pins of the device under test of the same site are connected to the channels of the same or different test units. The test unit mapping parameter represents the correspondence between the site associated with the test unit and the channel of the test unit in different test boards.

[0098] Step S230: Convert the pin matching result according to the test unit mapping parameters to obtain the site matching result of the corresponding site.

[0099] Step S240: After determining that the pin matching result of the corresponding site has been received based on the site identifier carried in the test unit mapping parameters, and the site matching result meets the matching completion condition, the pin result matching is complete. Here, the corresponding site refers to the site enabled in the site identifier.

[0100] In one embodiment, the communication board includes a first controller and a second controller, which communicate with test units in corresponding test boards, respectively; step S240 includes:

[0101] After the first controller and the second controller detect that they have received the pin matching results sent by all test units in the corresponding test board according to the preset distribution map information, and the site matching results meet the matching completion conditions, they send a matching result collection completion command to each other. The distribution map information includes the test board slot number, the test unit number, and the correspondence between the test unit and the site. After the first controller and the second controller receive the matching result collection completion command, the pin result matching is completed.

[0102] In one embodiment, after the first controller and the second controller receive the instruction to complete the matching result collection, the pin result matching is completed, and the first controller and the second controller respectively broadcast a verification instruction to the corresponding test board.

[0103] The verification command is generated based on the pin matching result. It is used by the test unit to set the status of pins on the device under test (DUT) that failed to match according to the configured status flags, and to output an alarm message when the test unit detects a discrepancy between the number of matching completion loops it has executed and the number of matching completion loops carried in the verification command. The number of matching completion loops is the number of loops at which the corresponding site is successfully matched, or when the matching micro-instruction detects that the loop matching has reached the first-level loop count. Setting the status of pins on the DUT that failed to match includes setting them to continue running the pattern, outputting a high impedance state, outputting a low level, or outputting a high level.

[0104] In one embodiment, after the first controller and the second controller broadcast verification commands to their respective test boards, the method further includes:

[0105] The first controller broadcasts a continue execution instruction to the corresponding test board, and the second controller receives the continue execution instruction from the first controller and broadcasts a continue execution instruction to the corresponding test board. The continue execution instruction is used by the test unit to extract the next microinstruction from the pattern file, as well as the corresponding pattern and timing parameters, for the next operation.

[0106] In one embodiment, such as Figure 9 As shown, after step S240, the method further includes steps S250 and S260.

[0107] Step S250: If the cumulative number of verification commands issued has not reached the set number of matching groups, send a verification command and a continue execution command to the test unit.

[0108] Step S260: If the cumulative number of verification instructions issued reaches the set number of matching groups, send the verification instruction and the continue execution instruction to the test unit, and exit the matching data collection state.

[0109] The verification command is used by the test unit to set the status of pins of the device under test that failed to match according to the configured status flags, and to output an alarm message when the test unit detects that the number of matching completion loops it has executed is inconsistent with the number of matching completion loops carried by the verification command. The number of matching completion loops is the number of loops when the site identifier indicates successful matching at the corresponding site, or when the matching micro-instruction detects that the loop matching has reached the first-level loop count. The continue execution command is used by the test unit to extract the next micro-instruction, the corresponding pattern, and the corresponding timing parameters from the pattern file for the next operation.

[0110] As can be understood, the specific implementation method of the multi-line pattern pin result matching method based on the communication board has been explained in detail above, and will not be repeated here.

[0111] In one embodiment, such as Figure 2 As shown, a chip tester is also provided, including a host computer 100, a test board 300, and a communication board 200. The test board 300 includes multiple test units 310. Each test unit 310 is connected to the host computer 100 through the communication board 200. The channel of each test unit 310 is connected to the pin of the device under test (DUT) of the corresponding site. The chip tester performs pin result matching of multiple patterns according to the above method.

[0112] In one embodiment, the test board 300 further includes a PE chip 400; the test unit 310 includes a storage module 311, a micro-instruction module 312, a cache module 313, a test module 314, an uplink module 315, a downlink module 316, and a mode register (not shown in the figure). The micro-instruction module 312 is connected to the storage module 311, the cache module 313, the uplink module 315, the downlink module 316, and the mode register. The uplink module 315 is connected to the communication board 200, the downlink module 316 is connected to the communication board 200, the test module 314 is connected to the cache module 313 and the micro-instruction module 312, and the test module 314 is also connected to the pin of the device under test (DUT) of the corresponding site through the PE chip 400.

[0113] Specifically, the microinstruction module 312 is configured to: extract mode setting parameters from the mode register, and extract matching microinstructions, row vectors, expected patterns and timing parameters from the pattern file from the storage module 311 and cache them in the cache module 313; and when the mode setting parameters determine that the synchronous mode is selected, send the received pin matching result to the communication board 200.

[0114] The test module 314 is configured to: read the matching micro-instruction, row vector, expected pattern and timing parameters from the cache module 313; perform pattern configuration on the PE chip 400 by cyclically reusing the expected pattern and timing parameters of multiple rows according to the order of the row vector; and receive the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the expected pattern, analyze it to obtain the pin matching result of the DUT and send it to the micro-instruction module 312.

[0115] Test module 314 is also configured to: after the pin result matching is completed in synchronous or asynchronous mode, set the status of the pins that failed to match the device under test (DUT) according to the configured status flags.

[0116] In other embodiments, it is understood that the test board 300 includes a mode register located outside the test unit 310 and corresponding to the test unit 310.

[0117] In one embodiment, the test module 314 includes a vector cache module 3141, a vector read / write control module 3142, a driver module 3143, and a result statistics module 3144. The vector cache module 3141 is connected to the cache module 313 and the vector read / write control module 3142. The vector read / write control module 3142 is connected to the driver module 3143 and the result statistics module 3144. The driver module 3143 is connected to the PE chip 400. The result statistics module 3144 is connected to the PE chip 400 and the microinstruction module 312.

[0118] The vector caching module 3141 is configured to retrieve the matching microinstructions, expected pattern, and timing parameters from the caching module 313 and cache them.

[0119] The vector read / write control module 3142 is configured to read matching microinstructions from the vector cache module 3141 in the order of row vectors, and use a two-level nested method to cyclically call the multi-row expected pattern and timing parameters in the vector cache module 3141 and send them to the driver module 3143.

[0120] The driver module 3143 is configured to configure the PE chip 400 according to the received multi-line expected pattern and timing parameters. The driver module 3143 sends the multi-line expected pattern to the PE chip 400, instructing the PE chip 400 to compare the specified pins. The result statistics module 3144 is configured to receive the matching micro-instruction and expected pattern sent by the vector read / write control module 3142; and receive the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the expected pattern, analyze the results to obtain the pin matching results of the DUT, and send the pin matching results to the micro-instruction module 312.

[0121] The vector cache module 3141 is also configured to: after the pin result matching is completed in synchronous or asynchronous mode, set the status of the pins that failed to match the device under test (DUT) according to the configured status flag.

[0122] In one embodiment, the test unit 310 further includes a matching failure cache module 317, and the test board 300 further includes a result storage device 320. The matching failure cache module 317 is connected to the result statistics module 3144 and the result storage device 320.

[0123] The result statistics module 3144 is also configured to: send the matching failure result data and storage instruction to the matching failure cache module 317 based on the response pattern received when the matching micro-instruction detection reaches the first-level loop count; wherein, the matching failure result data includes the row vector of the matching failure, the matching pin information corresponding to the row vector of the matching failure, and the corresponding expected pattern and response pattern.

[0124] The matching failure caching module 317 is configured to convert the matching failure result data according to the storage protocol based on the storage instruction and store it into the result storage device 320.

[0125] As can be understood, the specific implementation method of the chip testing machine mentioned above has been explained in detail, and will not be repeated here.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for matching pin results of multi-line patterns, characterized in that, include: The host computer sends the pattern file and mode setting parameters to the test units in the test board, and sends the test unit mapping parameters to the communication board; wherein, the test unit mapping parameters represent the correspondence between the site associated with the test unit and the test unit channel in different test boards; The test unit extracts the matching micro-instructions and expected pattern from the pattern file, and repeatedly reuses multiple lines of the expected pattern according to the matching micro-instructions to obtain the pin matching result obtained by matching the output signal of the device under test. When the test unit determines that it is in synchronous mode based on the mode setting parameters, it sends the pin matching result to the communication board. In synchronous mode, the channel of the same test unit is connected to the pins of the device under test (DUT) of the same or different sites, and the pins of the DUT of the same site are connected to the channels of the same or different test units. The communication board receives the pin matching results sent by each test unit in the test board, converts the pin matching results according to the test unit mapping parameters to obtain the site matching results of the corresponding site, and determines that the pin matching results of the corresponding site have been received according to the site identifier carried in the test unit mapping parameters. If the site matching results meet the matching completion conditions, the pin matching is completed.

2. The method according to claim 1, characterized in that, Before the host computer sends the pattern file and mode setting parameters to the test unit in the test board, and sends the test unit mapping parameters to the communication board, it also includes: When the host computer carries matching microinstructions in the pattern file, it determines the corresponding mode setting parameters based on the test unit mapping parameters and the pattern file.

3. The method according to claim 1, characterized in that, The host computer sends the pattern file and mode setting parameters to the test unit in the test board, including: the host computer sending the pattern file to the storage module of the test unit and sending the mode setting parameters to the mode register in the test unit; wherein, the test unit is configured to: read the mode setting parameters in the mode register to determine the working mode.

4. The method according to claim 3, characterized in that, The pattern file also includes row vectors and timing parameters corresponding to matching micro-instructions; the test unit extracts the matching micro-instructions and expected pattern from the pattern file, and repeatedly uses multiple rows of the expected pattern according to the matching micro-instructions to obtain the pin matching result obtained by matching the output signal of the device under test, including: The test unit extracts the matching micro-instructions, row vectors, expected pattern, and timing parameters from the pattern file from the storage module and sends them to the internal cache module for caching. The test unit reads the matching microinstruction, row vector, expected pattern and timing parameters from the cache module, and performs pattern configuration on the PE chip by cyclically reusing the expected pattern and timing parameters of multiple rows according to the order of the row vector and the matching microinstruction. The test unit receives the response pattern returned by the PE chip after comparing the output signal of the device under test with the expected pattern, and analyzes it to obtain the pin matching result of the device under test.

5. The method according to claim 4, characterized in that, The test unit reads matching microinstructions, row vectors, expected patterns, and timing parameters from the cache module. Following the order of the row vectors, it cyclically reuses multiple rows of expected patterns and timing parameters according to the matching microinstructions to configure the PE chip's pattern, including: The test unit obtains the matching micro-instructions, expected pattern, and timing parameters from the cache module and caches them into its internal vector cache module. The test unit reads matching micro-instructions from the vector cache module in the order of row vectors, and uses a two-level nested approach to cyclically call multiple rows of expected pattern and timing parameters in the vector cache module; The test unit configures the PE chip according to the multi-line expected pattern and timing parameters.

6. The method according to claim 5, characterized in that, The matching micro-instructions include the MatchStart micro-instruction, the MatchLoop micro-instruction, and the EndMatch micro-instruction; the test unit reads the matching micro-instructions from the vector cache module in the order of the row vectors, and uses a two-level nested approach to cyclically call the multi-row expected pattern and timing parameters in the vector cache module, including: The operands of the MatchStart microinstruction are used as the first-level loop counts, and the operands of the MatchLoop microinstruction are used as the inner second-level loop counts. The expected pattern and corresponding timing parameters between the MatchStart and EndMatch microinstructions are called in the order of the row vector. The first-level loop is from the MatchStart microinstruction to the MatchLoop microinstruction, and the second-level loop is from the MatchLoop microinstruction to the EndMatch microinstruction.

7. The method according to claim 6, characterized in that, The test unit extracts the matching microinstructions and expected pattern from the pattern file, and after repeatedly using multiple lines of the expected pattern according to the matching microinstructions to obtain the pin matching result obtained by matching the output signal of the device under test, it further includes: The test unit stores the matching failure result data into the result storage device based on the response pattern received when the matching micro-instruction detects the first-level loop count. The matching failure result data includes the row vector of the matching failure, the matching pin information corresponding to the row vector of the matching failure, and the corresponding expected pattern and response pattern.

8. The method according to claim 1, characterized in that, After determining that the pin matching result for the corresponding site has been received based on the site identifier carried in the test unit mapping parameters, and the site matching result meets the matching completion condition, the pin result matching is then completed, and the process further includes: The communication board generates a verification command based on the converted pin matching result and sends it to the test unit. The converted pin matching result is obtained by the test unit mapping parameters by converting the site matching result. After receiving the verification command, the test unit sets the status of the pins of the device under test that failed to match according to the configured status flags. Among them, the state settings of the pins of the device under test that failed to match include setting the pins of the device under test that failed to match to continue running the pattern, output high impedance, output low level, or output high level.

9. The method according to claim 8, characterized in that, After the communication board generates a verification command based on the converted PIN matching result and sends it to the test unit, it also includes: When the test unit detects that the number of matching completion loops it executes is inconsistent with the number of matching completion loops carried by the verification command, it outputs an alarm message; The number of matching cycles is the number of cycles when the site identifier is successfully matched with the corresponding site, or when the matching micro-instruction detects that the cycle matching has reached the first-level cycle count.

10. The method according to claim 8, characterized in that, After the communication board generates a verification command based on the converted PIN matching result and sends it to the test unit, it also includes: The communication board sends a continue execution command to the test unit; After receiving the continue execution instruction, the test unit extracts the next micro-instruction, the corresponding pattern, and the corresponding timing parameters from the pattern file for the next operation.

11. The method according to any one of claims 1 to 10, characterized in that, The matching completion condition is that each site is successfully matched or the cyclic matching reaches the first-level cycle count.

12. The method according to any one of claims 1 to 10, characterized in that, The test unit extracts the matching microinstructions and expected pattern from the pattern file, and after repeatedly using multiple lines of the expected pattern according to the matching microinstructions to obtain the pin matching result obtained by matching the output signal of the device under test, it further includes: When the test unit determines that the mode is asynchronous based on the mode setting parameters and the pin result matching is completed, it extracts the next micro-instruction, the corresponding pattern, and the corresponding timing parameters from the pattern file for the next operation. In asynchronous mode, the test unit and the site correspond one-to-one, and the pins of the device under test in the same site are connected to the channel of the same test unit.

13. A method for matching pin results of multi-line patterns, implemented based on a communication board, characterized in that, include: Receive test unit mapping parameters sent by the host computer; The test board receives pin matching results from each test unit. The pin matching results are obtained by the test unit extracting matching micro-instructions and expected patterns from the pattern file, repeatedly using multiple lines of the expected pattern according to the matching micro-instructions, matching the output signal of the device under test, and sending it to the communication board in synchronous mode. In synchronous mode, the channel of the same test unit is connected to the pins of the devices under test in the same or different sites, and the pins of the devices under test in the same site are connected to the channels of the same or different test units. The test unit mapping parameters characterize the correspondence between the site associated with the test unit and the test unit channel in different test boards; The pin matching result is converted according to the test unit mapping parameters to obtain the site matching result of the corresponding site; If the pin matching result of the corresponding site is received based on the site identifier carried in the test unit mapping parameters, and the site matching result meets the matching completion condition, then the pin result matching is complete.

14. The method according to claim 13, characterized in that, The communication board includes a first controller and a second controller, which communicate with the test units in the corresponding test boards, respectively. After determining that the pin matching result for the corresponding site has been received based on the site identifier carried in the mapping parameters of the test unit, and the site matching result meets the matching completion condition, the pin matching is considered complete, including: After the first controller and the second controller detect that they have received the pin matching results sent by all test units in the corresponding test board according to the preset distribution map information, and the site matching results meet the matching completion conditions, they send a matching result collection completion command to each other; the distribution map information includes the test board slot number, the test unit number, and the correspondence between the test unit and the site. After receiving the instruction that the matching result collection is complete, the first controller and the second controller complete the pin result matching.

15. The method according to claim 14, characterized in that, After receiving the instruction that the matching result collection is complete, the first and second controllers, after the pin result matching is complete, also include: The first controller and the second controller broadcast verification instructions to the corresponding test boards respectively. The verification instructions are generated based on the pin matching results. The verification instructions are used by the test unit to set the status of the pins of the device under test that failed to match according to the configured status flags, and to output alarm information when the test unit detects that the number of matching completion loops it has executed is inconsistent with the number of matching completion loops carried in the verification instructions. The number of matching cycles is the number of cycles when the site identifier is successfully matched or when the matching micro-instruction detects that the cycle matching has reached the first-level cycle count; the state settings of the pins of the device under test that failed to match include setting the pins of the device under test that failed to match to continue running the pattern, output high impedance, output low level, or output high level.

16. The method according to claim 15, characterized in that, After the first and second controllers broadcast verification commands to their respective test boards, the following steps are also included: The first controller broadcasts a continue execution instruction to the corresponding test board, and the second controller receives the continue execution instruction from the first controller and broadcasts the continue execution instruction to the corresponding test board. The continue execution instruction is used by the test unit to extract the next micro-instruction from the pattern file, as well as the corresponding pattern and timing parameters, for the next operation.

17. The method according to claim 13, characterized in that, After determining that the pin matching result for the corresponding site has been received based on the site identifier carried in the test unit mapping parameters, and the site matching result meets the matching completion condition, the pin result matching is then completed, and the process further includes: If the cumulative number of verification commands issued does not reach the set number of matching groups, a verification command and a continue execution command are sent to the test unit. If the cumulative number of verification instructions issued reaches the set number of matching groups, a verification instruction and a continue execution instruction are sent to the test unit, and the matching data collection state is exited. The verification instruction is used by the test unit to set the status of the pin of the device under test that failed to match according to the configured status flag, and to output an alarm message when the test unit detects that the number of matching completion loops it has executed is inconsistent with the number of matching completion loops carried by the verification instruction; the number of matching completion loops is the number of loops when the site identifier corresponds to the site and the matching micro-instruction detects that the loop matching has reached the first level of loop count. The continue execution instruction is used by the test unit to extract the next microinstruction from the pattern file, as well as the corresponding pattern and timing parameters, for the next operation.

18. A chip testing machine, characterized in that, The device includes a host computer, a test board, and a communication board. The test board includes multiple test units, each of which is connected to the host computer via the communication board. The channel of each test unit is connected to the pin of the device under test (DUT) of the corresponding site. The chip tester performs pin result matching of multiple patterns according to the method described in any one of claims 1 to 12.

19. The chip testing machine according to claim 18, characterized in that, The test board also includes a PE chip; the test unit includes a storage module, a micro-instruction module, a cache module, a test module, an uplink module, a downlink module, and a mode register. The micro-instruction module is connected to the storage module, the cache module, the uplink module, the downlink module, and the mode register. The uplink module is connected to the communication board, the downlink module is connected to the communication board, the test module is connected to the cache module and the micro-instruction module, and the test module is also connected to the pin of the device under test of the corresponding site through the PE chip. The microinstruction module is configured to: extract mode setting parameters from the mode register, and extract matching microinstructions, row vectors, expected patterns and timing parameters from the pattern file from the storage module and cache them in the cache module; and when the mode setting parameters determine that the synchronous mode is selected, send the received pin matching result to the communication board. The test module is configured to: read matching micro-instructions, row vectors, expected patterns, and timing parameters from the cache module; configure the PE chip with a pattern by cyclically reusing the expected patterns and timing parameters of multiple rows according to the order of the row vectors; and receive the response pattern returned by the PE chip after comparing the output signal of the device under test with the expected pattern, analyze it to obtain the pin matching result of the device under test, and send it to the micro-instruction module. The test module is also configured to: after the pin result matching is completed in synchronous or asynchronous mode, set the status of the pins that failed to match the device under test according to the configured status flag.

20. The chip testing machine according to claim 19, characterized in that, The test board also includes a result storage device; the test module includes a vector cache module, a vector read / write control module, a driver module, a result statistics module, and a matching failure cache module. The vector cache module is connected to the cache module and the vector read / write control module. The vector read / write control module is connected to the driver module and the result statistics module. The driver module is connected to the PE chip. The result statistics module is connected to the PE chip and the microinstruction module. The matching failure cache module is connected to the result statistics module and the result storage device. The vector caching module is configured to: retrieve the matching microinstructions, expected pattern, and timing parameters from the caching module and cache them; The vector read / write control module is configured to: read matching micro-instructions from the vector cache module in the order of row vectors, and use a two-level nested approach to cyclically call multiple rows of expected pattern and timing parameters in the vector cache module and send them to the driver module; The driving module is configured to: configure the PE chip according to the received multi-line expected pattern and timing parameters; The result statistics module is configured to: receive matching micro-instructions and expected patterns sent by the vector read / write control module; receive the response pattern returned by the PE chip after comparing the output signal of the device under test with the expected pattern, analyze and obtain the pin matching result of the device under test, and send the pin matching result to the micro-instruction module; and send matching failure result data and storage instructions to the matching failure cache module according to the response pattern received when the matching micro-instruction detects that the first-level loop count has been reached; wherein, the matching failure result data includes the row vector of the matching failure, the matching pin information corresponding to the matching failure row vector, and the corresponding expected pattern and response pattern; The vector cache module is also configured to: after the pin result matching is completed in synchronous or asynchronous mode, set the status of the pin that failed to match the device under test according to the configured status flag; The matching failure caching module is configured to: convert the matching failure result data according to the storage protocol based on the storage instruction, and store it into the result storage device.

Images