Automatic calibration method and device for chip testing machine

Abstract

The invention discloses an automatic calibration method and device for a chip testing machine, and relates to the technical field of chip testing, and the method comprises the steps: forming a four-end-pair closed path through two channels, building a symmetric reciprocal calibration ring, carrying out the zero check, and generating a loop health vector; based on the loop health vector, bidirectional four-quadrant sequencing is performed on the first channel and the second channel, and independent errors of a source chain and a measurement chain are separated to form a channel error map; according to the channel error atlas, slope standard deviation piecewise linearization processing is executed on each measuring range and each frequency point, a middle linear region and nonlinear regions at the two ends are determined, and a sectional calibration table is generated. According to the method, bidirectional four-quadrant sequencing is executed under a healthy loop, and source chain and measurement chain errors are separated, so that an independent error map of each channel is obtained, and error term aliasing in traditional calibration is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to an automatic calibration method and device of a chip testing machine. BACKGROUND

[0002] With the development of chip testing technology towards high precision, high frequency and multi-channel direction, the calibration method of traditional chip testing machine generally relies on manual or semi-automatic fixed-point comparison method. The existing calibration process usually calibrates the output and measurement response of each channel by connecting external standard impedance, standard resistance or reference voltage source. Therefore, to realize the automatic, self-closed loop and high robustness calibration method in complex environment has become the key direction of the development of high-performance chip testing equipment.

[0003] However, the existing automatic calibration technology still has many deficiencies. On the one hand, the multi-channel calibration loop generally lacks real-time detection and quantitative index of channel reciprocity and symmetry, which leads to that the calibration result cannot reflect the bidirectional consistency of the channel; on the other hand, the existing linearization method mostly uses single model fitting in the whole interval, which is difficult to cope with the local drift of the nonlinear section. In addition, the guard ring setting of the high resistance node is usually fixed or manually adjusted, without considering the dynamic optimal setting of the leakage current, which leads to poor repeatability in the low current section. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides an automatic calibration method of a chip testing machine to solve the problem that the existing chip testing machine cannot dynamically correct the non-linear region drift and guard ring leakage in multi-channel reciprocity calibration.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides an automatic calibration method of a chip testing machine, which comprises: establishing a symmetric and reciprocal calibration loop by surrounding a four-terminal pair closed path through two channels, and performing zero position check to generate a loop health vector;

[0008] Based on the loop health vector, bidirectional four-quadrant sequencing is performed on channel one and channel two, and independent errors of source chain and measurement chain are separated to form a channel error map;

[0009] According to the channel error map, slope standard deviation segmentation linearization processing is performed on each range and frequency point to determine the middle linear region and the two end nonlinear regions, and a segmented calibration table is generated;

[0010] On the high resistance node, the segmented calibration table is taken as the baseline to perform guard ring potential scanning and standard capacitance slope review to determine the leakage minimum guard ring setting, and leakage-baseline compensation is generated;

[0011] The segmented calibration table and leakage-baseline compensation are embedded into a register and piecewise linear fine-tuning is performed to generate the final parameter package.

[0012] As a preferred embodiment of the automatic calibration method for the chip testing machine described in this invention, the specific steps for establishing a symmetrical reciprocal calibration loop and performing a zero-point check are as follows:

[0013] A precision resistor and a symmetrical RC network are connected in series between the source and measurement ends of the two channels to form a closed path;

[0014] Programmable bidirectional solid-state relays are configured at both ends of the closed path to enable source-measure interchange and positive-reverse connection switching, forming a switchable calibration loop;

[0015] Connect the switchable calibration ring to the guard ring and the reference ground, complete the isothermal waiting and time base locking, and perform a zero-point check to obtain the zero-point deviation;

[0016] Based on the zero-position deviation, a short scan is triggered to record the symmetry characteristics of the transfer standard, the loop parasitic parameters, and the thermoelectric potential deviation state, thereby generating a loop health vector.

[0017] As a preferred embodiment of the automatic calibration method for the chip testing machine described in this invention, the specific steps for performing bidirectional four-quadrant sequencing on channel one and channel two are as follows:

[0018] Based on the loop health vector, a measurement point sequence is selected, and under positive connection conditions, a forward scan is performed with channel 1 as the source chain and channel 2 as the measurement chain to obtain the first set of readings.

[0019] Keeping the polarity unchanged, switch channel 2 to the source chain and channel 1 to the test chain, perform a forward scan, and obtain the second set of readings;

[0020] Keeping the role unchanged, reverse the polarity and perform a reverse scan to obtain the third set of readings;

[0021] A reverse scan is performed under opposite polarity and opposite role conditions to obtain a fourth set of readings. The four sets of readings are then combined to form the original set of readings in the four quadrants.

[0022] In a preferred embodiment of the automatic calibration method for the chip testing machine described in this invention, the specific steps for separating the independent errors of the source chain and the test chain are as follows:

[0023] The polarity-related component and the role-related component are obtained by summing and differencing four readings at the same measurement point in the four-quadrant raw reading set.

[0024] Based on the polarity-related components and the role-related components, the zero-point bias of the measurement chain, the gain of the excitation chain, and the linear term are determined to obtain the error vector for each channel.

[0025] The error vectors of each measurement point are grouped according to the range and frequency point, and the initial values of the phase and group delay are supplemented to form a channel error map.

[0026] As a preferred scheme of the automatic calibration method of the chip tester, the slope standard deviation is segmented linearly, and the specific steps are as follows,

[0027] Based on the channel error map, an equidistant setpoint sequence is generated at each range and each frequency point, and a slope sequence of adjacent points is calculated.

[0028] The standard deviation peaks are found in the left and right half regions of the slope sequence of adjacent points, and the left and right segment points are determined to obtain the middle linear region and the two end nonlinear regions.

[0029] The linear coefficients of the middle linear region and the polynomial coefficients of the two end nonlinear regions are extracted, and the segment points are corrected to generate a segmented coefficient set.

[0030] As a preferred scheme of the automatic calibration method of the chip tester, the segmented calibration table is indexed according to the channels, ranges and frequency points in the segmented coefficient set, records the applicable range and the middle working point and the end segment boundary, and is written into the register address to form a lookup table structure.

[0031] As a preferred scheme of the automatic calibration method of the chip tester, the guard ring potential scanning and standard capacitance slope review are performed, and the specific steps are as follows,

[0032] The range and working point of high resistance measurement are set according to the segmented calibration table, and the guard ring potential is changed to obtain a leakage current curve.

[0033] The leakage minimum guard ring position is determined according to the leakage current curve.

[0034] The leakage minimum guard ring position is maintained, the high resistance node is connected to the standard transfer capacitor, a linear slope is applied to obtain a review reading, and the low current segment coefficient in the segmented calibration table is closed loop fine tuned to generate leakage-baseline compensation.

[0035] As a preferred scheme of the automatic calibration method of the chip tester, the low current segment coefficient in the segmented calibration table is closed loop fine tuned, which means that under the condition of maintaining the leakage minimum guard ring position, the review reading is subtracted from the predicted reading of the segmented calibration table at the same measurement point to obtain a closed loop error signal, the zero term, gain term and end segment connection term coefficients of the low current segment are automatically adjusted, and are written back to the corresponding register.

[0036] As a preferred scheme of the automatic calibration method of the chip tester, wherein: the segment type calibration table and the leakage-base compensation are solidified to the register, and the segmented linear fine adjustment is performed, and the specific steps are as follows,

[0037] The segment type calibration table and the leakage-base compensation are combined into a parameter set and written into a nonvolatile register.

[0038] The parameter set is called by a lookup table structure at runtime, a corresponding segmented linear fine adjustment item is selected according to interval values of temperature, humidity and power-on time, the lookup table structure at runtime is updated, and a final parameter package is generated.

[0039] In a second aspect, the present application provides an automatic calibration device of a chip tester, comprising,

[0040] The reciprocity calibration module surrounds the symmetric reciprocity calibration loop by the two-way channel to form a four-terminal pair closed path, performs zero position checking, and generates a loop health vector.

[0041] The error decoupling module performs bidirectional four-quadrant sequencing on channel one and channel two based on the loop health vector, and separates the independent errors of the source chain and the measurement chain to form a channel error map.

[0042] The segmented linearization module performs segmented linearization processing of the slope standard deviation on the channel error map in each range and frequency point, determines the middle linear region and the two end nonlinear regions, and generates a segment type calibration table.

[0043] The guard ring review module performs guard ring potential scanning and standard capacitance slope review on the high resistance node based on the segment type calibration table as a baseline, determines the leakage minimum guard ring setting, and generates a leakage-base compensation.

[0044] The parameter solidification module solidifies the segment type calibration table and the leakage-base compensation to the register, and performs segmented linear fine adjustment to generate a final parameter package.

[0045] The present application has the beneficial effects that: by establishing the symmetric reciprocity calibration loop of the four-terminal pair closed path and generating the loop health vector, the thermal drift, leakage current, thermoelectric potential and port symmetry of the channel are quantitatively characterized, and real-time health judgment basis is provided for subsequent calibration; by performing bidirectional four-quadrant sequencing on the healthy loop and separating the source chain and measurement chain errors, the independent error map of each channel is obtained, and the error item aliasing problem in the traditional calibration is avoided; the slope standard deviation segmented linearization processing divides the range interval into linear and nonlinear partitions, adaptive fitting in different regions is realized, and the precision and stability of the calibration model in a wide range are improved. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0047] Fig. 1 Flow chart of the automatic calibration method of the chip tester.

[0048] Fig. 2 Flow chart of the calibration ring and health check.

[0049] Fig. 3 Flow chart of the error separation and channel error map generation.

[0050] Fig. 4 Flow chart of the piecewise linearization, guard ring review and parameter solidification. DETAILED DESCRIPTION

[0051] In order to make the above objectives, features and advantages of the present application more apparent and comprehensible, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0052] In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0053] Secondly, the "one embodiment" or "embodiment" referred to herein means that the specific features, structures or characteristics can be included in at least one implementation of the present application. "In one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an independent or alternative embodiment that excludes other embodiments.

[0054] Reference Figs. 1-4 For one embodiment of the present application, the embodiment provides an automatic calibration method of a chip tester, comprising the following steps:

[0055] S1. A symmetric and reciprocal calibration ring is established by surrounding a four-terminal pair closed path through two paths, and zero position check is performed to generate a loop health vector.

[0056] S1.1. Select Channel 1 and Channel 2 as the calibration channels within the chip testing machine. Connect the source end of Channel 1 to the test end of Channel 2, and simultaneously connect the source end of Channel 2 to the test end of Channel 1 to form a closed path. Connect a four-terminal traceable transfer standard in series between the source end and the test end of the calibration channel, while maintaining strict separation of the four-terminal connection specifications (current end, voltage end, and shield end) to construct an initial symmetrical reciprocal calibration loop.

[0057] A set of programmable bidirectional solid-state relays is arranged at both ends of the initial symmetrical reciprocal calibration loop. By controlling the conduction direction of the programmable bidirectional solid-state relays, the "source ↔ measurement" role interchange and "positive connection ↔ reverse connection" polarity reversal between channels are realized, ensuring that subsequent measurements can realize bidirectional excitation and response interchange under symmetrical conditions.

[0058] It should be noted that the four-terminal traceable transfer standard refers to an electrical transfer device with a four-terminal connection structure and a traceable evidence chain. During DC calibration, a four-terminal precision resistor network is used to provide a traceable resistance reference, while during AC calibration, a symmetrical RC network is used to provide an impedance reference with traceable amplitude and phase.

[0059] S1.2. Connect the guard rings of Channel 1 and Channel 2 to the reference ground according to the four-terminal pair specification, and adjust the potential difference between the guard ring potential and the reference ground to ensure that the potential of the shielding layer of the test circuit and the measurement circuit are balanced, and prevent leakage error caused by uneven potential. After the channel connection is completed, start the high-stability time base and direct digital synthesis signal source to put the entire symmetrical reciprocal calibration ring under constant temperature and stable frequency conditions and enter the isothermal waiting stage. After the isothermal waiting is completed, perform a zero-point check and measure the residual potential at both ends of the channel under no-excitation conditions to determine whether there is residual bias or thermal drift in the calibration ring. If so, re-enter the isothermal waiting stage and adjust the contact pressure until the residual potential meets the requirements.

[0060] It should be noted that the retaining ring refers to the shielding electrode that is set around the high-resistivity measurement node and kept at the same potential as the measurement circuit, in order to reduce surface leakage current and distributed capacitance coupling.

[0061] A high-stability time base refers to a reference clock source with low phase noise and low drift characteristics. A direct digital synthesized signal source refers to an excitation source that outputs a controllable sine signal based on a frequency synthesis method using digital phase accumulation and table lookup.

[0062] The constant temperature is achieved through the temperature control chamber inside the chip tester, set at 25±0.5℃; the stable frequency is obtained by a high-stability time-base phase-locked loop direct digital synthesis signal source, set at 1MHz±0.1Hz.

[0063] S1.3. When the zero position check is qualified, trigger a short time scan, compare the measured impedance of the four-terminal pair transfer standard under the positive and negative connection conditions, record the symmetry characteristic, loop parasitic parameter and thermoelectric potential deviation state of the transfer standard, wherein the symmetry characteristic of the transfer standard reflects the consistency of the response under the positive and negative excitation conditions, the loop parasitic parameter is used to evaluate the additional impedance in the closed path, and the thermoelectric potential deviation state is used to reflect the small electromotive force caused by the thermal unevenness between the contact point and the conductor.

[0064] According to the symmetry characteristic, loop parasitic parameter and thermoelectric potential deviation state of the transfer standard measured by the short time scan, the comprehensive health index of the loop is calculated, and the loop health vector is generated, which contains four parameters of temperature drift amount, guard ring leakage amount, thermoelectric potential deviation amount and port symmetry degree, for characterizing the overall stability and availability of the current calibration loop, and if the loop health vector is within the preset threshold range, it is considered that the calibration loop meets the reciprocity condition.

[0065] It should be noted that the comprehensive health index is defined as the maximum value of the four normalized components, and the expression for calculating the comprehensive health index of the loop is:

[0066] ;

[0067] wherein, represents the comprehensive health index, ≤1 determines that the symmetric reciprocity calibration loop meets the reciprocity condition and is in a healthy state; when >1, the isothermal frequency stabilization and zero position check need to be re-executed, represents the temperature drift amount, represents the guard ring leakage amount, represents the thermoelectric potential deviation amount, represents the port symmetry degree error, , , and respectively represent the temperature drift threshold, the guard ring leakage threshold, the thermoelectric potential deviation threshold and the port symmetry degree error threshold.

[0068] The preset threshold includes the temperature drift threshold, the guard ring leakage threshold, the thermoelectric potential deviation threshold and the port symmetry degree error threshold.

[0069] The temperature drift threshold is set based on the thermal inertia characteristics of the temperature control cavity in the test machine under steady state conditions, and is set to ±0.1℃. The value is obtained by analyzing the thermal drift of the channel device and the stability of the steady state temperature.

[0070] The guard ring leakage threshold is set based on the leakage current test of the surface resistivity and humidity change of the guard ring material, and the guard ring leakage threshold is set to be less than or equal to 1×10 -12A, the value is obtained according to the analysis of the wet and dry state leakage current comparison of the insulating material and the repeatability of the high resistance measurement.

[0071] The thermal electromotive force deviation threshold is determined according to the thermal electromotive force drift of different metal terminal combinations under a steady state temperature difference, and the thermal electromotive force deviation threshold is set to be less than or equal to 50 µV, and the value is obtained according to the measured characteristics of the metal contact thermal electromotive force drift curve and the symmetry verification result of the channel.

[0072] The port symmetry error threshold is set based on the symmetry statistical results of the channel matching degree and the excitation response ratio, and the port symmetry error threshold is set to be less than or equal to 0.01%, and the value is obtained by fitting the measured data of the channel gain matching and phase difference.

[0073] When all components in the loop health vector are within the preset threshold range, it is determined that the symmetric and reciprocal calibration loop meets the reciprocity condition and is in a healthy state; when any component exceeds the corresponding threshold, it is determined that there is an asymmetric factor or environmental disturbance in the calibration loop, and the isothermal frequency stabilization and zero position check need to be performed again.

[0074] S2. Based on the loop health vector, bidirectional four-quadrant sequencing is performed on channel one and channel two, and independent errors of the source chain and the measurement chain are separated to form a channel error map.

[0075] S2.1. Utilize the temperature drift amount, guard ring leakage amount, thermal electromotive force deviation amount, and port symmetry in the loop health vector to determine the amplitude range, step size, and dwell time of the measurement point sequence, so that the measurement point sequence covers the required range and typical frequency and avoids the end extreme region;

[0076] Under the positive connection condition, channel one is used as the source chain and channel two is used as the measurement chain, forward scanning is performed according to the measurement point sequence from low to high, and stable waiting and multiple sampling are completed at each measurement point to obtain a first set of readings;

[0077] Without changing the polarity, channel two is set as the source chain and channel one is set as the measurement chain, forward scanning is performed according to the same measurement point sequence, and a second set of readings is obtained;

[0078] Without changing the roles of the source chain and the measurement chain, the condition is reversed to the reverse connection condition, reverse scanning is performed according to the measurement point sequence from high to low, and a third set of readings is obtained;

[0079] Under the reverse connection condition, channel one is set as the measurement chain and channel two is set as the source chain, reverse scanning is performed according to the measurement point sequence, and a fourth set of readings is obtained. The first set of readings, the second set of readings, the third set of readings, and the fourth set of readings are correspondingly combined according to the measurement points to form a four-quadrant original reading set.

[0080] It should be noted that the typical frequency points refer to a representative set of frequencies covering the application bandwidth in AC mode, such as 10 Hz, 100 Hz, 1 kHz, 10 kHz and 100 kHz, which are pre-set according to the bandwidth of the chip tester and the use scene of the measured object.

[0081] S2.2. For each measurement point in the four-quadrant original reading set, the polarity-related component reflecting the polarity reversal effect and the role-related component reflecting the role exchange effect of the source chain and the measurement chain are obtained by symmetric summation and difference method respectively;

[0082] The polarity-related component is used to represent the baseline shift amount of the measurement chain when the excitation symbol changes, and to determine the zero point offset of the measurement chain, and the role-related component is used to represent the amplitude ratio and linear deviation amount of the excitation chain when the role is exchanged, and to determine the gain and linear term of the excitation chain;

[0083] The measurement chain zero point offset, excitation chain gain and linear term are collected according to the channel dimension to obtain the error vector of channel one and the error vector of channel two, and at the AC measurement point, the phase difference between the excitation and response is measured based on the reference time base of the direct digital synthesis signal source, and the phase difference change amount of adjacent frequency points is converted into the initial value of group delay and added to the error vector of channel one and the error vector of channel two.

[0084] It should be noted that the polarity-related component reflecting the polarity reversal effect and the role-related component reflecting the role exchange effect of the source chain and the measurement chain are obtained by symmetric summation and difference method, and the expression is:

[0085] , ;

[0086] Among them, represents the baseline shift amount caused by polarity reversal, represents the amplitude ratio and linear deviation amount caused by role exchange, represents the reading of positive connection and channel one as source chain and channel two as measurement chain, represents the reading of positive connection and channel two as source chain and channel one as measurement chain, represents the reading of negative connection and channel one as source chain and channel two as measurement chain, represents the reading of negative connection and channel two as source chain and channel one as measurement chain.

[0087] The expression for converting the phase difference change amount of adjacent frequency points into the initial value of group delay is:

[0088] ;

[0089] Among them, represents the initial value of group delay at frequency point , represents the initial value of group delay at frequency point the phase of the difference between the stimulus and the response at the frequency point, the phase of the difference between the stimulus and the response at the frequency point, the phase of the difference between the stimulus and the response at the frequency point, the index of the frequency point.

[0090] S2.3. Group and merge the error vectors of channel one and the error vectors of channel two by the direct current range, the alternating current amplitude range, and the frequency point index, so that each range and each frequency point has complete entries of the measurement chain zero point offset, the stimulus chain gain, the linear term, the phase initial value, and the group delay initial value; perform consistency check on the entries of each range and each frequency point, eliminate abnormal points that do not satisfy the loop health vector constraint, and replace the abnormal points with stable readings of adjacent measurement points;

[0091] After completing the grouping and merging and the consistency check, generate the channel error atlas containing the entries of all ranges and all frequency points of channel one and the channel error atlas containing the entries of all ranges and all frequency points of channel two.

[0092] It should be noted that the loop health vector constraint refers to the threshold limit of the temperature drift amount, the guard ring leakage amount, the thermoelectric potential deviation amount, and the port symmetry degree.

[0093] S3. According to the channel error atlas, perform slope standard deviation piecewise linearization processing on each range and each frequency point to determine the middle linear region and the two end nonlinear regions, and generate a piecewise calibration table.

[0094] S3.1. Take the entries of each range and each frequency point of each channel in the channel error atlas as the starting point, generate an equidistant setpoint sequence according to the upper and lower limits of the range and the typical working interval, the number of points of the equidistant setpoint sequence is not less than twenty points, and each end has a safety margin point to avoid end saturation; call the entries in the channel error atlas point by point for the equidistant setpoint sequence, obtain the response readings corresponding to the equidistant setpoint sequence one by one, and calculate the slope sequence of adjacent points by the reading difference of adjacent points and the set difference.

[0095] It should be noted that the upper and lower limits of the range refer to the nominal lower limit and the nominal upper limit of the chip tester corresponding to the range grading; the typical working interval refers to the central working interval after removing the 10% end safety margin of the upper and lower limits of the range, and the 10% is because the end region is more prone to changes in relay contact resistance, amplifier saturation, and quantization nonlinear amplification, and 10% can avoid the end distortion region while retaining sufficient data density, forming a symmetric safety margin; if it is significantly less than 10%, the influence of end nonlinear on segment point identification increases, and if it is significantly greater than 10%, the effective working area is excessively compressed, which is not conducive to stable fitting of coefficients.

[0096] The number of points in the setpoint sequence is no less than 21 because taking an odd number of points makes it easier to define a single median index for left and right half-region division and peak location. Each half-region contains at least ten slope samples, which can stably estimate the slope dispersion and suppress the influence of isolated outliers. Three-segment fitting (linear in the middle segment and three-order at both ends) requires sufficient degrees of freedom. 21 is the minimum scale that can satisfy robust segmentation and fitting.

[0097] The expression for calculating the slope sequence of adjacent points is:

[0098] ;

[0099] in, Indicates the first The first set point and the first Discrete slope between set points Indicates the first A set point, Indicates the first The response readings corresponding to each setpoint Indicates the first A set point, Indicates the first The response readings corresponding to each set point Indicates the setpoint index. This indicates the total number of set points.

[0100] S3.2. Divide the slope sequence of adjacent points into a left half and a right half according to the median index of the equidistant setpoint sequence. Calculate the slope dispersion in the left half using an increasing prefix method and locate the peak index of the dispersion. Use the equidistant setpoint position corresponding to the peak index as the left segment point. Calculate the slope dispersion in the right half using a decreasing suffix method and locate the peak index of the dispersion. Use the equidistant setpoint position corresponding to the peak index as the right segment point. Divide the equidistant setpoint sequence into a left-end nonlinear region, a middle-end linear region, and a right-end nonlinear region using the left and right segment points.

[0101] It should be noted that the expression for calculating the slope dispersion in the left half of the region is:

[0102] ;

[0103] in, Indicates prefix length is The slope dispersion in the left half of the time period Indicates the prefix length index of the left half region. The index representing the count of the slope samples. Indicates the first Slope samples of adjacent points, This indicates that the prefix length of the left half region is... The average slope at that time.

[0104] S3.3. Perform linear fitting of minimum residual on the equidistant setpoint sequence and corresponding response readings in the middle linear region to obtain the linear coefficients of the middle linear region; in the left and right end nonlinear regions, perform third-order polynomial fitting of minimum residual on the equidistant setpoint sequence and corresponding response readings in the respective regions to obtain the polynomial coefficients of the left end nonlinear region and the polynomial coefficients of the right end nonlinear region;

[0105] Perform continuity correction of the linear coefficients of the middle linear region and the polynomial coefficients of the two end nonlinear regions at the left and right segmentation points, and make slight adjustments to the linear coefficients and polynomial coefficients to form a segmented coefficient set, and select the center point of the equidistant setpoint sequence in the middle linear region as the middle working point, and select the positions of the left and right segmentation points as the end region boundaries.

[0106] S3.4. Establish a three-dimensional index of the segmented coefficient set according to the channel, range, and frequency point, record the middle linear region linear coefficients, left end nonlinear region polynomial coefficients, right end nonlinear region polynomial coefficients, left segmentation point position, right segmentation point position, middle working point, and end region boundaries of each channel at each range and each frequency point, and assign a register address to each item to form a lookup table structure; generate a segmented calibration table by taking the index items of all channels, all ranges, and all frequency points as a set, the segmented calibration table covers the direct current range items and alternating current frequency point items, and each item can output a predicted reading at the corresponding setpoint through the lookup table structure.

[0107] S4. Take the segmented calibration table as the baseline, perform guard ring potential scanning and standard capacitance slope review on the high resistance node, determine the guard ring position with the smallest leakage, and generate leakage-baseline compensation.

[0108] S4.1. Take the middle working point in the low current segment corresponding range as the initial working point based on the segmented calibration table, set the measurement range, integration time, and sampling number of the high resistance node, and limit the working interval according to the end region boundaries of the segmented calibration table; set the guard ring potential scanning range and step around the measurement loop potential on the high resistance node (e.g. -1.0V to +1.0V relative to the measurement loop potential, step 50mV), keep a fixed dwell time and collect stable readings at each guard ring potential step, record the corresponding relationship between the guard ring potential and the corresponding leakage current, and form a leakage current curve.

[0109] S4.2. Search for the global minimum point in the leakage current curve, and obtain the leakage minimum shield ring setting; solidify the leakage minimum shield ring setting to the shield ring control channel, and keep the leakage minimum shield ring setting as the fixed working state of all high resistance and ultra-low current measurements, while marking the working point information corresponding to the leakage minimum shield ring setting in the range entry of the segment calibration table as the starting condition of the standard capacitance slope review.

[0110] S4.3. Under the condition that the leakage minimum shield ring setting remains unchanged, connect the high resistance node to the standard transfer capacitor, apply a linear voltage ramp to generate traceable micro-current using a direct digital synthesis signal source, select a small number of representative measurement points in the low current segment according to the measurement point sequence of S2.1, perform bidirectional four-quadrant short-time scanning, collect four sets of readings of positive and negative connections, source chain and measurement chain interchanged, and obtain review readings after stable waiting and multiple sampling stability processing;

[0111] Compare the review readings with the predicted readings of the segment calibration table at the same measurement points and under the same wiring conditions point by point to obtain a closed-loop error signal, and obtain an error signal set for low current segment correction.

[0112] It should be noted that the standard transfer capacitor refers to a capacitor with traceable evidence chain and negligible dielectric loss and leakage, which is used to convert a linear voltage ramp into traceable micro-current.

[0113] S4.4. According to the error signal set, under the constraint of keeping the function values and first-order derivatives of the left and right segment points continuous, perform item-by-item micro-adjustment for the zero point, gain and end segment connection of the low current segment until the error signals of all representative measurement points are within the preset convergence threshold; the adjusted low current segment coefficients and the leakage minimum shield ring setting are summarized as leakage-baseline compensation.

[0114] It should be noted that the preset convergence threshold is set according to the statistical upper limit of the high resistance range noise floor, the quantization resolution and the end segment connection error, which is used to constrain the termination condition of the low current segment closed-loop fine tuning process. In order to balance the convergence accuracy and adjustment stability, the preset convergence threshold is defined as the larger one of the "micro-current absolute threshold" and the "full-scale percentage threshold". In numerical value, the micro-current absolute threshold is usually set to 1 × 10 -13 A~5×10 -13Between A and F corresponds to the noise level of high-impedance measurement; the full-scale percentage threshold is usually set to 0.005% to 0.01%FS to limit the relative residual at the large signal end. When the noise is high or the range is large, the percentage threshold is dominant; when the range is small or in the ultra-low current range, the absolute threshold is dominant. If only a larger threshold is used, the closed-loop adjustment will terminate prematurely, and the residual will still retain deviation at the end. If the threshold is too small, multiple repeated measurements and fine-tuning are required, the convergence speed will decrease and the noise amplification effect will be significant. Therefore, choosing a larger one as the final threshold can achieve a balance between convergence efficiency, adjustment stability and residual controllability.

[0115] S5. Solidify the segmented calibration table and leakage-baseline compensation into the register, and perform piecewise linear fine-tuning to generate the final parameter package.

[0116] S5.1. Merge the segment calibration table and leakage-baseline compensation into a parameter set, assign register addresses to each entry of channel, range and frequency point and write them to non-volatile registers, and load the index and coefficients of the parameter set into the lookup table structure at runtime.

[0117] Read the current interval values ​​of temperature, humidity and power-on duration, select the corresponding segmented linear fine-tuning item according to the middle segment working point and end segment boundary recorded in the segmented calibration table, perform linear fine-tuning on the zero point item, gain item and end segment connection item and update the lookup table structure during operation.

[0118] It should be noted that the index refers to the quadruple of channel number, range number, frequency point number and segment number; the coefficients refer to the linear coefficients of the middle linear region, the third-order polynomial coefficients of the left nonlinear region, the third-order polynomial coefficients of the right nonlinear region, as well as the left segment point position, the right segment point position, the middle working point and the end segment boundary.

[0119] S5.2. Under the updated runtime lookup table structure, select one point each from the middle working point and the end boundary in each range to form the minimum proof point set. Reuse the bidirectional four-quadrant scanning process of S2.1 to complete the minimum proof point retest. Calculate the residual index and the reciprocity consistency index and compare them with the minimum proof point judgment threshold and the reciprocity consistency threshold, respectively. When the residual index is less than or equal to the minimum proof point judgment threshold and the reciprocity consistency index is less than or equal to the reciprocity consistency threshold, it indicates that the fitting accuracy and reciprocity consistency of the minimum proof point meet the requirements. Pack the parameter set in the non-volatile register and the runtime lookup table structure version information to generate the final parameter package.

[0120] When any indicator fails to meet the corresponding threshold, locate the range and frequency of the corresponding channel and segment, return to S2.1 to perform a local rescan on the located part, update the channel error spectrum according to S2.2 and S2.3, and then perform calibration in S3 and S4 until the threshold condition is met and the final parameter package is generated.

[0121] It should be noted that the minimum proof point determination threshold is the long-term repetitive statistical data of the chip tester under typical environmental fluctuation conditions after the linearization processing of the segment calibration table and the upper limit of the range linearization residual, which is usually set to 0.005%FS~0.01%FS. In multiple full-range calibration cycles, the measured deviations of the middle segment working point and the end segment boundary point under the same range are calculated, the standard deviation and the maximum deviation of the deviation are calculated, and the 95% confidence upper limit is taken as the threshold baseline. Then, combined with the measurement resolution and ADC quantization step margin, the threshold is obtained. If the threshold is too small, it will cause excessive scanning and false triggering of the callback below the noise floor, affecting the test efficiency. If the value is too large, it will mask the fitting deviation and cause the subsequent predicted reading drift.

[0122] The reciprocity consistency threshold is set based on the statistical upper limit of the channel symmetry error and the reciprocity decoupling residual of the chip tester, which is usually set to 0.01%FS~0.02%FS. The value is obtained by analyzing the forward / backward reading pairs of a large number of samples to obtain the range distribution of the reciprocity error, and decomposing the channel gain difference, phase shift and parasitic impedance asymmetry term. If the value is too strict (such as <0.005%FS), it will be sensitive to small noise or thermal drift error, resulting in false judgment. If the value is too wide (such as >0.05%FS), it may mask the real asymmetry error between channels, affecting the accuracy of reciprocity verification.

[0123] The expression for calculating the residual index is:

[0124] ;

[0125] Among them, The residual index is used to quantify the average normalized deviation of the minimum proof point set. The smaller the value, the more consistent the measured reading and the predicted reading, The number of minimum proof points participating in statistics (positive integer) corresponds to the number of set points being retested, The proof point index, The measured reading of the The predicted reading of the The minimum proof point according to the segment calibration table and the lookup table structure, The measured reading of the The full-scale constant is used to normalize the deviation and eliminate the difference in numerical scale under different ranges;

[0126] The expression for calculating the reciprocity consistency index is:

[0127] ;

[0128] Among them, represents reciprocity consistency index, used to quantify the worst normalized difference between the minimum proof point set in forward / backward measurement, the smaller the value, the better the reciprocity consistency, represents the read count of the th minimum proof point under forward sequencing condition, represents the read count of the th minimum proof point under reverse sequencing condition.

[0129] The embodiment also provides an automatic calibration device of a chip tester, including:

[0130] The reciprocity calibration module establishes a symmetric reciprocity calibration loop through a four-terminal pair closed path through two channels, and performs zero position checking to generate a loop health vector.

[0131] The error decoupling module performs bidirectional four-quadrant sequencing on channel one and channel two based on the loop health vector, and separates the independent errors of the source chain and the measurement chain to form a channel error map.

[0132] The segmented linearization module performs slope standard deviation segmented linearization processing on the channel error map at each range and frequency point to determine the middle linear region and the two end nonlinear regions, and generates a segmented calibration table.

[0133] The guard ring review module takes the segmented calibration table as a baseline at the high resistance node, performs guard ring potential scanning and standard capacitance slope review, determines the leakage minimum guard ring setting, and generates leakage-baseline compensation.

[0134] The parameter solidification module solidifies the segmented calibration table and the leakage-baseline compensation to the register, and performs segmented linear fine tuning to generate a final parameter package.

[0135] The embodiment also provides a computer device suitable for the automatic calibration method of the chip tester, including a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute the computer executable instructions to realize the automatic calibration method of the chip tester as proposed in the above embodiment.

[0136] The computer device can be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is configured to perform wired or wireless communication with an external terminal. The wireless communication can be achieved by WIFI, an operator network, NFC (Near Field Communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0137] The embodiment also provides a storage medium having a computer program stored thereon, the program being executed by a processor to implement the automatic calibration method of the chip tester proposed in the above embodiment; and the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk or an optical disk.

[0138] To sum up, the application establishes a symmetric and reciprocal calibration loop of a four-terminal pair closed path and generates a loop health vector, so that the thermal drift, leakage current, thermoelectric potential and port symmetry of the channel are quantitatively characterized, and real-time health judgment basis is provided for subsequent calibration; by performing bidirectional four-quadrant sequencing under the healthy loop and separating source chain and measurement chain errors, independent error maps of each channel are obtained, and the problem of error term aliasing in traditional calibration is avoided; by using slope standard deviation segmented linearization processing, the range interval is divided into linear and nonlinear partitions, adaptive fitting in different regions is realized, and the precision and stability of the calibration model in a wide range are improved.

[0139] It should be noted that the above examples are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application is described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or equivalently replaced, without departing from the spirit and scope of the technical solutions of the present application, which should be covered in the scope of the claims of the present application.

Claims

1. A method of automatic calibration of a chip tester, characterized by: The method comprises the following steps of: A symmetric and reciprocal calibration loop is established by two channels, and a zero position check is performed to generate a loop health vector; Based on the loop health vector, bidirectional four-quadrant sequencing is performed on the channel one and the channel two, and independent errors of the source chain and the measurement chain are separated to form a channel error atlas; According to the channel error atlas, a slope standard deviation segmented linearization process is performed on each range and frequency point to determine a middle linear region and two end nonlinear regions, and a segmented calibration table is generated; Based on the segmented calibration table, a guard ring potential scanning and a standard capacitance slope rechecking are performed on a high resistance node to determine a leakage minimum guard ring setting, and a leakage-baseline compensation is generated; The segmented calibration table and the leakage-baseline compensation are solidified into a register, and a segmented linear fine adjustment is performed to generate a final parameter package.

2. The method of automatic calibration of a chip tester of claim 1, wherein: The method of establishing the symmetric and reciprocal calibration loop and performing the zero position check comprises the following steps of: A precise resistance and a symmetric RC network are connected in series between the source end and the measurement end of the two channels to form a closed path; Programmable bidirectional solid-state relays are configured at both ends of the closed path to perform source-measurement interchanging and positive-negative connection switching to form a switchable calibration loop; The switchable calibration loop is connected to a guard ring and a reference ground to complete isothermal waiting and time base locking, and a zero position check is performed to obtain a zero position deviation; Based on the zero position deviation, a short scan is triggered, and a symmetric characteristic, a loop parasitic parameter and a thermoelectric potential deviation state of a transfer standard are recorded to generate a loop health vector.

3. The method of automatic calibration of a chip tester of claim 1, wherein: The method of performing bidirectional four-quadrant sequencing on the channel one and the channel two comprises the following steps of: A measurement point sequence is selected according to the loop health vector, and a forward scan is performed under a positive connection condition with the channel one as the source chain and the channel two as the measurement chain to obtain a first group of readings; The polarity is kept unchanged, the channel two is switched as the source chain and the channel one is switched as the measurement chain, a forward scan is performed to obtain a second group of readings; The role is kept unchanged, and a reverse scan is performed by reversing the polarity to obtain a third group of readings; A reverse scan is additionally performed under opposite polarity and opposite role conditions to obtain a fourth group of readings, and the four groups of readings are combined to form a four-quadrant original reading set.

4. The method of automatic calibration of a chip tester of claim 1, wherein: The method of separating the independent errors of the source chain and the measurement chain comprises the following steps of: Summation and difference of four readings of the same measurement point in the four-quadrant original reading set are performed to obtain polarity-related components and role-related components; According to the polarity-related components and the role-related components, a measurement chain zero point bias, an excitation chain gain and a linear term are determined to obtain an error vector of each channel; The error vectors of each measurement point are collected according to the range and the frequency point, and phase and group delay initial values are supplemented to form a channel error atlas.

5. The method of automatic calibration of a chip tester of claim 1, wherein: The method of performing a slope standard deviation segmented linearization process comprises the following steps of: Based on the channel error atlas, an equidistant set point sequence is generated at each range and each frequency point, and an adjacent point slope sequence is calculated; Standard deviation peaks are found in the left and right half regions of the adjacent point slope sequence to determine left and right segmentation points, and a middle linear region and two end nonlinear regions are obtained; Linear coefficients of the middle linear region and polynomial coefficients of the two end nonlinear regions are extracted, and correction is performed at the segmentation point positions to generate a segmented coefficient set.

6. The method of automatic calibration of a chip tester of claim 1, wherein: The segment type calibration table is a look-up table structure indexed by channel, range and frequency point in the segment coefficient set, recording the applicable range and middle segment working point and end segment boundary, and written into the register address.

7. The method of automatic calibration of a chip tester of claim 1, wherein: The execution of the guard ring potential scanning and the standard capacitance slope review includes the following specific steps, The range and working point of the high resistance measurement are set according to the segment type calibration table, and the guard ring potential is changed to obtain a leakage current curve; The leakage minimum guard ring setting is determined according to the leakage current curve; The leakage minimum guard ring setting is maintained, the high resistance node is connected to the standard transfer capacitance, a linear slope is applied to obtain a review reading, the low current segment coefficient in the segment type calibration table is closed loop fine tuned, and the leakage-baseline compensation is generated.

8. The method of automatic calibration of a chip tester of claim 1, wherein: The closed loop fine tuning of the low current segment coefficient in the segment type calibration table refers to that under the condition of maintaining the leakage minimum guard ring setting, the review reading is subtracted from the predicted reading of the segment type calibration table at the same measurement point to obtain a closed loop error signal, the zero point term, the gain term and the end segment connection term coefficient of the low current segment are automatically adjusted, and are written back to the corresponding register.

9. The method of automatic calibration of a chip tester of claim 1, wherein: The segment type calibration table and the leakage-baseline compensation are solidified to the register, and the segmented linear fine tuning is performed, including the following specific steps, The segment type calibration table and the leakage-baseline compensation are merged into a parameter set and written into a non-volatile register; The parameter set is called through the look-up table structure at runtime, the corresponding segmented linear fine tuning term is selected according to the interval value of temperature, humidity and power-on time, the look-up table structure at runtime is updated, and the final parameter package is generated.

10. An apparatus for automatically calibrating a chip tester, based on the method for automatically calibrating a chip tester according to any one of claims 1 to 9, characterized by: It includes, The reciprocity calibration module surrounds the symmetric reciprocity calibration loop by the two-way channel to form a four-terminal pair closed path, performs zero position check, and generates a loop health vector; The error decoupling module performs bidirectional four-quadrant sequencing on channel one and channel two based on the loop health vector, and separates the independent errors of the source chain and the measurement chain to form a channel error map; The segmented linearization module performs slope standard deviation segmented linearization processing on the channel error map at each range and frequency point to determine the middle segment linear region and the two end nonlinear regions, and generates a segment type calibration table; The guard ring review module takes the segment type calibration table as the baseline at the high resistance node to perform guard ring potential scanning and standard capacitance slope review, determines the leakage minimum guard ring setting, and generates leakage-baseline compensation; The parameter solidification module solidifies the segment type calibration table and the leakage-baseline compensation to the register, and performs segmented linear fine tuning to generate the final parameter package. The parameter solidification module solidifies the segment type calibration table and the leakage-baseline compensation to the register, and performs segmented linear fine tuning to generate the final parameter package.

Images