Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a plurality of pixel areas arranged in the first direction and the second direction, and the first direction intersects with the second direction. The display panel further comprises a plurality of scanning line groups and a plurality of common signal lines; the plurality of scanning line groups are arranged along the second direction, each scanning line group comprises at least two scanning lines arranged along the second direction, and the scanning lines extend along the first direction; the common signal lines extend along a first direction, and the plurality of common signal lines are arranged along a second direction; wherein a scanning line group and two common signal lines are arranged between every two adjacent pixel areas in the second direction, and the two common signal lines are located on the two sides, away from each other, of the scanning line group in the second direction respectively; according to the display panel, the common signal lines can shield signal crosstalk of the scanning lines to the pixel areas, one scanning line group comprises at least two scanning lines, the number of the common signal lines can be reduced, the occupied space of the common signal lines is reduced, and the aperture opening ratio of the display panel is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The liquid crystal display panel is generally made by bonding an array substrate and a counter substrate, filling liquid crystal between the two array substrates and the counter substrate, and setting pixel electrodes and common electrodes on at least one of the array substrate and the counter substrate, so as to drive the liquid crystal molecules to rotate by the electric field between the pixel electrodes and the common electrodes, and then cooperate with the light emitted by the backlight module to display images.

[0003] The array substrate is formed with a plurality of sub-pixel areas by a plurality of scanning lines and a plurality of data lines. The scanning lines and the data lines are used to connect thin film transistors in the sub-pixel areas to control the transmission of signals. However, the scanning lines cause signal crosstalk to the pixel electrodes in the sub-pixel areas, thereby affecting the display effect of the liquid crystal display panel. SUMMARY

[0004] The display panel and the display device provided by the embodiments of the present application can reduce the signal crosstalk of the scanning lines to the pixel areas, reduce the occupied space of the common signal lines, and improve the aperture ratio of the display panel.

[0005] The display panel provided by the embodiments of the present application comprises a plurality of pixel areas arranged along a first direction and a second direction, and the first direction intersects the second direction. The display panel further comprises: a plurality of scanning line groups arranged along the second direction, wherein each scanning line group comprises at least two scanning lines arranged along the second direction, and the scanning lines extend along the first direction; a plurality of common signal lines extending along the first direction, and the common signal lines are arranged along the second direction; wherein one scanning line group and two common signal lines are arranged between two adjacent pixel areas along the second direction, and the two common signal lines are respectively located on two sides of the scanning line group along the second direction.

[0006] In an embodiment of the present application, the pixel area comprises a plurality of sub-pixel areas, and the display panel further comprises: a plurality of data lines, wherein the data lines are arranged along the first direction, the data lines extend along the second direction, and at least one data line is arranged between two adjacent sub-pixel areas along the first direction.

[0007] In an embodiment of the present application, the pixel region comprises four sub-pixel regions, and the four sub-pixel regions are arranged as two in the first direction and as two in the second direction. In the same pixel region, two sub-pixel regions arranged in the second direction are arranged between two adjacent data lines.

[0008] In an embodiment of the present application, the display panel further comprises a pixel electrode and a thin film transistor arranged in the sub-pixel region, and the thin film transistor is connected to the scan line, the data line and the pixel electrode. Two scan lines in the same scan line group are connected to the thin film transistors in two adjacent pixel regions in the second direction.

[0009] In an embodiment of the present application, in the same pixel region, the thin film transistors in two sub-pixel regions arranged in the first direction are connected to the same scan line, and the thin film transistors in two sub-pixel regions arranged in the second direction are connected to different scan lines.

[0010] In an embodiment of the present application, in the same pixel region, the thin film transistors in two sub-pixel regions arranged in the first direction are respectively connected to two adjacent data lines, and the thin film transistors in two sub-pixel regions arranged in the second direction are respectively connected to two adjacent data lines.

[0011] In an embodiment of the present application, in the same pixel region, the maximum length of the pixel electrode in each sub-pixel region in the first direction is equal. And / or, in the same pixel region, the maximum length of the pixel electrode in each sub-pixel region in the second direction is equal.

[0012] In an embodiment of the present application, the display panel comprises: A first conductive layer comprising the scan line and the common signal line; An electrode layer arranged on one side of the first conductive layer and comprising the pixel electrode and the common electrode arranged at intervals; The common electrode comprises a first common main part and a second common main part, the first common main part extends in the second direction and is located between adjacent pixel regions in the first direction, the second common main part extends in the first direction and is located between adjacent sub-pixel regions in the second direction, and the second common main part is located between adjacent scan groups in the second direction, and the first common main part and the second common main part are connected to form a grid shape.

[0013] In an embodiment of the present application, the common electrode further comprises a first adapter part, the first adapter part is connected between the first common body part and the second common body part, and the first adapter part is electrically connected to the common signal line.

[0014] In an embodiment of the present application, a width of the first adapter part along the first direction is greater than a width of the first body part along the first direction. And / or, a width of the first adapter part along the second direction is greater than a width of the second body part along the second direction.

[0015] In an embodiment of the present application, the pixel electrode comprises a pixel body part and a plurality of pixel branch parts, the pixel body part extends along the first direction, the plurality of pixel branch parts are arranged in the sub-pixel area along the first direction at intervals, one end of each of the pixel branch parts is connected to the pixel body part, and the other end of each of the pixel branch parts extends along the second direction. The common electrode further comprises a plurality of common branch parts, the plurality of common branch parts are arranged in the sub-pixel area along the first direction at intervals, one end of each of the common branch parts is connected to the second common body part, and the other end of each of the common branch parts extends along the second direction. In the sub-pixel area, the plurality of pixel branch parts and the plurality of common branch parts are arranged alternately along the first direction.

[0016] In an embodiment of the present application, one of the data lines is arranged between two of the sub-pixel areas along the first direction, and the potential signals loaded on the two adjacent data lines along the first direction have opposite polarities.

[0017] In an embodiment of the present application, the display panel further comprises a color filter layer, the color filter layer comprises a plurality of color resistance blocks and a light transmission part arranged in the pixel area at least. In the same pixel area, the color resistance blocks are arranged in part of the sub-pixel areas, the color resistance blocks in different sub-pixel areas have different colors, and the light transmission part is arranged in another part of the sub-pixel areas.

[0018] In an embodiment of the present application, the display panel further comprises a pixel electrode and a thin film transistor arranged in the sub-pixel area, and the thin film transistor is connected to the scan line, the data line and the pixel electrode. The display panel further comprises: A second conductive layer comprising a source electrode and a drain electrode of the thin film transistor. an electrode layer disposed on one side of the second conductive layer and comprising the pixel electrode; The color film layer is disposed between the second conductive layer and the electrode layer.

[0019] In an embodiment of the present application, the color film layer comprises at least two color resistance blocks stacked on the side of the thin film transistor close to the electrode layer, and the colors of the at least two color resistance blocks are different from each other.

[0020] According to the above-mentioned purposes of the present application, the embodiments of the present application further provide a display device comprising a backlight module and the display panel as described above.

[0021] The present application provides a display panel and a display device. At least two scanning lines are combined into a scanning line group, and the scanning line group is disposed between adjacent pixel regions in a second direction. The opposite sides of the scanning line group are respectively provided with a common signal line, so that the scanning line group and the pixel region are separated by the common signal line. On the one hand, the common signal line can shield the signal crosstalk of the scanning line to the pixel region. On the other hand, the scanning line group contains at least two scanning lines, so that the common signal line does not need to be arranged on the opposite sides of each scanning line, the number of common signal lines can be saved, the occupied space of the common signal lines can be reduced, and the aperture ratio of the display panel can be improved.

[0022] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0023] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0024] Figure 1 A film layer stack diagram of the display panel provided by the embodiments of the present application; Figure 2 A planar distribution schematic diagram of the display panel provided by the embodiments of the present application; Figure 3 A cross-sectional structure schematic diagram of the display panel provided by the embodiments of the present application; Figure 4 A film layer structure diagram of the first conductive layer provided by the embodiments of the present application; Figure 5A film layer structure diagram of the second conductive layer provided by the embodiment of the present application; Figure 6 A film layer stacking diagram of the first conductive layer and the second conductive layer provided by the embodiment of the present application; Figure 7 A structure schematic diagram of the electrode layer provided by the embodiment of the present application; Figure 8 A film layer structure diagram of the semiconductor layer provided by the embodiment of the present application; Figure 9 A film layer stacking diagram of the first conductive layer, the second conductive layer, the electrode layer and the semiconductor layer provided by the embodiment of the present application; Figure 10 A sub-pixel area distribution schematic diagram of the display panel provided by the embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.

[0026] Please refer to Figure 1 The embodiment of the present application provides a display panel, which comprises a plurality of pixel areas 101 arranged along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect.

[0027] The display panel further comprises a plurality of scan line groups 11 and a plurality of common signal lines 12; the plurality of scan line groups 11 are arranged along the second direction Y, and each scan line group 11 comprises at least two scan lines 111 arranged along the second direction Y, and the scan lines 111 extend along the first direction X; the plurality of common signal lines 12 extend along the first direction X, and the plurality of common signal lines 12 are arranged along the second direction Y.

[0028] Among them, one scan line group 11 and two common signal lines 12 are arranged between two adjacent pixel areas 101 along the second direction Y, and the two common signal lines 12 are respectively located on the two sides of the scan line group 11 along the second direction Y and away from each other.

[0029] In the application process, the embodiment of the present application synthesizes at least two scan lines 111 into a scan line group 11, and sets the scan line group 11 between adjacent pixel regions 101 along the second direction Y; and the opposite sides of the scan line group 11 are respectively provided with a common signal line 12, so that the scan line group 11 is spaced apart from the pixel region 101 by the common signal line 12; on the one hand, the common signal line 12 can shield the signal crosstalk of the scan line 111 to the pixel region 101, and on the other hand, one scan line group 11 contains at least two scan lines 111, so that it is not necessary to set the common signal line 12 on the opposite sides of each scan line 111, the number of common signal lines 12 can be saved, the occupied space of the common signal line 12 is reduced, and the aperture ratio of the display panel is improved.

[0030] Specifically, please refer to Figure 1 and Figure 2 , the display panel includes a display area AA and a non-display area NA adjacent to the display area AA; wherein the non-display area NA can be arranged around the display area AA, and the non-display area NA can be a frame area in the display panel.

[0031] The display panel further includes a gate drive circuit 13, a source drive circuit 14, a plurality of scan lines 111 and a plurality of data lines 21 arranged in the non-display area NA, wherein the plurality of scan lines 111 are arranged along the second direction Y, the scan lines 111 extend along the first direction X, and the first direction X and the second direction Y intersect; the plurality of data lines 21 are arranged along the first direction X, and the data lines 21 extend along the second direction Y.

[0032] In some embodiments, the first direction X and the second direction Y are perpendicular.

[0033] Further, both ends of each scan line 111 are connected to the gate drive circuit 13, and the scan signal can be transmitted to each scan line 111 through the gate drive circuit 13; at least one end of each data line 21 is connected to the source drive circuit 14, and the data signal can be transmitted to each data line 21 through the source drive circuit 14.

[0034] The plurality of scan lines 111 and the plurality of data lines 21 are staggered to enclose a plurality of sub-pixel regions 1011, and the data signal in the data line 21 is input into the preset sub-pixel region 1011 through the control of the scan signal in the scan line 111.

[0035] In the embodiment of the present application, the plurality of scan lines 111 are divided into a plurality of scan line groups 11 arranged along the second direction Y, and each scan line group 11 includes at least two scan lines 111 arranged along the second direction Y, and the scan lines 111 extend along the first direction X; the common signal lines 12 extend along the first direction X, and the plurality of common signal lines 12 are arranged along the second direction Y. Among them, one scan line group 11 and two common signal lines 12 are arranged between two adjacent pixel areas 101 along the second direction Y, and the two common signal lines 12 are respectively located on the two sides of the scan line group 11 away from each other along the second direction Y; therefore, in the embodiment of the present application, at least two scan lines 111 are combined into one scan line group 11, and are arranged between the adjacent pixel areas 101 along the second direction Y; and one common signal line 12 is arranged on the opposite sides of the scan line group 11, so that the scan line group 11 is separated from the pixel area 101 by the common signal line 12; on the one hand, the common signal line 12 can shield the signal crosstalk of the scan line 111 to the pixel area 101, and on the other hand, one scan line group 11 contains at least two scan lines 111, so that it is not necessary to arrange a common signal line 12 on the opposite sides of each scan line 111, thereby saving the number of common signal lines 12, reducing the occupied space of the common signal lines 12, and improving the aperture ratio of the display panel.

[0036] It should be noted that the display area AA of the display panel can include a plurality of pixel areas 101 arranged along the first direction X and the second direction Y, and each pixel area 101 can be composed of a plurality of sub-pixel areas 1011; the light-emitting colors of the sub-pixel areas 1011 in each pixel area 101 are different from each other, and the number and arrangement of the sub-pixel areas 1011 in the plurality of pixel areas 101 are the same, that is, the pixel area 101 can be the smallest repeating unit in the display area AA.

[0037] Further, the film layer structure of the display panel is described in detail below.

[0038] The display panel provided by the embodiment of the present application includes a substrate 61, a first conductive layer 10 arranged on the substrate 61, a first insulating layer 62 arranged on the substrate 61 and covering the first conductive layer 10, a semiconductor layer 50 arranged on the first insulating layer 62, a second conductive layer 20 arranged on the semiconductor layer 50, a second insulating layer 63 covering the second conductive layer 20 and the semiconductor layer 50, a color film layer 40 arranged on the second insulating layer 63, a third insulating layer 64 arranged on the color film layer 40, and an electrode layer 30 arranged on the third insulating layer 64.

[0039] The first conductive layer 10 can include a plurality of scanning lines 111 and a plurality of common signal lines 12; the semiconductor layer 50 can include an active part 51; the second conductive layer 20 can include a plurality of data lines 21, a source electrode 22 and a drain electrode 23; and the electrode layer 30 can include a plurality of pixel electrodes 31 and a common electrode 32.

[0040] It can be understood that the scanning lines 111 are multiplexed as gate electrodes in the portions overlapping the active part 51 along the thickness direction of the display panel, and the active part 51, the gate electrode, the source electrode 22 and the drain electrode 23 constitute a thin film transistor.

[0041] In some embodiments, the display panel can include the pixel electrode 31 and the thin film transistor arranged in each sub-pixel region 1011; the plurality of sub-pixel regions 1011 are arranged in an array along a first direction X and a second direction Y, the gate electrode of the thin film transistor can be connected to the corresponding scanning line 111, the source electrode 22 of the thin film transistor can be connected to the corresponding data line 21, and the drain electrode 23 of the thin film transistor can be connected to the pixel electrode 31 in the same sub-pixel region 1011. The on-off of the thin film transistor is controlled by the scanning signal in the scanning line 111, so as to input the data signal in the data line 21 to the pixel electrode 31 in the corresponding sub-pixel region 1011, and an electric field is formed between the common electrode 32 and the pixel electrode 31. The substrate 61 and the above-mentioned film layers on the substrate 61 can constitute an array substrate in the display panel.

[0042] The source electrode 22 and the drain electrode 23 are only two signal transmission ends of the thin film transistor, which are only distinguished in naming and can be exchanged, and are not specifically limited herein.

[0043] In some embodiments, the display panel further includes a counter substrate arranged on the side of the electrode layer 30 away from the substrate 61 and a liquid crystal layer arranged between the electrode layer 30 and the counter substrate. The electric field formed between the common electrode 32 and the pixel electrode 31 can be used to control the deflection of liquid crystal molecules in the liquid crystal layer. The potential signal on the pixel electrode 31 in each sub-pixel region 1011 can be controlled to regulate whether light passes through or how much light passes through in each sub-pixel region 1011, so as to realize the display function of the display panel.

[0044] In some embodiments, the plurality of data lines 21 are arranged along the first direction X, the data lines 21 extend along the second direction Y, and at least one data line 21 is arranged between two adjacent sub-pixel areas 1011 along the first direction X; further, one data line 21 is arranged between two adjacent sub-pixel areas 1011 along the first direction X, that is, each sub-pixel area 1011 is provided with a data line 21 on each side thereof along the first direction X, and the potential signals loaded on two adjacent data lines 21 along the first direction X have opposite polarities; since the signals in the data lines 21 will interfere with the signals of the pixel electrodes 31 in the adjacent sub-pixel areas 1011, and then the data lines 21 will generate parasitic capacitance with the adjacent pixel electrodes 31, however, when the polarities of the potentials in the data lines 21 on both sides of a sub-pixel area 1011 are opposite, the coupling effects of the two data lines 21 on the parasitic capacitance can be offset, and then the signal interference of the data lines 21 on the adjacent pixel electrodes 31 can be reduced.

[0045] In some embodiments, the material of the electrode layer 30 can be selected from transparent conductive materials, for example, can be selected from Indium Tin Oxide (ITO).

[0046] In some embodiments, the color filter layer 40 is arranged between the second conductive layer 20 and the electrode layer 30, and can be reused as an insulating spacing layer between the second conductive layer 20 and the electrode layer 30, the embodiments of the present application can composite the second conductive layer 20 in the array substrate of the display panel, so as to reduce the thickness of the display panel, save the process, and reduce the cost.

[0047] In some embodiments, the color filter layer 40 can include a plurality of color resistance blocks 41, and the plurality of color resistance blocks 41 can be distributed in each sub-pixel area 1011; specifically, each sub-pixel area 1011 is distributed with one color resistance block 41 which at least partially overlaps with the pixel electrode 31 along the thickness direction of the display panel, and the color resistance blocks 41 overlapping with the pixel electrode 31 in each sub-pixel area 1011 in the same pixel area 101 are different in color; for example, the color resistance blocks 41 corresponding to the plurality of pixel electrodes 31 in the same pixel area 101 can include a combination of at least two of red color resistance blocks, green color resistance blocks, blue color resistance blocks, and yellow color resistance blocks.

[0048] Further, the color filter layer 40 further includes at least two color resistance blocks 41 located in each sub-pixel area 1011 and stacked on the side of the thin film transistor close to the electrode layer 30, and the colors of the at least two color resistance blocks 41 are different from each other, thereby playing a role of shading the thin film transistor to reduce light reflection. Therefore, in the embodiment of the present application, the color filter layer 40 is integrated above the second conductive layer 20, and the at least two color resistance blocks 41 with different colors in the color filter layer 40 are stacked to form a shading part to cover the thin film transistor, so that the preparation of the black matrix can be reduced, thereby further reducing the thickness of the display panel, saving the process procedure, and reducing the process cost.

[0049] In the embodiment of the present application, each pixel area 101 can include four sub-pixel areas 1011, and the four sub-pixel areas 1011 can be arranged in an array along the first direction X and the second direction Y, that is, the four sub-pixel areas 1011 can be arranged in two rows and two columns along the first direction X and the second direction Y. The four sub-pixel areas are arranged in two along the first direction X and in two along the second direction Y.

[0050] In some embodiments, in the same pixel area 101, two sub-pixel areas 1011 arranged along the second direction Y are arranged between two adjacent data lines 21, and a plurality of pixel areas 101 arranged along the first direction X are arranged between two adjacent scan line groups 11.

[0051] In some embodiments, in the same pixel area 101, the areas of the sub-pixel areas 1011 are the same, and each sub-pixel area 1011 can be a square, thereby making the optical performance of each sub-pixel area 1011 consistent, which is convenient for optical design.

[0052] Further, the areas and shapes of the sub-pixel areas 1011 are the same between different pixel areas 101.

[0053] Correspondingly, in the same pixel area 101, the maximum lengths of the pixel electrodes 31 in each sub-pixel area 1011 along the first direction X are equal; and / or, in the same pixel area 101, the maximum lengths of the pixel electrodes 31 in each sub-pixel area 1011 along the second direction Y are equal; so that the areas and shapes of the pixel electrodes 31 in each sub-pixel area 1011 in the same pixel area 101 are consistent, thereby making the optical performance of each sub-pixel area 1011 consistent, which is convenient for optical design.

[0054] In some embodiments, in the same pixel area 101, the color filter layer 40 can further include a light transmission part 42, and the light transmission part 42 can be made of transparent material, for example, transparent resin material, so that the light directly transmits through the light transmission part 42 without filtering effect, thereby making the light passing through the light transmission part 42 white light.

[0055] In some embodiments, in the same pixel region 101, color resistance blocks 41 are arranged in a part of the sub-pixel regions 1011, the color resistance blocks in different sub-pixel regions 1011 are of different colors, and a light-transmitting part 42 is arranged in another part of the sub-pixel regions 1011. Color display and color gamut regulation are realized through the sub-pixel regions 1011 with the color resistance blocks 41, and white light display is realized through the sub-pixel regions 1011 with the light-transmitting part 42, which has a greater light transmittance, can improve the brightness and aperture ratio of the display panel, and can further make the area of each sub-pixel region 1011 smaller, so that more sub-pixel regions 1011 can be arranged in the display panel to improve the resolution of the display panel.

[0056] For example, in one pixel region 101, four sub-pixel regions 1011 can be arranged in two rows and two columns, and red, green and blue color resistance blocks are arranged in three sub-pixel regions 1011 respectively, and a light-transmitting part 42 is arranged in the remaining one sub-pixel region 1011 to form a WRGB sub-pixel in the pixel region 101, so as to improve the brightness of the display panel and reduce the power consumption of the display panel.

[0057] The specific structure of each film layer in the display panel provided in the embodiments of the present application will be described below.

[0058] Please refer to Figure 1 and Figure 4 The first conductive layer 10 includes a plurality of scan line groups 11 arranged along the second direction Y and a plurality of common signal lines 12 arranged along the second direction Y; each scan line group 11 includes at least two scan lines 111 arranged along the second direction Y, and the scan lines 111 extend along the first direction X; the common signal lines 12 extend along the first direction X.

[0059] Further, a row of pixel regions 101 arranged along the first direction X is arranged between two adjacent scan line groups 11, that is, the pixel regions 101 are arranged on opposite sides of the scan line groups 11 along the second direction Y.

[0060] In the embodiment of the present application, one scan line group 11 and two common signal lines 12 are arranged between two adjacent pixel regions 101 along the second direction Y, and the two common signal lines 12 are respectively located on the two sides of the scan line group 11 away from each other along the second direction Y. Therefore, in the embodiment of the present application, at least two scan lines 111 are combined into one scan line group 11 and arranged between the adjacent pixel regions 101 along the second direction Y, and one common signal line 12 is arranged on each of the two opposite sides of the scan line group 11, so that the common signal line 12 is arranged between the scan line group 11 and the pixel region 101. On the one hand, the common signal line 12 can shield the signal crosstalk of the scan line 111 to the pixel region 101, and on the other hand, one scan line group 11 contains at least two scan lines 111, so that the common signal line 12 does not need to be arranged on the two opposite sides of each scan line 111, thereby saving the number of common signal lines 12, reducing the occupied space of the common signal line 12, and improving the aperture ratio of the display panel.

[0061] In some embodiments, the first conductive layer 10 further includes a common auxiliary line 121 and a connecting part 122, and the common auxiliary line 121 is connected between the common signal line 12 and the connecting part 122. The common auxiliary line 121 extends along the second direction Y and is arranged on the two opposite sides of each sub-pixel region 1011 along the first direction X. In addition, the two common auxiliary lines 121 form a group, and one group of common auxiliary lines 121 is located between two adjacent sub-pixel regions 1011 along the first direction X. The connecting part 122 is located in at least one sub-pixel region 1011, that is, one end of the connecting part 122 is connected to the common auxiliary line 121, and the other end of the connecting part 122 extends towards the adjacent sub-pixel region 1011. For example, the connecting part 122 can be located in two sub-pixel regions 1011 arranged along the second direction Y.

[0062] Please refer to Figure 1 , Figure 3 and Figure 5 , the second conductive layer 20 includes a plurality of data lines 21 arranged along the first direction X, and the data lines 21 extend along the second direction Y. The data lines 21 can be located between two adjacent columns of sub-pixel regions 1011 along the first direction X.

[0063] Further, the second conductive layer 20 can further include a source 22 and a drain 23, and the source 22 is connected to the data line 21, and the drain 23 is arranged apart from the source 22 and can be connected to the two opposite sides of the channel of the active part 51.

[0064] In some embodiments, one end of the source electrode 22 is connected to the data line 21 in two arc-shaped branches, and the other end of the source electrode 22 is arc-shaped and spaced apart from the drain electrode 23; and the one end of the source electrode 22 in two arc-shaped branches can increase the connection area of the source electrode 22 and the data line 21, and on the other hand, can reduce the light shielding area of the source electrode 22, thereby improving the aperture ratio of the display panel.

[0065] Please refer to Figure 1 , Figure 3 , Figure 4 , Figure 5 and Figure 6 , the spacing area between the source electrode 22 and the drain electrode 23 can be located above the scan line 111, that is, the channel portion of the active part 51 is located above the scan line 111, and the channel portion of the active part 51 is formed by the scan signal in the scan line 111 to form a path, so that the data signal in the data line 21 can be transmitted to the sub-pixel area 1011 through the source electrode 22 and the drain electrode 23.

[0066] In some embodiments, the orthographic projection of the data line 21 on the substrate 61 is located between the orthographic projection of a group of common auxiliary lines 121 on the substrate 61, and the group of common auxiliary lines 121 can play a signal shielding role for the data line 21 located in the middle.

[0067] In some embodiments, the area of the common signal line 12 is increased at the position overlapping the drain electrode 23 along the thickness direction of the display panel, so that more parts of the drain electrode 23 overlap the common signal line 12, thereby improving the effect of shielding signal crosstalk.

[0068] Please refer to Figure 1 , Figure 4 and Figure 7 , the electrode layer 30 includes a plurality of pixel electrodes 31 and a common electrode 32, and the pixel electrodes 31 and the common electrode 32 are spaced apart, and the plurality of pixel electrodes 31 are correspondingly arranged in the plurality of sub-pixel areas 1011, and further, the plurality of pixel electrodes 31 and the plurality of sub-pixel areas 1011 are one-to-one correspondingly arranged.

[0069] Each of the pixel electrodes 31 comprises a pixel main body 311, a plurality of pixel branch parts 312 and a second adapter part 313. The pixel main body 311 extends along the first direction X. The second adapter part 313 and the pixel branch parts 312 are respectively located on opposite sides of the pixel main body 311 along the second direction Y. The second adapter part 313 is located on the side of the pixel main body 311 close to the thin film transistor in the same sub-pixel area 1011, and is used to be connected with the drain 23 of the thin film transistor. The pixel branch parts 312 are arranged in the sub-pixel area 1011 along the first direction X. One end of each of the pixel branch parts 312 is connected with the pixel main body 311. The other end of each of the pixel branch parts 312 extends along the second direction Y away from the pixel main body 311 connected therewith, i.e. extends along the second direction Y. The adjacent pixel branch parts 312 are arranged with a spacing therebetween.

[0070] The common electrode 32 comprises a first common main body 321, a second common main body 322, a common branch part 323 and a first adapter part 324. The first common main body 321 extends along the second direction Y and is located between two adjacent sub-pixel areas 1011 along the first direction X. The second common main body 322 extends along the first direction X and is connected with the first common main body 321. The second common main body 322 is located between two adjacent sub-pixel areas 1011 along the second direction Y. Further, the second common main body 322 is located between two adjacent scan line groups 11 along the second direction Y. The second common main body 322 and the first common main body 321 are connected to form a grid shape. One end of each of the common branch parts 323 is connected with the second common main body 322. The other end of each of the common branch parts 323 extends away from the side of the second common main body 322 connected therewith, i.e. extends along the second direction Y. The adjacent common branch parts 323 are arranged with a spacing therebetween.

[0071] In the same sub-pixel area 1011, the pixel branch parts 312 and the common branch parts 323 are alternately arranged along the first direction X. One common branch part 323 is arranged between two adjacent pixel branch parts 312, and / or one pixel branch part 312 is arranged between two adjacent common branch parts 323. When the pixel electrode 31 and the common electrode 32 are loaded with voltages, a horizontal electric field can be formed between the pixel electrode 31 and the common electrode 32 to control the deflection of the liquid crystal molecules in the liquid crystal layer.

[0072] Each of the sub-pixel areas 1011 can be formed by the first common main body 321, the second common main body 322 and the pixel main body 311.

[0073] In some embodiments, the first adapter 324 is connected between the first common body 321 and the second common body 322, and the first adapter 324 at least partially overlaps the connecting portion 122 in the thickness direction of the display panel; the display panel further comprises a contact hole 301, the first adapter 324 is connected with the connecting portion 122 through the contact hole 301, and the first adapter 324 is connected with the common signal line 12; that is, the common electrode 32 is connected with the common signal line 12 through the contact hole 301, thereby effectively reducing the impedance of the common electrode 32; and the contact hole 301 is located in the at least one sub-pixel area 1011.

[0074] In some embodiments, the width of the first adapter 324 in the first direction X is greater than the width of the first common body 321 in the first direction X; and / or, the width of the first adapter 324 in the second direction Y is greater than the width of the second common body 322 in the second direction Y; that is, the area of the common electrode 32 at the first adapter 324 is increased, thereby increasing the contact area between the common electrode 32 and the common signal line 12, and further reducing the impedance of the common electrode 32.

[0075] Correspondingly, the contact hole 301 passes through the pixel electrode 31 in the at least one sub-pixel area 1011, and the area of the pixel electrode 31 in the sub-pixel area 1011 where the contact hole 301 is formed is smaller than the area of the pixel electrode 31 in the sub-pixel area 1011 where the contact hole 301 is not formed.

[0076] Please refer to Figure 1 , Figure 4 , Figure 8 and Figure 9 , the semiconductor layer 50 is arranged between the first conductive layer 10 and the second conductive layer 20, and the semiconductor layer 50 comprises an active part 51, and the source electrode 22 and the drain electrode 23 are located on the side of the active part 51 away from the substrate 61, and the active part 51 is formed with a channel in the interval region corresponding to the source electrode 22 and the drain electrode 23; the active part 51 further partially overlaps the scan line 111 in the thickness direction of the display panel, thereby enabling the channel of the active part 51 to form a path under the control of the scan signal on the scan line 111, enabling the source electrode 22 and the drain electrode 23 to be conductive, and realizing signal transmission.

[0077] Further, the connection mode of the sub-pixel area 1011 and each signal line in the display panel is described below.

[0078] Please refer to Figure 1 and Figure 10 , the two scan lines 111 in the same scan line group 11 are connected to the thin film transistors in the two adjacent pixel areas 101 in the second direction Y.

[0079] Further, in some embodiments, within the same pixel region 101, the thin film transistors in the two sub-pixel regions 1011 arranged along the first direction X are connected to the same scan line 111, the thin film transistors in the two sub-pixel regions 1011 arranged along the second direction Y are connected to different scan lines 111, and the thin film transistors in the two sub-pixel regions 1011 arranged along the second direction Y are connected to two scan lines 111 in two adjacent scan line groups 11, that is, the plurality of pixel regions 101 arranged along the first direction X contains two rows of sub-pixel regions 1011, and two scan line groups 11 are arranged on the two sides away from each other of the two rows of sub-pixel regions 1011, one row of sub-pixel regions 1011 is connected to one scan line 111 in one of the two scan line groups 11, and the other row of sub-pixel regions 1011 is connected to one scan line 111 in the other of the two scan line groups 11; thus, one scan line 111 can drive one row of sub-pixel regions 1011, and one scan line group 11 can drive two rows of sub-pixel regions 1011, and thus, compared with the related art in which at least two scan lines are used to drive one row of sub-pixel regions, the on time of the scan line 111 is longer, and the charging rate is higher.

[0080] In some embodiments, within the same pixel region 101, the thin film transistors in the two sub-pixel regions 1011 arranged along the first direction X are connected to the same scan line 111, the thin film transistors in the two sub-pixel regions 1011 arranged along the second direction Y are connected to different scan lines 111, and the thin film transistors in the two sub-pixel regions 1011 arranged along the second direction Y are connected to two scan lines 111 in two adjacent scan line groups 11, that is, the plurality of pixel regions 101 arranged along the first direction X contains two rows of sub-pixel regions 1011, and two scan line groups 11 are arranged on the two sides away from each other of the two rows of sub-pixel regions 1011, one row of sub-pixel regions 1011 is connected to one scan line 111 in one of the two scan line groups 11, and the other row of sub-pixel regions 1011 is connected to one scan line 111 in the other of the two scan line groups 11; thus, one scan line 111 can drive one row of sub-pixel regions 1011, and one scan line group 11 can drive two rows of sub-pixel regions 1011, and thus, compared with the related art in which at least two scan lines are used to drive one row of sub-pixel regions, the on time of the scan line 111 is longer, and the charging rate is higher.

[0081] In addition, the plurality of pixel regions 101 arranged along the first direction X contains two rows of sub-pixel regions 1011, one row of sub-pixel regions 1011 is connected to the data line 21 on the left side thereof, and the other row of sub-pixel regions 1011 is connected to the data line 21 on the right side thereof; further, the plurality of sub-pixel regions 1011 arranged along the second direction Y, the odd-numbered rows of sub-pixel regions 1011 are connected to the left side data line 21, and the even-numbered rows of sub-pixel regions 1011 are connected to the right side data line 21; or the even-numbered rows of sub-pixel regions 1011 are connected to the left side data line 21, and the odd-numbered rows of sub-pixel regions 1011 are connected to the right side data line 21 In summary, the embodiment of the present application synthesizes at least two scan lines 111 into a scan line group 11, which is arranged between adjacent pixel regions 101 along the second direction Y. The opposite sides of the scan line group 11 are respectively provided with a common signal line 12, so that the scan line group 11 is spaced apart from the pixel region 101 by the common signal line 12. On the one hand, the common signal line 12 can shield the signal crosstalk of the scan line 111 to the pixel region 101. On the other hand, one scan line group 11 contains at least two scan lines 111, so that the common signal line 12 does not need to be arranged on the opposite sides of each scan line 111, thereby saving the number of common signal lines 12, reducing the occupied space of the common signal line 12, and improving the aperture ratio of the display panel.

[0082] In addition, the embodiment of the present application also provides a display device, which comprises a backlight module and the display panel as described in the above embodiments.

[0083] In some embodiments, the display device can comprise a mobile phone, a television, a computer, a tablet, a wearable device, a virtual reality display device, and the like.

[0084] It can be understood that the display device provided by the embodiment of the present application has the same display panel as the above-described embodiments, and therefore has the same beneficial effects as the display panel described in the above embodiments, which will not be described herein.

[0085] In the description of the present application, the terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first" and "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0086] In the above embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0087] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0088] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present application, without departing from the technical solution of the present application, still falls within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a plurality of pixel regions arranged along a first direction and a second direction, the first direction intersecting the second direction; The display panel further comprises: a plurality of scan line groups arranged along the second direction, each scan line group comprising at least two scan lines arranged along the second direction, the scan lines extending along the first direction; a plurality of common signal lines extending along the first direction, the common signal lines arranged along the second direction; wherein between any two adjacent pixel regions along the second direction, one scan line group and two common signal lines are arranged, and the two common signal lines are respectively located on two sides of the scan line group along the second direction.

2. The display panel of claim 1, wherein, The pixel region comprises a plurality of sub-pixel regions, and the display panel further comprises: a plurality of data lines arranged along the first direction, the data lines extending along the second direction, and at least one data line being arranged between any two adjacent sub-pixel regions along the first direction.

3. The display panel of claim 2, wherein, The pixel region comprises four sub-pixel regions arranged along the first direction as two and along the second direction as two; In the same pixel region, two sub-pixel regions arranged along the second direction are arranged between any two adjacent data lines.

4. The display panel of claim 3, wherein, The display panel further comprises a pixel electrode and a thin film transistor arranged in the sub-pixel region, the thin film transistor being connected to the scan line, the data line and the pixel electrode; In the same scan line group, the two scan lines are connected to the thin film transistors in the two adjacent pixel regions along the second direction.

5. The display panel of claim 4, wherein, In the same pixel region, the thin film transistors in the two sub-pixel regions arranged along the first direction are connected to the same scan line, and the thin film transistors in the two sub-pixel regions arranged along the second direction are connected to different scan lines.

6. The display panel of claim 4, wherein, In the same pixel region, the thin film transistors in the two sub-pixel regions arranged along the first direction are respectively connected to two adjacent data lines, and the thin film transistors in the two sub-pixel regions arranged along the second direction are respectively connected to two adjacent data lines.

7. The display panel of claim 4, wherein, In the same pixel region, the maximum length of the pixel electrode in each sub-pixel region along the first direction is equal; and / or, in the same pixel region, the maximum length of the pixel electrode in each sub-pixel region along the second direction is equal.

8. The display panel of claim 4, wherein, The display panel comprises: a first conductive layer comprising the scan lines and the common signal lines; an electrode layer arranged on one side of the first conductive layer and comprising the pixel electrodes and a common electrode arranged at intervals; The common electrode comprises a first common body part and a second common body part, the first common body part extends along the second direction and is located between the pixel regions adjacent along the first direction, the second common body part extends along the first direction and is located between the sub-pixel regions adjacent along the second direction, and the second common body part is located between the scanning groups adjacent along the second direction, the first common body part is connected with the second common body part to form a grid shape.

9. The display panel of claim 8, wherein, The common electrode further comprises a first adapter part connected between the first common body part and the second common body part, and the first adapter part is electrically connected to the common signal line.

10. The display panel of claim 9, wherein, The width of the first adapter part along the first direction is greater than the width of the first body part along the first direction. And / or, the width of the first adapter part along the second direction is greater than the width of the second body part along the second direction.

11. The display panel of claim 8, wherein, The pixel electrode comprises a pixel body part and a plurality of pixel branch parts, the pixel body part extends along the first direction, a plurality of pixel branch parts are arranged in the sub-pixel region along the first direction, one end of each pixel branch part is connected to the pixel body part, and the other end of each pixel branch part extends along the second direction. The common electrode further comprises a plurality of common branch parts, a plurality of common branch parts are arranged in the sub-pixel region along the first direction, one end of each common branch part is connected to the second common body part, and the other end of each common branch part extends along the second direction. In the sub-pixel region, a plurality of pixel branch parts and a plurality of common branch parts are alternately arranged along the first direction.

12. The display panel of claim 2, wherein, A data line is arranged between two adjacent sub-pixel regions along the first direction, and the potential signals loaded on two adjacent data lines along the first direction have opposite polarities.

13. The display panel of any of claims 2 to 12, wherein, The display panel further comprises a color filter layer, the color filter layer comprises a plurality of color resistance blocks and a light transmission part arranged in the pixel region at least; In the same pixel region, the color resistance blocks are arranged in part of the sub-pixel regions, and the color resistance blocks in different sub-pixel regions have different colors, and the light transmission part is arranged in another part of the sub-pixel regions.

14. The display panel of claim 13, wherein, The display panel further comprises a pixel electrode and a thin film transistor arranged in the sub-pixel region, and the thin film transistor is connected to the scanning line, the data line and the pixel electrode; The display panel further comprises: A second conductive layer comprising a source electrode and a drain electrode of the thin film transistor; An electrode layer arranged on one side of the second conductive layer and comprising the pixel electrode; The color filter layer is arranged between the second conductive layer and the electrode layer.

15. The display panel of claim 14, wherein, The color filter layer comprises at least two color resistance blocks arranged on the side of the thin film transistor close to the electrode layer, and the colors of the at least two color resistance blocks are different.

16. A display device comprising: The display device comprises a backlight module and the display panel according to any one of claims 1 to 15.

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