Method, product and apparatus for predicting the effect of a reticle defect on imaging at the wafer level

Abstract

This invention provides a method, product, and device for predicting the imaging effect of mask defects at the silicon wafer level. The method includes: acquiring a target mask pattern, wherein the target mask pattern is a pattern with potential defects; generating a target aerial image of the target mask pattern using an aerial image measurement system; analyzing and processing the target aerial image to obtain a target optical profile; and generating a target silicon wafer imaging profile corresponding to the target optical profile based on a pre-trained artificial intelligence prediction model. This method allows for the determination of the silicon wafer imaging profile after patterning of the target mask pattern based on the target aerial image, thus fully considering the physicochemical characteristics during the patterning process, achieving accurate prediction of the silicon wafer imaging profile, significantly improving the accuracy of defect printability assessment, and meeting the prediction accuracy requirements of advanced processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method, product, and device for predicting the imaging effect of mask defects at the silicon wafer level. Background Technology

[0002] In the current semiconductor technology field, patterning processes such as photolithography and etching are the core steps in transferring design patterns to silicon wafers. As the pattern carrier, the surface defects of the photomask can easily form printable defects on the silicon wafer, directly affecting chip yield and functionality. Aerial image measurement systems are key equipment for evaluating the printability of photomask defects. By simulating the optical environment of a photolithography machine to acquire aerial images, the imaging effect of defects can be predicted without actual exposure, becoming a core decision-making basis for defect detection and repair.

[0003] However, aerial image measurement systems essentially output an aerial image before photolithography. The final manifestation of mask defects on the silicon wafer depends not only on this optical image but also on a combination of process effects, including the chemical diffusion and development behavior of the photoresist during subsequent photolithography, and deviations in material removal during etching. Existing methods typically only perform simple thresholding of the aerial image to obtain the contour, using this as the basis for silicon wafer defect prediction. This process cannot cover the pattern distortions introduced by photolithography and etching processes, resulting in insufficient prediction accuracy. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a method, product and device for predicting the imaging effect of mask defects at the silicon wafer level to overcome or at least partially solve the above problems.

[0005] One object of the present invention is to achieve accurate prediction of the imaging profile of potential defects in a photomask on a silicon wafer after photolithography or etching;

[0006] Another further objective of this invention is to avoid overfitting of the trained artificial intelligence prediction model.

[0007] Specifically, the present invention provides a method for predicting the imaging effect of mask defects at the silicon wafer level, comprising:

[0008] Obtain the target mask layout, which is a layout with potential defects;

[0009] Aerial image of the target using an aerial image measurement system to generate a target mask map;

[0010] The target's optical profile is obtained by analyzing and processing the aerial image of the target;

[0011] The target silicon wafer imaging profile is generated based on the pre-trained prediction model. The prediction model is used to learn the mapping relationship between the optical profile before the patterning process and the silicon wafer imaging profile after the patterning process, and outputs the corresponding silicon wafer imaging profile based on the input optical profile.

[0012] Optionally, the prediction model is an artificial intelligence prediction model;

[0013] The training steps for an artificial intelligence prediction model include:

[0014] Obtain a pre-established graphical process model, which is used to generate the outline of the mask pattern after graphical processing based on the input mask pattern;

[0015] Simulation data is generated based on the patterned process model. The simulation data consists of a data pair consisting of the optical contour of the mask pattern before the patterning process and the silicon wafer imaging contour after the patterning process.

[0016] An artificial intelligence prediction model is trained based on simulation data and actual measurement data. The actual measurement data consists of a data pair composed of the optical contour obtained by the aerial image measurement system from the actual measurement of the mask pattern and the silicon wafer imaging contour extracted from the scanning electron microscope image obtained by the actual measurement of the mask pattern after the patterning process.

[0017] Optionally, the steps for training an artificial intelligence prediction model based on simulation data and actual measurement data include:

[0018] The contour information recorded by both simulation data and actual measurement data is converted into a symbolic distance field image;

[0019] An artificial intelligence prediction model is obtained by training based on the symbolic distance field image.

[0020] Optionally, the steps for training an artificial intelligence prediction model based on simulation data and actual measurement data include:

[0021] Determine the weight values ​​of simulation data and actual measurement data during the training process;

[0022] Simulation data and actual measurement data are input into a pre-defined neural network architecture;

[0023] An artificial intelligence prediction model is obtained by training simulation data and actual measurement data according to weight values ​​in a preset neural network architecture.

[0024] Optionally, the step of generating simulation data from the graphical process model includes:

[0025] Obtain the complete layout data corresponding to the simulation target chip;

[0026] The complete map data is grouped according to graphic features to obtain multiple graphic groups;

[0027] Select the target training graph from multiple graph groups;

[0028] The optical contours corresponding to the target training graphics and the silicon wafer imaging contours are generated using graphical process models, thereby obtaining simulation data.

[0029] Optionally, the steps for obtaining actual measurement data include:

[0030] Obtain the measured mask pattern and measured position corresponding to the measured optical profile in the actual measurement data;

[0031] Determine the image acquisition range for optical proximity correction simulation;

[0032] An optical profile simulation model was built based on the measured mask pattern, and the optical parameters and mask parameters in the optical profile simulation model were calibrated.

[0033] The simulated optical profile is obtained by simulating the actual optical profile in the measured mask pattern with the measured position as the center and according to the image acquisition range through the optical profile simulation model;

[0034] The center position of the simulated optical profile is replaced by the measured optical profile, and the measured optical profile is combined with the surrounding simulated optical profile to obtain the extended optical profile.

[0035] The actual measurement data is composed of the silicon wafer imaging contour extracted from the scanning electron microscope image obtained by patterning the extended optical profile and the measured mask pattern.

[0036] Optionally, the graphical process model includes a photolithography model and / or an etching model. The photolithography model is used to generate the photoresist outline of the mask pattern after photolithography based on the input mask pattern, and the etching model is used to generate the etched outline of the mask pattern after etching based on the input mask pattern.

[0037] For photolithography models, the silicon wafer imaging contour is the photoresist contour;

[0038] For the etching model, the silicon wafer imaging profile is the profile after etching.

[0039] According to another aspect of the present invention, a computer-readable storage medium is also provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the method for predicting the imaging effect of mask defects at the silicon wafer level as described above.

[0040] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the steps of the method for predicting the imaging effect of mask defects at the silicon wafer level as described above.

[0041] According to another aspect of the present invention, a computer device is also provided, including a memory, a processor, and a machine-executable program stored in the memory and running on the processor, wherein the processor executes the machine-executable program to implement the steps of the method for predicting the imaging effect of mask defects at the silicon wafer level as described above.

[0042] The present invention provides a method for predicting the imaging effect of mask defects at the silicon wafer level. After acquiring the target mask pattern, an aerial image of the target mask pattern is generated using an aerial image measurement system. This aerial image is then analyzed to obtain the target optical profile. Next, a target silicon wafer imaging profile corresponding to the target optical profile is generated based on a pre-trained artificial intelligence prediction model. The artificial intelligence prediction model learns the mapping relationship between the optical profile before patterning and the silicon wafer imaging profile after patterning, and outputs the corresponding silicon wafer imaging profile based on the input optical profile. Finally, defect analysis is performed on the target mask pattern based on the target silicon wafer imaging profile to determine whether potential defects affect the patterning process results. This method allows the silicon wafer imaging profile of the target mask pattern after patterning to be obtained from the target aerial image, thus fully considering the physicochemical characteristics during the patterning process, achieving accurate prediction of the silicon wafer imaging profile, significantly improving the accuracy of defect printability assessment, and meeting the prediction accuracy requirements of advanced processes.

[0043] Furthermore, the method for predicting the imaging effect of mask defects at the silicon wafer level according to the present invention includes the following training steps for the artificial intelligence prediction model: acquiring a pre-established patterned process model, which is used to generate the contour of the mask pattern after the patterning process based on the input mask pattern; generating simulation data based on the patterned process model, wherein the simulation data consists of a data pair composed of the optical contour of the mask pattern before the patterning process and the silicon wafer imaging contour after the patterning process; and training the artificial intelligence prediction model based on the simulation data and actual measurement data, wherein the actual measurement data consists of a data pair composed of the optical contour actually measured by the aerial image measurement system on the mask pattern and the silicon wafer imaging contour extracted from the scanning electron microscope image actually measured after the patterning process of the mask pattern. This method can generate massive amounts of simulation data using graphical process models, making up for the shortcomings of scarce actual measurement data and limited coverage of scenarios. It can significantly expand the breadth and diversity of training data, providing sufficient learning samples for artificial intelligence prediction models. At the same time, by integrating simulation data and actual measurement data to train the model, the model's generalization ability can be guaranteed by simulation data, while the actual process characteristics can be anchored by real measurement data, avoiding model overfitting and improving prediction reliability.

[0044] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0045] The following sections will describe some specific embodiments of the invention in a detailed manner by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0046] Figure 1 This is a schematic flowchart of a method for predicting the imaging effect of mask defects at the silicon wafer level according to an embodiment of the present invention.

[0047] Figure 2 This is a schematic diagram of the training process of an artificial intelligence prediction model in a method for predicting the imaging effect of mask defects at the silicon wafer level according to an embodiment of the present invention.

[0048] Figure 3 This is a schematic diagram illustrating the extended measurement process of a method for predicting the imaging effect of mask defects at the silicon wafer level according to an embodiment of the present invention.

[0049] Figure 4 This is a schematic diagram of a computer program product according to an embodiment of the present invention;

[0050] Figure 5This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and

[0051] Figure 6 This is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed Implementation

[0052] Those skilled in the art should understand that the embodiments described below are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. These partial embodiments are intended to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention. Based on the embodiments provided by the present invention, all other embodiments obtained by those skilled in the art without creative effort should still fall within the scope of protection of the present invention.

[0053] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0054] The most crucial step in semiconductor chip manufacturing is transferring the chip's design pattern onto a silicon wafer. Among the many process steps in chip manufacturing, the processes directly related to pattern transfer are mainly photolithography and etching, commonly referred to as patterning. In current mainstream integrated circuit manufacturing processes, photolithography involves chemically changing photoresist under exposure to specific wavelengths of light, such as 193nm or 248nm, and then transferring the pattern designed on the mask to the photoresist morphology on the silicon wafer through development. Etching, on the other hand, selectively removes unwanted materials with the help of the photoresist morphology, ultimately creating the desired micro-patterns on the silicon wafer. The starting point for these patterning processes is the mask. As the core pattern carrier, even minor defects on its surface (such as particles, crystal growth defects, electrostatic damage, etc.) can form printability defects on the silicon wafer, directly leading to chip malfunction or reduced yield. Therefore, in industrial practice, the requirement for masks is zero defects.

[0055] In the current semiconductor technology field, aerial image measurement systems have become key equipment for evaluating the imaging performance and printability of photomasks. Aerial image measurement systems directly acquire an aerial image of the photomask pattern by accurately simulating the optical conditions (including wavelength, numerical aperture, illumination mode, and polarization state) of a photolithography scanner. This aerial image is optically equivalent to the potential image projected onto the photoresist layer of the silicon wafer in the photolithography machine. Therefore, it can be used to predict the printability of defects or patterns on the photomask on the silicon wafer, thereby guiding photomask conformity assessment and defect repair decisions.

[0056] However, aerial image measurement systems essentially output an aerial image before photolithography. The final manifestation of mask defects on the silicon wafer depends not only on this optical image but also on the combined effects of multiple process factors, including the chemical diffusion and development behavior of the photoresist during subsequent photolithography, and deviations in material removal during etching. Current common methods in the semiconductor technology field generally involve simple thresholding of the aerial image to obtain its contour, which is then used as the basis for predicting silicon wafer defects. This process cannot cover the pattern distortions introduced by photolithography and etching processes, resulting in insufficient prediction accuracy.

[0057] While the development of multi-parameter photoresist models calibrated based on silicon wafer measurement data is relatively mature and has been widely used in the industrial practice of Optical Proximity Correction (OPC), ideally, the photoresist profile after lithography can be simulated using a multi-parameter photoresist calibration model based on an aerial image. However, this requires a precise understanding of the photoresist film stack structure and the process used by the wafer fab, making it difficult to obtain a corresponding photoresist calibration model. Furthermore, aerial image measurement systems are primarily used for mask defect assessment and do not involve subsequent lithography processes. Therefore, applying multi-parameter photoresist calibration models to aerial image measurement systems has practical limitations. Consequently, current aerial image measurement system practices still rely on simple threshold segmentation based on aerial images to obtain the profile, which is then used as the basis for silicon wafer defect prediction. This process neglects the pattern deformation introduced by lithography and etching, leading to insufficient prediction accuracy.

[0058] To address the aforementioned problems, this invention provides a method for predicting the imaging effect of mask defects at the silicon wafer level. Figure 1 This is a schematic flowchart of a method for predicting the imaging effect of mask defects at the silicon wafer level according to an embodiment of the present invention. In this embodiment, the method for predicting the imaging effect of mask defects at the silicon wafer level includes at least the following steps S101 to S104.

[0059] Step S101: Obtain the target mask layout. The target mask layout is the core pattern carrier of the chip patterning process. The surface of the mask may have potential defects such as particles, crystal growth defects, and electrostatic damage. Therefore, it is necessary to use an aerial image measurement system to evaluate the printability of the mask layout to determine whether it needs to be repaired.

[0060] Step S102: An aerial image of the target mask pattern is generated using an aerial image measurement system. The aerial image measurement system is the core component of this step, its key advantage being its ability to precisely replicate the optical imaging environment of the lithography machine. In some optional embodiments, the aerial image measurement system typically loads key parameters of the target lithography process, including the lithography machine's wavelength, numerical aperture (NA), illumination mode (e.g., ring, quadrupole off-axis illumination), partial coherence coefficient, and polarization state (TE wave, TM wave), ensuring that the system's optical environment is completely consistent with the actual lithography process. Subsequently, the aerial image measurement system illuminates the defect areas of the target mask pattern using an illumination system identical to that used in the lithography process. The beam is modulated by the mask pattern and diffracted, then collected by a high-resolution objective lens, ultimately forming a target aerial image optically equivalent to the latent image on the silicon wafer photoresist. Unlike the lithography machine, the aerial image measurement system magnifies the aerial image using an imaging lens and projects it onto a specific camera device, achieving precise acquisition of the aerial image without the need for actual silicon wafer exposure.

[0061] Step S103 involves analyzing and processing the target aerial image to obtain the target optical contour. The target aerial image is essentially an optical intensity distribution image, which needs to be transformed into a target optical contour (Aerial Contour) that can be used as input for an Artificial Intelligence (AI) model through a specific analysis and processing procedure. In one optional approach, the specific processing includes: first, preprocessing the acquired target aerial image, including noise removal and image normalization, to improve image quality; then, segmenting the preprocessed aerial image based on a preset threshold, which needs to be calibrated and determined according to factors such as target lithography process parameters and photoresist sensitivity to ensure that the segmentation result conforms to actual optical imaging laws; finally, extracting the target optical contour from the segmented image. This contour accurately reflects the geometric shape of the aerial image and is a key intermediate carrier linking mask defects and silicon wafer imaging effects.

[0062] Step S104: Generate the target silicon wafer imaging profile corresponding to the target optical profile based on the pre-trained prediction model. The prediction model learns the mapping relationship between the optical profile before patterning and the silicon wafer imaging profile after patterning, and outputs the corresponding silicon wafer imaging profile based on the input optical profile.

[0063] In some optional embodiments, the prediction model can generally be an artificial intelligence (AI) prediction model. The training steps for the AI ​​prediction model generally include: acquiring a pre-established graphical process model; generating simulation data based on the graphical process model, wherein the simulation data consists of data pairs comprising the optical contour of the mask pattern before the graphical process and the silicon wafer imaging contour after the graphical process; and training the AI ​​prediction model based on the simulation data and actual measurement data, wherein the actual measurement data consists of data pairs comprising the optical contour obtained by an aerial image measurement system from the actual measurement of the mask pattern and the silicon wafer imaging contour extracted from the scanning electron microscope image obtained by the actual measurement of the mask pattern after the graphical process.

[0064] The patterning process model is generally used to generate the outline of the mask pattern after patterning, based on the input mask pattern. Since patterning processes generally include photolithography and etching, this model typically includes two types: a photolithography model, built on the core algorithm of Optical Proximity Correction (OPC), integrating parameters related to the photolithography process, and accurately outputting the 3D outline of the photoresist after development based on the input mask pattern data; and an etching model, built on the physicochemical mechanism of the etching process, including parameters related to the etching process, and outputting the final pattern outline of the silicon wafer dielectric layer after etching based on the input photoresist outline data. Therefore, if the patterning process is photolithography, the aforementioned silicon wafer imaging outline is the photoresist outline; if the patterning process is etching, the aforementioned silicon wafer imaging outline is the etched outline.

[0065] Furthermore, considering that in reality, aerial image measurement systems actually measure the locations of potential defects discovered during mask inspection, AI models built solely based on data obtained from normal simulations of numerous mask patterns suffer from insufficient coverage of this potential defect data. Such AI models have extremely limited predictive capabilities for aerial image measurement system measurements. Actual aerial images and Critical Dimension Scanning Electron Microscope (CD-SEM) measurement data are very limited, typically only a few hundred images, and the measured range is also limited, usually within 750nm, while conventional lithography or etching considers a much larger range. Therefore, while building an AI model directly based on the measured optical profile and the corresponding CD-SEM measurement profile to predict the effect of the optical profile after lithography or etching might be feasible, the model is highly unreliable and prone to overfitting.

[0066] Based on the above analysis, this invention creatively generates simulation data from a graphical process model and trains an artificial intelligence prediction model by combining the simulation data and actual measurement data.

[0067] Optionally, the steps for generating simulation data generally include: acquiring the complete layout data corresponding to the target chip; generating the optical contour and silicon wafer imaging contour corresponding to the target training pattern using a graphical process model, thereby obtaining the simulation data. The optical contour can generally be calculated directly from the optical part of the graphical process model, starting from the mask layout, and obtained under a specific threshold; its essence is the same as the processing of aerial images. By inputting the same mask layout data into the graphical process model, selecting either a lithography model or an etching model as needed, and outputting the corresponding photoresist contour or post-etched contour, the silicon wafer imaging contour can be obtained. Pairing the optical contour corresponding to the same mask layout with the silicon wafer imaging contour forms a complete set of simulation data. Repeating the above process generates a massive simulation dataset covering multiple scenarios and multiple pattern types to meet the training requirements of AI models.

[0068] As can be seen from the above operations, this method can select graphical process models according to actual needs, thereby obtaining artificial intelligence prediction models with different functions.

[0069] For example, if the graphical process model selected is a photolithography model, the pre-trained AI prediction model learns the mapping relationship between the optical profile and the photoresist profile after photolithography. Therefore, the output of this step is the photoresist profile corresponding to the target optical profile, thus incorporating the influencing factors in the photolithography process. This allows subsequent defect analysis to further consider the impact of the photolithography process. For instance, tiny particle defects on the photomask may cause changes in the exposure sensitivity of the surrounding photoresist during photolithography, leading to linewidth shrinkage or jagged edge deformation after development. These details, which cannot be captured by aerial image thresholding alone, can be reflected through accurate prediction of the photoresist profile.

[0070] When the patterned process model is an etching model, the pre-trained AI prediction model learns the mapping relationship between the optical profile and the etched profile. Therefore, the output of this step is the etched profile corresponding to the target optical profile, thus incorporating the influencing factors in the photolithography and etching processes. This allows subsequent defect analysis to fully cover the entire process effects of photolithography and etching. For example, potential defects in the photomask may cause slight linewidth deviations in the photoresist profile, while lateral erosion and selective etching deviations during the etching process will further amplify the impact of these defects, ultimately forming substantial pattern defects on the silicon wafer. These cumulative effects of etching processes, which cannot be accurately captured by the target optical profile alone, can all be fully presented through the prediction of the etched profile.

[0071] The core of this step is to rely on a pre-trained artificial intelligence prediction model to achieve a precise mapping from the target optical profile to the target silicon wafer imaging profile, thereby covering multiple process effects such as photoresist chemical diffusion, development behavior, and etching material removal deviation, and making up for the current limitations of the semiconductor field that only relies on optical profile prediction.

[0072] Furthermore, to generate simulation data more effectively, the method of this invention can also introduce pattern grouping technology. For actual full-chip layouts, pattern grouping technology is applied to classify similar patterns into different groups according to their geometric characteristics (such as line width, spacing, shape structure, etc.), thereby selecting representative typical patterns from a massive number of patterns. Then, a benchmark graphical process model is used to generate simulation contours on these representative patterns and use them as input for neural network training, thereby obtaining more effective simulation data for subsequent AI model training and improving the generalization ability of the AI ​​model. Pattern grouping technology generally includes exact grouping and fuzzy grouping, etc. Those skilled in the art can choose the simulation data acquisition method according to the actual situation, such as using an exact grouping algorithm or a fuzzy grouping algorithm, or a common random sampling method.

[0073] Finally, after obtaining the target silicon wafer imaging profile corresponding to the target optical profile, defect analysis of the target mask pattern can be performed based on the target silicon wafer imaging profile to determine whether potential defects affect the patterning process results.

[0074] Specifically, by comparing the imaged contour of the target silicon wafer with the expected design contour of the chip layout, the impact of defects on the patterning process results is determined. If the analysis results show that the imaged contour of the target silicon wafer meets the design requirements, it is determined that the potential defect does not affect the patterning process results, and the mask does not need to be repaired; if it does not meet the design requirements, it is determined that the defect is printable, and the mask needs to be sent to the repair process. After repair, it can be re-inspected using this method to confirm the repair effect.

[0075] This method overcomes the limitations of existing aerial image measurement systems, obtaining the silicon wafer imaging profile after patterning based on the target aerial image of the mask pattern. This fully considers the physicochemical properties during the patterning process, and the entire framework is applicable to both photolithography and etching. It makes it possible to predict the silicon wafer imaging profile after photolithography and etching based on the aerial image, achieving accurate prediction of the silicon wafer imaging profile, significantly improving the accuracy of defect printability assessment, and meeting the prediction accuracy requirements of advanced processes.

[0076] Figure 2This is a schematic diagram illustrating the training process of an artificial intelligence prediction model in a method for predicting the imaging effect of mask defects at the silicon wafer level according to an embodiment of the present invention. Figure 2 As shown, the training method of this artificial intelligence prediction model includes at least the following steps S201 to S208.

[0077] Step S201: Obtain the pre-established graphical process model. The graphical process model can be a photoresist model or an etching model. The photoresist model can convert the input mask pattern into a photoresist contour through calculation, and the etching model can convert the input photoresist contour into an etched contour through calculation. Of course, the construction of these models themselves requires multiple rounds of calibration and optimization based on a large amount of actual silicon wafer data from the wafer fab.

[0078] Step S202: Obtain the complete layout data corresponding to the simulation target chip. To ensure that the simulation data closely matches the actual application scenario, a chip matching the target process node must be selected as the simulation object. This target chip must cover typical device structures (such as logic gates, memory cells, interconnects, etc.). Subsequently, extract the complete layout data corresponding to the target chip. This data typically contains key information such as the geometric dimensions, layout positions, and hierarchical information of all patterns on the chip, and serves as the basic data source for subsequent pattern grouping and selection of training patterns.

[0079] Step S203: Group the complete map data according to graphic features to obtain multiple graphic groups. During the generation of simulation data, since some graphics may be too simple or unrepresentative, this invention further introduces graphic grouping technology to accelerate training efficiency while ensuring the generalization ability of the artificial intelligence defect detection model. Finally, similar graphics are classified into different groups according to their geometric features (such as line width, spacing, shape structure, etc.), thereby selecting representative typical graphics from a massive dataset. The grouping algorithm (i.e., Pattern Grouping technology) can generally include exact grouping and fuzzy grouping algorithms, or random sampling can be used. Those skilled in the art can choose the appropriate grouping method according to actual needs.

[0080] Step S204: Select target training graphics from multiple graphic groups. This step generally involves selecting representative graphics from each graphic group as target training graphics, such as those covering the typical graphic features of each group, while also including graphics prone to process deviations. The selected target training graphics need to balance diversity and representativeness, ensuring that the model learns comprehensive process rules while avoiding excessive increases in training costs due to the selection of redundant graphics.

[0081] Step S205: The optical contour and silicon wafer imaging contour corresponding to the target training pattern are generated using the graphical process model, thereby obtaining simulation data. The simulation data consists of data pairs composed of the optical contour of the mask pattern before the patterning process and the silicon wafer imaging contour after the patterning process.

[0082] The specific execution process of this step generally includes: first, for the selected target training graphic, the imaging logic of the aerial image measurement system is simulated through the optical part in the graphical process model, and the optical profile consistent with the real output is calculated; then, the silicon wafer imaging profile corresponding to the target training graphic is output through the graphical process model; finally, the optical profile corresponding to the same target training graphic is paired with the silicon wafer imaging profile to form a set of corresponding simulation data; repeating the above process can generate a large-scale simulation dataset covering multiple graphic types.

[0083] Step S206 determines the weights of simulation data and actual measurement data during training. While simulation data has the advantages of wide coverage and large quantity, it deviates from the actual process; actual measurement data directly reflects the characteristics of the actual process, but it is costly to obtain and has a small sample size. This step balances the training contributions of the two types of data by setting weights. The weights are determined based on data reliability and sample size ratio: if the actual measurement data has a sufficient sample size and high reliability, a higher weight can be set; if the actual measurement data has a small sample size, its weight should be appropriately reduced to avoid model overfitting. A reasonable weight setting allows the model to learn both the generalization rules of simulation data and the true characteristics of actual measurement data.

[0084] Step S207: Input the simulation data and the actual measurement data into the preset neural network architecture.

[0085] Step S208: Train the simulation data and actual measurement data according to the weight values ​​in the preset neural network architecture to obtain an artificial intelligence prediction model.

[0086] Optionally, the steps for training an AI prediction model based on simulation data and actual measurement data generally include: converting the contour information recorded by both simulation data and actual measurement data into a signed distance field image; and training the AI ​​prediction model based on the signed distance field image. The signed distance field (SDF) is a mathematical function used to represent geometric shapes. For any point in space, the signed distance function returns the distance from that point to the nearest geometric surface, assigning a positive or negative sign based on the point's position relative to the shape. Generally, the distance is negative when the point is inside the geometric shape, positive when the point is outside the geometric shape, and zero when the point is exactly on the surface of the geometric shape. If both the optical contour and its corresponding photoresist contour are converted into signed distance field images, then an AI model can be constructed to complete the mapping from the input optical contour SDF image to the output photoresist contour SDF image. During inference, the AI ​​model first converts the input contour into an input SDF image, infers the output SDF image, and then converts it back into the output contour, thus completing the entire contour-to-contour process. The symbolic distance field image can more accurately represent the geometric shape and topological structure of the contour. Compared with the original binary contour image, it can provide the model with richer feature information and effectively improve the model's prediction accuracy for the contour of small defects.

[0087] This embodiment relies on a closed-loop design of precise data preparation, scientific grouping and sampling, and weighted hybrid training to systematically solve the problems of insufficient model generalization ability and low prediction accuracy caused by single data training, and provides high-performance model support for subsequent prediction of silicon wafer imaging effects with mask defects.

[0088] In some optional embodiments, the iterative training process of the artificial intelligence prediction model generally includes: the neural network first extracts the feature information of the optical contour through convolutional layers and pooling layers, and then restores the feature dimension through upsampling layers to output the predicted silicon wafer imaging contour; during training, the loss function (such as mean squared error loss) of the two types of data is calculated according to preset weight values, and the network parameters are continuously optimized through backpropagation algorithm; when the loss function converges to a preset threshold and the prediction accuracy of the model on the validation set meets the requirements, training is stopped, and the final artificial intelligence prediction model is obtained. The artificial intelligence prediction model trained in this way can learn the accurate mapping law between the optical contour and the silicon wafer imaging contour, such as: the basic correspondence between the optical contour geometry and the silicon wafer imaging contour; the nonlinear deformation law brought about by the lithography / etching process (optical proximity effect, etching load effect, etc.); the imaging specific law of mask defects (the correlation between defect type, size and silicon wafer imaging shape); and the fusion of the ideal process law of simulation data and the real process deviation law of measured data, etc.

[0089] It should be noted that this method uses a neural network adapted for image-to-image contour mapping tasks as the core model. The core training framework generally includes a feature extraction module, a feature restoration / mapping module, and a feature fusion module (if needed). Each module works synergistically to meet the core requirement of optical contour feature input and silicon wafer imaging contour feature output. Various neural networks with contour mapping capabilities (such as convolutional neural networks, encoder-decoder structures, etc.) can be trained based on this framework. The training environment uses a conventional deep learning framework and adapted hardware configuration. Basic parameters include training batch size, training epochs, initial learning rate and adjustment strategy, loss function type, optimizer type, and core parameters, all reasonably set according to the characteristics of the selected neural network and task requirements. The loss function is selected to be adapted to the contour mapping task (such as mean squared error loss) to measure the deviation between the predicted contour and the true contour; the optimizer uses a conventional gradient descent optimizer to update model parameters. Those skilled in the art can choose a specific neural network architecture according to the actual situation. Training data can also use conventional initialization methods adapted to the selected neural network (such as normal initialization, Xavier initialization, He initialization, etc.) to ensure a reasonable initial parameter distribution, laying the foundation for training convergence.

[0090] Optionally, the training process for an artificial intelligence prediction model may generally include:

[0091] Forward propagation: The training set input data is fed into the model, and after collaborative processing by the model's various general functional modules, the predicted silicon wafer imaging contour data is output. The generalization components of each module typically include a feature extraction layer / module, a feature transformation layer / module, and optionally, a feature fusion layer / module and an output mapping layer / module. The processing generally proceeds as follows: First, the input optical contour standardized data is subjected to multi-scale feature extraction through a feature extraction layer (such as convolutional layers, pooling layers, etc.) to obtain contour feature maps at different levels (including basic features such as edges, textures, and geometric shapes, as well as deep semantic features). Then, the extracted feature maps are adjusted in dimension, enhanced, or restored through a feature transformation layer (such as fully connected layers, transposed convolutional layers, attention layers, etc.) to adapt to the feature representation requirements of the silicon wafer imaging contour. If the model includes a feature fusion layer (such as a stitching layer, additive layer, etc.), the feature maps at different levels are simultaneously fused to supplement feature details and improve the completeness of feature representation. Finally, the processed features are converted into silicon wafer imaging contour prediction data matching the output format through the output mapping layer.

[0092] Loss calculation: Based on the preset weights of simulation data and actual measurement data, the weighted loss is calculated to quantify the deviation between the predicted result and the actual result.

[0093] Backpropagation and parameter update: Clear the gradient cache from the previous round, calculate the gradient of the loss function with respect to the model parameters, and update the model parameters through the optimizer.

[0094] Optionally, after each training round, the model can be set to validation mode, gradient calculation can be turned off, validation set data can be loaded to perform forward propagation, and core metrics such as validation set loss and contour matching degree can be calculated to evaluate model performance.

[0095] Optionally, an early stopping strategy can be adopted to avoid model overfitting. If the loss on the validation set does not decrease effectively after several consecutive rounds, training is stopped. During training, the model with the best performance on the validation set is saved, and key information such as model parameters and optimizer status is recorded for easy loading and use later.

[0096] Finally, the optimal model is fine-tuned based on the training results, and parameters such as the learning rate are adjusted to further optimize performance. Finally, the training is confirmed to be complete according to the preset convergence criteria (such as the validation set loss stabilizing below the threshold and the contour matching degree meeting the standard), and the final artificial intelligence prediction model is output.

[0097] In some alternative embodiments, since the measured range of the aerial image on the mask pattern during actual operation is limited to approximately 750 nm, while the range considered by ordinary lithography or etching is much larger than this, in order to ensure the accuracy of the artificial intelligence prediction model, it is also possible to optimize the actual measurement data. Figure 3This is a schematic diagram illustrating the extended measurement process of a method for predicting the imaging effect of mask defects at the silicon wafer level according to an embodiment of the present invention, as shown in the diagram. Figure 3 As shown, the training method of this artificial intelligence prediction model includes at least the following steps S301 to S306.

[0098] Step S301: Obtain the measured mask pattern and measured position corresponding to the measured optical profile.

[0099] Step S302: Determine the image acquisition range for the optical proximity correction simulation. The image acquisition range needs to be set based on the actual requirements of the target patterning process, generally meeting two conditions: first, it needs to cover the area of ​​the OPC simulation; second, it should be centered on the measured location obtained in S301, ensuring that the measured area is at the core of the simulation range, with the surrounding extended area completely covering the process influence range.

[0100] This step ensures that the subsequent supplementary surrounding contours contain all the key graphic information that affects the imaging of the core measured area; at the same time, it ensures the dominant position of the core measured area with the measured location as the center.

[0101] Step S303 involves building an optical profile simulation model based on the measured mask pattern and calibrating the optical parameters and mask parameters in the simulation model. An uncalibrated simulation model exhibits parameter deviations, resulting in a significant difference between the output simulated optical profile and the actual process scenario. Directly using this model for supplementation and expansion would distort the expanded optical profile, thereby reducing the model's training accuracy. Therefore, the model parameters must be calibrated using the actual measured optical profile as a benchmark to ensure that the output characteristics of the simulation model are completely consistent with the aerial image measurement system, thus guaranteeing the reliability of the supplemented profile.

[0102] Step S304: Using an optical profile simulation model, a simulated optical profile is obtained by simulating the measured position and the image acquisition range within the measured mask pattern. This step uses the optical profile simulation model to obtain a complete optical profile over a wide area, which includes the simulated portion corresponding to the core measured area and the simulated portion of the surrounding extended area. This compensates for the limited measured range of the aerial image measurement system. Furthermore, since the model has been calibrated, the deviation between the simulated profile and the actual process is minimal, making it suitable for subsequent extended stitching.

[0103] Step S305 involves replacing the center position of the simulated optical profile with the measured optical profile and then stitching the measured optical profile with the surrounding simulated optical profiles to obtain the extended optical profile. Directly using the fully simulated wide-area profile would lose the true process characteristics of the measured data, causing the extended data to lose its value in anchoring the real process; conversely, retaining only the measured small-area profile would not solve the problem of limited scope. Therefore, this step adopts a stitching strategy of core measured replacement + surrounding simulated supplementation, which can both retain the true process information of the core area and supplement the process interaction information of the surrounding wide area; at the same time, if there are abrupt changes at the stitching boundary, it will cause profile distortion, requiring smoothing processing to ensure the integrity and continuity of the profile.

[0104] The resulting extended optical profile combines realism and wide-area coverage: the measured profile of its core area ensures that the data closely matches the actual process, while the surrounding simulated profile supplements complete process interaction information, solving the core problem of insufficient measurement range of the aerial image measurement system; edge smoothing avoids splicing distortion, ensuring the consistency between the extended profile and the real wide-area optical profile, and providing high-quality input data for the AI ​​model to learn complete process rules.

[0105] Step S306: The extended optical profile and the silicon wafer imaging profile extracted from the actual measurement image obtained by the actual measurement of the measured mask pattern after patterning are combined to form the actual measurement data. The extended optical profile serves as input data for subsequent AI model training, while the silicon wafer imaging profile is the output of the AI ​​model training process. The size of the silicon wafer imaging profile is consistent with the CD-SEM measurement data.

[0106] This operation allows for the construction of high-quality actual measurement data pairs with a large input range and a small output range. This enables a larger input mask range to comprehensively consider process effects, while a smaller output range matches the design goals of CD-SEM measurements. It retains the advantage of measured data closely reflecting real-world processes, while the OPC-level large-range setting compensates for the insufficient measurement range of aerial image measurement systems. Ultimately, when used for model training, this data pair can significantly improve the prediction accuracy of silicon wafer imaging contours, especially for defects heavily influenced by surrounding processes, thus significantly enhancing prediction accuracy.

[0107] It should be understood that in some embodiments, the components may be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods may be implemented using software or firmware stored in memory and executed by a suitable instruction execution system.

[0108] This embodiment also provides a computer program product 10, a computer-readable storage medium 20, and a computer device 30. Figure 4This is a schematic diagram of a computer program product 10 according to an embodiment of the present invention. Figure 5 This is a schematic diagram of a computer-readable storage medium 20 according to an embodiment of the present invention. Figure 6 This is a schematic diagram of a computer device 30 according to an embodiment of the present invention. The computer program product 10 includes a computer program 11, which, when executed by the processor 32, implements the steps of the method for predicting the imaging effect of mask defects at the silicon wafer level according to any of the above-described embodiments. A computer-readable storage medium 20 stores the computer program 11 thereon, which, when executed by the processor 32, implements the steps of the method for predicting the imaging effect of mask defects at the silicon wafer level according to any of the above-described embodiments. The computer device 30 may include a memory 31, a processor 32, and the computer program 11 stored in the memory 31 and running on the processor 32.

[0109] The computer program 11 used to perform the operations of this invention may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​and procedural programming languages. The computer program 11 may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a Local Area Network (LAN) or Wide Area Network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, Field-Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing state information from computer-readable program instructions.

[0110] For the purposes of this embodiment, computer program product 10 is a related product containing computer program 11. For the purposes of this embodiment, computer-readable storage medium 20 is a tangible device capable of holding and storing computer program 11, and can be any device capable of containing, storing, communicating, propagating, or transmitting program 11 for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable storage medium 20 include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanical encoding device, and any suitable combination thereof.

[0111] Computer device 30 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer device 30 can be a cloud computing node. Computer device 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer device 30 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.

[0112] Computer device 30 may include a processor 32 adapted to execute stored instructions and a memory 31 that provides temporary storage space for the operation of said instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any other configuration. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0113] Computer device 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows external devices that can be connected to the computer device to input and output data. The network adapter / interface provides communication between the computer device and a network, typically represented as a communication network.

[0114] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.

Claims

1. A method for predicting the imaging effect of mask defects at the silicon wafer level, comprising: Obtain the target mask layout, wherein the target mask layout is a layout with potential defects; An aerial image of the target mask pattern is generated using an aerial image measurement system; The target's optical profile is obtained by analyzing and processing the aerial image of the target. The target silicon wafer imaging profile corresponding to the target optical profile is generated according to the pre-trained prediction model. The prediction model is used to learn the mapping relationship between the optical profile before the patterning process and the silicon wafer imaging profile after the patterning process, and outputs the corresponding silicon wafer imaging profile based on the input optical profile. The prediction model is an artificial intelligence prediction model; The training steps of the artificial intelligence prediction model include: acquiring a pre-established graphical process model, which is used to generate the outline of the mask pattern after graphical processing based on the input mask pattern; Simulation data is generated based on the graphical process model. The simulation data consists of a data pair composed of the optical contour of the mask pattern before the graphical process and the silicon wafer imaging contour after the graphical process. The artificial intelligence prediction model is trained based on the simulation data and the actual measurement data. The actual measurement data consists of a data pair composed of the optical contour obtained by the aerial image measurement system from the actual measurement of the mask pattern and the silicon wafer imaging contour extracted from the scanning electron microscope image obtained by the actual measurement of the mask pattern after the graphical process.

2. The method for predicting the imaging effect of mask defects at the silicon wafer level according to claim 1, wherein, The step of training the artificial intelligence prediction model based on the simulation data and actual measurement data includes: The contour information recorded by both the simulation data and the actual measurement data is converted into a symbolic distance field image; The artificial intelligence prediction model is obtained by training the symbolic distance field image.

3. The method for predicting the imaging effect of mask defects at the silicon wafer level according to claim 1, wherein, The step of training the artificial intelligence prediction model based on the simulation data and actual measurement data includes: Determine the weight values ​​of the simulation data and the actual measurement data during the training process; The simulation data and the actual measurement data are input into a preset neural network architecture; The artificial intelligence prediction model is obtained by training the simulation data and the actual measurement data according to the weight values ​​in the preset neural network architecture.

4. The method for predicting the imaging effect of mask defects at the silicon wafer level according to claim 1, wherein, The step of generating simulation data based on the graphical process model includes: Obtain the complete layout data corresponding to the simulation target chip; The complete map data is grouped according to graphic features to obtain multiple graphic groups; Select the target training graph from the multiple graph groups; The optical profile and silicon wafer imaging profile corresponding to the target training pattern are generated using the graphical process model, thereby obtaining the simulation data.

5. The method for predicting the imaging effect of mask defects at the silicon wafer level according to claim 1, wherein, The steps for obtaining the actual measurement data include: Obtain the measured mask pattern and measured position corresponding to the measured optical profile in the actual measurement data; Determine the image acquisition range for optical proximity correction simulation; An optical profile simulation model was built based on the measured mask pattern, and the optical parameters and mask parameters in the optical profile simulation model were calibrated. The optical profile simulation model is used to simulate the optical profile in the measured mask pattern, with the measured position as the center and according to the image acquisition range, to obtain the simulated optical profile. The measured optical profile is used to replace the center position of the simulated optical profile, and the measured optical profile is combined with the surrounding simulated optical profile to obtain the extended optical profile. The actual measurement data is composed of the silicon wafer imaging profile extracted from the scanning electron microscope image obtained by the actual measurement of the extended optical profile and the actual measured mask pattern after the patterning process.

6. The method for predicting the imaging effect of mask defects at the silicon wafer level according to claim 1, wherein, The graphical process model includes a photolithography model and / or an etching model. The photolithography model is used to generate the photoresist outline of the mask pattern after photolithography based on the input mask pattern. The etching model is used to generate the etched outline of the mask pattern after etching based on the input mask pattern. For the photolithography model, the silicon wafer imaging profile is the photoresist profile; For the etching model, the silicon wafer imaging profile is the etched profile.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that... When the computer program is executed by a processor, it implements the steps of the method for predicting the imaging effect of mask defects at the silicon wafer level as described in any one of claims 1 to 6.

8. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method for predicting the imaging effect of mask defects at the silicon wafer level as described in any one of claims 1 to 6.

9. A computer device comprising a memory, a processor, and a machine-executable program stored in the memory and running on the processor, wherein the processor, when executing the machine-executable program, implements the steps of the method for predicting the imaging effect of mask defects at the silicon wafer level according to any one of claims 1 to 6.

Images