Clock measuring circuit and micro-processing chip

Abstract

The invention provides a time measuring circuit which comprises a logic transmission loop, the logic transmission loop is provided with a large number counting circuit, the large number counting circuit comprises an oscillation delay line, and the oscillation delay line is composed of N time sequence delay elements and a logic gate which are sequentially connected in series to form a closed loop and is used for providing a captured decimal part; the counter is coupled to the oscillation delay line and is used for recording the complete cycle index of closed-loop oscillation of the oscillation delay line in real time so as to provide a captured large number part; one end of the edge signal processing module is connected with the first input end of the processing module, the other end of the edge signal processing module receives an input signal to be detected, and the edge signal processing module is used for outputting a capture trigger signal to the oscillation delay line when an edge signal is detected; a second input end of the processing module is connected with the oscillation delay line, a third input end of the processing module is connected with the counter, and the processing module is used for reading and storing output signals of each logic gate of the current oscillation delay line and the counter when the capture trigger signal is received.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of precise time measurement, and in particular to a circuit for realizing high-resolution coarse-fine time digital conversion by using an oscillation delay line, a counter and a logic transfer loop. BACKGROUND

[0002] A conventional time-to-digital converter (TDC) adopts a vernier delay chain or a tapped delay chain structure, and the area thereof exponentially increases with the increase of resolution, and is greatly affected by process, voltage and temperature (PVT) fluctuations.

[0003] At present, there is an urgent need for a new TDC scheme with small area, low power consumption and capable of multiplexing coarse counting and fine counting functions in the same hardware loop. SUMMARY

[0004] The present application provides a clock measurement circuit and a micro processing chip, which uses an oscillation delay line as a fine time scale and realizes coarse counting through closed-loop oscillation, so as to simultaneously obtain a large dynamic range and high resolution with very little hardware. The loop start and stop are completely controlled by the input edge through a switch-NAND-NOR chain structure, so as to realize zero static power consumption for a single measurement. The difference between the two sampling points and the difference in the delay line state are used to calculate the integer period and the fractional delay, respectively, to complete the measurement of the picosecond time interval.

[0005] In a first aspect, the present application provides a clock measurement circuit, comprising: a logic transfer loop, wherein the logic transfer loop is provided with a large number statistical circuit, the large number statistical circuit comprises an oscillation delay line, the oscillation delay line is composed of N time sequence delay elements and logic gates which are sequentially connected to form a closed loop, and is used for providing a captured fractional part; a counter coupled to the oscillation delay line, used for recording the number of complete cycles of the closed-loop oscillation of the oscillation delay line in real time, so as to provide a captured large number part; an edge signal processing module, one end of which is connected to a first input end of a processing module, and the other end receives an input signal to be measured, used for outputting a capture trigger signal to the oscillation delay line when an edge signal is detected; and a processing module, a second input end of which is connected to the oscillation delay line, and a third input end of which is connected to the counter, used for reading and saving the output signals of the logic gates of the oscillation delay line and the counter at the moment when the capture trigger signal is received.

[0006] As an optional implementation, the logic transfer loop further comprises a time measurement module, and the time measurement module is composed of a large number statistical unit and a fractional statistical unit.

[0007] As an optional implementation, the large number statistical unit is used for calculating the difference between the two counter values, so as to obtain an integer time difference.

[0008] As an optional implementation, the fractional statistics unit is used to calculate the fractional time difference based on the difference in the output state of each delay unit of the oscillation delay line during two samplings.

[0009] As an optional implementation, the capture trigger signal is connected to the first input terminal of the NAND gate via a switch. The first input terminal of the first AND gate is connected to the output terminal of the NAND gate. The output terminal of the NAND gate is also connected to the counter. The first input terminals of subsequent AND gates are sequentially connected to the output terminals of the previous AND gate. The output terminal of the Nth AND gate is fed back to the NAND gate through the switch.

[0010] As an optional implementation, when the first edge point of the waveform under test is detected, a first trigger signal of logic "1" is output, the switch is turned on, the NAND gate outputs "1" to activate the logic transmission loop, the first AND gate outputs "1" and passes it on, the second input of the NAND gate receives "0" and outputs "0", the first input of the first AND gate receives "0" and outputs "0" and continues to pass "0" on.

[0011] As an optional implementation, when the second edge point of the waveform under test is detected, a second trigger signal of logic "0" is output to disconnect the switch and set the output terminals of the NAND gate and N AND gates to "1".

[0012] As an optional implementation, the large number counting unit counts the number of changes of "0" and "1" using the counter. If the transmission time of each logic gate is Δt and the count value is m, then the large number part of the time interval is (N+1)×m×Δt.

[0013] As an optional implementation, the fractional statistics unit records the output numbers of each AND gate at the first edge point and the output numbers of each AND gate at the second edge point. Based on the difference in the number of "1"s in the two records, it adds a fractional time corresponding to the difference in the number of "1"s × Δt to the large part of the time interval, where Δt is the propagation time of each logic gate.

[0014] In a second aspect, this application provides a microprocessor chip including a time measurement circuit as described in any of the preceding claims.

[0015] The clock measurement circuit and microprocessor chip provided in this application include a logic transfer loop with a large number statistics circuit. This circuit includes an oscillation delay line, which is composed of N sequentially connected timing delay elements and logic gates forming a closed loop, used to provide the captured fractional part. A counter, coupled to the oscillation delay line, records the complete number of cycles of the closed-loop oscillation of the oscillation delay line in real time to provide the captured large number part. An edge signal processing module, one end of which is connected to the first input terminal of the processing module and the other end of which receives the input signal to be measured, outputs a capture trigger signal to the oscillation delay line when an edge signal is detected. The processing module has a second input terminal connected to the oscillation delay line and a third input terminal connected to the counter, used to read and save the output signals of each logic gate of the oscillation delay line and the counter when the capture trigger signal is received. By using only one oscillation delay line, combined with a counter and an edge signal processing module, the complexity of traditional multi-delay-line structures is effectively simplified, while the synchronization problem of multiple delay lines is solved, achieving high-precision pulse width capture. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] Figure 1 This is a schematic diagram of a clock measurement circuit disclosed in an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of another clock measurement circuit disclosed in an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the large number statistical unit and the small number statistical unit disclosed in the embodiments of the present invention;

[0020] Figure 4 This is a schematic diagram of the oscillation delay chain disclosed in an embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of the oscillation delay line start-up control process disclosed in an embodiment of the present invention;

[0022] Figure 6 This is a schematic diagram of the oscillation delay line cessation control process disclosed in an embodiment of the present invention;

[0023] Figure 7 This is a schematic diagram of a microprocessor chip disclosed in an embodiment of the present invention.

[0024] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of clock measurement circuits and microprocessor chips consistent with some aspects of this application as detailed in the appended claims.

[0026] Currently, conventional clock measurement circuits can be divided into four categories: ① Counter type: using the high-frequency clock period T_clk as the smallest scale, START / STOP respectively start and stop the synchronous counter, and the reading N×T_clk is the measured interval. The structure is extremely simple, but the resolution is limited by the clock period (only 2 ns for a 500 MHz clock) and there is a ±1 counting quantization error. ② Tapped delay line type: using the START pulse to propagate step-by-step in the buffer chain, sampling each node on the chain when STOP arrives to obtain a "thermometer code," with the transition position corresponding to a fractional time. Resolution ≈ single-stage gate delay τ (20-30 ps under 65 nm process), dynamic range is usually <10 ns; code density calibration is required to correct the nonlinearity caused by process gradients. ③ Multiphase interpolation type...

[0027] A 4 / 8 / 16-channel fixed phase shift is generated for the high-frequency clock. Events are sampled simultaneously using multiple phase clocks, and then encoded to obtain "coarse + fine" results. For example, a 320 MHz four-phase system can achieve a fine resolution of 0.78 ns with lower power consumption than the frequency multiplication scheme, but it is sensitive to duty cycle and phase error. ④ Ring oscillator + counter: START turns on the ring oscillator, STOP freezes the ring oscillator phase and period counter. Fine time is given by the phase code, and coarse time is given by the counter. The resolution is still τ, the area is small and easy to shrink with process technology, but the temperature drift is large, requiring periodic self-calibration.

[0028] This application addresses the aforementioned problems by designing a clock measurement circuit, disclosing the core components of the time measurement circuit and the connection relationships between its modules, specifically in conjunction with... Figure 1 The overall structural diagram is explained below:

[0029] Oscillation Delay Line 10: A closed-loop structure is formed by connecting 31 inverters (10-1 to 10-31) in series, creating a self-excited oscillation circuit. Actual measurements show that the average delay time Δt of a single inverter is 30 ps. Since the signal in the closed-loop structure needs to pass through 31 inverters to complete one complete transmission, the closed-loop self-oscillation period is calculated using the formula "31 × Δt", yielding approximately 1.86 ns. This period provides a time reference for subsequent "coarse counting".

[0030] Counter 20: A 12-bit asynchronous adder counter is selected. Its clock input CK is connected to the output of the last stage inverter 10-31 of the oscillation delay line 10, so that the counting frequency of the counter is consistent with the natural frequency of the oscillation delay line. The enable terminal EN of the counter is connected to the capture trigger signal TRIG output by the edge signal processing module 30. The counter only performs addition counting when the TRIG signal is valid, so as to achieve precise control of the counting process.

[0031] Edge signal processing module 30: A single-stage D flip-flop is used as the core processing unit. The D terminal of the flip-flop is used to input the time signal TIN to be measured, the CK terminal is used to input the system clock CLK, and the output signal from the Q terminal is processed by combinational logic circuitry to generate a TRIG pulse signal with a width equal to 10 self-oscillation periods of the oscillation delay line. This design effectively suppresses metastability; reliability testing shows that the probability of metastability is less than 10⁻¹², ensuring the stability and reliability of the trigger signal.

[0032] Processing module 40: As the core of data processing and storage, it simultaneously performs two key data latching operations at the rising edge of the TRIG pulse signal: first, the output state of the 31-stage inverter in the oscillation delay line 10, forming 31-bit delay line state data DS[30:0]; second, the current count value of counter 20, forming 12-bit count value data CNT[11:0]. Processing module 40 integrates an APB bus interface, and the latched data can be transmitted to an external control unit or storage module via the APB bus for subsequent data reading and processing.

[0033] Please see Figure 2This is another clock measurement circuit disclosed in this embodiment of the invention. The oscillation delay line 10 consists of an n-stage AND gate (denoted as the first AND gate to the nth AND gate), a transmission gate TG (switch), and a NAND gate G0. The specific connection relationship is as follows: the first input terminal of the first AND gate is directly connected to the output terminal of the NAND gate G0, and the output terminal of the NAND gate G0 is also connected to the clock input terminal CK of the counter 20; the first input terminals of each subsequent AND gate are cascaded with the output terminals of the previous AND gate to form a signal transmission link; the output terminal of the nth AND gate is connected to the second input terminal of the NAND gate G0 through the transmission gate TG to form a complete closed loop. In this embodiment, n is 31, that is, including AND gates G1 to G31. According to actual measurement, the average delay time Δt of a single-stage AND gate is 30ps. The closed-loop self-oscillation period of the loop is calculated by the formula "n×Δt", which is about 1.86ns. This period provides a time reference for the subsequent "coarse counting".

[0034] Counter 20: A 12-bit asynchronous adder counter is selected. Its clock input terminal CK is connected to the output terminal of the last stage of the oscillation delay line 10, so that the counting frequency of the counter is consistent with the natural frequency of the oscillation delay line. The enable terminal EN of the counter is connected to the capture trigger signal TRIG output by the edge signal processing module 30. The counter only performs addition counting when the TRIG signal is valid, so as to achieve precise control of the counting process.

[0035] Edge signal processing module 30: Its core function is to receive the edge signals of the signal under test (TIN), identify them, and perform logical processing. When a start edge is detected, a first trigger signal with a logic value of "1" is generated; when an end edge is detected, a second trigger signal with a logic value of "0" is generated. This module uses a single-stage D flip-flop as the core processing unit. The D terminal receives the signal under test (TIN), the CK terminal is connected to the system clock CLK, and the first / second trigger signals output from the Q terminal are transmitted in two paths: one path is connected to the control terminal of the transmission gate TG (switch), and the other path is transmitted to the processing module 40. Simultaneously, the trigger signals are also connected to the first input terminal of the NAND gate G0. This design effectively suppresses metastability; reliability testing shows that the probability of metastability is less than 10⁻¹², ensuring the stability and reliability of the trigger signals.

[0036] Processing module 40: As the core of data interaction and control, its connection relationship is as follows: its input terminals are respectively connected to the output terminals of each AND gate (G1~G31) in the oscillation delay line 10, the output terminal of the counter 20, and the clock measurement module 50; it receives the first / second trigger signals transmitted by the edge signal processing module 30 and performs corresponding operations according to the trigger signals. At the rising edge of the first trigger signal (logic "1") and the falling edge of the second trigger signal (logic "0"), it completes two key data latches respectively: one is the output state of the 31 AND gates in the oscillation delay line 10 (31-bit delay line state data DS[30:0]), and the other is the current count value of the counter 20 (12-bit count value data CNT[11:0]). The processing module 40 integrates an APB bus interface, which can transmit the latched data to external units and send data processing instructions to the clock measurement module 50 at the same time.

[0037] It also includes a clock measurement module 50, which is an independent functional module directly connected to the processing module 40. Internally, it integrates a large number statistics unit 41 and a small number statistics unit 42.

[0038] Please see Figure 3 This invention discloses the functions of the large number statistics unit and the small number statistics unit in the clock measurement module, and discloses a time interval calculation scheme based on large number statistics and small number statistics. This scheme implements the large number statistics unit 41 and the small number statistics unit 42 through hardware logic, and their specific functions are as follows:

[0039] Large number statistics unit 41: Its core function is to calculate the difference in counter values ​​between two sampling points. Let the count value latched at the first sampling (corresponding to the start edge of the time interval to be measured) be CNT1, and the count value latched at the second sampling (corresponding to the end edge of the time interval to be measured) be CNT2. The large number statistics unit 41 performs the operation "CNT2 – CNT1", and the result is the integer number of cycles m of the oscillation delay line 10 between the two samplings. This integer number of cycles corresponds to the "integer part" of the time interval to be measured.

[0040] Decimal Statistics Unit 42: Its core function is to calculate the fractional delay time based on the difference in delay line state data. First, it performs an XOR operation (DS2⊕DS1) on the two sampled and latched delay line state data DS1 (first sample) and DS2 (second sample). The number of "1"s in the XOR result directly reflects the phase difference of the signal transmission within the delay line during the two samples. The number of "1"s, k, in the XOR result is obtained through a popcount operation (counting the number of "1"s in a binary number). The product of this k value and the single-stage inverter delay time Δt is the "fractional part" of the time interval to be measured.

[0041] The time interval calculation formula: Combining large and small number statistics, the calculation formula for the time interval T is "T = m × 1.86ns + k × 30ps", where 1.86ns is the natural period of the oscillation delay line, and 30ps is the average delay time of the single-stage inverter. To verify the accuracy of this scheme, a standard time interval test was conducted: a standard time interval signal of 200ns was input, and after measurement and calculation by this circuit, the error was only 0.06ns, meeting the design requirement of 0.1% accuracy, proving the accuracy and reliability of this calculation method.

[0042] Please see Figure 4 This is a schematic diagram of the oscillation delay chain disclosed in an embodiment of the present invention. The transmission gate TG serves as the control switch for loop on / off, employing a complementary NMOS and PMOS structure, wherein the aspect ratio of both the NMOS and PMOS is designed to be 1μm / 40nm. Through process simulation and actual measurement, the on-resistance of this transmission gate is approximately 200Ω, ensuring effective signal transmission within the loop; the leakage current in the off state is less than 10pA, providing a guarantee for achieving low-power design.

[0043] Logic gate circuits: including one NAND gate G0 and 31 AND gates G1~G31, all using devices from the standard digital logic cell library to ensure compatibility with existing digital processes. During the layout design phase, the cascaded wiring of G1~G31 is optimized for length matching to ensure that the "0" level signal maintains monotonic propagation characteristics on the traveling wavefront in the gate circuit chain, avoiding signal distortion caused by wiring delay differences and ensuring the stability of loop oscillations.

[0044] Please see Figure 5 This is a schematic diagram of the oscillation delay line start-up control process disclosed in an embodiment of the present invention.

[0045] 1. Trigger signal generation: When the signal under test TIN has a rising edge (i.e., the trigger moment at point a), the TRIG signal output by the edge signal processing module 30 jumps from low level to high level (TRIG=1). This high-level signal controls the transmission gate TG to turn on, so that the logic gate circuit chain forms a closed loop path.

[0046] 2. Initial signal transition: After the transmission gate TG is turned on, both input signals of the NAND gate G0 are temporarily high. According to the logic characteristics of the NAND gate, its output signal transitions from high to low. This low-level signal is input to the CK terminal of counter 20, causing the counter's clock signal to generate its first falling edge, and the counter performs an addition operation (count +1).

[0047] 3. Loop Oscillation Start-up: The low-level signal output from NAND gate G0 is input to the subsequent AND gate G1. G1 receives the low-level signal and outputs a low level. This low-level signal is then passed sequentially to G2~G31, causing the output states of the 31 AND gates to flip sequentially. When the output signal of G31 is fed back to the input of NAND gate G0, one signal loop transmission is completed. Subsequently, the signal continues to flip within the closed loop, and the oscillation delay line officially enters a stable oscillation state.

[0048] Please see Figure 6 This is a schematic diagram of the oscillation delay line cessation control process disclosed in an embodiment of the present invention.

[0049] 1. Trigger signal reset: When the test signal TIN has a falling edge (i.e., the trigger time at point b), the TRIG signal output by the edge signal processing module 30 jumps from high level to low level (TRIG=0), and the transmission gate TG is turned off under the control of the low level, cutting off the closed-loop path of the logic gate circuit chain.

[0050] 2. Loop Fast Oscillation Stop: After the transmission gate TG is turned off, one input signal of the NAND gate G0 is forced to a high level. Combined with the state of its other input signal, the output signal of G0 immediately jumps from a low level to a high level. At the same time, the input terminals of AND gates G1~G31 are all pulled up to a high level through pull-up resistors, so that the output state of all AND gates jumps to a high level. The oscillation process of the oscillation delay line stops immediately, avoiding power waste caused by invalid oscillation.

[0051] 3. Data Latching and Power Consumption Indicators: At the falling edge of the TRIG signal, the processing module 40 latches the final count value CNT of the latch counter 20 and the final state data DS of the oscillation delay line to complete a single time measurement. In the oscillation-off state, the static current of the entire circuit drops to 5μA, achieving the design goal of zero standby power consumption, making it suitable for low-power applications.

[0052] The accuracy of the large number statistics unit 41 was verified through specific experiments. The experimental scheme and results are as follows: Two pulse signals were generated using a high-precision signal generator, and the time interval between the two pulses was set to 960ns. This pulse signal was then used as the signal to be measured, TIN, and input to the circuit of this invention. Measurement results and calculations: After sampling and latching by the circuit, the difference in count values ​​between the two samples was obtained as m=516. Based on the structural parameters of the oscillating delay line, the theoretical time interval was calculated as "(31+1)×516×30ps=991ns". This result deviated from the set value by 31ns because the phase wrap-around phenomenon of the delay line state was not considered. The fractional number statistics unit 42 calculated k=-11 (the negative sign indicates phase wrap-around). After correction of the fractional part, the total time interval was "991ns + (-11)×30ps=960ns". The corrected measurement results were completely consistent with the actual measurement results of the oscilloscope, proving that the large number statistics method with phase wrap-around correction proposed in this invention is accurate and reliable, providing a guarantee for large dynamic range time measurement.

[0053] The accuracy of the decimal statistics unit 42 was verified through specific experiments. A high-precision pulse generator was used to generate pulse signals with minute time intervals, ensuring that the counter value remained unchanged between two samplings (i.e., m=0), and the decimal time interval was only reflected by the difference in the delay line state. During the first sampling (point a), the latched delay line state data DS1=32'h00000000 (i.e., all inverter outputs were low), and during the second sampling (point b), the latched delay line state data DS2=32'h0000000F (i.e., the lower 4 bits of the inverter output were high). After performing an XOR operation on DS1 and DS2, the number of "1"s was counted as k=4, and the decimal time interval was calculated as "4×30ps=120ps". Comparing this measurement result with the set value of the high-precision pulse generator, the error was only 0.01ns, proving that the calculation accuracy of the decimal statistics unit 42 can reach the picosecond level, meeting the requirements of high-resolution time measurement.

[0054] This embodiment discloses the calibration method and temperature compensation strategy of the circuit of the present invention to reduce the impact of process, voltage, and temperature (PVT) fluctuations on measurement accuracy, as described below:

[0055] Factory calibration: A 100MHz TCXO (temperature-compensated crystal oscillator) was used as the reference clock signal to calibrate the single-stage delay time Δt of the oscillation delay line. The temperature coefficient of Δt was measured to be 0.12ps / ℃ after calibration, and this data is stored in the on-chip non-volatile memory as the basic parameter for temperature compensation.

[0056] On-chip temperature monitoring: It integrates a high-resolution temperature sensor with a temperature measurement resolution of 0.5℃, which can collect the chip's operating temperature in real time and transmit the temperature data to the control unit.

[0057] Dynamic temperature compensation: The control unit reads temperature sensor data every 100ms and updates the correction coefficient calculated over the time interval in real time, based on the factory-calibrated Δt temperature coefficient. Testing showed that within the industrial temperature range of -40℃ to 85℃, this compensation strategy reduced the circuit's maximum measurement error from ±2% to ±0.3%, significantly improving temperature drift characteristics.

[0058] Please see Figure 7 This is a schematic diagram of a microprocessor chip disclosed in an embodiment of the present invention. This application also provides a microprocessor chip for executing the aforementioned clock measurement circuit. For example, the microprocessor chip may be a microcontroller unit (MCU), a digital signal processor (DSP), a microprocessor unit (MPU), a micro CPU (Central Processing Unit), or other micro-central control chips or system-on-a-chips capable of processing digital signals, analog signals, or performing signal functions, instruction processing, and computation.

[0059] The specific implementation process of the clock measurement circuit 701 included in the microprocessor chip 700 can be found in the above method embodiments, and its implementation principle and technical effect are similar, so it will not be repeated here. In the above embodiments, it should be understood that the microprocessor chip 700 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the invention can be directly embodied in the execution of hardware processors, or can be executed by a combination of hardware and software units in the processor. The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0060] The storage unit can be a readable storage medium, implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0061] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device. The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through interfaces, devices, or units, and may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate; components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0062] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0063] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0064] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0065] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A time measurement circuit, characterized in that, include: A logic pass loop includes an oscillation delay line, which is composed of N sequentially connected timing delay elements and logic gates forming a closed loop, used to provide the captured fractional part; A counter, coupled to the oscillation delay line, is used to record in real time the number of complete cycles of the closed-loop oscillation of the oscillation delay line to provide the large number portion of the captured data; An edge signal processing module, one end of which is connected to the first input terminal of the processing module, and the other end receives the input signal to be tested, and is used to output a capture trigger signal to the oscillation delay line through the processing module when an edge signal is detected; The processing module has its second input terminal connected to the oscillation delay line and its third input terminal connected to the counter. It is used to read and save the output signals of each logic gate of the oscillation delay line and the counter when the capture trigger signal is received.

2. The time measurement circuit according to claim 1, characterized in that, The capture trigger signal is connected to the first input terminal of the NAND gate via a switch. The first input terminal of the first AND gate is connected to the output terminal of the NAND gate. The output terminal of the NAND gate is also connected to the counter. The first input terminals of each subsequent AND gate are sequentially connected to the output terminal of the previous AND gate. The output terminal of the Nth AND gate is fed back to the NAND gate through the switch.

3. The time measurement circuit according to claim 2, characterized in that, When the first edge of the waveform under test is detected, a first trigger signal of logic "1" is output, the switch is turned on, the NAND gate outputs "1" to activate the logic propagation loop, the first AND gate outputs "1" and propagates it to the next level, the second input of the NAND gate receives "0" and outputs "0", the first input of the first AND gate receives "0" and outputs "0" and continues to propagate "0" to the next level.

4. The time measurement circuit according to claim 3, characterized in that, When the second edge of the waveform under test is detected, a second trigger signal of logic "0" is output, the switch is turned off, and the output terminals of the NAND gate and N AND gates are set to "1".

5. The time measurement circuit according to claim 1, characterized in that, The logic transmission loop also includes a time measurement module, which consists of a large number statistics unit and a small number statistics unit.

6. The time measurement circuit according to claim 5, characterized in that, The large number statistics unit is used to calculate the difference between the two counter values ​​to obtain the integer time difference.

7. The time measurement circuit according to claim 5, characterized in that, The fractional statistics unit is used to calculate the fractional time difference based on the difference in the output state of each delay unit of the oscillation delay line during two samplings.

8. The time measurement circuit according to any one of claims 5 to 7, characterized in that, The large number statistics unit counts the number of changes of "0" and "1" through the counter. If the transmission time of each logic gate is Δt and the count value is m, then the large number part of the time interval is (N+1)×m×Δt.

9. The time measurement circuit according to any one of claims 5 to 7, characterized in that, The fractional statistics unit records the output numbers of each AND gate at the first edge point and the output numbers of each AND gate at the second edge point. Based on the difference in the number of "1"s in the two records, it adds a fractional time corresponding to the difference in the number of "1"s × Δt to the large part of the time interval, where Δt is the propagation time of each logic gate.

10. A microprocessor chip, characterized in that, Includes the time measurement circuit as described in any one of claims 1-9.

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