Driving time sequence control method of short-wave infrared area array detector

Abstract

The invention discloses a driving time sequence control method for a short-wave infrared area array detector. The driving time sequence control method comprises the steps that RDN signals and DATA signals of the short-wave infrared area array detector are used for controlling gain adjustment line by line of the detector; wherein the RDN signal is a reset signal, and the DATA signal is a write-in control signal; the control time sequence of the line-by-line gain adjustment function of the short-wave infrared area array detector is as follows: after power-on, an RDN signal is at a low level, and is adjusted to a high level after being kept for at least T1 clocks; the DATA signal is allowed to be written into the row selection and row gain control signal only after the RDN signal is adjusted to the high level for at least T2 clocks. According to the invention, high-dynamic-range atmospheric humidity detection of different height layers can be realized in the same frame of image.

Description

Technical Field

[0001] This invention relates to the field of detector driving timing control technology, specifically a driving timing control method for a shortwave infrared array detector. Background Technology

[0002] Atmospheric humidity detectors are carried on satellite platforms to detect atmospheric humidity, typically using short-wavelength infrared detectors in the 1363–1368 nm band. Because the humidity profile signal intensity has a large dynamic range (approximately three orders of magnitude) at different altitudes, and humidity data from different altitudes are simultaneously imaged within the same frame, the energy differences between different spectral bands detected by the detector are very large. Limited by detector performance, effective measurements cannot be performed over a wide range of light intensity variations.

[0003] Current shortwave infrared detectors do not have the function of adjusting the gain line by line. They can only modify the gain of the entire image between the previous and next frames, and cannot achieve the function of adjusting the gain line by line within the same frame.

[0004] Existing shortwave infrared detectors drive timing pulses such as Figure 1 As shown, it mainly consists of two stages. First, exposure is performed, during which the RESET signal outputs a high level. SH1 is high because it represents the sampling time of the reference level VOUTR, and SH2 is high because it represents the sampling time of the signal level VOUTS. The actual signal is obtained by subtracting the reference level from the signal level. The second stage is pixel readout, which includes the control of signals such as the column clock signal (CLKCOL), row clock signal (CLKROW), row trigger clock signal (STROW), row / column trigger signal (STROWCOL), column operational amplifier trigger signal (STCOLOP), and column trigger signal (STCOL).

[0005] An existing invention patent with patent application number CN111273311A discloses a laser three-dimensional focal plane array imaging system. This patent uses a pixel-level time information measurement array, and each pixel uses snapshot integration. All pixels in the array are integrated simultaneously, and the time signal is converted before being output. It uses an intensity information measurement circuit with independent rows and multiplexed columns to convert and output the intensity signal column by column. However, the patent is in the field of laser imaging, not short-wave infrared imaging, and the row selection and column selection refer to the laser three-dimensional imaging readout circuit, not the row selection signal of the detector. An invention patent with patent application publication number CN109714545A discloses a high-speed hyperspectral imager image processing system. In this patent, the grayscale value is calculated for the already stored image, and then the gain of the entire image of the next image is adjusted, instead of adjusting row by row within the same image. Summary of the Invention

[0006] The technical problem to be solved by this invention is to solve the current problem that it is impossible to achieve large dynamic range detection of atmospheric humidity at different altitudes using the same frame image.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A driving timing control method for a shortwave infrared array detector includes: using the RDN signal and DATA signal of the shortwave infrared array detector to control the line-by-line gain adjustment of the detector; wherein, the RDN signal is a reset signal and the DATA signal is a write control signal; The control timing sequence for the line-by-line gain adjustment function of the shortwave infrared array detector is as follows: After power-on, the RDN signal is at a low level and remains there for at least T1 clock cycles before being adjusted to a high level. The DATA signal is only allowed to be written to the row select and row gain control signals after the RDN signal has been adjusted to a high level for at least T2 clock cycles.

[0008] In this embodiment, DATA[767:512] of the DATA signal is used to control whether each row is selected. High indicates selection and can be read out in sequence; low indicates no selection and is skipped when reading. Among them, DATA

[767] represents the strobe signal of the 1st row, DATA

[512] represents the strobe signal of the 256th row, and so on. The DATA[511:0] signal is used to control the gain of each row. The gain of each row is controlled by two signals. DATA[511:510] represents the gain control signal of the first row, DATA[1:0] represents the gain control signal of the 256th row, and so on.

[0009] In this embodiment, the control timing of the line-by-line gain adjustment function of the shortwave infrared array detector is driven by a state machine; the state transition of the state machine is achieved by the change of the counter and the generation of various signals. The state transitions of the state machine are controlled by changes in counters, which trigger jumps and generate various signals. A master counter clkrow_cnt is set as a reference, and the time for each count is tus. When the sampling enable imaging signal sample_en arrives, the master counter clkrow_cnt is counted. Then, the transition of each state and the generation of each signal are realized according to the count of the master counter clkrow_cnt.

[0010] In this embodiment, the transitions between states and the generation of signals are implemented based on the count of the main counter clkrow_cnt, including: The ST0 state machine is in the initial state, and all signals are in the initial state. When the start imaging signal sample_en arrives, the state machine jumps from the ST0 state to the ST1 state. The ST1 state machine is used to generate a high level for RDN; after the low level RDN signal is held for at least T1 clock cycles, it is adjusted to a high level and jumps to the ST2 state. State machine ST2 is used to write the row selection signal and the row gain control signal; after completion, it jumps to state machine ST3. The ST3 state machine is used to pull the RESET signal high. After completion, it jumps to the ST4 state machine. ST5 state machine is used to pull the SH2 signal and RESET signal low to complete the transition to state machine ST6; ST6 state machine is used to generate the row trigger clock signal STROW high-level pulse, and after completion, it jumps to state machine ST7; State machine ST7 is used to start outputting pixels, and after completion, it jumps to state machine ST8; The ST8 state machine is used to wait for the line data transmission to complete. After receiving the end prompt, it jumps back to the ST0 state and starts the imaging control of the next frame image.

[0011] In this embodiment, the jump to state machine ST2 includes: When the main counter clkrow_cnt counts to 69, the clock signal CLKCOL is inverted; when the main counter clkrow_cnt counts to 140, it is cleared to zero. At this time, it is a complete row trigger clock signal CLKROW cycle, and the system jumps to ST2 state.

[0012] In this embodiment, the jump to state machine ST3 includes: After waiting for 67 clock signal CLKCOL cycles, the rising edge of the clock signal CLKCOL begins writing the flag bit 11011, followed by writing the strobe signals for rows 1 to 256 and the 512-bit gain signal. When the main counter clkrow_cnt counts to 69, the clock signal CLKCOL is inverted. When the main counter clkrow_cnt counts to 139 and the row counter data_cnt counts to 12, the process jumps to state machine ST3.

[0013] In this embodiment, the jump to state machine ST4 includes: When the main counter clkrow_cnt counts to 69, the clock signal CLKCOL is inverted; when the main counter clkrow_cnt counts to 139, the RESET signal is pulled high, and the process jumps to state machine ST4.

[0014] In this embodiment, the jump to state machine ST5 includes: When the main counter clkrow_cnt counts to 69, the clock signal CLKCOL is inverted; when it counts to 140, it is reset to zero. At the same time, the column clock signal counter cnt is counted. When the column clock signal counter cnt counts to 9, SH1 is pulled high. When the column clock signal counter cnt counts to 59, SH1 is pulled low. When the column clock signal counter cnt counts to the set exposure time, the column clock signal counter cnt counts to zero, SH2 is pulled high, and the process jumps to state machine ST5.

[0015] In this embodiment, the jump to state machine ST6 includes: When the main counter clkrow_cnt counts to 69, the clock signal CLKCOL is inverted; at the same time, the column clock signal counter cnt is counted. When the column clock signal counter cnt counts to 49, SH2 is pulled low; when the column clock signal counter cnt counts to 59, RESET is pulled low; when the main counter clkrow_cnt counts to 139, the process jumps to state machine ST6.

[0016] In this embodiment, the jump to state machine ST7 includes: When the master counter clkrow_cnt reaches 69, the clock signal CLKCOL is inverted. When the master counter clkrow_cnt reaches 139, the counter is cleared, and the row counter stcol_cnt is incremented by 1. When the master counter clkrow_cnt reaches 139 and the row counter stcol_cnt reaches 256, the output of 256 rows of pixels ends, and the process jumps to state machine ST8.

[0017] Compared with the prior art, the beneficial effects of the present invention are: This invention employs a short-wave infrared detector with line-by-line adjustable gain and designs a specific timing control method using the Verilog hardware description language. This enables large dynamic range adjustment within a single frame, facilitating atmospheric humidity detection at different altitudes. Ultimately, it allows for high dynamic range atmospheric humidity detection at different altitudes within the same image frame. Attached Figure Description

[0018] Figure 1 This is a typical timing diagram for driving a shortwave infrared detector.

[0019] Figure 2 This is a control timing flowchart for the line-by-line gain adjustment function of the shortwave infrared array detector in an embodiment of the present invention.

[0020] Figure 3 This is a timing diagram of the detector drive according to an embodiment of the present invention.

[0021] Figure 4This is a schematic diagram of the detector line-by-line gain adjustment control timing in an embodiment of the present invention.

[0022] Figure 5 This is a state transition diagram for the state machine implementation of the detector driving timing control method in an embodiment of the present invention. Detailed Implementation

[0023] To facilitate understanding of the technical solution of the present invention by those skilled in the art, the technical solution of the present invention will now be further described in conjunction with the accompanying drawings.

[0024] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0025] Please see Figures 2 to 5 As shown, this invention also provides a driving timing control method for a shortwave infrared array detector, comprising: using the RDN signal and DATA signal of the shortwave infrared array detector to control the line-by-line gain adjustment of the detector, wherein the RDN signal is a reset signal and the DATA signal is a write control signal. Furthermore, the control timing of the line-by-line gain adjustment function of the shortwave infrared array detector is as follows: after power-on, the RDN signal is at a low level, remains low for at least T1 clock cycles, and then is adjusted to a high level. The DATA signal is only allowed to write the line selection and line gain control signals after the RDN signal has been adjusted to a high level for at least T2 clock cycles.

[0026] In this embodiment, the shortwave infrared array detector is a 1024*256 scale shortwave infrared detector with a response band of 0.95um~1.65um, a pixel size of 30um, and a saturated output voltage of 1.6V.

[0027] like Figure 3 The diagram shown is the timing diagram for driving this detector. Unlike previous shortwave infrared detectors, this detector has two signals, RDN and DATA, used to control the line-by-line gain adjustment. The RDN signal is the write reset signal, and the DATA signal is the write control signal.

[0028] Figure 4The diagram shows the control timing for the progressive scan gain adjustment function of this detector. After power-on, the RDN signal is low and remains low for at least two clock cycles before being adjusted to a high level. The DATA signal is only allowed to write command words (i.e., write the row select and row gain control signals) after the RDN signal has been high for at least three clock cycles. The first 768 bits after the initial read flag 11011 are the valid row select and row gain control signals. If the row select and row gain states are not refreshed, a re-reset and rewriting is not required.

[0029] The DATA signal, consisting of DATA[767:512], comprises 256 bits and is used to control whether each row is selected. A high value indicates selection, and rows can be read sequentially; a low value indicates no selection, and rows are skipped during reading. Specifically, DATA

[767] represents the strobe signal for the 1st row, DATA

[512] represents the strobe signal for the 256th row, and so on.

[0030] The DATA signal, DATA[511:0], consists of 512 bits and is used to control the gain of each row. The gain of each row is controlled by two bits, where DATA[511:510] represents the gain control signal for the first row, DATA[1:0] represents the gain control signal for the 256th row, and so on.

[0031] In this embodiment, the gain adjustment for each row of the detector has 4 levels, and the corresponding integrating capacitors are shown in Table 1 below.

[0032] Table 1. Integrating capacitance corresponding to detector gain

[0033] In this embodiment, an FPGA (programmable logic device) is selected to generate the driving waveform to enable the detector to operate normally. The FPGA program is designed using the Verilog hardware description language. The driving timing control is implemented using a state machine, such as... Figure 5 As shown, the state machine has a total of 9 states, from ST0 to ST8, and the transition between states is achieved by changing the counter.

[0034] In this embodiment, an FPGA is selected to generate the driving waveform to enable the detector to operate normally, and the FPGA program is designed using the Verilog hardware description language. The driving timing control is implemented using a state machine, such as... Figure 5As shown, the state machine has 9 states, from ST0 to ST8. State transitions are achieved through counter changes. Specifically, a master counter `clkrow_cnt` is set as a reference, with each count taking 1µs. When the sampling enable signal (imaging signal `sample_en`) arrives, the master counter `clkrow_cnt` is incremented. The transitions between states and the generation of signals are then determined based on the count of `clkrow_cnt`.

[0035] In this embodiment, the ST0 state machine is in the initial state, and all signals are in the initial state. When the imaging start signal sample_en arrives, the state machine jumps from the ST0 state to the ST1 state.

[0036] In this embodiment, the ST1 state machine generates a high level for RDN. Since the detector datasheet requires the RDN signal to be low after power-on and remain low for at least two clock cycles before being adjusted to high, this is achieved by counting the main counter clkrow_cnt. When the main counter clkrow_cnt reaches 69, the clock signal CLKCOL is inverted. When the main counter clkrow_cnt reaches 69, the RDN signal is pulled high. The main counter clkrow_cnt is reset to zero when it reaches 140, marking one complete row trigger clock cycle (CLKROW), at which point the process jumps to the ST2 state.

[0037] In this embodiment, the ST2 state machine is used to write the row strobe signal and the row gain control signal. Since the DATA signal consists of 5 flag bits and 768 data bits (773 bits in total), one bit of DATA data is written for each clock signal CLKCOL cycle. One row trigger clock signal CLKROW cycle is 70 clock signal CLKCOL cycles, therefore it is designed to be implemented using 12 row trigger clock signal CLKROW cycles. The implementation method is also achieved through clkrow_cnt counting. After waiting for 67 clock signal CLKCOL cycles, the rising edge of the clock signal CLKCOL begins writing the flag bit 11011, followed by the continuous writing of the 1st to 256th row strobe signals and the 512-bit gain signal. When the main counter clkrow_cnt counts to 69, the clock signal CLKCOL is inverted. When the main counter clkrow_cnt counts to 139 and the row counter data_cnt counts to 12, the process jumps to state machine ST3.

[0038] In this embodiment, the ST3 state machine functions to pull the RESET signal high. Specifically, it counts the main counter clkrow_cnt; when the main counter clkrow_cnt reaches 69, it inverts the clock signal CLKCOL. When the main counter clkrow_cnt reaches 139, it pulls the RESET signal high and jumps to state machine ST4.

[0039] In this embodiment, the ST4 state machine is used to generate the detector's exposure time. Specifically, it counts the main counter clkrow_cnt. When the main counter clkrow_cnt counts to 69, it inverts the clock signal CLKCOL. It resets to zero when it reaches 140. Simultaneously, it counts the column clock signal counter cnt. When the column clock signal counter cnt counts to 9, it pulls SH1 high (high level is the reference level VOUTR sampling time). When the column clock signal counter cnt counts to 59, it pulls SH1 low (signal level VOUTS sampling time). When the column clock signal counter cnt counts to the set exposure time, it resets to zero, pulls SH2 high, and jumps to state machine ST5.

[0040] In this embodiment, the ST5 state machine functions to pull the SH2 and RESET signals low. Specifically, it counts the main counter clkrow_cnt; when the main counter clkrow_cnt reaches 69, it inverts the clock signal CLKCOL. Simultaneously, it counts the column clock signal cnt; when the column clock signal cnt reaches 49, it pulls SH2 low, and when the column clock signal cnt reaches 59, it pulls RESET low. When the main counter clkrow_cnt reaches 139, it jumps to state machine ST6.

[0041] In this embodiment, the ST6 state machine is used to generate a high-level pulse for the row trigger clock signal STROW. Specifically, it counts the main counter clkrow_cnt. When the main counter clkrow_cnt counts to 69, it inverts the clock signal CLKCOL. When the main counter clkrow_cnt counts to 105, it pulls the row trigger clock signal STROW high. When the main counter clkrow_cnt counts to 139, it jumps to state machine ST7.

[0042] In this embodiment, the ST7 state machine is used to start outputting pixels. Specifically, it counts the main counter clkrow_cnt. When the main counter clkrow_cnt reaches 69, the CLKCOL signal is inverted. When the main counter clkrow_cnt reaches 139, the count is cleared, and the row count stcol_cnt is incremented by 1. When both the main counter clkrow_cnt and the row count stcol_cnt reach 256, the output of 256 rows of pixels ends, and the process jumps to state machine ST8.

[0043] In this embodiment, the ST8 state machine waits for the line data transmission to complete, and upon receiving an end notification, jumps back to the ST0 state to begin the imaging control for the next frame. Specifically, upon receiving `work_end==1'b1`, it jumps back to the ST0 state and begins the imaging control for the next frame.

[0044] Among them, the RDN signal, DATA signal, RESET signal, SH1 signal, SH2 signal, and STROW signal mentioned above are all signals in the detector drive timing sequence. The sample_en signal is the imaging start signal, which is input from the outside (host computer software).

[0045] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0046] The above embodiments are merely examples of implementation methods of the invention. The scope of protection of the present invention is not limited to the above embodiments. For those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A method of driving timing sequence control of a short-wave infrared focal plane array detector, characterized in that, The application relates to a short-wave infrared (SWIR) area array detector, and particularly relates to a control method of a row-by-row gain adjustment function of the SWIR area array detector. The RDN signal and the DATA signal of the short-wave infrared area array detector are used to control the row-by-row gain adjustment of the detector; wherein the RDN signal is a reset signal, and the DATA signal is a write control signal. The control timing of the row-by-row gain adjustment function of the short-wave infrared area array detector is as follows: After power-on, the RDN signal is low, and is adjusted to high after keeping for at least T1 clocks; The DATA signal is allowed to write the row selection and row gain control signals only after the RDN signal is adjusted to high for at least T2 clocks.

2. The method of driving timing control of a short-wave infrared focal plane array detector according to claim 1, wherein, DATA[767:512] of the DATA signal is used to control whether each row is selected, and is high to indicate selection and can be read out in sequence; and is low to indicate non-selection and is skipped during reading; wherein DATA[767] represents the first row selection signal, DATA[512] represents the 256th row selection signal, and the like. DATA[511:0] of the DATA signal is used to control the gain of each row, and the gain of each row is controlled by two signals, wherein DATA[511:510] represents the gain control signal of the first row, DATA[1:0] represents the gain control signal of the 256th row, and the like.

3. The method of claim 1, wherein the method further comprises: The control timing of the row-by-row gain adjustment function of the short-wave infrared area array detector is driven by using a state machine; the state transition of the state machine is realized by changing a counter to jump and generate signals. The state transition of the state machine is realized by changing a counter to jump and generate signals, and includes the following steps: A main counter clkrow_cnt is set as a reference, each time counting is tus, when a sample enable imaging signal sample_en arrives, the main counter clkrow_cnt is counted, and then the state jump and signal generation of each state are realized according to the counting of the main counter clkrow_cnt.

4. The method of driving timing control of a short-wave infrared focal plane array detector according to claim 3, wherein, The state jump and signal generation of each state are realized according to the counting of the main counter clkrow_cnt, and include the following steps: The ST0 state machine is an initial state, all signals are in the initial state, and when a start imaging signal sample_en arrives, the state machine jumps from the ST0 state to the ST1 state; The ST1 state machine is used to generate the RDN high level; when the low-level RDN signal is kept for at least T1 clocks, the RDN signal is adjusted to high, and jumps to the ST2 state; The ST2 state machine is used to complete the row selection signal and the row gain control signal write-in; and jumps to the ST3 state machine after completion; The ST3 state machine is used to pull up the RESET signal, and jumps to the ST4 state machine after completion; The ST5 state machine is used to pull down the SH2 signal and the RESET signal, and jumps to the ST6 state machine after completion; The ST6 state machine is used to generate the row trigger clock signal STROW high level pulse, and jumps to the ST7 state machine after completion; The ST7 state machine is used to start outputting the image element, and jumps to the ST8 state machine after completion; The ST8 state machine is used to wait for the row data transmission to be completed, and jumps back to the ST0 state after receiving an end prompt to start the next frame image imaging control.

5. The method of driving timing control of a short-wave infrared focal plane array detector according to claim 4, wherein, Jumping to the ST2 state machine includes the following steps: The clock signal CLKCOL is reversed when the main counter clkrow_cnt counts to 69; the main counter clkrow_cnt is cleared when it counts to 140, which is a complete row trigger clock signal CLKROW period, and jumps to the state machine ST2.

6. The method of claim 4, wherein the method further comprises: Jump to the state machine ST3, including: After waiting for 67 clock signal CLKCOL periods, the flag bit 11011 is written at the rising edge of the clock signal CLKCOL, followed by the continuous writing of the 1st-256 row gate signals and 512-bit gain signals. The clock signal CLKCOL is reversed when the main counter clkrow_cnt counts to 69; when the main counter clkrow_cnt counts to 139 and the row counter data_cnt counts to 12, jump to the state machine ST3.

7. The method of claim 4, wherein the method further comprises: Jump to the state machine ST4, including: The clock signal CLKCOL is reversed when the main counter clkrow_cnt counts to 69; the RESET signal is pulled high when the main counter clkrow_cnt counts to 139, and jumps to the state machine ST4.

8. The method of claim 4, wherein the method further comprises: Jump to the state machine ST5, including: The clock signal CLKCOL is reversed when the main counter clkrow_cnt counts to 69; the counter cnt is counted when the main counter clkrow_cnt counts to 140 and is cleared, the SH1 is pulled high when the column clock signal counter cnt counts to 9, and the SH1 is pulled low when the column clock signal counter cnt counts to 59; the column clock signal counter cnt is cleared when it counts to the set exposure time, the SH2 is pulled high, and jumps to the state machine ST5.

9. The method of claim 4, wherein the method further comprises: Jump to the state machine ST6, including: The clock signal CLKCOL is reversed when the main counter clkrow_cnt counts to 69; the counter cnt is counted when the main counter clkrow_cnt counts to 140 and is cleared, the SH1 is pulled high when the column clock signal counter cnt counts to 9, and the SH1 is pulled low when the column clock signal counter cnt counts to 59; the column clock signal counter cnt is cleared when it counts to the set exposure time, the SH2 is pulled high, and jumps to the state machine ST5.

10. The method of claim 4, wherein the method further comprises: Jump to the state machine ST7, including: The clock signal CLKCOL is reversed when the main counter clkrow_cnt counts to 69; the counter cnt is counted when the main counter clkrow_cnt counts to 140 and is cleared, the SH1 is pulled high when the column clock signal counter cnt counts to 9, and the SH1 is pulled low when the column clock signal counter cnt counts to 59; the column clock signal counter cnt is cleared when it counts to the set exposure time, the SH2 is pulled high, and jumps to the state machine ST5. Jump to the state machine ST8, including: The clock signal CLKCOL is reversed when the main counter clkrow_cnt counts to 69; the counter cnt is counted when the main counter clkrow_cnt counts to 140 and is cleared, the SH1 is pulled high when the column clock signal counter cnt counts to 9, and the SH1 is pulled low when the column clock signal counter cnt counts to 59; the column clock signal counter cnt is cleared when it counts to the set exposure time, the SH2 is pulled high, and jumps to the state machine ST5.

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