Anti-overshoot auxiliary circuit, voltage regulator and anti-overshoot method

Abstract

The invention provides an anti-overshoot auxiliary circuit, a voltage regulator and an anti-overshoot method. The auxiliary circuit comprises a voltage sensing unit, a delay reference unit, an anti-undershoot unit and an anti-upshoot unit. The voltage induction unit rapidly induces the voltage change of the output end of the voltage regulator through capacitive coupling and generates an induced voltage signal. The delay reference unit performs RC delay processing on the induced voltage signal to generate a slowly changing delay reference signal. The undershoot prevention unit and the upshoot prevention unit respectively compare the induced voltage signal with the delay reference signal, and when voltage undershoot is detected, pull-up operation is carried out on the grid electrode of the main adjusting transistor; and when voltage uprush is detected, pull-down operation is carried out. According to the voltage regulator, when the load transients, the main regulation transistor is instantaneously controlled before the main loop, so that the overshoot and undershoot of the output voltage are effectively inhibited, and the transient response performance of the voltage regulator and the reliability of the system are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to an anti-overshoot auxiliary circuit, a voltage regulator and an anti-overshoot method. BACKGROUND

[0002] A voltage regulator is a widely used basic component in electronic systems, which mainly provides a stable and accurate DC voltage for a load. To better understand the technical background of the present application, please refer to Figure 1 which shows a conventional NMOS-driven voltage regulator. The regulator mainly includes an error amplifier, a main regulating transistor (or called adjusting tube) MN1 and a feedback network composed of resistors R1 and R2. In operation, the feedback network samples the output voltage VOUT by voltage division, and compares the sampled voltage with a reference voltage VREF in the error amplifier. The error amplifier outputs a control voltage according to the comparison result, which is used to drive the gate of the main regulating transistor MN1. Through this negative feedback main loop, the regulator can stabilize the output voltage VOUT at a preset value under static or slowly changing load conditions.

[0003] However, in modern integrated circuits, the load current may change dramatically in a very short time, for example, from the microampere (μA) level to the milliampere (mA) level or vice versa within microseconds (μs). Such transient changes in load current pose a severe challenge to the dynamic performance, i.e. transient response, of the voltage regulator.

[0004] Ideally, the output voltage of the voltage regulator should remain constant regardless of the changes in load current. However, in practical applications, due to the limitations of factors such as Figure 1 the bandwidth of the main feedback loop of the voltage regulator, power consumption and chip area, as shown in the figure, its response speed is limited. When the load current suddenly increases, the output voltage will instantaneously decrease, forming an "undershoot"; when the load current suddenly decreases, the output voltage will instantaneously increase, forming an "overshoot".

[0005] The overshoot and undershoot of the output voltage will have serious adverse effects. Excessive voltage undershoot may be lower than the minimum operating voltage of other circuit modules in the system, or even trigger the power-down reset of the system, causing abnormal operation or crash of the system. Excessive voltage overshoot may exceed the voltage withstand limit of downstream circuit devices, triggering the latch-up effect or permanent damage, seriously affecting the reliability and life of the system.

[0006] With the continuous advancement of semiconductor technology, the operating voltage of chips is decreasing, for example from 5V and 3.3V to 1.8V, 1.2V, and even lower. This reduces the tolerance of circuit systems to power supply voltage fluctuations (i.e., voltage margin). Therefore, effectively suppressing voltage overshoot and undershoot during transient response under limited voltage margin has become a key technical challenge in voltage regulator design.

[0007] Therefore, there is an urgent need in the existing technology for a circuit and method that can quickly respond to load transients and effectively reduce overshoot and undershoot of output voltage, such as that of traditional voltage regulators, in order to improve the stability and reliability of the system. Summary of the Invention

[0008] The purpose of this application is to provide an overshoot prevention auxiliary circuit for a voltage regulator, a voltage regulator including the auxiliary circuit, and an overshoot prevention method, aiming to solve the technical problem in the prior art that the voltage regulator has a large output voltage overshoot and undershoot due to slow transient response.

[0009] To achieve the above objectives, this application provides an overshoot protection auxiliary circuit for a voltage regulator. The voltage regulator includes a main regulating transistor, the gate of which receives a gate voltage, and the voltage regulator has an output terminal. The overshoot protection auxiliary circuit includes:

[0010] The voltage sensing unit has its input and output terminals capacitively coupled and is used to generate an induced voltage signal based on the voltage change at the output terminal.

[0011] The delay reference unit, connected to the output of the voltage sensing unit, is used to delay the induced voltage signal to generate at least one delay reference signal.

[0012] An undershoot protection unit, connected to the voltage sensing unit and the delay reference unit, is used to pull up the gate voltage of the main regulating transistor based on the comparison result between the sensing voltage signal and the delay reference signal when the voltage at the output terminal indicated by the sensing voltage signal drops; and

[0013] The overshoot prevention unit, connected to the voltage sensing unit and the delay reference unit, is used to pull down the gate voltage of the main regulating transistor based on the comparison result between the sensing voltage signal and the delay reference signal when the voltage at the output terminal of the sensing voltage signal rises.

[0014] Preferably, the delay reference unit includes at least one resistor-capacitor filter circuit consisting of resistors and capacitors.

[0015] Preferably, the delay reference unit includes:

[0016] a first resistive-capacitive filter circuit, an input terminal of which is connected to the node of the induced voltage signal, and an output terminal of which is configured to provide a first delayed reference signal; and

[0017] a second resistive-capacitive filter circuit, an input terminal of which is connected to the node of the induced voltage signal, and an output terminal of which is configured to provide a second delayed reference signal.

[0018] Preferably, the resistance of the first resistive-capacitive filter circuit and the resistance of the second resistive-capacitive filter circuit have substantially the same resistance value; and the capacitance of the first resistive-capacitive filter circuit and the capacitance of the second resistive-capacitive filter circuit have substantially the same capacitance value.

[0019] Preferably, the under-shoot prevention unit comprises:

[0020] a first NMOS transistor, a gate of which receives the induced voltage signal;

[0021] a second NMOS transistor, a gate of which receives the first delayed reference signal;

[0022] a first PMOS transistor and a second PMOS transistor configured as a first current mirror, the first PMOS transistor being a load of the first NMOS transistor, an output terminal of the first current mirror generating a first control signal; and

[0023] a switch PMOS transistor, a gate of which receives the first control signal, for pulling up a gate of a main regulation transistor.

[0024] Preferably, the delayed reference unit further comprises:

[0025] a third resistive-capacitive filter circuit, an input terminal of which is connected to a common drain node of the first PMOS transistor and the first NMOS transistor, and an output terminal of which is configured to provide a third delayed reference signal.

[0026] Preferably, the resistance value of the resistance of the third resistive-capacitive filter circuit is substantially the same as the resistance value of the first and second resistive-capacitive filter circuits; and the capacitance value of the capacitance of the third resistive-capacitive filter circuit is substantially the same as the capacitance value of the first and second resistive-capacitive filter circuits.

[0027] Preferably, the over-shoot prevention unit comprises:

[0028] a third NMOS transistor, a gate of which receives the second delayed reference signal;

[0029] a third PMOS transistor, a gate of which receives the third delayed reference signal, a drain of the third NMOS transistor and a drain of the third PMOS transistor being connected to an output node to generate a second control signal; and

[0030] A pull-down circuit, the pull-down circuit receiving a second control signal for pulling down a gate of the main regulation transistor.

[0031] Preferably, the second PMOS transistor and the third PMOS transistor each have a size K times that of the first PMOS transistor.

[0032] Preferably, the pull-down circuit comprises:

[0033] A fourth PMOS transistor and a fourth NMOS transistor, each having a gate connected to the output node; and

[0034] A fifth NMOS transistor having a gate driven by a common drain node of the fourth PMOS transistor and the fourth NMOS transistor, and a drain connected to the gate of the main regulation transistor.

[0035] Preferably, further comprising a biasing unit, the biasing unit comprising:

[0036] A first biasing transistor and a second biasing transistor for receiving a first biasing current to generate a biasing voltage; and

[0037] A third biasing transistor having a gate driven by the second biasing transistor for providing an operating current for the first NMOS transistor and the second NMOS transistor.

[0038] Preferably, the third biasing transistor has a size four times that of the first biasing transistor; and the first NMOS transistor, the second NMOS transistor and the third NMOS transistor each have a size substantially the same as that of the first biasing transistor.

[0039] Preferably, in a steady state where a load current on the voltage regulator remains unchanged, the output node of the anti-undershoot unit and the output node of the anti-overshoot unit are each at a high level close to a supply voltage, such that the switch PMOS transistor and the fourth PMOS transistor are each in an off state.

[0040] Preferably, a time constant determined by a product of a resistance value and a capacitance value of the resistance-capacitance filter circuit is slightly greater than a time scale corresponding to a main feedback loop bandwidth of the voltage regulator.

[0041] Preferably, the voltage sensing unit comprises a coupling capacitor connected between the output terminal and the node for sensing the voltage signal.

[0042] Preferably, a capacitance of the coupling capacitor is much greater than a parasitic capacitance of the node, such that a voltage variation ΔV1 of the node is close to ΔV when a transient voltage variation ΔV occurs at the output terminal.

[0043] The application also provides a voltage regulator comprising:

[0044] The main control circuit includes the main control transistor and the output terminal; and

[0045] As described above, any of the overshoot protection auxiliary circuits is connected to the output of the main regulating circuit and the gate of the main regulating transistor.

[0046] This application also provides an overshoot prevention method for a voltage regulator, the voltage regulator including a main regulating transistor, the method comprising:

[0047] Step 1: Generate an induced voltage signal by capacitively coupling the voltage change at the output of the induced voltage regulator;

[0048] Step 2: Delay the induced voltage signal to generate at least one delayed reference signal;

[0049] Step 3: Compare the induced voltage signal with the delayed reference signal. When the induced voltage signal is lower than the delayed reference signal, perform a pull-up operation on the gate voltage of the main control transistor to suppress voltage undershoot; and when the induced voltage signal is higher than the delayed reference signal, perform a pull-down operation on the gate voltage of the main control transistor to suppress voltage overshoot.

[0050] Step 4: After the output voltage stabilizes, the delayed reference signal approaches the induced voltage signal, and the pull-up or pull-down operation of the gate voltage is stopped.

[0051] Preferably, prior to step one, the method further includes a step of bringing the overshoot prevention auxiliary circuit to a stable operating state, which includes:

[0052] When the load current of the voltage regulator remains constant, the output voltage is kept stable.

[0053] The biasing unit ensures that the current flowing through the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor is all a first predetermined current value; and

[0054] The voltages of the output nodes of the anti-undershoot unit and the anti-overshoot unit are kept close to the power supply voltage, so that both the switching PMOS transistor and the fourth PMOS transistor remain off.

[0055] Preferably, in step two, generating at least one delayed reference signal is achieved through at least one resistor-capacitor filter circuit.

[0056] Preferably, in step three, when the voltage at the output terminal decreases due to the load current increasing from a small value, the delay reference signal remains essentially unchanged at that instant due to the RC delay, so that the current on the second NMOS transistor remains essentially unchanged, and at the same time, the output node of the anti-overshoot unit remains at a high level, so that the transistor remains off.

[0057] The pull-up operation on the gate voltage of the main regulating transistor comprises:

[0058] The drop of the induced voltage signal is amplified by the amplifier composed of transistors, so that the voltage of the output node of the amplifier drops from a state close to the power supply voltage;

[0059] When the voltage of the output node drops enough, the switch PMOS transistor is turned on, the gate is pulled up, the voltage of the gate is quickly raised, and the pull-up drive current of the main regulating transistor is increased, so that the voltage of the output end being pulled down is instantly pulled up.

[0060] Preferably, in step three, when the voltage of the output end rises due to the load current changing from large to small, the delay reference signal remains unchanged at the moment due to RC delay, while the voltage rise of the induced voltage signal makes the voltage of the common drain node lower, and the output node of the anti-undershoot unit rises to the power supply voltage, so that the switch PMOS transistor remains closed;

[0061] The pull-down operation on the gate voltage of the main regulating transistor comprises:

[0062] The pull-down current of the third NMOS transistor is increased due to the voltage rise of the induced voltage signal, while the pull-up current of the third PMOS transistor remains unchanged due to the unchanged delay reference signal, so that the voltage of the output node of the anti-overshoot unit drops;

[0063] When the voltage of the output node drops to a certain voltage, the transistor is turned on, so that the voltage of the gate drops instantly, thereby reducing the drive current of the main regulating transistor.

[0064] Preferably, in step four, after the RC time, the voltage of the delay reference signal is equal to the voltage of the induced voltage signal, which is due to the completion of the charging or discharging process of the resistance-capacitance filter circuit, so that the auxiliary circuit is in the equilibrium state again, the output node or the output node rises to close to the power supply voltage, thereby turning off the transistor, so that the auxiliary circuit does not affect the main regulating loop of the voltage regulator after the auxiliary circuit is stable.

[0065] As described above, the anti-overshoot auxiliary circuit, the voltage regulator and the anti-overshoot method of the present application have the following beneficial effects:

[0066] The application sets an anti-overshoot auxiliary circuit independent of the main regulation loop. The auxiliary circuit can quickly sense the transient change of the output voltage through capacitive coupling and generate a slowly changing reference by using RC delay network. By comparing the quickly changing sensing signal with the slowly changing reference signal, the auxiliary circuit can instantly determine whether the voltage has undershoot or overshoot and quickly pull up or pull down the gate of the main regulation transistor, so as to intervene in advance to suppress the voltage fluctuation before the main loop responds. When the system recovers to stable, the auxiliary circuit will automatically return to non-working state and does not affect the normal work of the main loop. This design effectively improves the transient response performance of the voltage regulator, significantly reduces the voltage overshoot and undershoot, and improves the stability and reliability of the system. BRIEF DESCRIPTION OF DRAWINGS

[0067] Figure 1 A circuit principle diagram of a voltage regulator driven by NMOS in the prior art is shown;

[0068] Figure 2 A circuit principle diagram of an anti-overshoot auxiliary circuit in an embodiment of the application is shown;

[0069] Figure 3 A circuit state diagram of an anti-undershoot working process in an embodiment of the application is shown;

[0070] Figure 4 A circuit state diagram of an anti-overshoot working process in an embodiment of the application is shown;

[0071] Figure 5 A simulation waveform diagram of a voltage regulator without the auxiliary circuit of the application under load transient condition is shown;

[0072] Figure 6 A simulation waveform diagram of a voltage regulator with the auxiliary circuit of the application under the same load transient condition is shown;

[0073] Figure 7 A flow chart of an anti-overshoot method for a voltage regulator in an embodiment of the application is shown. DETAILED DESCRIPTION

[0074] The embodiments of the present application will be described in detail hereinafter with specific reference to the drawings. Other advantages and effects of the present application can be easily understood by those skilled in the art from the contents disclosed in the present specification. The present application can also be implemented or applied by using different specific embodiments, and the details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0075] Please refer to Figure 1which shows a conventional voltage regulator driven by NMOS. The regulator mainly includes an error amplifier, a main regulating transistor (or called adjusting transistor) MN1 and a feedback network composed of resistors R1 and R2. In operation, the feedback network samples the output voltage VOUT by voltage division and compares the sampled voltage with a reference voltage VREF in the error amplifier. The error amplifier outputs a control voltage according to the comparison result, which is used to drive the gate of the main regulating transistor MN1. Through this negative feedback main loop, the regulator can stabilize the output voltage VOUT at a preset value under static or slowly varying load conditions. However, due to the limitations of the bandwidth, power consumption and chip area of the main feedback loop, its transient response performance is limited.

[0076] Please refer to Figure 5 which shows the simulation waveform diagram of a conventional voltage regulator without the auxiliary circuit of the present application when the load current experiences transient changes. The simulation conditions are set as follows: the power supply voltage is 2.5V, the load current Iload jumps from 100 microamperes (uA) to 5 milliampere (mA) in 1 microsecond (us), and then falls back from 5mA to 100uA in 1 microsecond (us), the process corner is typical, and the temperature is 25 degrees Celsius. From the waveform of Figure 5 it can be clearly observed that when the load current suddenly increases, the output voltage VOUT experiences a significant undershoot, and the voltage bottom point drops to about 1.006V; and when the load current suddenly decreases, the output voltage VOUT experiences a very large overshoot, and the voltage top point surges to about 1.454V. Such severe voltage fluctuations, as described in the background art, can pose a serious threat to the stability of the system and the reliability of the device.

[0077] To solve the above problems, the present application proposes an anti-overshoot auxiliary circuit. Please refer to Figure 2 which shows the circuit schematic diagram of the anti-overshoot auxiliary circuit in an embodiment of the present application. Some embodiments of the present disclosure provide an anti-overshoot auxiliary circuit for a voltage regulator, the voltage regulator including a main regulating transistor, a gate (NGATE) of the main regulating transistor for receiving a gate voltage, the voltage regulator having an output end (VOUT); the anti-overshoot auxiliary circuit includes: a voltage sensing unit, a delay reference unit, an anti-undershoot unit and an anti-overshoot unit. The input end of the voltage sensing unit is capacitively coupled with the output end (VOUT), and is used to generate a sensing voltage signal according to the voltage change of the output end (VOUT).

[0078] In some embodiments, the voltage sensing unit includes a coupling capacitor (Cc) connected between the output end (VOUT) and a node (A) of the sensing voltage signal.

[0079] In some embodiments, the coupling capacitor (Cc) has a capacitance much larger than the parasitic capacitance of node (A). This design ensures that the voltage perturbation at the output (VOUT) can be efficiently and nearly losslessly transferred to the sensing node (A) of the auxiliary circuit, providing an accurate trigger signal for the subsequent fast response. For example, when the output (VOUT) voltage experiences a transient change ΔV, the voltage change ΔV1 at node (A) can be substantially equal to ΔV. The coupling capacitor (Cc) can be implemented as a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, or a poly-insulator-poly (PIP) capacitor, etc., which are common capacitor devices in integrated circuit processes. The dielectric layer material can be selected from silicon dioxide, silicon nitride, or high-K materials such as hafnium oxide, zirconium oxide, etc., to achieve a large capacitance value within a limited chip area.

[0080] The delay reference unit is connected to the output of the voltage sensing unit, for performing delay processing on the sensed voltage signal to generate at least one delay reference signal.

[0081] In some embodiments, the delay reference unit includes at least one resistor-capacitor filter circuit composed of a resistor and a capacitor. The resistor-capacitor filter circuit is essentially a low-pass filter, which functions to filter out high-frequency transient changes in the sensed voltage signal, thereby generating a reference signal that is relatively smooth and represents the average level of the voltage. In addition to passive RC filters, other types of low-pass filters composed of active devices, such as filters based on operational amplifiers, can also be used to achieve similar delay functions or obtain steeper roll-off characteristics.

[0082] In some embodiments, referring to Figure 2 , the delay reference unit includes: a first resistor-capacitor filter circuit (R1, C1) having an input connected to node (A) of the sensed voltage signal and an output (D) for providing a first delay reference signal; and a second resistor-capacitor filter circuit (R0, C0) having an input connected to node (A) of the sensed voltage signal and an output (G) for providing a second delay reference signal.

[0083] In some embodiments, the resistance (R1) of the first resistor-capacitor filter circuit and the resistance (R0) of the second resistor-capacitor filter circuit have substantially the same resistance value; and the capacitance (C1) of the first resistor-capacitor filter circuit and the capacitance (C0) of the second resistor-capacitor filter circuit have substantially the same capacitance value. The resistance can be implemented as a polysilicon resistance, a well resistance, or a diffusion resistance, etc. The capacitance can be implemented using similar processes as the coupling capacitor (Cc). Matching the resistance and capacitance values helps to ensure that the delay characteristics of different reference signal paths are consistent, thereby improving the symmetry and accuracy of the circuit response.

[0084] In some embodiments, the time constant determined by the product of the resistance value and the capacitance value of the resistance-capacitance filter circuit is slightly larger than the time scale corresponding to the main feedback loop bandwidth of the voltage regulator. This setting is one of the keys of the present embodiments, which ensures that the auxiliary circuit can respond faster than the main loop when a fast transient occurs in the load. Due to the RC delay, the voltages at points D, G, and H can remain substantially unchanged at the moment when the transient occurs, providing a stable reference for subsequent voltage comparison, so as to accurately detect the transient overshoot or undershoot.

[0085] The anti-undershoot unit is connected with the voltage sensing unit and the delay reference unit, and is configured to perform a pull-up operation on the gate voltage (NGATE) of the main regulating transistor based on the comparison result of the sensed voltage signal and the delay reference signal when the sensed voltage signal indicates that the voltage at the output end (VOUT) decreases.

[0086] In some embodiments, with reference to Figure 2 , the anti-undershoot unit comprises: a first NMOS transistor (MN2) having a gate receiving the sensed voltage signal; a second NMOS transistor (MN1) having a gate receiving the first delay reference signal; a first PMOS transistor (MP1) and a second PMOS transistor (MP2) configured as a first current mirror, the first PMOS transistor (MP1) serving as a load of the first NMOS transistor (MN2), and an output end (B) of the first current mirror generating a first control signal; and a switch PMOS transistor (MP5) having a gate receiving the first control signal and configured to perform a pull-up operation on the gate (NGATE) of the main regulating transistor.

[0087] The anti-overshoot unit is connected with the voltage sensing unit and the delay reference unit, and is configured to perform a pull-down operation on the gate voltage (NGATE) of the main regulating transistor based on the comparison result of the sensed voltage signal and the delay reference signal when the sensed voltage signal indicates that the voltage at the output end (VOUT) increases.

[0088] In some embodiments, with reference to Figure 2 , the delay reference unit further comprises: a third resistance-capacitance filter circuit (R2, C2) having an input end connected with a common drain node (C) of the first PMOS transistor (MP1) and the first NMOS transistor (MN2), and an output end (H) configured to provide a third delay reference signal.

[0089] In some embodiments, the resistance value of the resistance (R2) of the third resistance-capacitance filter circuit is substantially the same as the resistance values of the first and second resistance-capacitance filter circuits; and the capacitance value of the capacitance (C2) of the third resistance-capacitance filter circuit is substantially the same as the capacitance values of the first and second resistance-capacitance filter circuits. Such a symmetrical design helps to ensure that the entire auxiliary circuit has similar time characteristics and performance when responding to overshoot and undershoot.

[0090] In some embodiments, referring to Figure 2 , the anti-uprush unit comprises: a third NMOS transistor (MN3) having its gate receiving the second delay reference signal; a third PMOS transistor (MP3) having its gate receiving the third delay reference signal, the drain of the third NMOS transistor (MN3) and the drain of the third PMOS transistor (MP3) being connected to an output node (E) to generate a second control signal; and a pull-down circuit receiving the second control signal for pulling down the gate (NGATE) of the main regulating transistor.

[0091] In some embodiments, referring to Figure 2 , further comprising a bias unit, the bias unit comprising: a first bias transistor (MS1) and a second bias transistor (MS2) provided with a bias current from a current source (I0) to generate a bias voltage; and a third bias transistor (MS3) having its gate driven by the second bias transistor (MS2) for providing operating currents for the first NMOS transistor (MN2) and the second NMOS transistor (MN1).

[0092] In some embodiments, the third bias transistor (MS3) has a size four times that of the first bias transistor (MS1); and the first NMOS transistor (MN2), the second NMOS transistor (MN1) and the third NMOS transistor (MN3) have substantially the same size as the first bias transistor (MS1). This precise size ratio relationship sets a precise static operating point for the circuit through the current mirror principle. For example, the currents on MS1 and MS2 are both I0, which are copied through the current mirror, so that the static currents of MN1, MN2 and MN3 are also I0 when stable, while MS3 can provide a tail current of 4*I0, ensuring the normal bias and symmetry of the circuit. These transistors (NMOS and PMOS) can be manufactured based on various semiconductor processes, such as bulk silicon (Bulk CMOS), silicon-on-insulator (SOI) or fin field effect transistor process, to adapt to different performance and power consumption requirements.

[0093] In some embodiments, the second PMOS transistor (MP2) and the third PMOS transistor (MP3) each have a size K times that of the first PMOS transistor (MP1). The value of K can be designed according to the required driving capability and response speed, for example, it can be set to an integer or non-integer value of 2, 3 or more to optimize the gain and transient performance of the circuit.

[0094] In some embodiments, referring to Figure 2The pull-down circuit comprises a fourth PMOS transistor (MP4) and a fourth NMOS transistor (MN4), both of which have their gates connected to the output node (E); and a fifth NMOS transistor (MN5) whose gate is driven by the common drain node (F) of the fourth PMOS transistor (MP4) and the fourth NMOS transistor (MN4), and whose drain is connected to the gate (NGATE) of the main regulating transistor. The pull-down circuit is formed by cascading an inverter (formed by MP4 and MN4) and a pull-down NMOS transistor (MN5). When the voltage at the E point drops, the inverter outputs a high level, thereby strongly turning on the MN5 and achieving rapid pull-down of the NGATE.

[0095] In some embodiments, in a steady state where the load current on the voltage regulator remains unchanged, the output node (B) of the anti-undershoot unit and the output node (E) of the anti-overshoot unit are both at a high level close to the power supply voltage, so that the switch PMOS transistor (MP5) and the fourth PMOS transistor (MP4) are both in the off state. This feature is a significant advantage of the present embodiment, which ensures that when the system is working stably, the anti-overshoot auxiliary circuit is completely in a "dormant" or high-impedance state, and its output stage is completely decoupled from the gate NGATE of the main regulating transistor, without any adverse effects on the stability, accuracy or static power consumption of the main loop of the voltage regulator, achieving the unity of high efficiency and low consumption.

[0096] Some embodiments of the present disclosure also provide a voltage regulator comprising: a main regulating circuit comprising a main regulating transistor and an output end (VOUT); and an anti-overshoot auxiliary circuit as described in any of the preceding embodiments, which is connected to the output end (VOUT) of the main regulating circuit and the gate (NGATE) of the main regulating transistor.

[0097] Reference is made to Figure 7 which shows a flowchart of an anti-overshoot method for a voltage regulator in an embodiment of the present application. Some embodiments of the present disclosure also provide an anti-overshoot method for a voltage regulator comprising a main regulating transistor, the method comprising:

[0098] Step one, sensing the voltage change at the output end (VOUT) through capacitive coupling (Cc) to generate a sensing voltage signal.

[0099] In some embodiments, before step one, the method further comprises a step of stabilizing the anti-overshoot auxiliary circuit, which comprises: maintaining the voltage of the output terminal (VOUT) stable when the load current of the voltage regulator remains unchanged; making the currents flowing through the first NMOS transistor (MN2), the second NMOS transistor (MN1) and the third NMOS transistor (MN3) all be the first predetermined current value (I0) by the biasing unit; and maintaining the voltages of the output node (B) of the anti-undershoot unit and the output node (E) of the anti-overshoot unit close to the power supply voltage, so that the switch PMOS transistor (MP5) and the fourth PMOS transistor (MP4) are both kept off.

[0100] Step two, delay processing is performed on the induced voltage signal to generate at least one delayed reference signal.

[0101] In some embodiments, in step two, the at least one delayed reference signal is generated by at least one resistance-capacitance filter circuit (R0 / C0, R1 / C1, R2 / C2).

[0102] Step three, comparing the induced voltage signal with the delayed reference signal, when the induced voltage signal is lower than the delayed reference signal, performing pull-up operation on the gate voltage (NGATE) of the main regulating transistor to suppress voltage undershoot; and when the induced voltage signal is higher than the delayed reference signal, performing pull-down operation on the gate voltage (NGATE) of the main regulating transistor to suppress voltage overshoot.

[0103] In some embodiments, in step three, when the voltage of the output terminal (VOUT) decreases due to the change of the load current from small to large, the voltage of the output terminal (VOUT) can be referenced to the voltage of the output node (B) of the anti-undershoot unit. Figure 3, which schematically illustrates the main effective paths and signal variation trends during the anti-undershoot operation. Due to the RC delay, the delayed reference signals (D, G, H) remain substantially unchanged at the moment, so that the current through the second NMOS transistor (MN1) remains substantially unchanged, and the output node (E) of the anti-undershoot unit remains at a high level so that the transistors (MP4, MN4, MN5) remain turned off; the pull-up operation on the gate voltage (NGATE) of the main regulating transistor includes: amplifying the drop of the induced voltage signal (A) through the amplifier composed of the transistors (MN2, MP1, MP2), so that the voltage of the output node (B) of the amplifier drops from a state close to the power supply voltage; when the voltage of the output node (B) drops sufficiently, the switch PMOS transistor (MP5) is turned on, the gate (NGATE) is pulled up, and the voltage of the gate (NGATE) is quickly raised, thereby increasing the pull-up driving current of the main regulating transistor, and the voltage of the output end (VOUT) being pulled down is instantaneously pulled up. This series of rapid chain reactions can provide a momentary large current supplement for the output end before the main feedback loop fully responds, thereby effectively suppressing the further drop of the voltage, and finally making the voltage regulator have a smaller undershoot, and improving the dynamic performance and stability of the system.

[0104] In some embodiments, when the voltage of the output end (VOUT) rises due to the load current changing from large to small in step three, the voltage of the output end (VOUT) can be referenced Figure 4 , which schematically illustrates the main effective paths and signal variation trends during the anti-undershoot operation. Due to the RC delay, the delayed reference signals (D, G, H) remain substantially unchanged at the moment, so that the current through the second NMOS transistor (MN1) remains substantially unchanged, and the output node (E) of the anti-undershoot unit remains at a high level so that the transistors (MP4, MN4, MN5) remain turned off; the pull-up operation on the gate voltage (NGATE) of the main regulating transistor includes: amplifying the drop of the induced voltage signal (A) through the amplifier composed of the transistors (MN2, MP1, MP2), so that the voltage of the output node (B) of the amplifier drops from a state close to the power supply voltage; when the voltage of the output node (B) drops sufficiently, the switch PMOS transistor (MP5) is turned on, the gate (NGATE) is pulled up, and the voltage of the gate (NGATE) is quickly raised, thereby increasing the pull-up driving current of the main regulating transistor, and the voltage of the output end (VOUT) being pulled down is instantaneously pulled up. This series of rapid chain reactions can provide a momentary large current supplement for the output end before the main feedback loop fully responds, thereby effectively suppressing the further drop of the voltage, and finally making the voltage regulator have a smaller undershoot, and improving the dynamic performance and stability of the system.

[0105] Step four, after the voltage at the output (VOUT) is stabilized, the delay reference signal approaches the sense voltage signal, and the pull-up or pull-down operation to the gate (NGATE) voltage is stopped.

[0106] In some embodiments, in step four, after the RC time, the voltage of the delay reference signal (D, G, H) is equal to the voltage of the sense voltage signal (A) due to the completion of the charging or discharging process of the RC filter circuit, so that the auxiliary circuit is in a balanced state again, the output node (B) or the output node (E) rises to near the power supply voltage, thereby turning off the transistor (MP5) or (MP4, MN4, MN5), so that the auxiliary circuit does not affect the main regulation loop of the voltage regulator after stabilization. This automatic balance recovery mechanism ensures that the auxiliary circuit only works during the transient period, achieving the compromise between transient performance and steady-state performance.

[0107] In order to verify the beneficial effects of the embodiments of the present application, a voltage regulator equipped with the Figure 2 anti-overshoot auxiliary circuit shown in FIG. 12 is simulated, and the results are shown in FIG. 13. Figure 6 The simulation conditions are exactly the same as those in Figure 5 From the waveform of Figure 6 (blue curve v(VOUT12) in FIG. 13), it can be seen that when the load current jumps from 100uA to 5mA, the undershoot of the output voltage is greatly improved, and the lowest voltage is only about 1.1187V. Similarly, when the load current falls from 5mA to 100uA, the overshoot of the output voltage is also effectively suppressed, and the highest voltage is only about 1.338V.

[0108] By comparing the simulation results of Figure 5 and Figure 6 , it can be concluded that the anti-overshoot auxiliary circuit provided by the embodiments of the present application can significantly reduce the undershoot and overshoot amplitude of the output voltage of the voltage regulator under the same load transient condition. Specifically, the voltage undershoot is greatly reduced from more than 200mV (assuming the nominal voltage is 1.2V) to about 80mV, and the voltage overshoot is greatly reduced from more than 250mV to about 140mV. This significant improvement in performance has very important practical significance for ensuring the stable operation and long-term reliability of modern low-voltage integrated circuit systems.

[0109] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in terms of type, number and proportion, and the layout pattern of the components may also be more complex.

[0110] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. An overshoot protection auxiliary circuit for a voltage regulator, the voltage regulator including a main regulating transistor, the gate (NGATE) of the main regulating transistor being used to receive a gate voltage, the voltage regulator having an output terminal (VOUT), characterized in that, The overshoot prevention auxiliary circuit includes: A voltage sensing unit, the input terminal of which is capacitively coupled to the output terminal (VOUT), is used to generate a sensed voltage signal based on the voltage change at the output terminal (VOUT). A delay reference unit, connected to the output terminal of the voltage sensing unit, is used to delay the induced voltage signal to generate at least one delay reference signal; An anti-undershoot unit, connected to the voltage sensing unit and the delay reference unit, is used to pull up the gate voltage (NGATE) of the main regulating transistor based on a comparison between the sensed voltage signal and the delay reference signal when the sensed voltage signal indicates a drop in the voltage at the output terminal (VOUT); and An anti-overshoot unit, connected to the voltage sensing unit and the delay reference unit, is used to pull down the gate voltage (NGATE) of the main regulating transistor based on the comparison result between the sensing voltage signal and the delay reference signal when the voltage at the output terminal (VOUT) indicates an increase.

2. The anti-overshoot auxiliary circuit according to claim 1, characterized in that: The delay reference unit includes at least one resistor-capacitor filter circuit consisting of resistors and capacitors.

3. The anti-overshoot auxiliary circuit according to claim 2, characterized in that: The delay reference unit includes: a first resistor-capacitor filter circuit (R1, C1), whose input terminal is connected to node (A) of the induced voltage signal, and whose output terminal (D) is used to provide a first delay reference signal; and a second resistor-capacitor filter circuit (R0, C0), whose input terminal is connected to node (A) of the induced voltage signal, and whose output terminal (G) is used to provide a second delay reference signal.

4. The anti-overshoot auxiliary circuit according to claim 3, characterized in that: The resistor (R1) of the first resistor-capacitor filter circuit and the resistor (R0) of the second resistor-capacitor filter circuit have essentially the same resistance value; the capacitor (C1) of the first resistor-capacitor filter circuit and the capacitor (C0) of the second resistor-capacitor filter circuit have essentially the same capacitance value.

5. The anti-overshoot auxiliary circuit according to claim 3, characterized in that: The anti-undershoot unit includes: a first NMOS transistor (MN2) whose gate receives the induced voltage signal; a second NMOS transistor (MN1) whose gate receives the first delayed reference signal; a first PMOS transistor (MP1) and a second PMOS transistor (MP2) configured as a first current mirror, the first PMOS transistor (MP1) serving as the load of the first NMOS transistor (MN2), and the output terminal (B) of the first current mirror generating a first control signal; and a switching PMOS transistor (MP5) whose gate receives the first control signal for pulling up the gate (NGATE) of the main regulating transistor.

6. The anti-overshoot auxiliary circuit according to claim 5, characterized in that: The delay reference unit further includes a third resistor-capacitor filter circuit (R2, C2), whose input terminal is connected to the common drain node (C) of the first PMOS transistor (MP1) and the first NMOS transistor (MN2), and whose output terminal (H) is used to provide a third delay reference signal.

7. The anti-overshoot auxiliary circuit according to claim 6, characterized in that: The resistance value of the resistor (R2) in the third resistor-capacitor filter circuit is basically the same as the resistance value of the first and second resistor-capacitor filter circuits; the capacitance value of the capacitor (C2) in the third resistor-capacitor filter circuit is basically the same as the capacitance value of the first and second resistor-capacitor filter circuits.

8. The anti-overshoot auxiliary circuit according to claim 6, characterized in that: The anti-overshoot unit includes: a third NMOS transistor (MN3) whose gate receives the second delay reference signal; a third PMOS transistor (MP3) whose gate receives the third delay reference signal, the drain of the third NMOS transistor (MN3) and the drain of the third PMOS transistor (MP3) being connected to the output node (E) to generate a second control signal; and a pull-down circuit that receives the second control signal and is used to pull down the gate (NGATE) of the main regulating transistor.

9. The anti-overshoot auxiliary circuit according to claim 8, characterized in that: The size of the second PMOS transistor (MP2) and the size of the third PMOS transistor (MP3) are both K times the size of the first PMOS transistor (MP1).

10. The anti-overshoot auxiliary circuit according to claim 8, characterized in that: The pull-down circuit includes: a fourth PMOS transistor (MP4) and a fourth NMOS transistor (MN4), the gates of which are both connected to the output node (E); and a fifth NMOS transistor (MN5), the gate of which is driven by the common drain node of the fourth PMOS transistor (MP4) and the fourth NMOS transistor (MN4), and the drain of the fifth NMOS transistor (MN5) is connected to the gate (NGATE) of the main regulating transistor.

11. The anti-overshoot auxiliary circuit according to claim 8, characterized in that: It also includes a biasing unit comprising: a first biasing transistor (MS1) and a second biasing transistor (MS2) for receiving a first biasing current (I0) to generate a biasing voltage; and a third biasing transistor (MS3) whose gate is driven by the second biasing transistor (MS2) for providing operating current to the first NMOS transistor (MN2) and the second NMOS transistor (MN1).

12. The anti-overshoot auxiliary circuit according to claim 11, characterized in that: The size of the third bias transistor (MS3) is four times that of the first bias transistor (MS1); and the sizes of the first NMOS transistor (MN2), the second NMOS transistor (MN1), and the third NMOS transistor (MN3) are substantially the same as those of the first bias transistor (MS1).

13. The anti-overshoot auxiliary circuit according to claim 10, characterized in that: Under stable conditions where the load current on the voltage regulator remains constant, the output node (B) of the anti-undershoot unit and the output node (E) of the anti-overshoot unit are both at a high level close to the power supply voltage, causing the switching PMOS transistor (MP5) and the fourth PMOS transistor (MP4) to be in the off state.

14. The anti-overshoot auxiliary circuit according to claim 2, characterized in that: The time constant determined by the product of the resistance and capacitance values ​​of the resistor-capacitor filter circuit is slightly larger than the time scale corresponding to the main feedback loop bandwidth of the voltage regulator.

15. The anti-overshoot auxiliary circuit according to claim 1, characterized in that: The voltage sensing unit includes a coupling capacitor (Cc) connected between the output terminal (VOUT) and the node (A) of the sensed voltage signal.

16. The anti-overshoot auxiliary circuit according to claim 15, characterized in that: The capacitance of the coupling capacitor (Cc) is much larger than the parasitic capacitance of the node (A) so that when the voltage at the output terminal (VOUT) undergoes a transient change ΔV, the voltage change ΔV1 of the node (A) is close to ΔV.

17. A voltage regulator, characterized in that, include: The main control circuit includes the main control transistor and the output terminal (VOUT); as well as The overshoot protection auxiliary circuit as described in any one of claims 1 to 16, wherein the overshoot protection auxiliary circuit is connected to the output terminal (VOUT) of the main regulating circuit and the gate (NGATE) of the main regulating transistor.

18. An overshoot prevention method for a voltage regulator, the voltage regulator including a main regulating transistor, characterized in that, include: Step 1: Sensing the voltage change at the output terminal (VOUT) of the voltage regulator via capacitive coupling (Cc) to generate an induced voltage signal; Step 2: Delay the induced voltage signal to generate at least one delayed reference signal; Step 3: Compare the induced voltage signal with the delay reference signal. When the induced voltage signal is lower than the delay reference signal, perform a pull-up operation on the gate (NGATE) voltage of the main regulating transistor to suppress voltage undershoot. And when the induced voltage signal is higher than the delayed reference signal, a pull-down operation is performed on the gate (NGATE) voltage of the main regulating transistor to suppress voltage surge; Step 4: After the voltage at the output terminal (VOUT) stabilizes, the delayed reference signal approaches the induced voltage signal, and the pull-up or pull-down operation on the gate (NGATE) voltage stops.

19. The anti-overshoot auxiliary circuit according to claim 18, characterized in that: Prior to step one, the method further includes a step of stabilizing the overshoot protection auxiliary circuit, which includes: maintaining the voltage at the output terminal (VOUT) stable when the load current of the voltage regulator remains constant; using a bias unit to ensure that the current flowing through the first NMOS transistor (MN2), the second NMOS transistor (MN1), and the third NMOS transistor (MN3) is a first predetermined current value (I0); and maintaining the voltage at the output node (B) of the undershoot protection unit and the output node (E) of the overshoot protection unit close to the power supply voltage, so that the switching PMOS transistor (MP5) and the fourth PMOS transistor (MP4) remain off.

20. The anti-overshoot auxiliary circuit according to claim 18, characterized in that: In step two, the generation of at least one delayed reference signal is achieved by at least one resistor-capacitor filter circuit (R0 / C0, R1 / C1, R2 / C2).

21. The anti-overshoot auxiliary circuit according to claim 18, characterized in that: In step three, when the voltage at the output terminal (VOUT) decreases due to the increase in load current, the delayed reference signal (D, G, H) remains essentially unchanged at that instant due to RC delay, making the current on the second NMOS transistor (MN1) essentially unchanged. At the same time, the output node (E) of the anti-overshoot unit remains at a high level, keeping the transistors (MP4, MN4, MN5) off. The pull-up operation on the gate (NGATE) voltage of the main regulating transistor includes: the decrease in the induced voltage signal (A) is amplified by the amplifier composed of transistors (MN2, MP1, MP2), causing the voltage at the output node (B) of the amplifier to decrease from a state close to the power supply voltage. When the voltage drop at the output node (B) is large enough, the switching PMOS transistor (MP5) is turned on to pull up the gate (NGATE), causing the voltage at the gate (NGATE) to rise rapidly, thereby increasing the pull-up drive current of the main regulating transistor and instantly pulling up the voltage at the output terminal (VOUT) that was pulled down.

22. The anti-overshoot auxiliary circuit according to claim 18, characterized in that: In step three, when the voltage at the output terminal (VOUT) rises due to the decrease in load current, the delay reference signal (D,G,H) remains unchanged at that instant due to RC delay. Simultaneously, the voltage of the induced voltage signal (A) increases, causing the voltage at the common drain node (C) to decrease, and the output node (B) of the anti-overshoot unit rises to the power supply voltage, keeping the switching PMOS transistor (MP5) off. The pull-down operation on the gate (NGATE) voltage of the main regulating transistor includes: the pull-down current of the third NMOS transistor (MN3) increases due to the increase in the induced voltage signal (A), while the pull-up current of the third PMOS transistor (MP3) remains unchanged due to the unchanged delay reference signal (H), thereby causing the voltage at the output node (E) of the anti-overshoot unit to decrease. When the voltage at the output node (E) drops to a certain voltage, transistors (MP4,MN4,MN5) are turned on, causing the gate (NGATE) voltage to drop instantaneously, thereby reducing the drive current of the main regulating transistor.

23. The anti-overshoot auxiliary circuit according to claim 18, characterized in that: In step four, after RC time, the voltage of the delayed reference signal (D,G,H) equals the voltage of the induced voltage signal (A), causing the auxiliary circuit to return to a balanced state. The output node (B) or output node (E) rises to near the power supply voltage, thereby turning off the transistor (MP5) or (MP4,MN4,MN5), so that the auxiliary circuit does not affect the main regulation loop of the voltage regulator after stabilization.

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