Instruction merging method and device, chip, equipment, storage medium and product

Abstract

The invention provides an instruction merging method and device, a chip, equipment, a storage medium and a product, and belongs to the technical field of chips and semiconductors. The method comprises the steps that a plurality of instructions in a data processing task are obtained, each instruction indicates to obtain data from at least one source register of the instruction and process the data, and a processing result is stored in a result register of the instruction; for each first instruction in the plurality of instructions, comparing a result register number of the first instruction with a respective source register number of at least one second instruction, the at least one second instruction being an instruction of which the processing sequence is located at a preset bit behind the first instruction; if a target instruction exists in the at least one second instruction, the target instruction is merged into the first instruction to obtain a third instruction, and the target instruction refers to an instruction with a source register identical to a result register of the first instruction. According to the method, the instruction processing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of chip and semiconductor technology, and in particular to an instruction merging method, apparatus, chip, device, storage medium and product. Background Technology

[0002] When a processor processes data in a data processing task, it typically does so based on multiple instructions within that task. These instructions specify where to retrieve the data to be processed, how to process it, and where to store the processed data.

[0003] To complete a data processing task, multiple instructions need to work together. These instructions are not unrelated; a second instruction might use the result of the first instruction. Therefore, related instructions are processed sequentially. However, during this sequential processing, the second instruction must wait for the first instruction to store its result at the specified memory location before it can process the data. This results in a longer waiting time for the second instruction, thus reducing processing efficiency. Summary of the Invention

[0004] This application provides an instruction merging method, apparatus, chip, device, storage medium, and product, which improves instruction processing efficiency. The technical solution is as follows.

[0005] On the one hand, an instruction merging method is provided, the method comprising: The system retrieves multiple instructions from a data processing task. Each instruction instructs the retrieval of data from at least one source register and the processing of the data, and stores the processing results in its respective result register. For each of the multiple instructions, the result register number of the first instruction is compared with the source register number of each of the at least one second instruction, wherein the at least one second instruction is an instruction whose processing order is located after the first instruction by a preset number; If a target instruction exists in at least one of the second instructions, the target instruction is merged into the first instruction to obtain a third instruction. The target instruction is an instruction whose source register is the same as the result register of the first instruction.

[0006] On the other hand, an instruction merging apparatus is provided, the apparatus comprising: The acquisition module is used to acquire multiple instructions in the data processing task. Each instruction instructs to acquire data from at least one source register and process it, and store the processing result in its respective result register. The comparison module is used to compare the result register number of each first instruction among the multiple instructions with the source register number of each of the at least one second instruction, wherein the at least one second instruction is an instruction whose processing order is located at a preset position after the first instruction; The merging module is used to merge the target instruction into the first instruction to obtain a third instruction if a target instruction exists in the at least one second instruction, wherein the target instruction is an instruction whose source register is the same as the result register of the first instruction.

[0007] In some embodiments, the source register of the third instruction includes the source register of the first instruction and the target source register of the target instruction, the result register of the target instruction includes the result register of the first instruction and the result register of the target instruction, and the target source register refers to a register in the source register of the target instruction that is different from the result register of the first instruction.

[0008] In some embodiments, the merging module is configured to: If a target instruction exists in at least one of the second instructions and there is no instruction between the target instruction and the first instruction, the target instruction is merged into the first instruction to obtain a third instruction.

[0009] In some embodiments, the merging module is configured to: If a target instruction exists in the at least one second instruction and a fourth instruction exists between the target instruction and the first instruction, the number of the target source register is compared with the number of the result register of the fourth instruction. The target source register refers to the register in the source register of the target instruction that is different from the result register of the first instruction. If the target source register is different from the result register of the fourth instruction, the target instruction is merged into the first instruction to obtain the third instruction.

[0010] In some embodiments, the device further includes an output module for: If there are multiple fifth instructions among the at least one second instruction, the fifth instruction with the earliest processing order among the multiple fifth instructions is output as the target instruction. Each fifth instruction refers to an instruction whose source register is the same as the result register of the first instruction.

[0011] In some embodiments, the comparison module is configured to: Based on the processing order of the at least one second instruction, the at least one second instruction is sequentially compared with the first instruction in ascending order; If a second instruction is matched to a source register that is the same as the result register of the first instruction, the matched second instruction is output as the target instruction.

[0012] In some embodiments, the comparison module is configured to: The instructions are traversed according to the processing order of the instructions, and the instructions that have been traversed are output to the first instruction. If the first instruction is not merged into other instructions, the result register number of the first instruction is compared with the source register number of each of at least one second instruction.

[0013] On the other hand, a chip is provided, the chip including a processor and a memory, the memory being used to store at least one program, the at least one program being loaded and executed by the processor to implement the instruction merging method in the embodiments of this application.

[0014] On the other hand, a computer device is provided, the computer device including a processor and a memory, the memory being used to store at least one program, the at least one program being loaded and executed by the processor to implement the instruction merging method in the embodiments of this application.

[0015] On the other hand, a computer-readable storage medium is provided, wherein at least one program is stored in the computer-readable storage medium, the at least one program being loaded and executed by a processor to implement the instruction merging method in the embodiments of this application.

[0016] On the other hand, a computer program product is provided, the computer program product comprising at least one program segment stored in a computer-readable storage medium, a processor of a computer device reading the at least one program segment from the computer-readable storage medium, the processor executing the at least one program segment, causing the computer device to perform the instruction merging method described in any of the above implementations.

[0017] This application provides an instruction merging method. Considering that the processing order of instructions can reflect dependencies to a certain extent, the comparison range of instructions is determined based on the processing order. For the first instruction, comparing it with instructions processed later in the order increases the probability of a successful comparison. During the comparison process, the result register number of the instruction and the source register number of the compared instruction are used to accurately identify the target instruction that has a dependency relationship with the first instruction. The target instruction is then merged into the first instruction to obtain the third instruction. Since the processing of the first instruction and the target instruction is performed synchronously in the third instruction, the processing result of the first instruction can be directly applied when processing the target instruction. In this case, the processing result of the first instruction is not stored separately in a result register, thus greatly saving storage time. Furthermore, the processing result of the first instruction is directly passed to the processing of the target instruction, further saving the reading time that might occur from separate storage, thereby improving instruction processing efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of an implementation environment provided in an embodiment of this application; Figure 2 This is a flowchart of an instruction merging method provided in an embodiment of this application; Figure 3 This is a flowchart of another instruction merging method provided in the embodiments of this application; Figure 4 This is a schematic diagram of key field information of an instruction provided in an embodiment of this application; Figure 5 This is a schematic diagram of a merging device provided in an embodiment of this application; Figure 6 This is a schematic diagram illustrating the merging of instructions provided in an embodiment of this application; Figure 7 This is a schematic diagram of a multi-dependency scenario provided in an embodiment of this application; Figure 8 This is a schematic diagram illustrating an instruction filtering method provided in an embodiment of this application; Figure 9 This is a flowchart of an execution unit provided in an embodiment of this application; Figure 10This is a schematic diagram of a processor provided in an embodiment of this application; Figure 11 This is a block diagram of an instruction merging device provided in an embodiment of this application; Figure 12 This is a block diagram of a terminal provided in an embodiment of this application; Figure 13 This is a block diagram of a server provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0021] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor are there any restrictions on quantity or execution order.

[0022] In this application, the term "at least one" means one or more, and "multiple" means two or more.

[0023] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, many of the instructions involved in this application were obtained with full authorization.

[0024] The following section describes the implementation environment involved in this application.

[0025] The instruction merging method provided in this application can be executed by a computer device, which can be a server or a terminal. The following is a schematic diagram illustrating the implementation environment of the instruction merging method provided in this application.

[0026] See Figure 1 , Figure 1This diagram illustrates an implementation environment for an instruction merging method according to an embodiment of this application. The implementation environment includes a terminal 101 and a server 102. The terminal 101 and server 102 can be directly or indirectly connected via wired or wireless communication, which is not limited herein. In some embodiments, the terminal 101 sends a data processing task to the server 102, which merges multiple instructions in the data processing task and then performs data processing based on the merged instructions. In other embodiments, the terminal 101 itself merges multiple instructions in the data processing task and then sends the merged instructions to the server 102, which performs data processing based on the merged instructions. Furthermore, the terminal 101 and server 102 each perform the above-described work through their respective internal chips, and more specifically, through processors on their respective chips.

[0027] In some embodiments, terminal 101 may be a smartphone, tablet, laptop, desktop computer, smart voice interaction device, smart home appliance, vehicle terminal, aircraft, VR (Virtual Reality) device, AR (Augmented Reality) device, etc., but is not limited thereto. In some embodiments, server 102 may be an independent server, a server cluster composed of multiple servers, or a distributed system. It may also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. In some embodiments, server 102 primarily undertakes computing tasks, while terminal 101 undertakes secondary computing tasks; or, server 102 undertakes secondary computing services, while terminal 101 undertakes primary computing tasks; or, server 102 and terminal 101 collaborate on computing using a distributed computing architecture.

[0028] See Figure 2 , Figure 2 A flowchart of an instruction merging method provided in an embodiment of this application is shown, the method including the following steps.

[0029] 201. A computer device acquires multiple instructions in a data processing task, each instruction instructing the acquisition and processing of data from at least one source register and storing the processing result in its respective result register.

[0030] In this embodiment, both the source register and the result register are used to store data. Each instruction carries at least one source register number and one result register number, which are used to identify the registers. The result register of one instruction may be the same as one of the source registers of another instruction, meaning that the processing of the other instruction depends on the processing result of the first instruction. Accordingly, the processing of the other instruction must wait for the first instruction to complete its processing and for its result register to be stored before the other instruction can retrieve data from the result register for processing.

[0031] In this embodiment, each instruction also indicates a calculation method for the data, based on which the data obtained from the source register is processed; that is, each instruction can only perform one step of the data calculation. Accordingly, each instruction has at most two source registers.

[0032] 202. For each first instruction in a set of multiple instructions, the computer device compares the result register number of the first instruction with the source register number of at least one second instruction, wherein the at least one second instruction is an instruction whose processing order is located at a preset position after the first instruction.

[0033] In this embodiment, multiple instructions have a sequential processing order. Instruction processing refers to retrieving data from the instruction's source register based on the instruction's indication, processing it, and storing the processing result in the instruction's result register. The computer device traverses the multiple instructions according to their processing order and outputs the traversed instruction as the first instruction.

[0034] The result register number of the first instruction is used to identify the result register of the first instruction. The source register number of the second instruction is used to identify the source register of the second instruction.

[0035] In this embodiment of the application, the result register number of the first instruction is compared with the source register number of at least one second instruction, that is, it is detected whether there is an instruction in at least one second instruction whose source register is the same as the result register of the first instruction.

[0036] The last preset bit can be set as needed. For example, if the last preset bit is three, then at least one second instruction is one of the three instructions whose processing order is three bits after the first instruction.

[0037] 203. If at least one of the second instructions contains a target instruction, the computer device merges the target instruction into the first instruction to obtain the third instruction. The target instruction is an instruction whose source register is the same as the result register of the first instruction.

[0038] In the embodiments of this application, the target instruction is an instruction whose source register number is the same as the result register number of the first instruction. Since the number is used to identify the register, the registers are the same if the numbers are the same.

[0039] Since the target instruction is merged into the first instruction to obtain the third instruction, the processing order of the third instruction is the same as the processing order of the first instruction. The third instruction is used not only to obtain the processing result of the first instruction but also to obtain the processing result of the target instruction. Furthermore, the processing result of the first instruction can be directly used by the target instruction without needing to retrieve it from the result register of the first instruction. Correspondingly, the processing result of the first instruction obtained based on the third instruction is still stored in the result register of the first instruction, and the processing result of the target instruction is still stored in the result register of the target instruction, thus facilitating the use of the processing results of these two instructions by subsequent instructions.

[0040] In this embodiment of the application, after the target instruction is merged into the first instruction, the target instruction becomes an invalid instruction, and there is no need to output it as the first instruction for processing in the future.

[0041] If at least one of the second instructions does not contain the target instruction, the first instruction is not merged and is output as a normal instruction. Accordingly, the instruction whose processing order is one instruction after the first instruction is output as the first instruction, and steps 202-203 above are continued until all instructions have been traversed.

[0042] This application provides an instruction merging method. Considering that the processing order of instructions can reflect dependencies to a certain extent, the comparison range of instructions is determined based on the processing order. For the first instruction, comparing it with instructions processed later in the order increases the probability of a successful comparison. During the comparison process, the result register number of the instruction and the source register number of the compared instruction are used to accurately identify the target instruction that has a dependency relationship with the first instruction. The target instruction is then merged into the first instruction to obtain the third instruction. Since the processing of the first instruction and the target instruction is performed synchronously in the third instruction, the processing result of the first instruction can be directly applied when processing the target instruction. In this case, the processing result of the first instruction is not stored separately in a result register, thus greatly saving storage time. Furthermore, the processing result of the first instruction is directly passed to the processing of the target instruction, further saving the reading time that might occur from separate storage, thereby improving instruction processing efficiency.

[0043] The above Figure 2 The basic process of the instruction merging method is as follows, based on... Figure 3 The method of merging instructions is described in further detail. See also Figure 3 , Figure 3 A flowchart of an instruction merging method provided in an embodiment of this application is shown, the method including the following steps.

[0044] 301. A computer device acquires multiple instructions in a data processing task, each instruction instructing the acquisition and processing of data from at least one source register and storing the processing result in its respective result register.

[0045] In the embodiments of this application, the data processing task can be a data processing task in various scenarios. Optionally, the data processing task is a data processing task related to artificial intelligence. For example, the data processing task can be a data processing task in scenarios such as image recognition and human-computer dialogue. Furthermore, the data processing task can be a data processing task in a robot movement scenario, or a data processing task in a phone call, etc., and will not be elaborated further here. In this embodiment, the data processing task includes multiple instructions, each of which is used to complete a single computational operation. Accordingly, the data processing task implements data processing based on these multiple instructions.

[0046] In the embodiments of this application, each instruction carries multiple types of information. Each instruction carries not only information about the source register and result register, but also information such as the operation method and an identifier indicating whether the instruction is valid. For example, see... Figure 4 , Figure 4 This is a schematic diagram illustrating key field information of an instruction provided in an embodiment of this application. Among them, `valid` is an identifier field, the value of which indicates whether the instruction is valid. Instruction merging and data processing are only performed if the identifier indicates the instruction is valid. `instr` is an information field, the value of which includes the operation method, data type, etc. `rd` (register destination) is the result register field, the value of which is the number of the result register. `rs` (register source) 0 and `rs1` are two source register fields, the values ​​of which are the numbers of the source registers.

[0047] In some embodiments, the computer device uses a processor to perform the instruction merging method provided in this application. Optionally, the computer device uses a front-end processing unit on the processor to obtain multiple instructions for a data processing task. The front-end processing unit performs instruction fetching and decoding operations, etc., to obtain multiple instructions.

[0048] 302. For each first instruction in a set of multiple instructions, the computer device compares the result register number of the first instruction with the source register number of at least one second instruction, wherein the at least one second instruction is an instruction whose processing order is located at a preset position after the first instruction.

[0049] In some embodiments, the computer device performs instruction merging via a merging device on the processor. The merging device includes a pipeline unit and a compare (cmp) unit. The pipeline unit and the compare unit are connected. The pipeline unit is used to fetch a first instruction and a second instruction, and to arrange the first instruction and the second instruction sequentially. The compare unit is used to compare their serial numbers.

[0050] In some embodiments, the computer device inputs a first instruction and at least one second instruction into a pipeline unit. The pipeline unit includes a preset number of instruction locations, the preset number being the sum of the number of the first instruction and at least one second instruction, and each instruction location is used to store one instruction.

[0051] In this process, multiple instruction positions are arranged sequentially, and the first instruction and at least one second instruction are input into the pipeline unit in the order of processing. Accordingly, the first instruction is stored in the first instruction position, and subsequent instructions are stored in each instruction position after the first instruction position. That is, multiple instructions are stored in different instruction positions respectively.

[0052] Different instruction locations correspond to different pipelines. A pipeline refers to the process where an instruction stored at a particular instruction location may move through multiple instruction locations during its journey from storage to retrieval, depending on its current location. For example, after the instruction at the first instruction location is retrieved, the instruction at the second instruction location is moved to the first instruction location, and the instruction at the third instruction location is moved to the second instruction location. Conversely, after the instruction moved to the first instruction location is retrieved, the instruction at the second instruction location is moved back to the first instruction location.

[0053] In some embodiments, the computer device uses a comparison unit on the processor to compare instruction numbers to determine which second instruction's source register is identical to the result register of the first instruction. If an identical register is found, the two instructions are merged. Since the first instruction and at least one second instruction are input to the pipeline unit in processing order, the instruction location of each instruction also indicates the instruction processing order. Accordingly, when the comparison unit retrieves the register number of an instruction from its location, it can also determine the processing order of the instruction based on its location.

[0054] For example, see Figure 5 , Figure 5This is a schematic diagram of a merging device provided in an embodiment of this application. The merging device includes a pipeline unit 501 and a comparison unit 502. Taking three second instructions as an example, the pipeline unit includes four instruction positions. Accordingly, the pipeline unit compares the four instructions at a time. The first instruction and the three second instructions are distributed in multiple instruction positions according to the processing order, and the names of the instruction positions are delay stage3, delay stage2, delay stage1, and delay stage0, respectively. Each instruction position includes multiple field positions. After multiple instructions are input to the pipeline unit, the pipeline unit obtains the information carried by each instruction and then fills the various information of the instruction into the multiple field positions of the instruction position, thereby facilitating the comparison unit to obtain the instruction information from the pipeline unit for comparison. For example, the comparison unit obtains the source register number of the second instruction and the result register number of the first instruction for number comparison.

[0055] In some embodiments, once an instruction is merged into another instruction, it cannot be merged into other instructions. Accordingly, the process by which the computer device compares the result register number of each first instruction among a plurality of instructions with the source register numbers of at least one second instruction includes the following steps: the computer device traverses the plurality of instructions according to the processing order of the plurality of instructions, and outputs the traversed instructions to the first instruction; if the first instruction is not merged into other instructions, the result register number of the first instruction is compared with the source register numbers of at least one second instruction.

[0056] In some embodiments, since each instruction also carries an identifier indicating whether the instruction is valid, optionally, after any instruction has been merged into other instructions, the identifier of that instruction is set to invalid, while for instructions not merged into other instructions, the identifier of that instruction remains valid. The valid and invalid identifiers can be set as needed, such as using 1 for a valid identifier and 0 for an invalid identifier. Accordingly, for each instruction encountered, if it carries a valid identifier, the computer device performs the step of comparing the result register number of the first instruction with the source register numbers of at least one second instruction; if it carries an invalid identifier, the instruction is no longer processed, that is, the instruction is no longer output as the first instruction for comparison with other instructions.

[0057] In this embodiment, since an instruction is processed once within the merged instruction after being merged into another instruction, merging it again would result in multiple processing iterations. This not only wastes resources but also causes program logic errors, preventing data processing tasks from executing correctly and reducing efficiency. However, in this embodiment, an instruction is merged only if it has not yet been merged into another instruction. If it has already been merged, it is not merged again, ensuring the accuracy of the merging process, avoiding program logic errors caused by merging the same instruction multiple times, and thus guaranteeing the efficiency of subsequent instruction processing.

[0058] In some embodiments, if any instruction has been merged into other instructions, the instruction will no longer be output as a second instruction, or the instruction will be output as an invalid second instruction, that is, the instruction will no longer be compared with the first instruction, so as to avoid the instruction causing program logic errors.

[0059] 303. If at least one of the second instructions contains a target instruction, the computer device merges the target instruction into the first instruction to obtain the third instruction. The target instruction is an instruction whose source register is the same as the result register of the first instruction.

[0060] In this embodiment, the source register of the third instruction includes the source register of the first instruction and the target source register of the target instruction. The result register of the third instruction includes the result register of the first instruction and the result register of the target instruction. The target source register refers to a register in the source register of the target instruction that is different from the result register of the first instruction. The third instruction instructs to obtain data from the source register of the first instruction and process it to obtain a first processing result, store the first processing result in the result register of the first instruction, and instruct to process the data based on the first processing result and the data obtained from the source register of the target instruction to obtain a second processing result, store the second processing result in the result register of the target instruction.

[0061] In this embodiment, the source register of the merged instruction includes the source register of the first instruction before merging and the target source register of the target instruction before merging. Since the other source register of the target instruction is the result register of the first instruction, when processing the target instruction in the third instruction, the processing result of the first instruction in the third instruction can be directly obtained without having to retrieve the processing result of the first instruction from its result register, thereby shortening the processing time and improving the processing efficiency of the instruction. Furthermore, the result register of the third instruction includes the result registers of the two instructions before merging, so that the processing results of the two instructions can still be stored in their respective result registers without destroying the original program logic of the instructions, thus ensuring that the instructions can be processed normally, that is, ensuring processing efficiency.

[0062] In the embodiments of this application, if a source register of the target instruction is the same as the result register of the first instruction, it is said that the two instructions are related, and thus such two instructions can be called related instructions.

[0063] For example, see Figure 6 , Figure 6 This is a schematic diagram of instruction merging provided in an embodiment of this application. The first instruction in delay stage 3 corresponds to subtraction, with source registers r0 and r1 and result register r2. That is, the first instruction indicates r2 = r0 - r1, meaning the data obtained from register r0 is subtracted from the data obtained from register r1 to obtain the data to be stored in register r2. The second instruction in delay stage 2 corresponds to multiplication, with source registers r4 and r3 and result register r5. That is, the second instruction indicates r5 = r4 × r3, meaning the data obtained from register r4 is multiplied by the data obtained from register r3 to obtain the data to be stored in register r5. The second instruction in delay stage 1 corresponds to addition, with source registers r2 and r6 and result register r7. That is, the second instruction indicates r7 = r2 + r6, meaning the data obtained from register r2 is added to the data obtained from register r6 to obtain the data to be stored in register r7. The comparison reveals that the source register r2 of the second instruction in delay stage 1 is the result register r2 of the first instruction in delay stage 3. These two instructions are related, and therefore they are merged. The merged instruction performs two operations: rd0 = rs0 - rs1; rd1 = rs0 - rs1 + rs2. After merging the instructions, the valid field of the second instruction in delay stage 1 is set to 0 to indicate that this instruction is invalid, meaning that it does not need to be processed further.

[0064] In some embodiments, since the target instruction is merged into the first instruction to obtain the third instruction, and the processing order of the third instruction is the same as the processing order of the first instruction, the processing order of the target instruction is moved forward. If there is an instruction that the target instruction depends on the processing result of the first instruction, since the processing order of the target instruction is earlier than that of the first instruction, it is obvious that when processing the target instruction, since the first instruction has not yet been processed, the logic of the processing program will be erroneous, resulting in a processing error.

[0065] Accordingly, the process of merging the target instruction into the first instruction to obtain the third instruction if at least one of the second instructions contains a target instruction also includes the following implementation: if at least one of the second instructions contains a target instruction and there is no instruction between the target instruction and the first instruction, the computer device merges the target instruction into the first instruction to obtain the third instruction.

[0066] Among them, the instruction between the target instruction and the first instruction is the instruction whose processing order is between the two. The processing order of this instruction is later than the processing order of the first instruction, but earlier than the processing order of the target instruction.

[0067] In this embodiment, the target instruction is merged into the first instruction only when there is a target instruction in at least one second instruction and there is no instruction between the target instruction and the first instruction. This avoids the problem of program logic errors caused by the merged instruction and the instructions between them during processing, so that subsequent instruction processing can proceed normally, thereby improving the instruction processing efficiency.

[0068] Accordingly, if at least one second instruction contains a target instruction and there is a fourth instruction between the target instruction and the first instruction, the computer device compares the number of the target source register with the number of the result register of the fourth instruction. The target source register refers to the register in the source register of the target instruction that is different from the result register of the first instruction. If the target source register is different from the result register of the fourth instruction, the target instruction is merged into the first instruction to obtain the third instruction.

[0069] In this embodiment, when there is an instruction between the target instruction and the first instruction, the result register of the first instruction is compared with other source registers of the target instruction. If they are different, it means that the target instruction does not depend on the processing results of other instructions. In other words, merging the target instruction into the first instruction will not affect the processing of other instructions. Therefore, the target instruction is merged into the first instruction only in this case, which ensures the accuracy of the merging and avoids the problem of program logic errors caused by the processing of the merged instruction and the instructions between them. This allows subsequent instruction processing to proceed normally, thereby improving the processing efficiency of the instructions.

[0070] Accordingly, if the target source register of the target instruction is the same as the result register of the fourth instruction, the target instruction will not be merged into the first instruction.

[0071] In the embodiments of this application, if the two source registers of the target instruction are the same as the result registers of the first instruction and the fourth instruction, respectively, it indicates that the target instruction depends on both the first instruction and the fourth instruction. Such an instruction can be called an instruction with multiple dependencies.

[0072] For example, see Figure 7 , Figure 7 This is a schematic diagram illustrating a multi-dependency scenario provided by an embodiment of this application. In this scenario, the source register r2 of the instruction in delay stage 1 is the result register r2 of the instruction in delay stage 3. However, the result register r6 of the instruction in delay stage 2 is the same as another source register of the instruction in delay stage 1. That is, the instruction in delay stage 1 depends on both the instruction in delay stage 3 and the instruction in delay stage 2. If the instruction in delay stage 1 is merged into the instruction in delay stage 3, it will lead to a semantic error in the program. Therefore, these two instructions cannot be merged. In this embodiment, when merging one instruction into another, it is also determined whether the instruction depends on the instruction between the two, thereby avoiding semantic errors and ensuring the processing efficiency of subsequent instructions.

[0073] In some embodiments, at least one second instruction may contain multiple instructions whose source register is the same as the result register of the first instruction. Accordingly, if at least one second instruction contains multiple fifth instructions, the computer device outputs the fifth instruction with the earliest processing order among the multiple fifth instructions as the target instruction. Each fifth instruction refers to an instruction whose source register is the same as the result register of the first instruction.

[0074] In this embodiment, the instruction with the earliest processing order is taken as the target instruction, that is, the instruction with the closest processing order to the first instruction is taken as the target instruction. Since the processing order between the first instruction and the target instruction is closer, the probability that there is an instruction between them is smaller. Furthermore, the probability that there is a fourth instruction that the target instruction depends on is smaller. That is, the probability of multiple dependencies can be effectively reduced, the possibility of instruction merging can be increased, and the processing efficiency of subsequent instructions can be improved.

[0075] In other embodiments, the computer device outputs the instruction with the earliest processing order among multiple fifth instructions that do not have multiple dependencies as the target instruction, in order to further increase the probability of instruction merging.

[0076] In some embodiments, the computer device outputs the target instruction in the following manner: The computer device compares multiple second instructions with the first instruction respectively to obtain a comparison result of preset bits. This preset bit count matches the number of second instructions; for example, if there are three second instructions, a 3-bit comparison result is output. The value of each bit represents the comparison result of one second instruction, with 1 indicating a match and 0 indicating a mismatch. Specifically, the computer device starts detecting bits with a value of 1 from the highest bit of the comparison result. The highest bit is the leftmost bit and indicates the comparison result of the instruction processed earliest. The instruction corresponding to the first detected bit with a value of 1 is output as the target instruction. Optionally, the computer device performs instruction comparison through a comparison unit and outputs the comparison result of the preset bits through the comparison unit.

[0077] In some embodiments, the merging apparatus further includes a leading zero detect (lzd) unit, which is connected to the comparison unit. The leading zero detect unit is used to determine the target instruction based on the comparison result of preset bits.

[0078] See Figure 8 , Figure 8 This is a schematic diagram of instruction filtering provided in an embodiment of this application. Taking a comparison result of 001 as an example, the leading zero detection unit traverses from the most significant bit of the comparison result, and the position of the first '1' is bit 0, meaning the instruction in delay stage 0 is the target instruction. As another example, taking a comparison result of 010 as an example, traversing from the most significant bit, the position of the first '1' is bit 1, and the instruction in delay stage 1 is the target instruction.

[0079] In other embodiments, the computer device compares the second instruction processed earlier with the first instruction. Once a target instruction is found, the remaining instructions are not compared, thus reducing the number of comparisons and saving resources. Accordingly, the process by which the computer device compares the result register number of the first instruction with the source register numbers of at least one second instruction includes the following steps: based on the processing order of the at least one second instruction, the computer device compares the at least one second instruction with the first instruction in ascending order; if a second instruction is found to have a source register that is the same as the result register of the first instruction, the matched second instruction is output as the target instruction.

[0080] In this process, at least one second instruction is compared with the first instruction in ascending order. That is, the earlier the processing order, the earlier the comparison order. Accordingly, the instruction with the earliest processing order among the at least one second instruction is compared with the first instruction first.

[0081] In the embodiments of this application, based on the processing order of at least one second instruction, at least one second instruction is compared with the first instruction in ascending order in sequence, thereby quickly matching the target instruction with an earlier processing order. After matching the target instruction with an earlier processing order, there is no need to compare the remaining second instructions, thereby reducing the number of comparisons, saving resources, and improving efficiency.

[0082] In some embodiments, the merging apparatus further includes an instruction merging unit connected to a leading zero detection unit. The instruction merging unit is used to merge instructions; that is, the computer device merges a target instruction into a first instruction to obtain a third instruction. Furthermore, the instruction merging unit is also connected to a pipeline unit to obtain instructions from the pipeline unit for merging.

[0083] In this embodiment of the application, since an instruction can be merged at most once, and since an instruction corresponds to one operation, an instruction can have at most two source registers. Therefore, the merged instruction can have at most three source registers and two result registers.

[0084] 304. The computer device sends a third instruction to the data processing device, which retrieves data from the source register of the first instruction and processes it to obtain a first processing result. Based on the first processing result and the data retrieved from the target source register of the target instruction, the device processes the data to obtain a second processing result. The first processing result is stored in the result register of the first instruction, and the second processing result is stored in the result register of the second instruction. The target source register refers to a register in the source register of the target instruction that is different from the result register of the first instruction.

[0085] In this embodiment of the application, the processor further includes a data processing device, which is used to obtain data from the source register based on instructions and process it to obtain the data processing result, and store the processing result in the result register. That is, the data processing device is used to process multiple instructions to obtain the data processing result.

[0086] In some embodiments, the merging apparatus further includes an issue queue unit connected to the instruction merging unit and the data processing device. The issue queue unit receives instructions sent by the instruction merging unit and sends the instructions to the data processing device. Wherein, after any instruction is merged into the first instruction, the instruction sent by the instruction merging unit is the third instruction. If any instruction is not merged into the first instruction, the instruction sent by the instruction merging unit is the first instruction.

[0087] Specifically, if the instruction queue unit processes received instructions immediately, it sends each received instruction to the data processing device. If the instruction queue unit processes received instructions periodically, it sends each instruction to the data processing device after the sending cycle has elapsed. If all instructions in the data processing task are traversed before processing, the instruction queue unit sends each instruction to the data processing device in the order they were processed after receiving the last instruction.

[0088] In this method, when executing the instruction merging process, the computer device can perform data processing based on the instructions after traversing all the instructions; or, since the computer device traverses the instructions according to their processing order, it can merge instructions with a later processing order while processing data based on instructions with a earlier processing order. That is, while the merging device processes instructions with a later processing order, the data processing device processes data based on instructions already processed by the merging device. By synchronizing the instruction merging process and the instruction processing process, the processing time of the data processing task is shortened, thereby improving processing efficiency.

[0089] In some embodiments, the data processing device retrieves data from the corresponding source register in the register library based on an instruction, and then sends the instruction and data to the execution unit. The register library includes multiple registers and the data stored in those registers. The execution unit comprises two levels, each used to execute a two-step operation within the merged instruction. The execution unit is connected to the register library and is used to store the processing results in registers within the register library.

[0090] Each execution unit can execute all instructions defined in the instruction set, including arithmetic instructions such as addition, subtraction, multiplication, and division, logical instructions such as AND, OR, and NOT, and shift operation instructions. The first-level execution unit executes the first instruction before merging, and the second-level execution unit executes the target instruction before merging. The second-level execution unit is connected to the first-level execution unit and can directly use the processing results of the first-level execution unit, thus eliminating the need to retrieve the processing results of the first instruction from registers.

[0091] The first-level execution unit can send the first processing result to the result register of the first instruction and the second-level execution unit respectively, so that the storage of the result of the first instruction and the processing of the target instruction do not interfere with each other. Alternatively, after obtaining the two processing results, the two processing results can be stored in their respective result registers. This parallel storage of the two processing results can effectively shorten the processing time and improve the processing efficiency compared to serial storage of the two processing results.

[0092] It should be noted that, since the execution unit in a scalar processor only needs to complete one operation, the hardware resources required by the execution unit are very small. Therefore, the area overhead of placing two identical execution units in the data processing device is very small, thereby improving the processing efficiency of instructions while reducing the impact on the processor hardware.

[0093] For example, see Figure 9 , Figure 9 This is a flowchart of an execution unit provided in an embodiment of this application. The merged instruction includes two operations: addition and multiplication. The instruction corresponding to the first-level execution unit is rd0 = rs0 + rs1, which instructs the unit to retrieve data from the source registers rs0 and rs1, perform addition, and store the result in the result register rd0. The instruction corresponding to the second-level execution unit is rd1 = (rs0 + rs1) × rs2, which instructs the unit to perform multiplication based on the data retrieved from the source register rs2 and the processing result of the first-level execution unit, and store the result in the result register rd1.

[0094] For example, see Figure 10 , Figure 10 This is a schematic diagram of a processor provided in an embodiment of this application. The processor includes a front-end processing unit, a merging unit, and a data processing unit. The merging unit includes a pipeline unit 1001, a comparison unit 1002, a leading zero detection unit 1003, an instruction merging unit 1004, and an instruction queue unit 1005. The data processing unit includes a register bank 1006 and a two-level execution unit 1007.

[0095] In some embodiments, when a processor processes a data processing task, the hardware executes multiple instructions defined for that task sequentially according to the instruction set, with each instruction occupying a corresponding instruction space. For example, in the instruction issue queue, an entry needs to be allocated for each instruction, but the total number of entries in the instruction issue queue is limited. When the instruction issue queue is full, it will block the pipeline, causing performance loss. However, in this embodiment, related instructions are merged, and the merged instruction occupies only one entry in the instruction issue queue, resulting in higher utilization of the instruction issue queue and thus improved performance. Furthermore, after two related instructions are merged into one instruction, they are executed together in that single instruction, requiring only one instruction issue instead of sending the related instructions separately, which obviously improves efficiency.

[0096] Therefore, the instruction merging method provided in this application reduces the instruction space usage and the number of instruction issues, and also reduces the time spent retrieving data from the result register of related instructions, thereby improving the overall processing performance of data processing tasks and thus improving the overall performance of the processor. Furthermore, more and more processor instruction sets are moving towards lightweight design; for example, the basic instruction set of the RISC-CV architecture contains only a few dozen instructions, meaning a data processing task consists of only a few dozen instructions. This simplifies the processor's microarchitecture design, allowing more space to be allocated to components that significantly impact performance, thus improving the overall processor performance.

[0097] The instruction merging method provided in this application takes advantage of the fact that related instructions have a high probability of appearing in a local area, and merges related instructions into one instruction. In this way, during the execution of subsequent instructions, only the storage space of one instruction is occupied, and the processing efficiency is very high, thereby improving the overall performance of data processing.

[0098] This application provides an instruction merging method. Considering that the processing order of instructions can reflect dependencies to a certain extent, the comparison range of instructions is determined based on the processing order. For the first instruction, comparing it with instructions processed later in the order increases the probability of a successful comparison. During the comparison process, the result register number of the instruction and the source register number of the compared instruction are used to accurately identify the target instruction that has a dependency relationship with the first instruction. The target instruction is then merged into the first instruction to obtain the third instruction. Since the processing of the first instruction and the target instruction is performed synchronously in the third instruction, the processing result of the first instruction can be directly applied when processing the target instruction. In this case, the processing result of the first instruction is not stored separately in a result register, thus greatly saving storage time. Furthermore, the processing result of the first instruction is directly passed to the processing of the target instruction, further saving the reading time that might occur from separate storage, thereby improving instruction processing efficiency.

[0099] Figure 11 This is a block diagram of an instruction merging apparatus according to an embodiment of this application. See also... Figure 11 The device includes: The acquisition module 1101 is used to acquire multiple instructions in the data processing task. Each instruction indicates that data should be acquired from at least one source register and processed, and the processing result should be stored in its respective result register. The comparison module 1102 is used to compare the result register number of each first instruction among multiple instructions with the source register number of each of at least one second instruction, wherein the at least one second instruction is an instruction whose processing order is located at a preset position after the first instruction; The merging module 1103 is used to merge the target instruction into the first instruction to obtain the third instruction if at least one second instruction contains a target instruction. The target instruction is an instruction whose source register is the same as the result register of the first instruction.

[0100] In some embodiments, the source register of the third instruction includes the source register of the first instruction and the target source register of the target instruction, the result register of the target instruction includes the result register of the first instruction and the result register of the target instruction, and the target source register refers to a register in the source register of the target instruction that is different from the result register of the first instruction.

[0101] In some embodiments, the merging module 1103 is configured to: If at least one second instruction contains a target instruction and there is no instruction between the target instruction and the first instruction, the target instruction is merged into the first instruction to obtain the third instruction.

[0102] In some embodiments, the merging module 1103 is configured to: If at least one second instruction contains a target instruction and there is a fourth instruction between the target instruction and the first instruction, the number of the target source register is compared with the number of the result register of the fourth instruction. The target source register refers to the register in the source register of the target instruction that is different from the result register of the first instruction. If the target source register is different from the result register of the fourth instruction, the target instruction is merged into the first instruction to obtain the third instruction.

[0103] In some embodiments, the apparatus further includes an output module for: If there are multiple fifth instructions in at least one second instruction, the fifth instruction with the earliest processing order among the multiple fifth instructions is output as the target instruction. Each fifth instruction refers to an instruction whose source register is the same as the result register of the first instruction.

[0104] In some embodiments, the comparison module 1102 is configured to: Based on the processing order of at least one second instruction, compare at least one second instruction with the first instruction in ascending order; If a second instruction is matched to a source register that is the same as the result register of the first instruction, the matched second instruction is output as the target instruction.

[0105] In some embodiments, the comparison module 1102 is configured to: The instructions are traversed according to the processing order, and the instructions that have been traversed are output to the first instruction. If the first instruction is not merged into other instructions, the result register number of the first instruction is compared with the source register numbers of at least one second instruction.

[0106] This application provides an instruction merging apparatus. Considering that the processing order of instructions can reflect dependencies to a certain extent, the comparison range of instructions is determined based on the processing order. Therefore, for a first instruction, comparing it with instructions processed later in the order increases the probability of a successful comparison. During the comparison process, the result register number of the instruction and the source register number of the compared instruction are used to accurately identify the target instruction that has a dependency relationship with the first instruction. The target instruction is then merged into the first instruction to obtain a third instruction. Since the processing of the first instruction and the target instruction is performed synchronously in the third instruction, the processing result of the first instruction can be directly applied when processing the target instruction. In this case, the processing result of the first instruction is not stored separately in a result register, thus greatly saving storage time. Furthermore, the processing result of the first instruction is directly passed to the processing of the target instruction, further saving the reading time that might occur from separate storage, thereby improving instruction processing efficiency.

[0107] It should be noted that the instruction merging device provided in the above embodiments is only illustrated by the division of the above functional modules when performing instruction merging. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the instruction merging device and instruction merging method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0108] In the embodiments of this application, the computer device can be a terminal or a server. When the computer device is a terminal, the terminal acts as the execution subject to implement the technical solution provided in the embodiments of this application; when the computer device is a server, the server acts as the execution subject to implement the technical solution provided in the embodiments of this application; or, the technical solution provided in this application can be implemented through the interaction between the terminal and the server. The embodiments of this application do not limit this.

[0109] Figure 12 A structural block diagram of a terminal 1200 provided in an exemplary embodiment of this application is shown.

[0110] Typically, terminal 1200 includes a processor 1201 and a memory 1202.

[0111] Processor 1201 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1201 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1201 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1201 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1201 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0112] The memory 1202 may include one or more computer-readable storage media, which may be non-transitory. The memory 1202 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1202 are used to store at least one program code, which is executed by the processor 1201 to implement the instruction merging method provided in the method embodiments of this application.

[0113] In some embodiments, the terminal 1200 may also optionally include a peripheral device interface 1203 and at least one peripheral device. The processor 1201, memory 1202, and peripheral device interface 1203 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 1203 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of the following: radio frequency circuitry 1204, display screen 1205, camera assembly 1206, audio circuitry 1207, and power supply 1208.

[0114] Peripheral device interface 1203 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 1201 and memory 1202. In some embodiments, processor 1201, memory 1202 and peripheral device interface 1203 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 1201, memory 1202 and peripheral device interface 1203 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0115] The radio frequency (RF) circuit 1204 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 1204 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 1204 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals back into electrical signals. Optionally, the RF circuit 1204 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The RF circuit 1204 can communicate with other terminals through at least one wireless communication protocol. This wireless communication protocol includes, but is not limited to: the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 1204 may also include circuitry related to NFC (Near Field Communication), which is not limited in this application.

[0116] Display screen 1205 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 1205 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 1201 for processing. In this case, display screen 1205 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 1205, disposed on the front panel of terminal 1200; in other embodiments, there may be at least two display screens, disposed on different surfaces of terminal 1200 or in a folded design; in still other embodiments, display screen 1205 may be a flexible display screen, disposed on a curved or folded surface of terminal 1200. Furthermore, display screen 1205 may also be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. The display screen 1205 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0117] The camera assembly 1206 is used to acquire images or videos. Optionally, the camera assembly 1206 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the terminal, and the rear-facing camera is located on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 1206 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm-light flash and a cool-light flash, which can be used for light compensation at different color temperatures.

[0118] The audio circuit 1207 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, converting the sound waves into electrical signals that are input to the processor 1201 for processing, or input to the radio frequency circuit 1204 for voice communication. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each positioned at a different location on the terminal 1200. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert electrical signals from the processor 1201 or the radio frequency circuit 1204 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 1207 may also include a headphone jack.

[0119] Power supply 1208 is used to power the various components in terminal 1200. Power supply 1208 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1208 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged via a wired line, and a wireless rechargeable battery is a battery that is charged via a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0120] In some embodiments, the terminal 1200 further includes one or more sensors 1209. The one or more sensors 1209 include, but are not limited to: an acceleration sensor 1210, a gyroscope sensor 1211, a pressure sensor 1212, an optical sensor 1213, and a proximity sensor 1214.

[0121] Accelerometer 1210 can detect the magnitude of acceleration on the three coordinate axes of a coordinate system established with terminal 1200. For example, accelerometer 1210 can be used to detect the components of gravitational acceleration on the three coordinate axes. Processor 1201 can control display screen 1205 to display the user interface in either a landscape or portrait view based on the gravitational acceleration signal acquired by accelerometer 1210. Accelerometer 1210 can also be used for games or for acquiring user motion data.

[0122] The gyroscope sensor 1211 can detect the orientation and rotation angle of the terminal 1200. The gyroscope sensor 1211 can work in conjunction with the accelerometer sensor 1210 to collect the user's 3D movements on the terminal 1200. Based on the data collected by the gyroscope sensor 1211, the processor 1201 can perform the following functions: motion sensing (e.g., changing the UI based on the user's tilt), image stabilization during shooting, game control, and inertial navigation.

[0123] The pressure sensor 1212 can be disposed on the side bezel of the terminal 1200 and / or on the lower layer of the display screen 1205. When the pressure sensor 1212 is disposed on the side bezel of the terminal 1200, it can detect the user's grip signal on the terminal 1200, and the processor 1201 can perform left / right hand recognition or quick operation based on the grip signal collected by the pressure sensor 1212. When the pressure sensor 1212 is disposed on the lower layer of the display screen 1205, the processor 1201 can control the operable controls on the UI interface based on the user's pressure operation on the display screen 1205. The operable controls include at least one of button controls, scroll bar controls, icon controls, and menu controls.

[0124] Optical sensor 1213 is used to collect ambient light intensity. In one embodiment, processor 1201 can control the display brightness of display screen 1205 based on the ambient light intensity collected by optical sensor 1213. Specifically, when the ambient light intensity is high, the display brightness of display screen 1205 is increased; when the ambient light intensity is low, the display brightness of display screen 1205 is decreased. In another embodiment, processor 1201 can also dynamically adjust the shooting parameters of camera assembly 1206 based on the ambient light intensity collected by optical sensor 1213.

[0125] The proximity sensor 1214, also known as a distance sensor, is typically located on the front panel of the terminal 1200. The proximity sensor 1214 is used to detect the distance between the user and the front of the terminal 1200. In one embodiment, when the proximity sensor 1214 detects that the distance between the user and the front of the terminal 1200 is gradually decreasing, the processor 1201 controls the display screen 1205 to switch from a screen-on state to a screen-off state; when the proximity sensor 1214 detects that the distance between the user and the front of the terminal 1200 is gradually increasing, the processor 1201 controls the display screen 1205 to switch from a screen-off state to a screen-on state.

[0126] Those skilled in the art will understand that Figure 12 The structure shown does not constitute a limitation on terminal 1200 and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0127] Figure 13This is a schematic diagram of a server structure according to an embodiment of this application. The server 1300 can vary considerably due to different configurations or performance. It may include one or more Central Processing Units (CPUs) 1301 and one or more memories 1302. The memories 1302 are used to store executable program code, and the processors 1301 are configured to execute the executable program code to implement the instruction merging method provided in the various method embodiments described above. Of course, the server may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server may also include other components for implementing device functions, which will not be elaborated here.

[0128] This application also provides a chip, which includes a processor and a memory. The memory is used to store at least one program, which is loaded and executed by the processor using an instruction merging method implemented in any of the above-described ways.

[0129] This application also provides a computer-readable storage medium storing at least one program, which is loaded and executed by a processor to implement the instruction merging method of any of the above implementations.

[0130] This application also provides a computer program product, which includes at least one program segment stored in a computer-readable storage medium. The processor of a computer device reads the at least one program segment from the computer-readable storage medium and executes the at least one program segment, causing the computer device to execute the instruction merging method of any of the above implementations.

[0131] In some embodiments, the computer program product involved in the present application can be deployed and executed on a computer device, or on multiple computer devices located in one location, or on multiple computer devices distributed in multiple locations and interconnected through a communication network. Multiple computer devices distributed in multiple locations and interconnected through a communication network can form a blockchain system.

[0132] All the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here. The above are only optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for merging instructions, characterized in that, The method includes: The system retrieves multiple instructions from a data processing task. Each instruction instructs the retrieval of data from at least one source register and the processing of the data, and stores the processing results in its respective result register. For each of the multiple instructions, the result register number of the first instruction is compared with the source register number of each of the at least one second instruction, wherein the at least one second instruction is an instruction whose processing order is located at a preset position after the first instruction; If a target instruction exists in at least one of the second instructions, the target instruction is merged into the first instruction to obtain a third instruction. The target instruction is an instruction whose source register is the same as the result register of the first instruction.

2. The method according to claim 1, characterized in that, The source register of the third instruction includes the source register of the first instruction and the target source register of the target instruction. The result register of the target instruction includes the result register of the first instruction and the result register of the target instruction. The target source register refers to a register in the source register of the target instruction that is different from the result register of the first instruction.

3. The method according to claim 1, characterized in that, If a target instruction exists in at least one of the second instructions, the target instruction is merged into the first instruction to obtain a third instruction, including: If a target instruction exists in at least one of the second instructions and there is no instruction between the target instruction and the first instruction, the target instruction is merged into the first instruction to obtain a third instruction.

4. The method according to claim 3, characterized in that, If a target instruction exists in at least one of the second instructions, the target instruction is merged into the first instruction to obtain a third instruction, including: If a target instruction exists in the at least one second instruction and a fourth instruction exists between the target instruction and the first instruction, the number of the target source register is compared with the number of the result register of the fourth instruction. The target source register refers to the register in the source register of the target instruction that is different from the result register of the first instruction. If the target source register is different from the result register of the fourth instruction, the target instruction is merged into the first instruction to obtain the third instruction.

5. The method according to claim 1, characterized in that, The method further includes: If there are multiple fifth instructions among the at least one second instruction, the fifth instruction with the earliest processing order among the multiple fifth instructions is output as the target instruction. Each fifth instruction refers to an instruction whose source register is the same as the result register of the first instruction.

6. The method according to claim 1, characterized in that, The step of comparing the result register number of the first instruction with the source register numbers of at least one second instruction includes: Based on the processing order of the at least one second instruction, the at least one second instruction is sequentially compared with the first instruction in ascending order; If a second instruction is matched to a source register that is the same as the result register of the first instruction, the matched second instruction is output as the target instruction.

7. The method according to claim 1, characterized in that, The step of comparing the result register number of each of the plurality of instructions with the source register number of each of the at least one second instruction includes: The instructions are traversed according to the processing order of the instructions, and the instructions that have been traversed are output to the first instruction. If the first instruction is not merged into other instructions, the result register number of the first instruction is compared with the source register number of each of at least one second instruction.

8. An instruction merging device, characterized in that, The device includes: The acquisition module is used to acquire multiple instructions in the data processing task. Each instruction instructs to acquire data from at least one source register and process it, and store the processing result in its respective result register. The comparison module is used to compare the result register number of each first instruction among the multiple instructions with the source register number of each of the at least one second instruction, wherein the at least one second instruction is an instruction whose processing order is located at a preset position after the first instruction; The merging module is used to merge the target instruction into the first instruction to obtain a third instruction if a target instruction exists in the at least one second instruction, wherein the target instruction is an instruction whose source register is the same as the result register of the first instruction.

9. A chip, characterized in that, The chip includes a processor and a memory, the memory being used to store at least one program, the at least one program being loaded by the processor and executed by the instruction merging method according to any one of claims 1-7.

10. A computer device, characterized in that, The computer device includes a processor and a memory, the memory being used to store at least one program, the at least one program being loaded by the processor and executed according to the instruction merging method of any one of claims 1 to 7.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store at least one program segment for executing the instruction merging method according to any one of claims 1 to 7.

12. A computer program product, characterized in that, The computer program product includes at least one program segment stored in a computer-readable storage medium, a processor of a computer device reads the at least one program segment from the computer-readable storage medium, and the processor executes the at least one program segment, causing the computer device to perform the instruction merging method according to any one of claims 1 to 7.

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