Display device and display method

Abstract

The invention provides a display device and a display method. The display device comprises a display panel and a driving circuit. The display panel comprises M rows of sub-pixels, a first gate line and M second gate lines, the first gate line is electrically connected with the first row of sub-pixels in the M rows of sub-pixels, and the M second gate lines are electrically connected with the M rows of sub-pixels in a one-to-one correspondence manner; the driving circuit is electrically connected with the first gate line and the M second gate lines; the driving circuit is used for receiving picture data of a to-be-displayed frame picture and outputting a first gate signal corresponding to the signal parameter and the picture data to the first gate line to open the first gate line when a display period of the to-be-displayed frame picture starts; and outputting corresponding second gate signals to the M second gate lines so as to turn on the M second gate lines line by line, wherein the signal parameters comprise at least one of turn-on voltage, rise time and fall time. According to the display device, the problem that the first row of sub-pixels become dark or bright can be solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to display devices and display methods. Background Technology

[0002] With the continuous development of display technology, TFT-LCD (Thin Film Transistor Liquid Crystal Display) has made significant progress in achieving high resolution, narrow bezels, and large sizes. However, display uniformity remains one of the key challenges affecting high-quality displays. Especially in certain picture modes, the first row of pixels on the screen is prone to observable darkening or brightening, a phenomenon known as display inhomogeneity (Mura). This problem seriously affects the user's visual experience and the quality of display products. Summary of the Invention

[0003] In view of this, the main objective of this application is to provide a display device and display method that aims to solve the problem that the first row of pixels in existing TFT-LCD screens is prone to observable dimming or brightening.

[0004] To achieve the above objectives, a first aspect of this application provides a display device, comprising a display panel and a driving circuit. The display panel includes M rows of sub-pixels, a first gate line, and M second gate lines, where M>1; wherein the first gate line and the M second gate lines extend along the row direction and are spaced apart along the column direction; the first gate line is electrically connected to a first row of sub-pixels in the M rows of sub-pixels, and the M second gate lines are electrically connected to each of the M rows of sub-pixels in a one-to-one correspondence; the driving circuit is electrically connected to both the first gate line and the M second gate lines; wherein the driving circuit is configured to receive image data of a frame to be displayed, and at the start of the display cycle of the frame to be displayed, output a first gate signal corresponding to the image data to the first gate line to turn on the first gate line, and output corresponding second gate signals to the M second gate lines to turn on the M second gate lines row by row; wherein the signal parameters include at least one of a turn-on voltage, a rise time, and a fall time.

[0005] The display device provided in this application provides a separate first gate line for the first row of sub-pixels, isolating the gate architecture of the first row of sub-pixels. This allows for independent driving of the first row of sub-pixels, physically and temporally isolating the charging process of the first row of sub-pixels from that of sub-pixels in other areas of the display panel. This completely avoids the problem of charging efficiency being affected by excessive transmission impedance. Furthermore, at the start of the display cycle of the frame to be displayed, the driving circuit outputs a first gate signal with signal parameters corresponding to the image data to the first gate line, thereby activating the first gate line. This allows for the dynamic selection of the most suitable first gate signal with the most appropriate signal parameters to activate the first gate line and charge the first row of sub-pixels, thus improving the problem of the first row of sub-pixels appearing too dark or too bright.

[0006] In some embodiments of this application, the driving circuit is used to determine the image type of the image to be displayed based on the image data of the image to be displayed; if the image to be displayed is an image type where the first line is lit, the driving circuit is used to output a first gate signal with a first parameter to the first gate line at the beginning of the display cycle of the image to be displayed; wherein, the first parameter is different from the signal parameter of the second gate signal.

[0007] In some embodiments of this application, if the frame to be displayed is a type of image with the first line darkened, the driving circuit is used to output a first gate signal with a second parameter to the first gate line at the beginning of the display cycle of the frame to be displayed; wherein the first parameter, the second parameter, and the signal parameters of the second gate signal are all different.

[0008] In some embodiments of this application, the first row of bright images includes at least one of overloaded images and solid grayscale images with a target brightness value higher than a first brightness threshold, and the first row of dark images includes solid grayscale images with a target brightness value lower than a second brightness threshold; wherein, the first brightness threshold is higher than the second brightness threshold.

[0009] In some embodiments of this application, the signal parameters include an on-state voltage; if the frame to be displayed is a type where the first line is lit, the driving circuit is used to output a first gate signal with an on-state voltage of the first on-state voltage to the first gate line at the start of the display cycle of the frame to be displayed; if the frame to be displayed is a type where the first line is dark, the driving circuit is used to output a first gate signal with an on-state voltage of the second on-state voltage to the first gate line at the start of the display cycle of the frame to be displayed; wherein, the first on-state voltage is less than the second on-state voltage.

[0010] In some embodiments of this application, the signal parameters include fall time; if the frame to be displayed is a type of image where the first line is lit, the driving circuit is used to output a first gate signal with a fall time of a first fall time to the first gate line at the beginning of the display cycle of the frame to be displayed; if the frame to be displayed is a type of image where the first line is dark, the driving circuit is used to output a first gate signal with a fall time of a second fall time to the first gate line at the beginning of the display cycle of the frame to be displayed; wherein, the first fall time is greater than the second fall time.

[0011] In some embodiments of this application, the M rows of sub-pixels are arranged in an M-row, N-column array; the display panel further includes N data lines, N>1; the N data lines extend along the column direction and are spaced apart along the row direction, and the N data lines correspond one-to-one with the N columns of sub-pixels; each sub-pixel includes a pixel electrode and a first scanning transistor. The first scanning transistor includes a first gate, a first electrode, and a second electrode. The first gate of the first scanning transistor is electrically connected to the second gate line corresponding to the sub-pixel in the same row, the first electrode of the first scanning transistor is electrically connected to the data line corresponding to the sub-pixel in the same column, and the second electrode of the first scanning transistor is electrically connected to the pixel electrode of the sub-pixel; wherein, each first scanning transistor in the first row of sub-pixels further includes a second gate, and the second gate is electrically connected to the first gate line.

[0012] In some embodiments of this application, the M rows of sub-pixels are arranged in an M-row, N-column array; the display panel further includes N data lines, N>1; the N data lines extend along the column direction and are spaced apart along the row direction, and the N data lines correspond one-to-one with the N columns of sub-pixels; each sub-pixel includes a pixel electrode and a second scanning transistor. The second scanning transistor includes a gate, a first electrode, and a second electrode. The gate of the second scanning transistor is electrically connected to the second gate line corresponding to the sub-pixel in the same row, the first electrode of the second scanning transistor is electrically connected to the data line corresponding to the sub-pixel in the same column, and the second electrode of the second scanning transistor is electrically connected to the pixel electrode of the sub-pixel; wherein, each sub-pixel in the first row further includes a third scanning transistor, wherein the third scanning transistor includes a gate, a first electrode, and a second electrode. The gate of the third scanning transistor is electrically connected to the first gate line, the first electrode of the third scanning transistor is electrically connected to the data line corresponding to the sub-pixel in the same column, and the second electrode of the second scanning transistor is electrically connected to the pixel electrode of the sub-pixel.

[0013] In some embodiments of this application, the driving circuit includes a level conversion module, a power management chip, and a timing controller. The level conversion module is electrically connected to the first gate line; the timing controller is electrically connected to both the level conversion module and the power management chip. The timing controller receives image data of a frame to be displayed, and at the start of the display cycle of the frame to be displayed, outputs a clock signal to the level conversion module. When the frame to be displayed is a frame type where the first line is lit, the timing controller controls the power management chip to output a first turn-on voltage to the level conversion module, so that the level conversion module outputs a first gate signal with a first turn-on voltage to the first gate line based on the clock signal and the first turn-on voltage. When the frame to be displayed is a frame type where the first line is dark, the timing controller controls the power management chip to output a second turn-on voltage to the level conversion module, so that the level conversion module outputs a first gate signal with a second turn-on voltage to the first gate line based on the clock signal and the second turn-on voltage.

[0014] A second aspect of this application also provides a display method applied to the display device described in the first aspect. The display method includes: receiving image data of a frame to be displayed via a driving circuit; turning on the first gate line by outputting a first gate signal with signal parameters corresponding to the image data to a first gate line in the display panel at the start of the display cycle of the frame to be displayed via the driving circuit; and turning on the M second gate lines row by row by outputting corresponding second gate signals to M second gate lines in the display panel via the driving circuit; wherein the signal parameters include at least one of a turn-on voltage, a rise time, and a fall time.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of an LCD display device in related technologies; Figure 2 This is a schematic diagram of the structure of the display device provided in the embodiments of this application; Figure 3 for Figure 2 The timing diagram of the first gate signal and the second gate signal in the display device shown; Figure 4 For this Figure 2 The diagram shown illustrates the charging effect of the display device driven by two first gate signals with different turn-on voltages. Figure 5 For this Figure 2The diagram shown illustrates the charging effect of the display device driven by two first gate signals with different fall times. Figure 6 for Figure 2 A schematic diagram of the first circuit structure of a sub-pixel in the display device shown; Figure 7 for Figure 2 A schematic diagram of a second circuit structure for a sub-pixel in the display device shown; Figure 8 for Figure 2 The timing diagram of the drive signals for the display device is shown. Figure 9 A flowchart illustrating the display method provided in an embodiment of this application.

[0017] The annotations in the attached figures are explained as follows: 1-Display device; 1'-Display device; 10-Display panel; 10'-Display panel; 20-Drive circuit; 20'-Drive circuit; 21-Timing controller; 22-Power management chip; 23-Level conversion module; 24-Data drive circuit; 25-Gate drive circuit; 11-First gate line; 12-Second gate line; 13-Data line; P-Sub-pixel; G1.1-First gate signal; G1.11-First gate signal; G1.12-First gate signal; G1.13-First gate signal; G1.14-First gate signal; G1-Second gate signal; G2-Second gate signal; G3-Second gate signal ; GM - Second gate signal; VGL - Turn-off voltage; VGH1 - Turn-on voltage; VGH2 - Turn-on voltage; VGH11 - First turn-on voltage; VGH12 - Second turn-on voltage; td1 - Fall time; td2 - Fall time; T1 - First scan transistor; T2 - Second scan transistor; T3 - Third scan transistor; 111 - Pixel electrode; t1 - Charging time; t2 - Charging time; t3 - Charging time; t4 - Charging time; Data - Data voltage; CK1.1in - Clock signal; CK1in - Clock signal; CK2in - Clock signal; CK1 - Clock signal; CK10 - Clock signal.

[0018] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0019] In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions "a," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, "at least one" and "one or more" refer to one or more (including two). The term "and / or" is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0020] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0021] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0022] The various embodiments of this application can be combined arbitrarily to achieve different technical effects.

[0023] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an LCD display device in related technologies.

[0024] A conventional display device 1' includes a display panel 10' and a driving circuit 20'.

[0025] The display panel 10' includes multiple sub-pixels P, multiple data lines 13, and multiple second gate lines 12. The multiple sub-pixels P are arranged in a multi-row, multi-column array. The multiple data lines 13 are electrically connected to the multiple columns of sub-pixels P in a one-to-one correspondence. The multiple second gate lines 12 are electrically connected to the multiple rows of sub-pixels P in a one-to-one correspondence.

[0026] The driving circuit 20 includes a gate driving circuit 25 and a data driving circuit 24. The gate driving circuit 25 is electrically connected to each of the second gate lines 12. The data driving circuit 24 is electrically connected to each of the data lines 13.

[0027] During operation, the gate driving circuit 25 outputs corresponding gate signals to the plurality of second gate lines 12 to sequentially activate the plurality of second gate lines 12, thereby scanning multiple rows of sub-pixels P sequentially. Simultaneously, the data driving circuit 24 outputs corresponding data voltages to the scanned sub-pixels P in the corresponding column of sub-pixels P through each of the data lines 13, causing the plurality of sub-pixels P to receive the corresponding data voltages and emit light for display. In this embodiment, activating a gate line can be understood as the gate signal received by that gate line becoming an activation voltage, thereby controlling the activation of the scanning transistor in the corresponding sub-pixel P.

[0028] However, for traditional display devices 1', display uniformity has always been one of the key challenges affecting high-quality display. Especially in certain screen modes, the first row of subpixels on the screen is prone to observable darkening or brightening, i.e. display non-uniformity (Mura) defects. This problem seriously affects the user's visual experience and the quality of display products.

[0029] Research has revealed the following reasons for the issue of the first row of sub-pixels appearing either too dark or too bright: Firstly, the display non-uniformity of the first row of sub-pixels P mainly stems from a series of technical challenges arising from their unique physical location and scanning timing. Firstly, under conventional driving methods, the pre-charging process of the first row of sub-pixels P has inherent defects. Since the first row of sub-pixels is typically furthest from the data driving circuit 24, the long signal transmission path results in a large load on the resistor-capacitor (RC) circuit on the data line 13, leading to significant signal delay and voltage drop. If the pre-charging voltage is insufficient, the pixel capacitor and storage capacitor of the first row of sub-pixels P will have low charging rates, failing to reach the target voltage value within the limited gate scan opening time, thus exhibiting a darkening phenomenon due to insufficient actual driving voltage. Conversely, if the pre-charging voltage is set too high, it may cause overcharging of the first row of sub-pixels P, causing the pixel electrode voltage to exceed the target value, thus exhibiting a brightening phenomenon due to over-driving. Existing technologies use a fixed pre-charging voltage, which is difficult to adapt to threshold voltage drift caused by process fluctuations, panel size changes, or long-term use, and cannot accurately compensate for the special charging environment of the first row of sub-pixels.

[0030] Secondly, traditional pre-charging technology exhibits poor adaptability to screen content. Its pre-charging strategy is typically fixed and cannot dynamically adjust based on the specific content of the displayed image in the current or preceding / following frames (such as grayscale information of adjacent rows). This fixed driving method cannot guarantee the uniformity of the first row brightness in all display scenarios, limiting further improvements in display quality.

[0031] Therefore, there is an urgent need for an innovative display device that can achieve precise and adaptive pre-charge control for the special characteristics of the first row of pixels in TFT-LCDs, thereby effectively suppressing the brightness unevenness of the first row of sub-pixels P under various display conditions and improving the overall display quality.

[0032] In view of this, this application provides a display device 1. Please refer to the following: Figures 2-3 , Figure 2 This is a schematic diagram of the structure of the display device provided in the embodiments of this application; Figure 3 for Figure 2 The timing diagram of the first gate signal and the second gate signal in the display device is shown.

[0033] like Figure 2 As shown, the display device 1 includes a display panel 10 and a driving circuit 20.

[0034] The display panel 10 includes M rows of sub-pixels P, a first gate line 11, and M second gate lines 12, where M>1. The first gate line 11 and the M second gate lines 12 extend along the row direction and are spaced apart along the column direction. The first gate line 11 is electrically connected to the first row of sub-pixels P in the M rows of sub-pixels P, and the M second gate lines 12 are electrically connected to each of the M rows of sub-pixels P in a one-to-one correspondence.

[0035] In this way, the first row of sub-pixels P can be controlled by two independent gate lines, the first gate line 11 and the first row of second gate line 12, thus designing a control path for the first row of sub-pixels P that is independent of the traditional scanning system.

[0036] Wherein, the first row of sub-pixels P refers to the row of sub-pixels P that is farthest from the data driving circuit 24 in the driving circuit 20 among the M rows of sub-pixels P. The first gate line 11 is electrically connected to the first row of sub-pixels P in the M rows of sub-pixels P, meaning that the first gate line 11 is electrically connected to each sub-pixel P in the first row of sub-pixels P. The M second gate lines 12 are electrically connected to each of the M rows of sub-pixels P in a one-to-one correspondence, meaning that each second gate line 12 is electrically connected to each sub-pixel P in the corresponding row of sub-pixels P.

[0037] The driving circuit 20 is electrically connected to the first gate line 11 and the M second gate lines 12.

[0038] The driving circuit 20 is used to receive the image data of the frame to be displayed, and when the display cycle of the frame to be displayed begins, it outputs a first gate signal corresponding to the image data to the first gate line 11 to turn on the first gate line 11, and outputs a corresponding second gate signal to the M second gate lines 12 to turn on the M second gate lines 12 line by line.

[0039] Specifically, the operation of the display device 1 is as follows: At the start of the display cycle of the frame to be displayed, the first gate line 11 and the first row second gate line 12 are turned on first, so that the data voltage only charges the first row sub-pixel P.

[0040] After the first row of sub-pixels P is fully charged, the first gate line 11 and the first row of second gate lines 12 are turned off. Then, the second row of second gate lines 12 to the Nth row of second gate lines 12 are turned on sequentially according to the timing sequence to charge the second row of sub-pixels P to the Nth row of sub-pixels P in sequence. At this time, the brightness of the first row of sub-pixels P will not be affected by subsequent scanning after the charging is completed.

[0041] For example, such as Figure 3As shown, G1.1 is the timing diagram of the first gate signal, G1 is the timing diagram of the second gate signal received by the second gate line 12 in the first row, and the timing of G1.1 and G1 can be the same. G2 is the timing diagram of the second gate signal received by the second gate line 12 in the second row, G3 is the timing diagram of the second gate signal received by the second gate line 12 in the third row, and GM is the timing diagram of the second gate signal received by the second gate line 12 in the Mth row. VGH1 is the turn-on voltage of the first gate signal, VGH2 is the turn-on voltage of the second gate signal, and VGL is the turn-off voltage of the first gate signal and the second gate signal. The turn-on voltage VGH2 of the second gate signal received by each row of the second gate line 12 is the same, but VGH1 can be different from VGH2.

[0042] The signal parameters include at least one of the following: turn-on voltage, rise time, and fall time.

[0043] The turn-on voltage of the first gate signal is the voltage that controls the scanning transistor in sub-pixel P to turn on, and correspondingly, the turn-off voltage of the first gate signal is the voltage that controls the scanning transistor in sub-pixel P to turn off. For example, when the scanning transistor in sub-pixel P is an N-type transistor, the turn-on voltage is a high-level voltage, and the turn-off voltage is a low-level voltage.

[0044] The rise time of the first gate signal is the time required for the first gate signal to rise from a low level to a high level. The fall time of the first gate signal is the time required for the first gate signal to fall from a high level to a low level. Rise time and fall time are fundamental indicators for measuring the speed of signal level transitions.

[0045] The display device 1 provided in this application has a separate first gate line 11 for the first row of sub-pixels P, which isolates the gate architecture of the first row of sub-pixels P. This allows for independent driving of the first row of sub-pixels P, physically and temporally isolating the charging process of the first row of sub-pixels P from that of other areas of the display panel 10. This completely avoids the problem of the charging efficiency of the first row of sub-pixels P being affected by excessive transmission impedance. In addition, when the display cycle of the frame to be displayed begins, the driving circuit 20 outputs a first gate signal with signal parameters corresponding to the image data to the first gate line 11 to turn on the first gate line 11. This allows for the dynamic selection of the most suitable first gate signal with the most appropriate signal parameters to turn on the first gate line 11 and charge the first row of sub-pixels P, thereby improving the problem of the first row of sub-pixels P being too dark or too bright.

[0046] In some embodiments of this application, the cross-sectional area of ​​the first gate line 11 is larger than that of the second gate line 12. This allows for a lower resistance in the first gate line 11, resulting in a lower voltage drop during the transmission of the first gate signal.

[0047] In some embodiments of this application, the driving circuit 20 is used to determine the image type of the frame to be displayed based on the image data of the frame to be displayed.

[0048] If the frame to be displayed is a type of image where the first line is lit, the driving circuit 20 is used to output a first gate signal with a first parameter to the first gate line 11 at the start of the display cycle of the frame to be displayed.

[0049] If the frame to be displayed is a type of image where the first line is darkened, the driving circuit 20 is used to output a first gate signal with a second parameter to the first gate line 11 at the beginning of the display cycle of the frame to be displayed. The first parameter, the second parameter, and the second gate signal are all different.

[0050] The "first row bright" and "first row dark" image types can be determined from multiple different display images by detecting the brightness difference between the first row of sub-pixels P and other rows of sub-pixels P when the conventional display device 1' displays multiple different display images. For example, when the conventional display device 1' displays a first display image, if the brightness of the first row of sub-pixels P is higher than the brightness of the adjacent row of sub-pixels P, and the absolute value of the brightness difference between the first row of sub-pixels P and the adjacent row of sub-pixels P is higher than a first brightness difference, then the first display image is a "first row bright" image type. When the conventional display device 1' displays a second display image, if the brightness of the first row of sub-pixels P is lower than the brightness of the adjacent row of sub-pixels P, and the absolute value of the brightness difference between the first row of sub-pixels P and the adjacent row of sub-pixels P is higher than a second brightness difference, then the second display image is a "first row dark" image type.

[0051] Research has revealed that the types of images with a bright first row include at least one of the following: overloaded images and solid grayscale images with a target brightness value higher than a first brightness threshold. The types of images with a dark first row include solid grayscale images with a target brightness value lower than a second brightness threshold. The first brightness threshold is higher than the second brightness threshold.

[0052] It should be noted that, in the embodiments of this application, the types of images with the first row lit up and the types of images with the first row darkened are not limited to the listed types.

[0053] The heavy load screen is the screen corresponding to the data voltage output when the power consumption of the data driving circuit 24 in the driving circuit 20 exceeds a predetermined power consumption value. For example, the "one line bright, one line black" (H-Line) screen is a typical heavy load screen.

[0054] A pure color grayscale image with a target brightness value higher than a first brightness threshold is called a high-brightness pure color grayscale image. Here, pure color grayscale means that the target grayscale of all sub-pixels P in the display panel 10 is the same grayscale. For example, the first brightness threshold is 800 nits.

[0055] A pure color grayscale image with a target brightness value lower than a second brightness threshold, i.e., a low-brightness pure color grayscale image. For example, the second brightness threshold is 90 nits.

[0056] Thus, by outputting a first gate signal with signal parameters corresponding to the image type to the first gate line 11 according to the image type of the frame to be displayed, the problem of the first row being too bright when the display panel 10 displays an image of the first row being bright can be avoided, as can the problem of the first row being too dark when the display panel 10 displays an image of the first row being dark.

[0057] Please see Figure 4 , Figure 4 For this Figure 2 The diagram shown illustrates the charging effect of the display device driven by two first gate signals with different turn-on voltages.

[0058] In some embodiments of this application, the signal parameters include a turn-on voltage.

[0059] If the frame to be displayed is a type of image where the first line is lit, the driving circuit 20 is used to output a first gate signal G1.11 with a first turn-on voltage VGH11 to the first gate line 11 at the start of the display cycle of the frame to be displayed.

[0060] If the frame to be displayed is a type of image where the first line is dark, the driving circuit 20 is used to output a second first gate signal G1.12 with a second turn-on voltage VGH12 to the first gate line 11 at the start of the display cycle of the frame to be displayed.

[0061] Wherein, the first turn-on voltage VGH11 is less than the turn-on voltage VGH2 of the second gate signal, and the turn-on voltage VGH2 of the second gate signal is less than the second turn-on voltage VGH12.

[0062] For example Figure 4As shown, in the first type, the turn-on voltage of the first gate signal G1.11 is the first turn-on voltage VGH11, and the charging time of the first row sub-pixel P under the drive of the first gate signal G1.11 is t1. In the second type, the turn-on voltage of the first gate signal G1.12 is the second turn-on voltage VGH12, and the charging time of the first row sub-pixel P under the drive of the first gate signal G1.11 is t2.

[0063] Since the first turn-on voltage VGH11 is less than the second turn-on voltage VGH12, the charging time t1 is less than the charging time t2. Because the luminous intensity of sub-pixel P is positively correlated with the charging time, the luminous intensity of the first row of sub-pixels P can be individually adjusted by adjusting the voltage value of the first gate signal's turn-on voltage VGH1.

[0064] Thus, when the frame to be displayed is a type of image where the first row is lit, the driving circuit 20 outputs a first gate signal G1.11 with a first turn-on voltage of VGH11 to the first gate line 11. That is, it outputs a first gate signal with a lower turn-on voltage, which can shorten the charging time of the first row sub-pixels P, thereby avoiding the problem of the first row being too bright when the display panel 10 displays an image of the type where the first row is lit.

[0065] Similarly, when the frame to be displayed is a type of image where the first row is dark, the driving circuit 20 outputs a second first gate signal G1.12 to the first gate line 11 with a second turn-on voltage VGH12. That is, it outputs a first gate signal with a higher turn-on voltage, which can extend the charging time of the first row sub-pixel P, thereby avoiding the problem of the first row being too dark when the display panel 10 displays an image of the type where the first row is dark.

[0066] Please see Figure 5 , Figure 5 For this Figure 2 The diagram shown illustrates the charging effect when the display device is driven by two first gate signals with different fall times.

[0067] In some embodiments of this application, the signal parameters include the fall time.

[0068] If the frame to be displayed is a type of image where the first line is lit, the driving circuit 20 is used to output a first gate signal with a fall time of a first fall time td1 to the first gate line 11 at the start of the display cycle of the frame to be displayed.

[0069] If the frame to be displayed is a type of image where the first line is dark, the driving circuit 20 is used to output a first gate signal with a fall time of the second fall time td2 to the first gate line 11 at the beginning of the display cycle of the frame to be displayed.

[0070] Wherein, the first fall time td1 is greater than the fall time of the second gate signal, and the fall time of the second gate signal is greater than the second fall time td2.

[0071] For example Figure 5 As shown, the fall time of the third type of first gate signal G1.13 is the first fall time td1, and the charging time of the first row sub-pixel P under the drive of the third type of first gate signal G1.13 is t3. The fall time of the fourth type of first gate signal G1.14 is the second fall time td2, and the charging time of the first row sub-pixel P under the drive of the fourth type of first gate signal G1.11 is t4.

[0072] Since the first fall time td1 is greater than the second fall time td2, the charging time t3 is less than the charging time t4. Because the luminance of sub-pixel P is positively correlated with the charging time, the luminance of the first row of sub-pixels P can be adjusted individually by regulating the fall time of the first gate signal.

[0073] Thus, when the frame to be displayed is a type of image where the first row is lit, the driving circuit 20 outputs a first gate signal G1.13 with a fall time of the first fall time td1 to the first gate line 11, that is, outputs a first gate signal with a longer fall time, which can shorten the charging time of the first row sub-pixel P, thereby avoiding the problem of the first row being too bright when the display panel 10 displays an image of the type where the first row is lit.

[0074] Similarly, when the frame to be displayed is a type of image where the first row is dark, the driving circuit 20 outputs a first gate signal G1.14 with a fall time of the second fall time td2 to the first gate line 11, that is, outputs a first gate signal with a shorter fall time, which can extend the charging time of the first row sub-pixel P, thereby avoiding the problem of the first row being too dark when the display panel 10 displays an image of the type of image where the first row is dark.

[0075] In some embodiments of this application, the driving circuit 20 can simultaneously adjust the fall time and turn-on voltage of the first gate signal according to the image type of the frame to be displayed.

[0076] Specifically, if the frame to be displayed is a type of image where the first line is lit, the driving circuit 20 is used to output a first gate signal to the first gate line 11 at the beginning of the display cycle of the frame to be displayed, with a first turn-on voltage VGH11 and a fall time td1.

[0077] If the frame to be displayed is a type of image where the first line is dark, the driving circuit 20 is used to output a first gate signal to the first gate line 11 at the beginning of the display cycle of the frame to be displayed, with the turn-on voltage being the second turn-on voltage VGH12 and the fall time being the second fall time td2.

[0078] Please see Figure 6 , Figure 6 for Figure 2 The diagram shows a first circuit structure of a sub-pixel in the display device.

[0079] In some embodiments of this application, the M rows of sub-pixels P are arranged in an M-row, N-column array. The display panel 10 also includes N data lines 13, where N>1. The N data lines 13 extend along the column direction and are spaced apart along the row direction, with each of the N data lines 13 corresponding to one of the N columns of sub-pixels P.

[0080] Each of the sub-pixels P includes a pixel electrode 111 and a first scanning transistor T1.

[0081] The first scanning transistor T1 includes a first gate, a first electrode, and a second electrode. The first gate of the first scanning transistor T1 is electrically connected to the second gate line 12 corresponding to the sub-pixel P in the current row. The first electrode of the first scanning transistor T1 is electrically connected to the data line 13 corresponding to the sub-pixel P in the current column. The second electrode of the first scanning transistor T1 is electrically connected to the pixel electrode 111 of the sub-pixel P.

[0082] Each sub-pixel P in the first row further includes a second gate, which is electrically connected to the first gate line 11. That is, the first scanning transistors T1 in the first row of sub-pixels P are all dual-gate transistors, thus the first scanning transistors T1 in the first row of sub-pixels P can be turned on by the first gate line 11 and / or the second gate line 12.

[0083] Please see Figure 7 , Figure 7 for Figure 2 The diagram shows a second circuit structure for a sub-pixel in the display device.

[0084] In some embodiments of this application, the M rows of sub-pixels P are arranged in an M-row, N-column array. The display panel 10 also includes N data lines 13, where N>1. The N data lines 13 extend along the column direction and are spaced apart along the row direction, with each of the N data lines 13 corresponding to one of the N columns of sub-pixels P.

[0085] Each of the sub-pixels P includes a pixel electrode 111 and a second scanning transistor T2.

[0086] The second scanning transistor T2 includes a gate, a first electrode, and a second electrode. The gate of the second scanning transistor T2 is electrically connected to the second gate line 12 corresponding to the sub-pixel P in the same row. The first electrode of the second scanning transistor T2 is electrically connected to the data line 13 corresponding to the sub-pixel P in the same column. The second electrode of the second scanning transistor T2 is electrically connected to the pixel electrode 111 of the sub-pixel P.

[0087] Each sub-pixel P in the first row further includes a third scanning transistor T3. The second scanning transistor T2 includes a gate, a first electrode, and a second electrode. The gate of the third scanning transistor T3 is electrically connected to the first gate line 11. The first electrode of the third scanning transistor T3 is electrically connected to the data line 13 corresponding to the sub-pixel P in this column. The second electrode of the third scanning transistor T3 is electrically connected to the pixel electrode 111 of the sub-pixel P.

[0088] In this embodiment, the scanning transistor can be a thin-film transistor (TFT). Of course, these transistors can also be other switching devices, as long as they can change their switching state under the action of a control signal. The first electrode of the scanning transistor can be either the source or the drain, and the second electrode can be either the source or the drain.

[0089] Please refer to the following: Figure 2 and Figure 8 , Figure 8 for Figure 2 The timing diagram of the drive signals for the display device is shown.

[0090] like Figure 2 As shown, the driving circuit 20 includes a timing controller (TCON) 21, a power management integrated circuit (PMIC) 22, a level shifter (LS) 23, a gate driving circuit 25, and a data driving circuit 24.

[0091] The gate driving circuit 25 is electrically connected to each of the second gate lines 12. The data driving circuit 24 is electrically connected to each of the data lines 13.

[0092] The level conversion module 23 is electrically connected to the gate drive circuit 25 and the first gate line 11, respectively.

[0093] The timing controller 21 is electrically connected to the level conversion module 23 and the power management chip 22, respectively.

[0094] The timing controller 21 is used to receive the image data of the frame to be displayed, and output clock signals CK1.1in, CK1in and CK2in to the level conversion module 23 at the start of the display cycle of the frame to be displayed.

[0095] The timing controller 21 is also used to control the power management chip 22 to output the turn-on voltage VGH2 and the turn-off voltage VGL to the level conversion module 23.

[0096] The timing controller 21 is further configured to control the power management chip 22 to output the first turn-on voltage VGH11 to the level conversion module 23 when the frame to be displayed is a frame type where the first line is lit, so that the level conversion module 23 outputs a first gate signal G1.11 with the first turn-on voltage VGH11 to the first gate line 11 based on the clock signal CK1.1in, the first turn-on voltage VGH11 and the turn-off voltage VGL.

[0097] The timing controller 21 is further configured to control the power management chip 22 to output the second turn-on voltage VGH12 to the level conversion module 23 when the frame to be displayed is a frame type with the first line darkened, so that the level conversion module 23 outputs a first gate signal G1.12 with the second turn-on voltage VGH12 to the first gate line 11 based on the clock signal CK1.1in, the second turn-on voltage VGH12 and the turn-off voltage VGL.

[0098] Specifically, the level conversion module 23 is changed from a traditional 2-in-10-out channel design to a 3-in-11-out channel design. More specifically, the level conversion module 23 is also used to output clock signals CK1 to CK10 to the gate drive circuit 25 based on the turn-off voltage VGL, the clock signal CK1in, and the clock signal CK2in, so that the gate drive circuit 25 outputs corresponding second gate signals to the M second gate lines 12 based on the clock signals CK1 to CK10.

[0099] Please see Figure 9 , Figure 9 A flowchart illustrating the display method provided in an embodiment of this application. Based on the same inventive concept, an embodiment of this application also provides a display method applied to the display device 1 described in any of the preceding embodiments.

[0100] like Figure 9 As shown, the display method includes: Step S1: Receive the image data of the frame to be displayed through the driving circuit 20; Step S2: When the display cycle of the frame to be displayed begins, the driving circuit 20 outputs a first gate signal corresponding to the image data to the first gate line 11 in the display panel 10 to turn on the first gate line 11. Step S3: The driving circuit 20 outputs corresponding second gate signals to the M second gate lines 12 in the display panel 10 to turn on the M second gate lines 12 row by row.

[0101] The signal parameters include at least one of the following: turn-on voltage, rise time, and fall time.

[0102] In some embodiments of this application, the step of turning on the first gate line 11 by outputting a first gate signal corresponding to the image data to the first gate line 11 in the display panel 10 at the start of the display cycle of the frame to be displayed via the driving circuit 20 includes: The driving circuit 20 determines the image type of the frame to be displayed based on the image data of the frame to be displayed. If the frame to be displayed is a type of image where the first line is lit, the driving circuit 20 outputs a first gate signal with a first parameter to the first gate line 11 at the beginning of the display cycle of the frame to be displayed. If the frame to be displayed is a type of image where the first line is dark, the driving circuit 20 outputs a first gate signal with a second parameter to the first gate line 11 at the beginning of the display cycle of the frame to be displayed.

[0103] The signal parameters of the first parameter, the second parameter, and the second gate signal are all different.

[0104] In some embodiments of this application, the signal parameters include a turn-on voltage.

[0105] If the frame to be displayed is a type of image where the first line is lit, the driving circuit 20 outputs a first gate signal with a first parameter to the first gate line 11 at the start of the display cycle of the frame to be displayed, including: If the frame to be displayed is a type of image where the first line is lit, the driving circuit 20 outputs a first gate signal with a first turn-on voltage to the first gate line 11 at the start of the display cycle of the frame to be displayed.

[0106] If the frame to be displayed is a type of image where the first line is darkened, the driving circuit 20 outputs a first gate signal with a second parameter to the first gate line 11 at the start of the display cycle of the frame to be displayed, including: If the frame to be displayed is a type of image where the first line is dark, the driving circuit 20 outputs a first gate signal with a second turn-on voltage to the first gate line 11 at the start of the display cycle of the frame to be displayed.

[0107] Wherein, the first turn-on voltage is less than the second turn-on voltage.

[0108] In some embodiments of this application, the signal parameters include the fall time.

[0109] If the frame to be displayed is a type of image where the first line is lit, the driving circuit 20 outputs a first gate signal with a first parameter to the first gate line 11 at the start of the display cycle of the frame to be displayed, including: If the frame to be displayed is a type of image where the first line is lit, the driving circuit 20 outputs a first gate signal with a fall time of the first fall time to the first gate line 11 at the beginning of the display cycle of the frame to be displayed.

[0110] If the frame to be displayed is a type of image where the first line is darkened, the driving circuit 20 outputs a first gate signal with a second parameter to the first gate line 11 at the start of the display cycle of the frame to be displayed, including: If the frame to be displayed is a type of image where the first line is dark, the driving circuit 20 outputs a first gate signal with a fall time of the second fall time to the first gate line 11 at the beginning of the display cycle of the frame to be displayed; wherein, the first fall time is greater than the second fall time.

[0111] It should be noted that the display method described corresponds to the scheme of display device 1 mentioned above. For a more detailed description, please refer to the contents of the various embodiments of display device 1 mentioned above, which will not be repeated here.

[0112] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A display device, characterized in that, The display device includes: A display panel includes M rows of sub-pixels, a first gate line, and M second gate lines, where M > 1; wherein the first gate line and the M second gate lines extend along the row direction and are spaced apart along the column direction; the first gate line is electrically connected to the first row of sub-pixels in the M rows of sub-pixels, and the M second gate lines are electrically connected to each of the M rows of sub-pixels in a one-to-one correspondence; and The driving circuit is electrically connected to both the first gate line and the M second gate lines. The driving circuit is used to receive image data of the frame to be displayed, and at the start of the display cycle of the frame to be displayed, outputs a first gate signal corresponding to the image data to the first gate line to turn on the first gate line, and outputs a corresponding second gate signal to the M second gate lines to turn on the M second gate lines line by line; wherein the signal parameters include at least one of turn-on voltage, rise time, and fall time.

2. The display device as claimed in claim 1, characterized in that, The driving circuit is used to determine the image type of the frame to be displayed based on the image data of the frame to be displayed. If the frame to be displayed is a type of image where the first line is lit, the driving circuit is used to output a first gate signal with a first parameter to the first gate line at the beginning of the display cycle of the frame to be displayed; wherein the first parameter is different from the signal parameter of the second gate signal.

3. The display device as claimed in claim 2, characterized in that, If the frame to be displayed is a type of image where the first line is dark, the driving circuit is used to output a first gate signal with a second parameter to the first gate line at the beginning of the display cycle of the frame to be displayed; wherein the first parameter, the second parameter, and the signal parameters of the second gate signal are all different.

4. The display device as claimed in claim 3, characterized in that, The first row of bright images includes at least one of heavy images and solid grayscale images with a target brightness value higher than a first brightness threshold; the first row of dark images includes solid grayscale images with a target brightness value lower than a second brightness threshold; wherein, the first brightness threshold is higher than the second brightness threshold.

5. The display device as claimed in claim 3, characterized in that, The signal parameters include the turn-on voltage; If the frame to be displayed is a type of image where the first line is lit, the driving circuit is used to output a first gate signal with a first turn-on voltage to the first gate line at the start of the display cycle of the frame to be displayed; if the frame to be displayed is a type of image where the first line is dark, the driving circuit is used to output a first gate signal with a second turn-on voltage to the first gate line at the start of the display cycle of the frame to be displayed; wherein, the first turn-on voltage is less than the second turn-on voltage.

6. The display device as claimed in claim 3, characterized in that, The signal parameters include the fall time; If the frame to be displayed is a type of image where the first line is lit, the driving circuit is used to output a first gate signal with a fall time of a first fall time to the first gate line at the beginning of the display cycle of the frame to be displayed; if the frame to be displayed is a type of image where the first line is dark, the driving circuit is used to output a first gate signal with a fall time of a second fall time to the first gate line at the beginning of the display cycle of the frame to be displayed; wherein, the first fall time is greater than the second fall time.

7. The display device as claimed in claim 1, characterized in that, The M rows of sub-pixels are arranged in an array of M rows and N columns; the display panel also includes N data lines, where N>1; the N data lines extend along the column direction and are arranged at intervals along the row direction, and the N data lines correspond one-to-one with the N columns of sub-pixels; Each of the sub-pixels includes: Pixel electrodes; and The first scanning transistor includes a first gate, a first electrode, and a second electrode. The first gate of the first scanning transistor is electrically connected to the second gate line corresponding to the sub-pixel in the same row. The first electrode of the first scanning transistor is electrically connected to the data line corresponding to the sub-pixel in the same column. The second electrode of the first scanning transistor is electrically connected to the pixel electrode of the sub-pixel. Each of the first scanning transistors in the sub-pixels of the first row further includes a second gate, which is electrically connected to the first gate.

8. The display device as claimed in claim 1, characterized in that, The M rows of sub-pixels are arranged in an array of M rows and N columns; the display panel also includes N data lines, where N>1; the N data lines extend along the column direction and are arranged at intervals along the row direction, and the N data lines correspond one-to-one with the N columns of sub-pixels; Each of the sub-pixels includes: Pixel electrodes; and The second scanning transistor includes a gate, a first electrode, and a second electrode. The gate of the second scanning transistor is electrically connected to the second gate line corresponding to the sub-pixel in the current row. The first electrode of the second scanning transistor is electrically connected to the data line corresponding to the sub-pixel in the current column. The second electrode of the second scanning transistor is electrically connected to the pixel electrode of the sub-pixel. Each sub-pixel in the first row further includes a third scanning transistor, wherein the third scanning transistor includes a gate, a first electrode, and a second electrode. The gate of the third scanning transistor is electrically connected to the first gate line, the first electrode of the third scanning transistor is electrically connected to the data line corresponding to the sub-pixel in this column, and the second electrode of the second scanning transistor is electrically connected to the pixel electrode of the sub-pixel.

9. The display device as claimed in claim 5, characterized in that, The driving circuit includes: The level conversion module is electrically connected to the first gate line; Power management chip; and The timing controller is electrically connected to the level conversion module and the power management chip, respectively. The timing controller receives image data of the frame to be displayed, and outputs a clock signal to the level conversion module at the start of the display cycle of the frame to be displayed. When the frame to be displayed is a type of image where the first line is lit, the controller controls the power management chip to output the first turn-on voltage to the level conversion module, so that the level conversion module outputs a first gate signal with the first turn-on voltage to the first gate line based on the clock signal and the first turn-on voltage. When the frame to be displayed is a type of image where the first line is dark, the controller controls the power management chip to output the second turn-on voltage to the level conversion module, so that the level conversion module outputs a first gate signal with the second turn-on voltage to the first gate line based on the clock signal and the second turn-on voltage.

10. A display method, said display method being applied to a display device as described in any one of claims 1 to 9, characterized in that, The display method includes: The driver circuit receives the image data of the frame to be displayed. The first gate line is turned on by the driving circuit outputting a first gate signal corresponding to the image data to the first gate line in the display panel at the start of the display cycle of the frame to be displayed; and The M second gate lines are turned on row by row by outputting corresponding second gate signals to the M second gate lines in the display panel through the driving circuit; The signal parameters include at least one of the following: turn-on voltage, rise time, and fall time.

Images