Row decoder circuit

Abstract

The invention provides a row decoder circuit suitable for a memory device. The row decoder circuit includes a pre-decoder, a plurality of decoders, and a mapping control circuit. The pre-decoder is configured to receive row address information and decode the row address information to provide a row selection signal set. The plurality of decoders sequentially correspond to a plurality of row address ranges. The mapping control circuit is configured to obtain a selected row address range according to the row selection signal group, and to cause the decoders having the same corresponding row address range as the selected row address range to output word line signals. The mapping control circuit reorders the row address range corresponding to the decoder according to the verification data.

Description

TECHNICAL FIELD

[0001] The present invention relates to a decoder circuit, and more particularly, to a row decoder circuit. BACKGROUND

[0002] With the development of memory process technology, the memory density increases, the die area increases, and the failure rate of each die also increases. It is almost impossible for all memory cells or memory blocks inside a memory product to be 100% non-defective. Therefore, the prior art mainly uses row / col redundancy techniques and error correction code (ECC) techniques to repair these defective memory cells. However, the repair capability of the above techniques is limited, and some memory devices (chips) with more defects cannot be completely repaired. Since the location of the defects is random, these partially defective memory devices cannot be shipped as normal products, which reduces the yield of the products. SUMMARY

[0003] The present invention provides a row decoder circuit that can make partially defective memory devices usable.

[0004] The row decoder circuit of the present invention is suitable for a memory device, which includes a predecoder, a plurality of decoders, and a mapping control circuit. The predecoder is configured to receive row address information and decode the row address information to provide a set of row selection signals. The plurality of decoders correspond to a plurality of row address ranges in sequence. The mapping control circuit is coupled to the predecoder and the decoders and is configured to obtain a selected row address range according to the set of row selection signals and cause the decoders whose corresponding row address ranges are the same as the selected row address range to output word line signals. The mapping control circuit reorders the row address ranges corresponding to the decoders according to verification data.

[0005] Based on the above, by reordering the row address ranges corresponding to the decoders, the row decoder circuit of the present invention can skip defective memory blocks during mapping and allow the memory device to be used normally. Thus, the partially defective memory device still has usability, and the yield of the product and the convenience of use can be increased.

[0006] In order to make the above features and advantages of the present invention more obvious and easy to understand, the following embodiments are specifically described below, and the detailed description is made below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block schematic diagram of a row decoder circuit according to an embodiment;

[0008] Figure 2 is an operation schematic diagram of a row decoder circuit according to an embodiment;

[0009] Figures 3A to 3C is a circuit schematic diagram of a mapping control circuit according to an embodiment;

[0010] Figures 4A to 4C is an operation schematic diagram of a mapping control circuit according to an embodiment;

[0011] Figures 5A to 5C is a block schematic diagram of a mapping control circuit according to another embodiment;

[0012] Figures 6A to 6C is an operation schematic diagram of a mapping control circuit according to another embodiment. DETAILED DESCRIPTION

[0013] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0014] Referring to Figure 1 , the row decoder circuit 100 of the present embodiment is suitable for a memory device conforming to a standard such as a hybrid memory cube (HMC), a high bandwidth memory (HBM), a double data rate (DDR), or a low power double data rate (LPDDR), for example. The row decoder circuit 100 includes a predecoder 110, decoders 120_0 to 120_11, and a mapping control circuit 130. The predecoder 110 can receive row address information RA of a memory cell to be accessed. The row address information RA can be composed of 13 bits, for example. The predecoder 110 can decode the row address information RA to provide a row selection signal group SELG. A first portion P1 of the row selection signal group SELG corresponds to a high-order portion of the row address, including a first row selection signal RSGSEL0[3:0] and a second row selection signal RSGSEL1[2:0]. A second portion P2 of the row selection signal group SELG corresponds to a low-order portion of the row address, including row selection signals RMWSEL0[7:0], RMWSEL1[3:0], RMWSEL2[2:0], and RFXSEL[7:0]. The predecoder 110 transmits the first portion P1 of the row selection signal group SELG to the mapping control circuit 130 and transmits the second portion P2 of the row selection signal group SELG to each of the decoders 120_0 to 120_11.

[0015] The decoders 120_0-120_11 correspond to the row address ranges RSG0-RSG11 in sequence. The row address ranges RSG0-RSG11 represent the initial default row address ranges of the 12 memory blocks enabled by the decoders 120_0-120_11, respectively, in the memory device. For example, assuming that the total range of row addresses available for the above-mentioned 12 memory blocks is 0-8191, the row address ranges RSG0-RSG11 are shown in Table 1 below.

[0016] RSG0 0～687 RSG1 688～1375 RSG2 1376～2047 RSG3 2048～2735 RSG4 2736～3423 RSG5 3424～4095 RSG6 4096～4783 RSG7 4784～5471 RSG8 5472～6143 RSG9 6144～6831 RSG10 6832～7519 RSG11 7250～8191

[0017] Table 1

[0018] In the case that none of the above-mentioned 12 memory blocks is defective (all available), the decoders 120_0-120_11 can output word line signals SWL0-SWLI l to the above-mentioned 12 memory blocks, respectively, to access the memory cells whose row addresses are within the row address ranges RSG0-RSG11.

[0019] The mapping control circuit 130 is coupled to the pre-decoder 110 and the decoders 120_0-120_11. The mapping control circuit 130 can obtain a selected row address range according to the row selection signal group SELG, and cause the decoders whose corresponding row address ranges are the same as the selected row address range to output the word line signals at an enable level (e.g., a high logic level).

[0020] Specifically, the mapping control circuit 130 can analyze and decode the signals of the first part P1 of the row selection signal group SELG to obtain a selected row address range in which the memory cells to be accessed are located. At this time, the decoders whose corresponding row address ranges are the same as the selected row address range can output the corresponding word line signals according to the second part P2 of the row selection signal group SELG. Further, when the selected row address range is equal to the row address range RSG0, the mapping control circuit 130 causes the decoder 120_0 to output the word line signal SWL0 at an enable level according to the second part P2 of the row selection signal group SELG. When the selected row address range is equal to the row address range RSG1, the mapping control circuit 130 causes the decoder 120_1 to output the word line signal SWLI at an enable level according to the second part P2 of the row selection signal group SELG, and so on.

[0021] In the present embodiment, the mapping control circuit 130 can also receive verification data DV. The verification data DV is, for example, data obtained in a chip probing (CP) stage. The mapping control circuit 130 can learn the locations of defective memory cells or defective memory blocks according to the verification data DV.

[0022] In addition, the mapping control circuit 130 can generate verification signals SDV0-SDV11 according to the plurality of bit values of the verification data DV. When a verification signal is at a high logic level (logic value 1), it indicates that the corresponding memory block is damaged due to the inability to completely repair defective memory cells. When a verification signal is at a low logic level (logic value 0), it indicates that the corresponding memory block can be completely repaired without defective memory cells. Further, when the verification signal SDV0 is at a high logic level (logic value 1), it indicates that the memory block opened by the decoder 120_0 is damaged, when the verification signal SDV1 is at a high logic level (logic value 1), it indicates that the memory block opened by the decoder 120_1 is damaged, and so on.

[0023] When there is a damaged defective memory block among the 12 memory blocks opened by the decoders 120_0-120_11 respectively, the mapping control circuit 130 can reorder the row address ranges corresponding to the decoders 120_0-120_11 according to the verification data DV. For example, as shown in FIG. 1B, when the memory block opened by the decoder 120_1 is a damaged defective memory block, the verification signal SDV1 is at a high logic level (logic value 1). Therefore, the mapping control circuit 130 can disable the decoder 120_1 as a defective memory block decoder according to the verification signal SDV1 at a high logic level. Figure 2

[0024] At this time, in order to allow the memory device to be used normally, the mapping control circuit 130 can also shift the row address ranges corresponding to the decoders 120_2-120_11 behind the decoder 120_1 as a defective memory block decoder from the row address ranges RSG2-RSG11 to the front of the row address ranges RSG1-RSG10, so that the decoder 120_2 replaces the decoder 120_1 to correspond to the row address range RSG1, and the memory block opened by the decoder 120_1 can no longer be mapped.

[0025] Similarly, each of the decoders 120_3-120_11 also replaces the previous decoder to correspond to the row address range originally corresponding to the previous decoder.

[0026] In this way, the row decoder circuit 100 of the present embodiment can skip the damaged defective memory block when mapping, so that the partially damaged memory device still has usability.

[0027] ​It is to be noted that although 12 decoders 120_0-120_11 capable of opening 12 memory blocks are used in the present embodiment for illustration, the present application is not limited thereto. Those skilled in the art can analogize the number of memory blocks and decoders to be less or more according to the present application and actual needs.

[0028] The following embodiment is used to illustrate the implementation of the mapping control circuit. The mapping control circuit 300 of the present embodiment is applicable to the case where there is a defective memory cell with a damaged memory block, and the row address range corresponding to the decoders 400_0-400_11 is reordered. The mapping control circuit 300 comprises a latch circuit 310, a first logic circuit 320, a second logic circuit 330, a multiplexing circuit 340, and a third logic circuit 350. For the sake of clarity, the internal structures of the latch circuit 310, the first logic circuit 320, the second logic circuit 330, the multiplexing circuit 340, and the third logic circuit 350 in the mapping control circuit 300 are represented by Figure 3A Figure 3B Figure 3C respectively.

[0029] Please refer to Figure 3A Figure 3B Figure 3C The latch circuit 310 can store the verification data DV received. When the system is powered on, the latch circuit 310 can obtain the verification data DV, for example, from another one-time programmable (OTP) memory. The latch circuit 310 comprises latches L0-L11. The latches L0-L11 can sequentially store a plurality of bit values constituting the verification data DV, and output them as verification signals SDV0-SDV11 respectively.

[0030] The first logic circuit 320 is coupled to the latch circuit 310. The first logic circuit 320 can receive the verification signals SDV0-SDV10 and a low logic level signal VSS, and perform a multi-stage operation using the verification signals SDV0-SDV10 and the low logic level signal VSS to generate control signals ST0-ST10.

[0031] In detail, in the present embodiment, the first logic circuit 320 comprises a first logic gate G0, a second logic gate G1, a third logic gate G2, a fourth logic gate G3, a fifth logic gate G4, a sixth logic gate G5, a seventh logic gate G6, an eighth logic gate G7, a ninth logic gate G8, a tenth logic gate G9, and an eleventh logic gate G10. Figure 3B ​​​​In detail, the first logic circuit 320 includes OR gates 322_0-322_10. The OR gates 322_0-322_10 are connected in series. The first input terminals of the OR gates 322_0-322_10 receive verification signals SDV0-SDV10, respectively. The output terminals of the OR gates 322_0-322_10 output control signals ST0-ST10, respectively. The second input terminal of the OR gate (OR gate 322_0) of the first stage receives a low logic level signal VSS. The second input terminals of the OR gates (OR gate 322_1-OR gate 322_10) other than the first stage receive control signals outputted by the output terminals of the OR gate of the previous stage.

[0032] The second logic circuit 330 receives a first part P1 of the row selection signal group SELG, and performs AND operation on a first row selection signal RSGSEL0[3:0] in the first part P1 and a second row selection signal RSGSEL1[2:0] in the first part P1 to generate operation signals RS0-RS11.

[0033] The second logic circuit 330 includes AND gates 332_0-332_11. The first input terminals of the AND gates 332_0-332_11 receive corresponding first row selection signals in the first row selection signal RSGSEL0[3:0]. The second input terminals of the AND gates 332_0-332_11 receive corresponding second row selection signals in the second row selection signal RSGSEL1[2:0]. The output terminals of the AND gates 332_0-332_11 output the operation signals RS0-RS11, respectively.

[0034] In detail, the multiplexing circuit 340 includes multiplexers 342_0-342_10. The first input terminals and the second input terminals of each of the multiplexers 342_0-342_10 receive corresponding two operation signals in the operation signals RS0-RS11. For example, the first input terminal of the multiplexers 342_0 receives the operation signal RS0, and the second input terminal of the multiplexers 342_0 receives the operation signal RS1. The first input terminal of the multiplexers 342_1 receives the operation signal RS1, and the second input terminal of the multiplexers 342_1 receives the operation signal RS2, and so on. Figure 3C

[0035] In detail, the multiplexing circuit 340 includes multiplexers 342_0-342_10. The first input terminals and the second input terminals of each of the multiplexers 342_0-342_10 receive corresponding two operation signals in the operation signals RS0-RS11. For example, the first input terminal of the multiplexers 342_0 receives the operation signal RS0, and the second input terminal of the multiplexers 342_0 receives the operation signal RS1. The first input terminal of the multiplexers 342_1 receives the operation signal RS1, and the second input terminal of the multiplexers 342_1 receives the operation signal RS2, and so on.

[0036] ​The control terminals of the multiplexers 342_0-342_10 receive control signals ST0-ST10, respectively, and the output terminals of the multiplexers 342_0-342_10 output decoded signals SCD0-SCD10, respectively. Each of the multiplexers 342_0-342_10 selects one of the signal received by its first input terminal (upper input terminal) and the signal received by its second input terminal (lower input terminal) as the corresponding decoded signal to output at its output terminal according to the received control signal. Taking the multiplexer 342_1 as an example, when the control signal ST1 of high logic level is received, the multiplexer 342_1 selects the operation signal RS1 received by its first input terminal (upper input terminal) as the decoded signal SCD1 to output. When the control signal ST1 of low logic level is received, the multiplexer 342_1 selects the operation signal RS2 received by its second input terminal (lower input terminal) as the decoded signal SCD1 to output.

[0037] The third logic circuit 350 is coupled to the latch circuit 310, the second logic circuit 330, and the multiplexing circuit 340. The third logic circuit 350 can receive the verification signals SDV0-SDV11, the operation signal RS0 corresponding to the lowest address among the operation signals RS0- RS11, and the decoded signals SCD0-SCD10, and perform AND operations between the verification signals SDV0-SDV11 after being inverted and the operation signal RS0 and the decoded signals SCD0-SCD10, respectively, to output the generated enable signals SE0-SE11 to the decoders 400_0-400_11, respectively.

[0038] In detail, the third logic circuit 350 includes inverters 352_0-352_11 and AND gates 354_0-354_11. The input terminals of the inverters 352_0-352_11 receive SDV0-SDV11, respectively.

[0039] The first input terminal of the AND gate 354_0 receives the operation signal RS0. The first input terminals of the AND gates 354_1-354_11 receive the decoded signals SCD0-SCD10, respectively. The second input terminals of the AND gates 354_0-354_11 are coupled to the output terminals of the inverters 352_0-352_11, respectively. The output terminals of the AND gates 354_0-354_11 output the enable signals SE0-SE11, respectively.

[0040] In operation, for example, as Figure 4A , Figure 4B , Figure 4CAs shown, in the case where there is a defective bad memory cell in the memory block enabled by the decoder 400_1, the inverter 352_1 in the third logic circuit 350 receives the verification signal SDV1 of high logic level (logic value 1) from the latch L1 in the latch circuit 310. Thus, the AND gate 354_1 can only output the enable signal SE1 of low logic level (logic value 0) to the decoder 400_1, thereby disabling the decoder 400_1 as a bad memory block decoder.

[0041] At this time, the OR gate 322_1 in the first logic circuit 320 also receives the verification signal SDV1 of high logic level. Since the OR gates 322_0-322_10 are connected in series, the control signals ST1-ST10 outputted by the OR gates 322_1-322_10 are all adjusted to high logic level. In this case, the multiplexers 342_1-342_10 in the multiplexing circuit 340 change to select the operation signals RS1-RS10 received by the first input terminals (upper input terminals) thereof as the decoding signals SCD1-SCD10 for output.

[0042] In this way, the row address ranges corresponding to the decoders 400_2-400_11 following the decoder 400_1 as a bad memory block decoder are shifted forward from the row address ranges RSG2-RSG11 to the row address ranges RSG1-RSG10. Thus, the decoder 400_2 replaces the decoder 400_1 to correspond to the row address range RSG1, and the memory block enabled by the decoder 400_1 can no longer be mapped.

[0043] Another embodiment of the mapping control circuit will be described below. The mapping control circuit 500 of this embodiment is adapted to the case where one or two memory blocks are defective and the row address ranges corresponding to the decoders 600_0-600_11 are reordered. The mapping control circuit 500 includes a latch circuit 510, a first logic circuit 520, a second logic circuit 530, a multiplexing circuit 540, and a third logic circuit 550. For the sake of clear illustration, the internal structures of the latch circuit 510, the first logic circuit 520, the second logic circuit 530, the multiplexing circuit 540, and the third logic circuit 550 in the mapping control circuit 500 are represented by Figure 5A 、 Figure 5B 、 Figure 5C

[0044] Please refer to Figure 5A 、 Figure 5B 、 Figure 5C ​The latch circuit 510 can store the received verification data DV. The latches L0-L11 included in the latch circuit 510 can sequentially store the plurality of bit values constituting the verification data DV and output them as verification signals SDV0-SDV11, respectively.

[0045] The first logic circuit 520 is coupled to the latch circuit 510. The first logic circuit 520 can receive the verification signals SDV0-SDV10 and the low logic level signal VSS and perform a multi-stage operation using the verification signals SDV0-SDV10 and the low logic level signal VSS to generate control signals ST0-ST10. Unlike the foregoing embodiment, in the present embodiment, each of the control signals ST0-ST10 is composed of two bit signals. For example, the control signal ST0 is composed of a bit signal ST0<0> and a bit signal ST0<1>, the control signal ST1 is composed of a bit signal ST1<0> and a bit signal ST1<1>, and so on.

[0046] In detail, in the first logic circuit 520, the or gates 522_0-522_10 are connected in series. The first input terminals of the or gates 522_0-522_10 receive the verification signals SDV0-SDV10, respectively. The output terminals of the or gates 522_0-522_10 output bit signals ST0<0>-ST10<0>, respectively. The second input terminal of the or gate (or gate 522_0) of the first stage receives the low logic level signal VSS. The second input terminals of the or gates (or gates 522_1-522_10) other than the first stage receive bit signals output from the output terminals of the or gates of the previous stage. Figure 5B

[0047] The first input terminals of the and gates 524_0-524_10 receive the verification signals SDV1-SDV11, respectively. The second input terminals of the and gates 524_0-524_10 receive the bit signals ST0<0>-ST10<0>, respectively.

[0048] The or gates 526_0-526_10 are connected in series. The first input terminals of the or gates 526_0-526_10 are coupled to the output terminals of the and gates 524_0-524_10, respectively. The output terminals of the or gates 526_0-526_9 output bit signals ST1<1>-ST10<1>, respectively. The second input terminal of the or gate (or gate 526_0) of the first stage receives the low logic level signal VSS. The second input terminals of the or gates (or gates 526_1-526_10) other than the first stage receive bit signals output from the output terminals of the or gates of the previous stage.

[0049] ​The second logic circuit 530 can receive the first part P1 of the row selection signal group SELG, and perform and operation of a first row selection signal RSGSEL0[3:0] in the first part P1 with a second row selection signal RSGSEL1[2:0] in the first part P1 through the AND gates 532_0~532_11 to generate operation signals RS0~RS11.

[0050] In Figure 5C The multiplexing circuit 540 is coupled to the first logic circuit 520 and the second logic circuit 530. The multiplexing circuit 540 receives the control signals ST0~ST10 and the operation signals RS0~RS11, and selects a plurality of the operation signals RS0~RS11 as the decoding signals SCD0~SCD10 according to the control signals ST0~ST10.

[0051] In detail, the multiplexing circuit 540 includes multiplexers 542_0~542_10. Different from the foregoing embodiment, a first input of the multiplexer 542_0 receives a low logic level signal VSS, and a second input and a third input of the multiplexer 542_0 receive the operation signals RS0 and RS1. The first input, the second input and the third input of each of the multiplexers 542_1~542_10 receive three corresponding operation signals among the operation signals RS0~RS11. For example, the first input of the multiplexer 542_1 receives the operation signal RS0, the second input of the multiplexer 542_1 receives the operation signal RS1, and the third input of the multiplexer 542_1 receives the operation signal RS2. The first input of the multiplexer 542_2 receives the operation signal RS1, the second input of the multiplexer 542_2 receives the operation signal RS2, and the third input of the multiplexer 542_2 receives the operation signal RS3, and so on.

[0052] The control terminals of the multiplexers 542_0-542_10 receive control signals ST0-ST10, respectively, and the output terminals of the multiplexers 542_0-542_10 output decoded signals SCD0-SCD10, respectively. Each of the multiplexers 542_0-542_10 selects one of the signal received by its first input terminal (upper input terminal), the signal received by its second input terminal (middle input terminal), and the signal received by its third input terminal (lower input terminal) as the corresponding decoded signal and outputs it at its output terminal according to the received control signal. Taking the multiplexer 542_1 as an example, when receiving a control signal ST1 (logic value 11) composed of a high logic level bit signal ST1<0> and a high logic level bit signal ST1<1>, the multiplexer 542_1 selects the operation signal RS0 received by its first input terminal (upper input terminal) as the decoded signal SCD1 and outputs it. When receiving a control signal ST1 (logic value 01) composed of a high logic level bit signal ST1<0> and a low logic level bit signal ST1<1>, the multiplexer 542_1 selects the operation signal RS1 received by its second input terminal (middle input terminal) as the decoded signal SCD1 and outputs it. When receiving a control signal ST1 (logic value 00) composed of a low logic level bit signal ST1<0> and a low logic level bit signal ST1<1>, the multiplexer 542_1 selects the operation signal RS2 received by its third input terminal (lower input terminal) as the decoded signal SCD1 and outputs it.

[0053] The third logic circuit 550 is coupled to the latch circuit 510, the second logic circuit 530, and the multiplexing circuit 540. The third logic circuit 550 can receive the verification signals SDV0-SDV11, the operation signal RS0 corresponding to the lowest address among the operation signals RS0-RS11, and the decoded signals SCD0-SCD10, and perform and operation with the operation signal RS0 and the decoded signals SCD0-SCD10 through inverters 552_0-552_11 and AND gates 554_0-554_11, respectively, after inverting the verification signals SDV0-SDV11, to output the generated enable signals SE0-SE11 to the decoders 600_0-600_11, respectively.

[0054] In operation, for example, as Figure 6A , Figure 6B , Figure 6CAs shown, in the case where there is a defect in both memory blocks opened by decoders 600_1 and 600_5, inverters 552_1 and 552_5 in third logic circuit 550 receive the verification signals SDV1 and SDV5 of high logic level (logic value 1) from latches L1 and L5 in latch circuit 510, respectively. Thus, AND gates 554_1 and 554_5 can only output the enable signals SE1 and SE5 of low logic level (logic value 0) to decoders 600_1 and 600_5, respectively, thereby disabling decoders 600_1 and 600_5 as defective memory block decoders.

[0055] At this time, OR gate 522_1 in first logic circuit 520 also receives the verification signal SDV1 of high logic level. Since OR gates 522_0-522_10 are connected in series, the bit signals ST1<0>-ST10<0> outputted by OR gates 522_1-522_10 are all adjusted to high logic level. In addition, the output terminals of AND gates 524_1-524_10 receiving the bit signals ST1<0>-ST10<0> are adjusted to the same logic levels as the verification signals SDV2-SDV11, respectively. That is, the output terminal of AND gate 524_4 is adjusted to the same high logic level as SDV5.

[0056] Since OR gates 526_0-526_10 are also connected in series, the bit signals ST5<1>-ST10<1> outputted by OR gates 526_4-526_9 are all adjusted to high logic level. In this case, the logic values of control signals ST1-ST3 are "01", and the logic values of control signals ST5-ST10 are "11", so multiplexers 542_1-542_3 in multiplexing circuit 540 change to select the operation signals RS1-RS3 received by their second input terminals (middle input terminals) as the decoding signals SCD1-SCD3 for output, and multiplexers 542_5-542_10 change to select the operation signals RS4-RS9 received by their first input terminals (upper input terminals) as the decoding signals SCD5-SCD10 for output.

[0057] In this way, the row address ranges corresponding to decoders 600_2-600_4 following decoder 600_1 as the defective memory block decoder are shifted forward from row address ranges RSG2-RSG4 to row address ranges RSG1-RSG3, and the row address ranges corresponding to decoders 600_6-600_11 following decoder 600_5 as the defective memory block decoder are shifted forward from row address ranges RSG6-RSG11 to row address ranges RSG4-RSG9. Thus, decoder 600_2 replaces decoder 600_1 to correspond to row address range RSG1, and decoder 600_7 replaces decoder 600_5 to correspond to row address range RSG5, so that the two memory blocks opened by decoders 600_1 and 600_5 can no longer be mapped.

[0058] It should be noted that, for the convenience of understanding, the above embodiments take the case of one or two memory blocks having defective storage units as examples for illustration, but the present application is not limited thereto. Those skilled in the art can adjust the internal structure of the mapping control circuit according to the teaching of the present application to make it applicable to the case of more memory blocks having defective storage units.

[0059] In summary, the row decoder circuit of the present application does not repair the memory blocks having defective storage units in the traditional way, but reorders the row address ranges corresponding to the decoders. In this way, the defective memory blocks can be skipped when mapping, so that the memory device can be used normally, the partially damaged memory device still has usability, and the yield of the product and the convenience of use can be increased.

[0060] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A row decoder circuit, suitable for a memory device, characterized in that it comprises: A pre-decoder is configured to receive row address information and decode the row address information to provide a row selection signal group; Multiple decoders, sequentially corresponding to multiple row address ranges; as well as A mapping control circuit, coupled to the pre-decoder and the plurality of decoders, is configured to obtain a selected row address range based on the row selection signal group, and to output word line signals for decoders whose corresponding row address range is the same as the selected row address range. The mapping control circuit reorders the multiple row address ranges corresponding to the multiple decoders based on the verification data.

2. The row decoder circuit according to claim 1, wherein the mapping control circuit obtains the selected row address range according to the first part of the row selection signal group, and the decoder whose corresponding row address range is the same as the selected row address range outputs the corresponding word line signal according to the second part of the row selection signal group.

3. The row decoder circuit according to claim 1, wherein the mapping control circuit generates a plurality of verification signals based on the verification data, and disables at least one bad memory block decoder among the plurality of decoders based on the plurality of verification signals.

4. The row decoder circuit according to claim 3, wherein the mapping control circuit shifts forward the plurality of row address ranges corresponding to the plurality of decoders following the at least one bad memory block decoder according to the plurality of verification signals, thereby replacing the at least one bad memory block decoder.

5. The row decoder circuit according to claim 1, wherein the mapping control circuit comprises: A latching circuit is configured to store the verification data, wherein the latching circuit includes a plurality of latches, and the plurality of latches output the plurality of bit values ​​constituting the verification data as a plurality of verification signals.

6. The row decoder circuit according to claim 5, wherein the mapping control circuit further comprises: A first logic circuit, coupled to the latch circuit, is configured to receive the plurality of verification signals and low logic level signals, and to perform multi-level operations using the plurality of verification signals and the low logic level signals to generate a plurality of control signals.

7. The row decoder circuit according to claim 6, wherein the first logic circuit comprises: Multiple OR gates are connected in serial order. The first input of each OR gate receives the corresponding verification signal, and the output of each OR gate outputs the corresponding control signal. The second input of the first-stage OR gate receives the low logic level signal, and the second input of the OR gates other than the first-stage OR gate receives the control signal output by the output of the previous-stage OR gate.

8. The row decoder circuit according to claim 6, wherein each of the plurality of control signals includes a first bit signal and a second bit signal, and the first logic circuit includes: Multiple first OR gates are connected in serial order. The first input terminal of each of the multiple first OR gates receives the corresponding verification signal, and the output terminal of each of the multiple first OR gates outputs the corresponding first bit signal. The second input terminal of the first OR gate of the first stage receives the low logic level signal. The second input terminal of the first OR gate other than the first stage receives the first bit signal output by the output terminal of the first OR gate of the previous stage. Multiple AND gates, each of which has a first input terminal receiving a corresponding verification signal and a second input terminal receiving a corresponding first bit signal; as well as Multiple second OR gates are connected in series. The first input of each of the multiple second OR gates is coupled to the output of the corresponding AND gate. The output of each of the multiple second OR gates outputs the corresponding second bit signal. The second input of the second OR gate of the first stage receives the low logic level signal. The second input of the second OR gate other than the first stage receives the second bit signal output by the output of the second OR gate of the previous stage.

9. The row decoder circuit according to claim 6, wherein the mapping control circuit further comprises: A second logic circuit is configured to receive a first portion of the row selection signal group and to perform operations on a plurality of first row selection signals and a plurality of second row selection signals in the first portion to generate a plurality of operation signals.

10. The row decoder circuit according to claim 9, wherein the second logic circuit comprises: A plurality of AND gates are provided, wherein the first input terminal of each plurality of AND gates receives the corresponding first row selection signal, the second input terminal of each plurality of AND gates receives the corresponding second row selection signal, and the output terminal of the plurality of AND gates outputs the corresponding operation signal.

11. The row decoder circuit according to claim 9, wherein the mapping control circuit further comprises: A multiplexing circuit, coupled to the first logic circuit and the second logic circuit, is configured to receive the plurality of control signals and the plurality of operational signals, and selects a plurality of the plurality of operational signals as a plurality of decoding signals according to the plurality of control signals.

12. The line decoder circuit according to claim 11, wherein the multiplexing circuit comprises: Multiple multiplexers, each multiplexer having a first input terminal and a second input terminal receiving two corresponding operational signals, and a control terminal of each multiplexer receiving a corresponding control signal, thereby selecting one of the signals received by its first input terminal and the signal received by its second input terminal as the corresponding decoding signal and outputting it at its output terminal.

13. The line decoder circuit according to claim 11, wherein the multiplexing circuit comprises: Multiple multiplexers are provided, wherein the first input terminal of one of the multiple multiplexers receives the low logic level signal, the second and third input terminals of the same multiplexer receive two corresponding operational signals, the first, second, and third input terminals of the other multiple multiplexers receive three corresponding operational signals, and the control terminal of each multiple multiplexer receives a corresponding control signal, and selects one of the signals received by its first input terminal, the signal received by its second input terminal, and the signal received by its third input terminal as the corresponding decoding signal and outputs it at its output terminal.

14. The row decoder circuit according to claim 11, wherein the mapping control circuit further comprises: The third logic circuit, coupled to the latch circuit, the second logic circuit, and the multiplexing circuit, is configured to receive the plurality of verification signals, the operation signal with the lowest corresponding address among the plurality of operation signals, and the plurality of decoding signals. The third logic circuit inverts the plurality of verification signals and performs AND operations with the operation signal with the lowest corresponding address and the plurality of decoding signals respectively, so as to output the generated plurality of enable signals to the plurality of decoders respectively.

15. The row decoder circuit according to claim 14, wherein the third logic circuit comprises: Multiple inverters, each of which receives a corresponding verification signal at its input terminal; as well as A plurality of AND gates are provided, wherein the first input of one of the plurality of AND gates receives the operation signal with the lowest address among the plurality of operation signals, the first input of each of the other AND gates receives the corresponding decoding signal, the second input of each of the plurality of AND gates is coupled to the output of the corresponding inverter, and the output of each of the plurality of AND gates outputs the corresponding enable signal.

16. The row decoder circuit of claim 1, wherein the mapping control circuit determines the location of at least one damaged faulty memory block based on the verification data.

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