High-capacity Nor Flash partition data recovery method and device

Abstract

The invention provides a high-capacity Nor Flash partition data recovery method and device, relates to the field of data storage, and solves the technical problem that the reliability and the performance of an existing high-capacity Nor Flash are not high enough. The method comprises the steps that Nor Flash is powered on and reset, and the size of a single data recovery area is obtained from a physical configuration area; when the chip receives an erasing instruction, executing an erasing operation on the target storage area; obtaining the address of the storage area needing data recovery currently from the physical state area; based on the weak state judgment voltage and the strong state judgment voltage, judging the logic states of the storage units in the storage area, and executing data recovery operation on the storage units which are judged to be 'weak 0'; and calculating the storage address of the next data recovery area, and writing the storage address into the physical state area. The data recovery method and device are used for the data recovery process of the high-capacity Nor Flash partition.

Description

Technical Field

[0001] This application relates to the field of data storage, and in particular to a method and apparatus for recovering large-capacity Nor Flash partition data. Background Technology

[0002] Nor Flash, a floating-gate non-volatile memory device, is widely used in embedded systems and firmware storage due to its data retention capability even when power is off. Its basic operations include reading, programming, and erasing, and can be further subdivided into single-wire or four-wire reading, single-wire or four-wire programming, and block erasure or full-chip erasure depending on the interface protocol. Nor Flash represents logic "1" or "0" by injecting or releasing charge into the floating gate to change the threshold voltage of the memory cells. However, long-term use leads to charge decay in the floating gate, causing a decrease in the threshold voltage of programmed cells. "Weak 0" cells may be misread as logic 1, resulting in insufficient data retention time and decreased reliability. Existing technologies mainly address this by restoring full-chip data during power-on reset or by threshold convergence only on the programming or erasing areas. However, these methods suffer from limitations such as limited recovery area, long power-on reset time, and the potential for data errors even after long-term operation, leading to insufficient reliability and performance of high-capacity Nor Flash. Therefore, an effective method is urgently needed to solve these problems. Summary of the Invention

[0003] This application provides a method and apparatus for recovering partitioned data from a large-capacity Nor Flash memory, which solves the technical problems of insufficient reliability and performance of existing large-capacity Nor Flash memory.

[0004] To achieve the above objectives, this application adopts the following technical solution: Firstly, a method for recovering partitioned data in a large-capacity Nor Flash memory is provided, comprising: powering on and resetting the Nor Flash; obtaining the size of the data recovery area for a single operation from the physical configuration area; when the chip receives an erase command, performing an erase operation on the target storage area; obtaining the address of the storage area that needs data recovery from the physical status area; determining the logical state of the storage cells within the storage area based on the weak-state determination voltage and the strong-state determination voltage, and performing a data recovery operation on the storage cells determined to be "weak 0"; calculating the storage address of the area that needs data recovery next time, and writing it into the physical status area.

[0005] In conjunction with the first aspect above, in one possible implementation, when the chip receives an erase command, it performs an erase operation on the target memory region, including: generating a high-voltage erase voltage and applying it to the gate of the target memory block; releasing the charge in the memory cell by grounding the source and substrate; and restoring the threshold voltage of all memory cells in the target memory region to the factory initial state.

[0006] In conjunction with the first aspect mentioned above, in one possible implementation, the logic state of the memory cell within the memory region is determined based on the weak-state determination voltage and the strong-state determination voltage, including: applying the weak-state determination voltage and the strong-state determination voltage to the target memory cell respectively; reading the conduction state of the target memory cell and comparing the readout results under the two voltages; when the memory cell is on under the weak-state determination voltage and off under the strong-state determination voltage, it is determined as "weak 0"; when the memory cell is off under both the weak-state determination voltage and the strong-state determination voltage, it is determined as "strong 0".

[0007] In conjunction with the first aspect above, in one possible implementation, a data recovery operation is performed on a memory cell determined to be "weak 0", including: connecting the memory cell to the programming path, applying a high programming voltage to the gate, applying a bias voltage to the drain, and grounding the source; injecting charge into the floating gate by driving channel hot electron injection through the programming voltage; after completing one programming pulse, using a read circuit to determine the weak and strong states of the memory cell; when the determination result is "weak 0", repeatedly applying the programming voltage pulse until the determination result is "strong 0", thus completing the data recovery.

[0008] In conjunction with the first aspect mentioned above, in one possible implementation, calculating the storage address of the area that needs to be recovered next time and writing it into the physical status area includes: after completing a data recovery operation, incrementing the current storage address; using the incremented address as the starting address for the next data recovery; and writing the starting address into the address register unit of the physical status area.

[0009] In conjunction with the first aspect mentioned above, in one possible implementation, the physical configuration area is used to store various configuration parameters loaded when the Nor Flash is powered on. The configuration parameters include the duration of each voltage during read, write, and erase operations, the password required to enter the chip test mode, and the size configuration of the data recovery area. The physical configuration area has the function of sending the size parameter of the data recovery area to the recovery area address accumulator module.

[0010] In conjunction with the first aspect mentioned above, in one possible implementation, a physical state area is used for the current state parameters of the memory chip. The state parameters include the address range of the current write-protected region, the current interface mode, and the address of the memory region that needs to be recovered next time. The physical state area has the function of sending the address of the memory region that needs to be recovered next time to the recovery region address accumulator module.

[0011] In conjunction with the first aspect mentioned above, in one possible implementation, the size of the single data recovery area can be defined according to the NorFlash capacity.

[0012] Secondly, a high-capacity Nor Flash partition data recovery device is provided, comprising: a communication unit and a processing unit; the communication unit is used to obtain the size of a single data recovery area from the physical configuration area and the address of the storage area that currently needs data recovery from the physical status area; the processing unit is used to perform an erase operation on the target storage area when the chip receives an erase command; to determine the logic state of the storage cells in the storage area based on the weak state determination voltage and the strong state determination voltage, and to perform a data recovery operation on the storage cells determined to be "weak 0"; and to calculate the storage address of the area that needs data recovery next time and write it into the physical status area.

[0013] Thirdly, this application provides an electronic device, including: a processor and a storage medium; the storage medium includes instructions, and the processor is configured to execute the instructions to implement the methods described in the first aspect and any possible implementation thereof. This electronic device may be an electronic device or a chip within an electronic device.

[0014] Fourthly, this application provides a large-capacity Nor Flash partitioned data recovery system, including: an I / O interface module, a physical configuration area module, a physical status area module, a recovery area address accumulator module, a logic control circuit module, a multiplexer module, an analog circuit module, a row decoding circuit module, a column decoding circuit module, a storage array module, and a sensitive amplifier module. The I / O interface module receives instructions, addresses, data, and other information from outside the chip and sends the externally sent addresses to the logic control circuit module. The physical configuration area module stores various configuration parameters that need to be loaded when the chip is powered on, such as the duration of various voltages during read, write, and erase operations, the password for entering the chip test mode, and the size configuration of each data recovery area mentioned in this patent, and sends the size configuration of each data recovery area to the recovery area address accumulator module. The physical status area module stores various current status parameters of the chip, such as the address range of the current write-protected area, the current interface mode, and the address of the storage area that needs to be recovered next, as used in this patent, and sends the address of the storage area that needs to be recovered next to the recovery area address accumulator module. The recovery area address accumulator module receives the size configuration of the data recovery area from the physical configuration area and the address of the storage area requiring data recovery from the physical status area. It calculates the address of the area requiring data recovery this time and sends it to the multiplexer module. Then, it calculates the address of the area requiring data recovery next time and sends it to the physical status area. The logic control circuit module receives the address information to be erased from the I / O interface module, calculates the starting address of the memory block containing that address and sends it to the multiplexer module. It also controls the analog circuit module to generate different voltages, including "strong 0" and "weak 0" read voltages, as well as voltages used for programming and erasing. The multiplexer module receives and selects the addresses from the recovery area address accumulator and the logic control circuit. When performing an erase operation, it selects the address from the logic control circuit and sends it to the row decoding circuit module and the column decoding circuit module. After the erase operation is complete, it selects the address from the recovery area address accumulator and sends it to the row decoding circuit module and the column decoding circuit module to perform the data recovery operation on the storage area. The analog circuit module receives control signals from the logic control circuit module and generates the voltages used for read, program, and erase operations, which are then sent to the row and column decoding circuit modules. The row decoding circuit module receives voltage signals from the analog circuit module under various operational conditions, as well as address signals from the multiplexer module. It selects the word line of the memory block corresponding to the address and applies the voltages used for read, program, and erase operations to the gates of each memory cell on the selected word line. The column decoding circuit module receives voltage signals from the analog circuit module under various operational conditions, as well as address signals from the multiplexer module.During a read operation, the bit line of the memory block corresponding to the address is connected to the sensitive amplifier module, and the voltage used for reading is applied to the drain of each memory cell on the selected bit line to complete the read operation. During programming and erase operations, the sensitive amplifier module is isolated, and the voltage used for programming and erasing is applied to the drain of each memory cell on the selected bit line to complete the programming and erase operations. The memory array module is composed of memory cells arranged in a crisscross pattern, forming memory blocks. The gates of each row of memory cells are connected to form word lines, and the drains of each column of memory cells are connected to form bit lines. The sensitive amplifier module receives voltage or current signals sent by the column decoding circuit module and compares them with the voltage or current signals of the internal reference memory cell to obtain the data state of the memory cell as "0" or "1".

[0015] Fifthly, this application provides a computer-readable storage medium storing instructions that, when executed on a mass NOR Flash partition data recovery device, cause the mass NOR Flash partition data recovery device to perform the method described in the first aspect and any possible implementation thereof.

[0016] In a sixth aspect, this application provides a computer program product containing instructions that, when run on an electronic device, cause the electronic device to perform the methods described in the first aspect and any possible implementation thereof.

[0017] This application provides a method and apparatus for recovering partitioned data in a large-capacity Nor Flash memory. By obtaining the size of the data recovery area for a single operation from the physical configuration area during the power-on reset phase, and after the erase operation, performing weak and strong state determinations on the memory cells based on the storage addresses recorded in the physical state area, the method identifies "weak 0" cells and performs data recovery operations. This method covers the entire memory area through partitioned, step-by-step recovery, maintaining even critical data areas that have not been accessed for a long time. Furthermore, the size of each recovery area can be flexibly adjusted according to actual needs, achieving a balance between reliability and performance. This improves the chip's data retention capability and overall reliability during daily use, solving the technical problem of insufficient reliability and performance in existing large-capacity Nor Flash memory.

[0018] It should be understood that the descriptions of technical features, technical solutions, beneficial effects, or similar language in this application do not imply that all features and advantages can be achieved in any single embodiment. Rather, it is understood that the description of a feature or beneficial effect means that a specific technical feature, technical solution, or beneficial effect is included in at least one embodiment. Therefore, the descriptions of technical features, technical solutions, or beneficial effects in this specification do not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions, and beneficial effects described in this embodiment can be combined in any suitable manner. Those skilled in the art will understand that embodiments can be implemented without one or more specific technical features, technical solutions, or beneficial effects of a particular embodiment. In other embodiments, additional technical features and beneficial effects may be identified in specific embodiments that do not embody all embodiments. Attached Figure Description

[0019] Figure 1 A system architecture diagram of a large-capacity Nor Flash partition data recovery system provided in this application embodiment; Figure 2 A flowchart illustrating a method for recovering large-capacity Nor Flash partition data provided in this application embodiment; Figure 3 A flowchart illustrating another method for recovering large-capacity Nor Flash partition data provided in this application embodiment; Figure 4 A flowchart illustrating another method for recovering large-capacity Nor Flash partition data provided in this application embodiment; Figure 5 A flowchart illustrating another method for recovering large-capacity Nor Flash partition data provided in this application embodiment; Figure 6 A schematic diagram of a large-capacity Nor Flash partition data recovery device provided in this application embodiment; Figure 7 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0021] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0022] The data recovery method for large-capacity Nor Flash partitions provided in this application embodiment can be applied to, for example... Figure 1 The large-capacity Nor Flash partition data recovery system 100 shown above, such as Figure 1 As shown, the system includes: an I / O interface module, a physical configuration area module, a physical status area module, a recovery area address accumulator module, a logic control circuit module, a multiplexer module, an analog circuit module, a row decoding circuit module, a column decoding circuit module, a storage array module, and a sensitive amplifier module.

[0023] The I / O interface module is used to receive instructions, addresses, data and other information from outside the chip, and to send the addresses sent in from outside to the logic control circuit module.

[0024] The physical configuration area module is used to store various configuration parameters that need to be loaded when the chip is powered on, such as the duration of various voltages during read, write and erase operations, the password to enter the chip test mode, and the size configuration of each data recovery area mentioned in this patent. The size configuration of each data recovery area is sent to the recovery area address accumulator module.

[0025] The physical status area module is used to store various current status parameters of the memory chip, such as the address range of the current write-protected area, the current interface mode, and the address of the memory area that needs to be recovered next, as used in this patent. The memory area address that needs to be recovered next is sent to the recovery area address accumulator module.

[0026] The recovery area address accumulator module receives the size configuration of the data recovery area from the physical configuration area and the address of the storage area that needs data recovery from the physical status area. It calculates the address of the area that needs data recovery this time and sends it to the multiplexer module. Then it calculates the address of the area that needs data recovery next time and sends it to the physical status area.

[0027] The logic control circuit module receives the address information to be erased from the IO interface module, calculates the starting address of the memory block containing that address, sends it to the multiplexer module, and controls the analog circuit module to generate different voltages, including the read voltage "strong 0" state and "weak 0" state, as well as the voltage used for programming and erasing.

[0028] The multiplexer module receives and selects addresses from the recovery area address accumulator and logic control circuit. During an erase operation, it selects the address from the logic control circuit and sends it to the row decoding circuit module and column decoding circuit module. After the erase operation is completed, it selects the address from the recovery area address accumulator and sends it to the row decoding circuit module and column decoding circuit module to perform data recovery operations on the storage area.

[0029] The analog circuit module receives control signals from the logic control circuit module, generates voltages used for read, program, and erase operations, and sends them to the row decoding circuit module and column decoding circuit module.

[0030] The row decoding circuit module is used to receive voltage signals under various operations sent by the analog circuit module, as well as address signals sent by the multiplexer module, to select the word line of the memory block corresponding to the address, and to apply the voltage used for read, program, erase and other operations to the gate of each memory cell on the selected word line.

[0031] The column decoding circuit module receives voltage signals from the analog circuit module under various operating conditions, as well as address signals from the multiplexer module. During a read operation, the bit line of the memory block corresponding to the address is connected to the sensitive amplifier module, and the voltage used for reading is applied to the drain of each memory cell on the selected bit line to complete the read operation. During programming and erase operations, the sensitive amplifier module is isolated, and the voltage used for programming, erasing, etc., is applied to the drain of each memory cell on the selected bit line to complete the programming and erase operations.

[0032] A memory array module is composed of memory cells arranged in a crisscross pattern, forming memory blocks. The gates of each row of memory cells are connected to form word lines, and the drains of each column of memory cells are connected to form bit lines.

[0033] The sensitive amplifier module is used to receive the voltage or current signal sent by the column decoding circuit module, compare it with the voltage or current signal of the internal reference memory cell, and obtain the data state "0" or "1" of the memory cell.

[0034] To address the technical issues of insufficient reliability and performance of large-capacity Nor Flash in existing technologies, this application provides a method for recovering partitioned data from large-capacity Nor Flash. The method includes: powering on and resetting the Nor Flash; obtaining the size of the data recovery area for a single operation from the physical configuration area; performing an erase operation on the target storage area when the chip receives an erase command; obtaining the address of the storage area requiring data recovery from the physical state area; determining the logical state of the storage cells within the storage area based on weak-state and strong-state determination voltages, and performing data recovery operations on storage cells determined to be "weak 0"; calculating the storage address of the area requiring data recovery next time, and writing it into the physical state area.

[0035] Figure 2 This application provides a flowchart illustrating a method for recovering data from a large-capacity Nor Flash partition. Figure 2 As shown, the method includes: S201, Nor Flash power-on reset, obtain the size of the single data recovery area from the physical configuration area.

[0036] The physical configuration area is a dedicated storage area within the Nor Flash memory used to store various configuration parameters required for chip operation, including the area size, voltage and duration configuration for each data recovery, chip test mode password, and other information.

[0037] In one possible implementation, when the large-capacity Nor Flash is powered on and reset, the control logic circuit automatically reads the size of the single data recovery area recorded in the physical configuration area and passes this information to the recovery area address accumulator module so that subsequent data recovery operations can be performed step by step according to the partition size, ensuring that each recovery operation is completely covered and not repeated.

[0038] It should be noted that the size of the data recovery area in a single operation can be customized according to the chip capacity and design requirements, such as 4Mbit, 8Mbit or larger, to balance recovery efficiency and the time overhead of erasing operations, ensuring that high-capacity chips can respond quickly in daily use.

[0039] As an example, in this embodiment of the application, in a 1Gbit capacity Nor Flash, each recovery area can be set to 4Mbit, and the control circuit sequentially covers the entire storage array to realize partitioned data recovery, and the recovery progress is recorded in the physical state area.

[0040] S202. When the chip receives an erase command, it performs an erase operation on the target storage area.

[0041] In one possible implementation, after receiving an external erase command, the high-voltage signal required for erasure is generated by the logic control circuit of the large-capacity Nor Flash partition data recovery device. This signal is then applied to the row or column decoding module through the analog circuit to select the target memory block, causing the floating gate charge of each memory cell to be released and the erase operation to be completed. At the same time, an over-erasure recovery step can be performed to prevent excessive threshold voltage drift and ensure the accuracy of subsequent judgment operations.

[0042] It should be noted that the order and voltage amplitude of the erase operation can be flexibly adjusted according to the chip design to avoid affecting adjacent memory cells, while ensuring uniform erasure of high-capacity memory areas.

[0043] As an example, in an embodiment of this application, when erasing a 4Mbit memory block, the logic control circuit applies high-voltage gate voltage and drain bias voltage sequentially in row block order, and controls the analog circuit to apply voltage precisely, so that the erasure process is completed under safe and efficient conditions.

[0044] S203. Obtain the address of the storage area where data recovery is currently required from the physical status area.

[0045] The physical state area is used to record the chip's current storage state information, including the write-protected area, interface mode, and the address of the data area that needs to be restored next, providing a state reference for phased recovery.

[0046] In one possible implementation, the recovery area address accumulator reads the starting address of the storage area that needs to be recovered from the physical status area and sends it to the multiplexer and logic control module to ensure that subsequent data recovery operations can directly locate the target storage block and avoid repeated operations.

[0047] It should be noted that by recording the address of the recovery area, the chip can achieve phased and continuous data recovery, which not only improves the reliability of long-term inactive storage blocks, but also reduces the impact of full-chip recovery on system performance.

[0048] As an example, in this embodiment of the application, if the address of the storage block where the last recovery was completed is A, then the starting address of the next recovery recorded in the physical status area is also A, and the control logic directly uses this address to perform operations in the next recovery cycle.

[0049] S204. Based on the weak state determination voltage and the strong state determination voltage, determine the logic state of the storage cell in the storage area, and perform data recovery operation on the storage cell determined to be "weak 0".

[0050] The weak-state determination voltage Vweak-zero and the strong-state determination voltage Vstrong-zero are used to distinguish the logic stability of the memory cell. The "weak 0" cell indicates that the threshold voltage is slightly low, which may lead to the logic value being misjudged as "1" after long-term use, while the "strong 0" cell indicates that the logic state is stable and reliable.

[0051] In one possible implementation, the high-capacity Nor Flash partitioned data recovery device generates Vweak-zero and Vstrong-zero read voltage signals through a logic control circuit. These signals are applied to the selected memory cells, and the read results are latched to determine whether the memory cell is in a "weak zero" state. When a "weak zero" cell is detected, the controller triggers a programming operation, applying a higher gate voltage and drain bias voltage to raise the threshold voltage of the "weak zero" cell to a "strong zero" state, thereby completing the data recovery operation.

[0052] As an example, in this embodiment, data recovery is performed only on memory cells identified as "weak zeros," avoiding the application of additional voltage to normally stable cells, thus reducing power consumption and potential risks. In a single 4Mbit recovery region operation, the control circuit sequentially applies Vweak-zero and Vstrong-zero reads to each memory cell, and immediately performs a high-voltage programming operation upon detecting a "weak zero" cell, achieving reliable restoration of the logic state.

[0053] S205. Calculate the storage address of the area that needs to be recovered next time, and write it into the physical status area.

[0054] The address of the next recovery area is used to record the progress of the phased recovery operation, ensuring continuous coverage of the entire storage array and preventing data loss or accumulation of logical errors.

[0055] In one possible implementation, after the recovery area address accumulator completes the data recovery of the current area, it calculates the starting address of the next recovery area and writes it into the physical status area so that the target storage block can be directly located in the next erase or data recovery cycle.

[0056] It should be noted that by updating the address in stages, the chip can achieve continuous cyclic recovery, which can maintain even critical data areas that have not been operated for a long time, while avoiding the problem of excessive power-on time caused by a one-time full chip recovery.

[0057] In one possible implementation of the embodiments of this application, combined with Figure 2 ,like Figure 3 As shown, the logic state of the memory cell within the memory region determined by the weak-state determination voltage and the strong-state determination voltage in S204 can be specifically implemented through the following S301 to S304, which are explained in detail below: S301. Apply weak-state determination voltage and strong-state determination voltage to the target memory cell respectively.

[0058] In one possible implementation, the high-capacity Nor Flash partition data recovery device generates Vweak-zero and Vstrong-zero voltage signals through a logic control module, which are then applied sequentially to the gate of the selected target memory cell. At the same time, the source is grounded and a small bias voltage is applied to the drain to ensure that the read circuit can correctly determine the cell's conduction state.

[0059] It should be noted that when applying different judgment voltages to the memory cell, the voltage amplitude should be accurate and the duration should be reasonable to avoid judgment errors or damage to the floating gate due to overvoltage or excessively short pulses.

[0060] S302. Read the conduction state of the target memory cell and compare the readout results under two voltages.

[0061] Among them, the conduction state indicates the current conduction status of the storage cell under the applied judgment voltage, which is the basic information for judging the logic state.

[0062] In one possible implementation, the column decoding circuit connects the memory cell bit line to a sensitive amplifier. The sensitive amplifier detects the current signal based on the applied judgment voltage, latches the read result, and the logic control module then compares the two read results to determine whether the memory cell is a "weak 0" or a "strong 0".

[0063] It should be noted that, in order to ensure the accuracy of the judgment, the reading operation must be performed under stable voltage conditions, and the target cell must be accurately selected in conjunction with the row decoding circuit to avoid interference from neighboring cells.

[0064] As an example, during the reading process, Vweak-zero is applied first to read and latch the conduction state, then Vstrong-zero is applied to read and latch the conduction state, and then the two results are logically compared to obtain the judgment basis.

[0065] S303. When a memory cell is turned on under a weak-state determination voltage and turned off under a strong-state determination voltage, it is determined to be "weak 0".

[0066] In one possible implementation, the logic control circuit determines, based on the comparison result of S302, that when a memory cell is turned on under Vweak-zero and turned off under Vstrong-zero, the cell is marked as "weak 0" and its address is passed to the data recovery module for subsequent programming operations.

[0067] It should be noted that this determination method can effectively identify potentially unstable memory cells, thereby enabling targeted programming operations to be applied during the data recovery process, thus improving the reliability of critical chip data.

[0068] As an example, if a memory cell has a current that reaches the threshold of the sensitive amplifier under weak voltage but a current that is below the threshold under strong voltage, the cell is identified as "weak 0" and enters the data recovery queue.

[0069] S304. When the memory cell is cut off under both the weak-state determination voltage and the strong-state determination voltage, it is determined to be "strong 0".

[0070] In one possible implementation, the logic control module determines the type of memory cell based on the comparison results. If the cell is cut off under both Vweak-zero and Vstrong-zero conditions, it is marked as "strong 0," eliminating the need for data recovery and thus saving power and programming resources. "Strong 0" cells do not require reprogramming but still need to be monitored to ensure they are not misused during subsequent erase or programming operations.

[0071] As an example, when scanning a 4Mbit memory block, if a cell is detected to be cut off under both determination voltages, its state remains "strong 0", and the recovery module skips the cell and continues to process the next cell.

[0072] This application's embodiments introduce a dual-voltage determination mechanism—a weak-state determination voltage and a strong-state determination voltage—to accurately distinguish between weak 0 and strong 0 memory cells, thereby specifically identifying potentially unstable memory cells during data recovery. This avoids the problem of weak 0 cells being misread as logic "1" due to threshold voltage decay over long-term use, improving the accuracy of determination and the targeting of data recovery. Simultaneously, by comparing read results under different voltages, multi-dimensional judgment of the memory cell's logic state is achieved, making data recovery no longer dependent on global operations but based on refined determination to execute recovery strategies. This improves the reliability of critical chip areas and reduces power consumption and latency caused by unnecessary recovery operations.

[0073] In one possible implementation of the embodiments of this application, combined with Figure 2 ,like Figure 4 As shown, the data recovery operation performed on the storage unit determined to be "weak 0" in S204 can be specifically implemented through the following S401 to S404, which are explained in detail below: S401. Connect the memory cell to the programming path, apply a high programming voltage to the gate, apply a bias voltage to the drain, and ground the source.

[0074] The programming path includes voltage application paths for the gate, drain, and source, which are used to adjust the floating gate charge through channel hot electron injection.

[0075] In one possible implementation, the logic control circuit controls the multiplexer and analog circuitry to connect memory cells identified as "weak 0" to the programming path. A high programming voltage is applied to the gate, a bias voltage is applied to the drain, and the source is grounded to ensure that hot electrons from the channel can be successfully injected into the floating gate. The amplitude of the programming voltage and the pulse duration need to be precisely controlled to avoid over-injection that could lead to excessively high cell threshold voltages or damage to the memory cells.

[0076] As an example, in 4Mbit recovery region operation, each programming pulse applies an 8-10V gate voltage, a 3-5V drain bias, and ground to the cell, forming a complete programming operation.

[0077] S402: Charge is injected into the floating gate by driving the hot electron injection of the channel through the programming voltage.

[0078] Among them, channel hot electron injection is the main mechanism for increasing the threshold voltage of memory cells, which drives electrons to cross the oxide layer and enter the floating gate through voltage.

[0079] In one possible implementation, the logic control circuit, in conjunction with the analog circuit, generates a high-voltage pulse to control the source-drain current, accelerating electron injection into the floating gate within the channel and thus boosting the threshold voltage. The charge injection process must precisely control the current and time to ensure the cell threshold voltage reaches the "strong 0" requirement while preventing neighboring cells from being affected.

[0080] S403. After completing a programming pulse, the read circuit is used to determine the weak and strong states of the memory cell.

[0081] In one possible implementation, after completing a programming pulse, the logic control module applies Vweak-zero and Vstrong-zero decision voltages, reads the cell's conduction state through column decoding and a sensitive amplifier, and latches the result for decision-making. This decision-making operation avoids over-programming, stops subsequent pulses when the cell has reached the "strong 0" state, saves power consumption, and extends chip lifespan.

[0082] As an example, if the reading result shows that the unit is turned on under weak voltage and turned off under strong voltage, it is still determined to be "weak 0" and programming needs to continue; if it is turned off under both voltages, it is determined to be "strong 0" and the recovery is completed.

[0083] S404. When the determination result is "weak 0", the programming voltage pulse is applied repeatedly until the determination result is "strong 0", then the data recovery is completed.

[0084] The cyclic programming operation ensures that the threshold voltage of all "weak 0" cells is raised to a reliable range, thus enabling data recovery.

[0085] In one possible implementation, the logic control module applies programming pulses cyclically based on the read circuit's determination result, re-determining the state after each pulse until the cell reaches a "strong 0" state. This cyclic process is performed independently for each memory cell, ensuring the stability of the logic state of critical data areas, while partitioned recovery avoids the high power consumption and latency issues associated with processing the entire chip at once.

[0086] This application embodiment performs staged programming recovery on memory cells determined to be weak zero, gradually increasing the floating gate charge until its threshold voltage stabilizes at a strong zero level, thereby effectively eliminating the potential failure risk of weak-state memory cells. Unlike one-time global programming, this method combines a judgment circuit to perform real-time verification of weak and strong states after each programming pulse, avoiding overprogramming or insufficient charge injection, and improving the accuracy and controllability of data recovery. Simultaneously, this iterative recovery method also reduces interference to normal memory cells, lowers device lifespan, and extends the overall service life of the Nor Flash. Therefore, the data recovery process not only achieves high reliability and high accuracy but also balances energy efficiency and device stability, enhancing the data security capabilities of large-capacity Nor Flash in practical applications.

[0087] The above primarily describes the solutions of the embodiments of this application from the perspective of device implementation. It is understood that each device, such as a large-capacity Nor Flash partition data recovery device, includes at least one of the hardware structures and software modules corresponding to the execution of each function in order to achieve the above-mentioned functions. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0088] As an example, in an embodiment of this application, Figure 5 This is a flowchart illustrating the data recovery process for large-capacity Nor Flash partitions. Figure 5As shown, the first step involves reading the data state of the same memory cell using both the "weak 0" read voltage (Vweak-zero) and the "strong 0" read voltage (Vstrong-zero), and latching them separately. The second step determines if the data read using the two voltages are equal. If they are equal, the process switches to the next set of memory cells and repeats the first step. If they are not equal, the memory cell is programmed by switching the voltage to the programming voltage, increasing the threshold voltage of the memory cell, and changing the stored state from "weak 0" to "strong 0". After programming, the first step is repeated to verify successful programming of the memory cell. In the first step, the read voltages Vweak-zero and Vstrong-zero refer to the voltages connected to the gate of the memory cell, typically around 6-9V. Vstrong-zero is slightly higher than Vweak-zero. The source is grounded, and the drain is connected to a bias voltage of approximately 0.5-1V. The programming principle in the second step is different from the principle of reading data status in the first step. It mainly uses channel hot electron injection, which requires a large bias voltage to be applied to the source and drain to generate a large current. Here, the source is still grounded, the drain is connected to a bias voltage of about 3-5V, and the gate is connected to a voltage of about 8-10V, which is greater than the voltage read in the first step.

[0089] This application embodiment can divide the large-capacity Nor Flash partition data recovery device into functional units according to the above method example. For example, each function can be divided into separate functional units, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0090] When using integrated units, Figure 6 A possible structural schematic diagram of the large-capacity Nor Flash partition data recovery device (referred to as large-capacity Nor Flash partition data recovery device 60) involved in the above embodiments is shown. The large-capacity Nor Flash partition data recovery device 60 includes a processing unit 601 and a communication unit 602, and may also include a storage unit 603. Figure 6 The schematic diagram shown can be used to illustrate the structure of the large-capacity NorFlash partition data recovery device involved in the above embodiments.

[0091] when Figure 6The schematic diagram shown illustrates the structure of the large-capacity Nor Flash partition data recovery device involved in the above embodiments. The processing unit 601 is used to control and manage the operation of the large-capacity Nor Flash partition data recovery device, the communication unit 602 is used for the large-capacity Nor Flash partition data recovery device to communicate with other devices, and the storage unit 603 is used to store the program code and data of the large-capacity Nor Flash partition data recovery device.

[0092] For example, communication unit 602 is used to obtain the size of a single data recovery area from the physical configuration area and the address of the storage area that currently needs data recovery from the physical status area.

[0093] The processing unit 601 is used to perform an erase operation on the target storage area when the chip receives an erase command; to determine the logic state of the storage cell in the storage area based on the weak state determination voltage and the strong state determination voltage, and to perform a data recovery operation on the storage cell determined to be "weak 0"; to calculate the storage address of the area where the data needs to be recovered next time, and to write it into the physical state area.

[0094] In one possible implementation, the processing unit 601 is further configured to perform an erase operation on the target memory region when the chip receives an erase command, including: generating a high-voltage erase voltage and applying it to the gate of the target memory block; releasing the charge in the memory cell by grounding the source and substrate; and restoring the threshold voltage of all memory cells in the target memory region to the factory initial state.

[0095] In one possible implementation, the processing unit 601 is further configured to determine the logic state of the memory cell within the storage region based on the weak-state determination voltage and the strong-state determination voltage, including: applying the weak-state determination voltage and the strong-state determination voltage to the target memory cell respectively; reading the conduction state of the target memory cell and comparing the readout results under the two voltages; determining "weak 0" when the memory cell is on under the weak-state determination voltage and off under the strong-state determination voltage; and determining "strong 0" when the memory cell is off under both the weak-state determination voltage and the strong-state determination voltage.

[0096] In one possible implementation, the processing unit 601 is further configured to perform a data recovery operation on the memory cell determined to be "weak 0", including: connecting the memory cell to the programming path, applying a programming high voltage to the gate, applying a bias voltage to the drain, and grounding the source; driving channel hot electron injection through the programming voltage to inject charge into the floating gate; after completing one programming pulse, using the read circuit to determine the weak state and strong state of the memory cell; when the determination result is "weak 0", repeatedly applying the programming voltage pulse until the determination result is "strong 0", then completing the data recovery.

[0097] In one possible implementation, the processing unit 601 is further configured to calculate the storage address of the area to be recovered next time and write it into the physical status area, including: after completing a data recovery operation, incrementing the current storage address; using the incremented address as the starting address for the next data recovery; and writing the starting address into the address register unit of the physical status area.

[0098] In one possible implementation, the processing unit 601 is further configured to store various configuration parameters loaded when the Nor Flash is powered on in the physical configuration area. The configuration parameters include the duration of each voltage during read, write, and erase operations, the password required to enter the chip test mode, and the size configuration of the data recovery area. The physical configuration area has the function of sending the size parameters of the data recovery area to the recovery area address accumulator module.

[0099] In one possible implementation, the processing unit 601 is further configured in a physical state area for the current state parameters of the memory chip. The state parameters include the address range of the current write-protected region, the current interface mode, and the address of the memory region that needs to be recovered next time. The physical state area has the function of sending the address of the memory region that needs to be recovered next time to the recovery region address accumulator module.

[0100] In one possible implementation, the processing unit 601 is also configured to allow the size of the single data recovery area to be defined according to the Nor Flash capacity.

[0101] The processing unit 601 can be a processor or a controller, and the communication unit 602 can be a communication interface, transceiver, transceiver circuit, transceiver device, etc. The term "communication interface" is a general term and may include one or more interfaces. The storage unit 603 can be a memory. When the large-capacity Nor Flash partitioned data recovery device 60 is a chip, the processing unit 601 can be a processor or a controller, and the communication unit 602 can be an input interface and / or an output interface, pins, or circuits, etc. The storage unit 603 can be a storage unit within the chip (e.g., a register, cache, etc.) or a storage unit located outside the chip (e.g., read-only memory (ROM), random access memory (RAM, etc.).

[0102] The communication unit can also be called a transceiver unit. The antenna and control circuit with transceiver functions in the large-capacity Nor Flash partition data recovery device 60 can be considered as the communication unit 602 of the large-capacity Nor Flash partition data recovery device 60, and the processor with processing functions can be considered as the processing unit 601 of the large-capacity Nor Flash partition data recovery device 60. Optionally, the device in the communication unit 602 that implements the receiving function can be considered as the communication unit. The communication unit is used to execute the receiving steps in the embodiments of this application, and the communication unit can be a receiver, a receiver circuit, etc. The device in the communication unit 602 that implements the transmitting function can be considered as the transmitting unit. The transmitting unit is used to execute the transmitting steps in the embodiments of this application, and the transmitting unit can be a transmitter, a transmitter, a transmitting circuit, etc.

[0103] Figure 6 If the integrated units in the process are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. Storage media for storing computer software products include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0104] Figure 6 The units in the process can also be called modules; for example, a processing unit can be called a processing module.

[0105] This application also provides a hardware structure diagram of an electronic device (denoted as electronic device 70), see [link to diagram]. Figure 7 The electronic device 70 includes a processor 701, and optionally, a memory 702 connected to the processor 701.

[0106] In the first possible implementation, see Figure 7The electronic device 70 also includes a transceiver 703. The processor 701, memory 702, and transceiver 703 are connected via a bus. The transceiver 703 is used to communicate with other devices or communication networks. Optionally, the transceiver 703 may include a transmitter and a receiver. The device in the transceiver 703 that implements the receiving function can be considered as a receiver, which is used to perform the receiving steps in the embodiments of this application. The device in the transceiver 703 that implements the transmitting function can be considered as a transmitter, which is used to perform the transmitting steps in the embodiments of this application.

[0107] Based on the first possible implementation method Figure 7 The structural diagram shown can be used to illustrate the structure of the electronic device involved in the above embodiments.

[0108] in, Figure 7 This can also be illustrated by a system chip in an electronic device. In this case, the actions performed by the aforementioned electronic device can be implemented by this system chip; the specific actions performed can be found above and will not be repeated here.

[0109] In implementation, each step of the method provided in this embodiment can be completed by integrated logic circuits in the processor or by instructions in software form. The steps of the method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules in the processor.

[0110] The processor in this application may include, but is not limited to, at least one of the following: a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a microcontroller unit (MCU), or an artificial intelligence processor, etc., which are various computing devices that run software. Each computing device may include one or more cores for executing software instructions to perform calculations or processing. The processor may be a standalone semiconductor chip or integrated with other circuits into a single semiconductor chip. For example, it may be integrated with other circuits (such as encoding / decoding circuits, hardware acceleration circuits, or various bus and interface circuits) to form a System-on-a-Chip (SoC), or it may be integrated as a built-in processor within an ASIC. The ASIC with the integrated processor may be packaged separately or together with other circuits. In addition to the cores for executing software instructions to perform calculations or processing, the processor may further include necessary hardware accelerators, such as field-programmable gate arrays (FPGAs), PLDs (programmable logic devices), or logic circuits that implement dedicated logic operations.

[0111] The memory in the embodiments of this application may include at least one of the following types: read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; or electrically erasable programmable-only memory (EEPROM). In some scenarios, the memory may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto.

[0112] This application also provides a computer-readable storage medium including instructions that, when run on a computer, cause the computer to perform any of the methods described above.

[0113] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the methods described above.

[0114] This application also provides a chip including a processor and an interface circuit. The interface circuit is coupled to the processor. The processor is used to run computer programs or instructions to implement the above-described method. The interface circuit is used to communicate with other modules outside the chip.

[0115] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks (SSDs)).

[0116] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0117] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A method for recovering data from a large capacity Nor Flash partition, comprising: The method comprises the following steps: ​ Nor Flash power reset, get single data recovery area size from the physical configuration area; When the chip receives an erase instruction, perform an erase operation on the target storage area; Get the address of the storage area that needs data recovery from the physical state area; Determine the logical state of the storage unit in the storage area based on the weak state determination voltage and the strong state determination voltage, and perform a data recovery operation on the storage unit determined as "weak 0"; Calculate the storage address of the next data recovery area and write it to the physical state area.

2. The method of claim 1, wherein, When the chip receives an erase instruction, perform an erase operation on the target storage area, which comprises: Generate a high-voltage erase voltage and apply it to the gate of the target storage block; Release the charge in the storage unit by grounding the source and substrate; Restore the threshold voltage of all storage units in the target storage area to the factory initial state.

3. The method of claim 1, wherein, Determine the logical state of the storage unit in the storage area based on the weak state determination voltage and the strong state determination voltage, which comprises: Apply weak state determination voltage and strong state determination voltage to the target storage unit respectively; Read the conduction state of the target storage unit and compare the read results under the two voltages; When the storage unit is on under the weak state determination voltage and off under the strong state determination voltage, it is determined as "weak 0"; When the storage unit is off under the weak state determination voltage and the strong state determination voltage, it is determined as "strong 0".

4. The method of claim 3, wherein, Perform a data recovery operation on the storage unit determined as "weak 0", which comprises: Connect the storage unit to the programming path, apply a programming high voltage to the gate, apply a bias voltage to the drain, and ground the source; Drive the channel hot electron injection by the programming voltage to inject charge into the floating gate; After completing a programming pulse, determine the weak state and strong state of the storage unit using the read circuit; When the determination result is "weak 0", repeat the programming voltage pulse until the determination result is "strong 0", and the data recovery is completed.

5. The method of claim 1, wherein, Calculate the storage address of the next data recovery area and write it to the physical state area, which comprises: After completing a data recovery operation, perform address accumulation on the current storage address; Use the accumulated address as the starting address of the next data recovery; Write the starting address to the address register unit of the physical state area.

6. The method of claim 1, wherein, The physical configuration area is used to store various configuration parameters loaded when the Nor Flash is powered on, including the duration of each voltage in the read, write, and erase operation process, the password required to enter the chip test mode, and the size configuration of the data recovery area; wherein the physical configuration area has the function of sending the size parameter of the data recovery area to the recovery area address accumulator module.

7. The method of claim 1, wherein, The physical state area is used to store the current state parameters of the chip, including the address range of the current write protection area, the current interface mode, and the storage area address that needs data recovery next time; wherein the physical state area has the function of sending the storage area address that needs data recovery next time to the recovery area address accumulator module.

8. The method of claim 1, wherein, The size of the single data recovery area can be defined according to the capacity of the NorFlash.

9. A mass Nor Flash partition data recovery apparatus, characterized by, The device comprises a communication unit and a processing unit; The communication unit is used to acquire the single data recovery area size from the physical configuration area and the storage area address currently requiring data recovery from the physical state area; The processing unit is used to execute the erasing operation on the target storage area when the chip receives the erasing instruction; judge the logic state of the memory cell in the storage area based on the weak state decision voltage and the strong state decision voltage, execute the data recovery operation on the memory cell judged as "weak 0"; calculate the storage address of the next data recovery area and write into the physical state area.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores instructions, when the instructions run on the electronic device, make the electronic device execute the method as claimed in any one of claims 1-8.

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