A circuit structure for automatic power-on reset of a chip to enter a readable mode.
By designing an automatic reset circuit structure on the chip, the problem of needing to configure registers to read data upon power-up was solved, enabling data reading without configuration, expanding application scenarios, improving flexibility, and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU NIOBIA ELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2025-07-17
- Publication Date
- 2026-05-26
AI Technical Summary
Existing chips require register configuration upon power-up to read data, limiting their application scenarios and failing to meet customers' needs for directly obtaining raw data.
Design a circuit structure for automatic power-on reset of a chip to enter a readable mode, including an RC circuit, an oscillator, logic gates, and a D flip-flop. By generating a high-level active power-on reset signal and a synchronous reset signal, the chip automatically enters a full "0" state after power-on, and the controller can directly read the data.
It enables data reading without configuring registers, expands the application scope, meets the needs of advanced users to write their own algorithms, simplifies module design, reduces costs, and improves flexibility and applicability to various application scenarios.
Smart Images
Figure CN224289770U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit design technology, specifically to a circuit structure for automatically resetting a chip upon power-up to enter a readable mode. Background Technology
[0002] The E93186 chip, designed by the German company ELMOS, integrates register logic control functions. The lower 25 bits of the register can be configured with different parameter values to achieve different logic algorithms and control functions, adapting to various application scenarios. In the higher 15 bits of the register, except for the most significant bit (Bit 39), which is an overflow indicator to show whether the signal value exceeds the ADC dynamic range (±54mV), the remaining 14 bits (Bits 38-25) directly change with the slight voltage difference between the N and P pins. Their data values indicate the movement status signal value of the infrared heat source (such as a human body) within the detection range. This data can be read directly by the controller via the single-wire communication port DOCI for logic judgments and functions such as switch closure or alarm.
[0003] Perhaps when the German company ELMOS designed the E93186 chip, they believed that the logic algorithm control functions achievable by its internal registers were practical and sufficiently rich. Therefore, they did not consider a power-on forced reset function for the chip registers, meaning it could not directly enter a reset, forced-read operating mode upon power-up. Instead, users were required to configure the internal registers with their preferred algorithms, and then the chip would output logic interrupt values according to the configured algorithms. However, in actual use, many customers want the chip to directly enter a mode that can read PIR raw data upon power-up without register configuration. This allows customers with a strong understanding of PIR systems and deep embedded system design skills to write their own algorithms based on the acquired raw data, adapting to a wider range of application scenarios. The ELMOS E93186 chip cannot meet the needs of these customers. Currently, similar chips on the domestic market all reference the architecture of the ELMOS E93186 chip. The chip can only operate and output response level signals or data according to the configured operating mode after the registers are configured; without register configuration, the register data cannot be forcibly reset, resulting in the chip's signal output channel being closed and the controller unable to read data or communicate.
[0004] Therefore, the E93186 chip designed by the German company ELMOS and similar domestic products have the following defects:
[0005] 1. The register has no forced reset function after power-on. The user must configure the register parameters first. Otherwise, the register data cannot be read, the signal output channel is closed, and the controller cannot communicate.
[0006] 2. Without configuring registers, the chip cannot enter the data output state, which limits the application scenarios where only the chip needs to perform AD conversion (the logic control algorithm is completed by the microcontroller), resulting in a narrow range of applications. Utility Model Content
[0007] In view of this, and in response to the problem that existing technologies require chip registers to be configured to read data and limit application scenarios, this utility model proposes a circuit structure for automatic reset of the chip upon power-up to enter a readable mode, enabling the chip to directly read data without configuring registers after power-up, thus expanding the application scope.
[0008] This utility model solves the above problems through the following technical means:
[0009] This utility model provides a circuit structure for automatic reset of a chip upon power-up to enter a readable mode, including an RC circuit, an oscillator, logic gates, and a D flip-flop;
[0010] The logic gates are respectively connected to the RC circuit, the oscillator, and the D flip-flop;
[0011] When the RC circuit is powered on, it generates a high-level active power-on reset signal POR_1; the oscillator internally generates a high-level active synchronous reset signal POR_2 and a clock signal.
[0012] After receiving the power-on reset signal POR_1 and the synchronous reset signal POR_2, the logic gate will generate a low-level active clear signal, which clears all D flip-flops inside the chip.
[0013] After all D flip-flops are cleared, the clock of the D flip-flops operates normally, outputting a POR signal of 1. At the same time, the synchronous reset signal POR_2 of the oscillator is turned off, releasing the reset state, and the chip's registers automatically enter the forced data read mode.
[0014] Preferably, the RC circuit includes resistors and capacitors that are electrically connected to each other.
[0015] Preferably, in the forced data read mode, the high-order registers Bit38-Bit25 output the AD value of the voltage difference conversion between the N / P pins in real time.
[0016] Preferably, the chip package structure includes a 7-pin package, with all pins brought out, including the register configuration pin Serin.
[0017] Preferably, the chip package structure includes a 5-pin package, which grounds and fixes the register configuration pin Serin, so that the high 15-bit data register is kept in a continuously updated state.
[0018] Preferably, the circuit structure for automatic power-on reset of the chip is disposed on the chip.
[0019] Compared with the prior art, the beneficial effects of this utility model include at least the following:
[0020] 1. Reading data without register configuration: Through the circuit structure of automatic power-on reset, the registers of the chip automatically enter the all "0" state after power-on. The controller can directly force the reading of data through the DOCI single-wire communication port without the need for user register configuration. This meets the needs of some customers who want to directly obtain the raw data after power-on and write their own algorithms, expanding the application range of the chip and making it suitable for scenarios where only the chip needs to perform AD data conversion and other logic control functions are completed by the microcontroller.
[0021] 2. Enhanced Usage Flexibility: The chip is available in both 7-pin and 5-pin packages. The 5-pin package grounds the register configuration pin Serin, which can maintain the continuous update of the high 15 bits of data, making it easier to use the chip as an AD conversion chip and providing module users with greater flexibility. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of the circuit structure for automatic power-on reset of a chip, which is based on this utility model.
[0024] Figure 2 This is a reset flowchart of the circuit structure for automatic power-on reset of a chip, which is based on this utility model. Detailed Implementation
[0025] To make the above-mentioned objectives, features, and advantages of this utility model more apparent and understandable, the technical solution of this utility model will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the described embodiments are merely some embodiments of this utility model, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.
[0026] Considering the logic functions defined by each register of the chip, when all configurable bits of the register are "0", the corresponding controller of the chip can force data to be read through the DOCI single-wire communication port (i.e., the default working mode). If this data can be read by the controller, through the controller's write algorithm, it can adapt to a wider range of logic judgments and output judgment values, meeting the needs of the aforementioned types of customers. Based on this, this utility model improves the chip circuit design, changing the circuit design that register configuration is a necessary prerequisite for data output, and adds automatic forced reset of the register after power-on, that is, entering the all "0" state, i.e., the controller's forced reading mode. This improvement makes the chip applicable to application scenarios where only the SSP chip needs to perform AD data conversion (other logic control functions are completed by the microcontroller), thereby expanding the application range of the chip. In addition to the 7 pins being fully exposed, the chip can also be packaged in a bare die package with the register configuration pin Serin grounded and fixed (only 5 pins need to be exposed), thus maintaining the continuous update of the high 15 bits of data, making it more convenient for the chip to be used only as an AD conversion chip, expanding the applicable flexibility and applicable scenarios for module users. It has already been applied to the NY86 chip.
[0027] like Figure 1-2 As shown, this utility model provides a circuit structure for automatic power-on reset of a chip, including an RC circuit, an oscillator, a logic gate, and a D flip-flop;
[0028] The logic gates are respectively connected to the RC circuit, the oscillator, and the D flip-flop;
[0029] When the RC circuit is powered on, it generates a high-level active power-on reset signal POR_1; the oscillator internally generates a high-level active synchronous reset signal POR_2 and a clock signal.
[0030] After receiving the power-on reset signal POR_1 and the synchronous reset signal POR_2, the logic gate will generate a low-level active clear signal, which clears all D flip-flops inside the chip.
[0031] After all D flip-flops are cleared, the clock of the D flip-flops operates normally, outputting a POR signal of 1. At the same time, the synchronous reset signal POR_2 of the oscillator is turned off, releasing the reset state, and the chip's registers automatically enter the forced data read mode.
[0032] This ensures that all DFF values are reset to zero before CLOCK is activated, allowing the chip to directly enter the forced read register mode without needing to configure the register initial values.
[0033] Specifically, the RC circuit includes resistors and capacitors that are electrically connected to each other.
[0034] The chip comes in two packaging formats:
[0035] The 7-pin package exposes all 7 pins of the chip.
[0036] In the 5-pin package, the register configuration pin Serin is grounded and fixed in the bare die package, with only 5 pins exposed to keep the high 15 bits of data continuously updated.
[0037] This utility model has the following advantages:
[0038] 1. Addressing industry pain points: The innovative addition of a function that automatically forces the registers to all "0"s upon power-up solves the limitation of traditional similar chips (such as the German E93186 and domestic imitations) requiring pre-configuration of the registers to function. Users do not need any initialization configuration; the chip is ready to work upon power-up.
[0039] 2. Enable configuration-free raw data reading mode: When all registers are "0", the chip automatically enters forced reading mode. The controller can directly and in real time read the raw PIR data (such as human movement signal value) that changes with the NP voltage difference in the high-order register (Bit38-Bit25) and the overflow indicator bit (Bit39) of the low-order register through the DOCI single-wire communication port.
[0040] 3. Significantly improves application flexibility:
[0041] Empowering advanced users: Customers familiar with the PIR system can directly access raw data and independently develop more complex and adaptable backend algorithms to meet diverse and customized scenario needs that cannot be covered by the original German solution.
[0042] Simplified basic applications: The chip can be used as a pure AD converter, only responsible for converting analog micro-differential pressure into digital signal output (high 15 bits). All logic control functions (such as switch judgment and alarm) are completed by an external microcontroller, which greatly simplifies module design.
[0043] Package optimization reduces costs: In bare die packaging, the configuration pin Serin can be grounded to fix this mode, requiring only 5 pins to be brought out (reserving necessary pins such as data output and power supply), which is more economical than the 7-pin full-pin package and is especially suitable for scenarios that only require AD function.
[0044] 4. Reliable technical implementation: By designing a clever POR (Power-On Reset) circuit (combining RC delay POR_1 and POR_2 generated by OSC clock), it ensures that all internal DFFs are cleared before the clock stabilizes, thus reliably and stably achieving power-on reset to the target state.
[0045] This invention enables the chip to be forcibly reset to a full "0" state upon power-on, eliminating the need for mandatory register configuration and pioneering a direct read-from-the-box mode for raw data. This not only meets the deep customization needs of high-end users and expands application scenarios (especially pure AD conversion applications), but also reduces costs in specific scenarios through packaging optimization, significantly improving the product's market competitiveness and user convenience.
[0046] The following are specific application examples.
[0047] Example 1: Application of Human Body Sensing Module in Smart Home
[0048] In smart home human body sensing modules, it is necessary to monitor the movement of people indoors in real time to trigger lighting, security and other devices. This chip adopts a 5-pin package. In the bare die package, the register configuration pin Serin is grounded and fixed, and only 5 pins are brought out (including N and P infrared detection pins, power pin, ground pin and DOCI communication pin).
[0049] Upon power-up, the chip's automatic forced reset circuit immediately activates: the RC circuit generates a POR_1 signal, and the internal oscillator OSC synchronously generates a POR_2 signal. These two signals are processed by the logic unit to generate a low-level clear signal, clearing all DFFs. After the CLOCK operates normally and samples, the POR output is 1, all configurable bits in the register are in a "0" state, and the high 15 bits (Bit39-Bit25) change in real time with the slight voltage difference between the N and P pins (caused by human infrared radiation).
[0050] The controller continuously reads the high 15 bits of raw data via the DOCI single-wire communication port. Bit 39 is used to determine whether the signal exceeds the ADC dynamic range (±54mV), and bits 38-25 reflect the human movement status. The controller's built-in algorithm performs identification analysis and threshold judgment on the raw data. When a signal is detected and determined to be human movement, a control signal is output to trigger lighting to turn on or security arming to activate. No additional configuration of the chip registers is required, simplifying the module design process and adapting to the needs of smart homes for rapid deployment and flexible development.
[0051] Example 2: Application in Industrial Security Alarm Systems
[0052] An industrial security alarm system needs to simultaneously realize infrared heat source (such as abnormal equipment heating) monitoring and local logic judgment functions. This chip adopts a 7-pin package form, with all pins brought out (including Serin configuration pins).
[0053] Upon power-up, the chip automatically enters a full "0" reset state. The controller first reads the initial raw data (ambient noise floor) through the DOCI port. If the system needs to enable some of the chip's built-in logic (such as simplified signal filtering), specific configuration parameters (not in a full "0" state) can be written to the lower 25 bits of the register via the Serin pin. At this time, the chip preprocesses the signal according to the configuration logic and outputs an interrupt or data. If the system needs to switch to a custom algorithm mode later, the controller can trigger a chip reset via software (simulating power-on reset logic), causing the register to return to a full "0" state, read the raw data again, and execute complex algorithms (such as using time series analysis to determine abnormal heat source movement).
[0054] In this application, the flexibility of the 7-pin package allows the chip to function as a standalone AD converter in conjunction with the controller to implement complex logic, or to simplify system design by utilizing built-in logic, thus meeting diverse functional requirements in industrial scenarios.
[0055] Example 3: Application in portable infrared temperature measurement devices
[0056] Portable infrared temperature measurement devices require small size, low power consumption, and the temperature signal of the object being measured needs to be converted into a digital value for the microcontroller to calculate the temperature value. This chip uses a small 7-pin package and configures the register for temperature measurement mode via the Serin pin.
[0057] Upon power-up, the chip automatically resets to a state of all "0", immediately entering operational mode and shortening device startup time. The controller then configures its register to enter ADC offset measurement mode, reading the offset value as a data calibration reference. The microcontroller subsequently configures its register to temperature measurement mode and, through a calibration algorithm (such as the temperature-AD value relationship formula) on the acquired AD data, quickly outputs the temperature measurement result, meeting the high-efficiency and compact design requirements of portable devices.
[0058] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.
Claims
1. A circuit structure for on-chip power-on automatic reset into a readable mode, characterized by, The RC circuit, the oscillator, the logic gate and the D flip-flop are included. The logic gate is connected with the RC circuit, the oscillator and the D flip-flop respectively. The RC circuit generates a high-level effective power-on reset signal POR_1 when powered on; the oscillator internally generates a high-level effective synchronous reset signal POR_2 and a clock signal. After receiving the power-on reset signal POR_1 and the synchronous reset signal POR_2, the logic gate generates a low-level effective clear signal, which clears all the D flip-flops in the chip. After all the D flip-flops are cleared, the clock of the D flip-flop works normally, the output POR signal is 1, the synchronous reset signal POR_2 of the oscillator is closed, the reset state is released, and the registers of the chip automatically enter the forced data reading mode.
2. The circuit structure for automatic power-on reset into a readable mode on chip according to claim 1, wherein, The RC circuit includes a resistor and a capacitor which are electrically connected with each other.
3. The circuit structure for automatic power-on reset into a readable mode on chip according to claim 1, wherein, In the forced data reading mode, the high-bit registers Bit38-Bit25 output the AD value converted by the pressure difference between the N pin and the P pin in real time.
4. The circuit structure for automatic power-on reset into a readable mode on chip according to claim 1, wherein, The chip packaging structure includes a 7pin package, and the 7pin package leads all the pins, including the register configuration pin Serin.
5. The circuit structure for automatic power-on reset into a readable mode on a chip according to claim 1, wherein, The chip packaging structure includes a 5pin package, and the 5pin package grounds the register configuration pin Serin, so that the high 15-bit data registers remain in a continuous updating state.
6. The circuit structure for automatic power-on reset into a readable mode on a chip according to claim 1, wherein, The circuit structure for automatically resetting the chip to enter the readable mode is arranged on the chip.