Impulse negative charge drive circuit for suppressing crosstalk and switching power converter

Abstract

This application relates to the field of semiconductor technology. Embodiments of this application provide a surge negative charge driving circuit and a switching power converter for suppressing crosstalk, comprising: a driving module and a surge negative charge module; a first terminal of the driving module receives an input signal, and a second terminal of the driving module is connected to the gate node of a silicon carbide MOSFET, used to control the turn-on and turn-off of the silicon carbide MOSFET according to the input signal; a first terminal of the surge negative charge module receives the input signal, a second terminal of the surge negative charge module is connected to a power supply terminal, a third terminal of the surge negative charge module is connected to a ground terminal, and a fourth terminal of the surge negative charge module is connected to the gate node of the silicon carbide MOSFET, used to release negative charge to the gate node during the turn-off process of the silicon carbide MOSFET when the drain voltage of the silicon carbide MOSFET rises, causing Miller current to flow back to the gate node, in order to neutralize the Miller current. Highly efficient crosstalk suppression is achieved through the physical method of charge neutralization, without relying on a continuous negative voltage power supply, simplifying the system architecture and reducing costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a surge negative charge driving circuit and a switching power converter for suppressing crosstalk. Background Technology

[0002] Silicon-carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are widely used in high-frequency power electronic converters due to their faster switching speed and higher voltage change rate (dv / dt). However, during turn-off, their drain voltage rises sharply. This rapid voltage change is coupled to the gate through the device's inherent gate-drain capacitance (Miller capacitance), generating a positive crosstalk voltage pulse at the gate. This phenomenon is commonly referred to as gate crosstalk caused by the "Miller effect."

[0003] This crosstalk voltage will cause the gate-source voltage (ΔV) to increase. GS If the voltage rises, and its amplitude exceeds the gate-source threshold voltage (V) of the device... GS This crosstalk will cause the power transistor, which should be turned off, to turn on again, leading to bridge arm shoot-through risk, circuit oscillation, and additional switching losses, and in severe cases, even device damage. Furthermore, the threshold voltage of silicon carbide MOSFETs decreases with increasing temperature, further exacerbating the risk of mis-turn-on due to crosstalk voltage at high temperatures. Therefore, effectively suppressing this type of gate crosstalk and preventing mis-turn-on has become a crucial technical problem that needs to be solved to improve system reliability. Summary of the Invention

[0004] In view of this, embodiments of this application provide an impulse negative charge drive circuit and a switching power converter for suppressing crosstalk, in order to overcome the technical deficiencies existing in the prior art.

[0005] In a first aspect, embodiments of this application provide an impulse negative charge driving circuit for suppressing crosstalk, comprising: a driving module and an impulse negative charge module;

[0006] The first end of the drive module receives the input signal, and the second end of the drive module is connected to the gate node of the silicon carbide MOSFET, which is used to control the turn-on and turn-off of the silicon carbide MOSFET according to the input signal.

[0007] The first terminal of the impact negative charge module receives the input signal, the second terminal of the impact negative charge module is connected to the power supply terminal, the third terminal of the impact negative charge module is connected to the ground terminal, and the fourth terminal of the impact negative charge module is connected to the gate node of the silicon carbide MOSFET. It is used to release negative charge to the gate node to neutralize the Miller current when the drain voltage of the silicon carbide MOSFET rises and causes the Miller current to flow back to the gate node during the turn-off process of the silicon carbide MOSFET.

[0008] In one possible implementation, the impact negative charge module includes an impact capacitor, a signal receiving unit, and a switch control unit;

[0009] The first end of the impact capacitor is connected to the gate node of the silicon carbide MOSFET;

[0010] The first end of the signal receiving unit receives the input signal, the second end of the signal receiving unit is connected to the power supply terminal, the third end of the signal receiving unit is connected to the ground terminal, and the fourth end of the signal receiving unit is electrically connected to the first end of the switch control unit.

[0011] The second terminal of the switch control unit is connected to the power supply terminal, the third terminal of the switch control unit is connected to the ground terminal, and the fourth terminal of the switch control unit is connected to the second terminal of the surge capacitor to control the connection state of the second terminal of the surge capacitor.

[0012] In one possible implementation, the switch control unit is configured as follows:

[0013] When the input signal is at the first level, the second terminal of the control impulse capacitor is connected to the power supply terminal to precharge the impulse capacitor, so that a pre-charge voltage difference is established between the first and second terminals of the impulse capacitor.

[0014] When the input signal changes to the second level and Miller current is generated, the second terminal of the control impulse capacitor is switched from the power supply terminal to the ground terminal.

[0015] In one possible implementation, the switch control unit includes a first switch and a second switch;

[0016] The drains of both the first and second switching transistors are connected to the second terminal of the surge capacitor. The source of the first switching transistor is connected to the power supply terminal, and the gate of the first switching transistor is connected to the gate of the second switching transistor. The source of the second switching transistor is connected to the ground terminal.

[0017] When the input signal is at the first level, the first switch is turned on and the second switch is turned off, and the second end of the impulse capacitor is connected to the power supply.

[0018] When the input signal is at the second level, the first switch is turned off and the second switch is turned on, and the second terminal of the surge capacitor is switched from the power supply terminal to the ground terminal.

[0019] In one possible implementation, the signal receiving unit includes a third switch and a fourth switch;

[0020] The source of the third switch is connected to the power supply terminal, and the drains of both the third and fourth switches are connected to the gate of the first switch. The gate of the third switch is electrically connected to the gate of the fourth switch. The source of the fourth switch is connected to the ground terminal.

[0021] In one possible implementation, the impact negative charge module also includes a timing control circuit;

[0022] The input terminal of the timing control circuit is electrically connected to the drain of the third switching transistor, and the output terminal of the timing control circuit is electrically connected to the gate of the first switching transistor. After detecting that the input signal changes from the first level to the second level, a timing control signal is generated to control the switch control unit after a preset delay. The timing control signal controls the first switching transistor to turn off and the second switching transistor to turn on, so that the second terminal of the surge capacitor is switched from the power supply terminal to the ground terminal.

[0023] In one possible implementation, the impact negative charge driving circuit also includes a pre-charging circuit;

[0024] The pre-charge circuit is connected between the third terminal of the drive module and the second terminal of the impact negative charge module. It is used to power the drive module and to provide a pre-charge current to the impact capacitor during the conduction of the silicon carbide MOSFET, so that the voltage across its terminals reaches a preset value.

[0025] In one possible implementation, the power supply terminal is the output terminal of the pre-charge circuit, and the preset value is greater than the voltage value of the turn-off drive level output by the drive module; wherein, the turn-off drive level is the level output by the second terminal of the drive module, which is used to control the turn-off of the silicon carbide MOSFET.

[0026] In one possible implementation, the impulse negative charge module includes multiple impulse capacitor units connected in parallel, each impulse capacitor unit including an impulse capacitor and its corresponding switch control unit; each impulse capacitor unit is configured to independently release negative charge to the gate node.

[0027] Secondly, embodiments of this application provide a switching power converter, including: a switching power transistor, a control circuit, a conversion circuit, and a surge negative charge driving circuit for suppressing crosstalk according to the first aspect of this application; the switching power transistor is a silicon carbide MOSFET; the output terminal of the surge negative charge driving circuit is connected to the gate of the silicon carbide MOSFET for driving the silicon carbide MOSFET; the control circuit is used to generate a PWM control signal and send it to the surge negative charge driving circuit; the conversion circuit is connected to the drain of the silicon carbide MOSFET for controlling the conversion of voltage or current.

[0028] The technical solution provided in this application embodiment constructs a two-stage transient response architecture by setting up a driving module and a negative charge impulse module that cooperate with each other. The driving module is responsible for executing basic switching control based on PWM signals; while the negative charge impulse module acts as a dedicated dynamic compensation unit, triggered at the moment when the silicon carbide MOSFET is turned off and the drain voltage rises sharply. Through its direct connection to the gate node, this module can accurately inject pre-stored or real-time generated negative charges into the gate node, thereby directly offsetting the positive displacement current generated by Miller capacitance coupling. This mechanism effectively suppresses abnormal gate voltage rises, fundamentally preventing false turn-on and oscillations caused by voltage exceeding the threshold. Based on this circuit structure, on the one hand, it achieves efficient crosstalk suppression through the physical method of charge neutralization, without relying on a continuous negative voltage power supply, simplifying the system architecture and reducing costs; on the other hand, this module only operates during the turn-off transient, avoiding the continuous losses or switching speed reduction problems that may be caused by traditional crosstalk suppression schemes, thus improving system reliability while ensuring switching efficiency. Attached Figure Description

[0029] Figure 1 This is a detailed structural diagram of the Si driving circuit in related technologies;

[0030] Figure 2 This is a schematic diagram of the structure of a shock negative charge driving circuit for suppressing crosstalk provided in one embodiment of this application;

[0031] Figure 3 This is a detailed structural diagram of an impulse negative charge driving circuit for suppressing crosstalk provided in one embodiment of this application;

[0032] Figure 4 This is a detailed structural diagram of an impulse negative charge driving circuit for suppressing crosstalk provided in one embodiment of this application;

[0033] Figure 5 This is a detailed structural diagram of an impact negative charge module provided in one embodiment of this application;

[0034] Figure 6 This is a schematic diagram of the operation of an impact negative charge module provided in one embodiment of this application;

[0035] Figure 7 This is a schematic diagram of the turn-off control of a silicon carbide MOSFET provided in one embodiment of this application. Detailed Implementation

[0036] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0037] The terminology used in one or more embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of one or more embodiments of this application. The singular forms “a” and “the” as used in one or more embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this application refers to and includes any or all possible combinations of one or more associated listed items.

[0038] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this application, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0039] To facilitate understanding of the technical solutions in the embodiments of this application, the terms and concepts involved in one or more embodiments of this application are explained.

[0040] 1. Miller current: When a power device (such as a MOSFET) is turned off, its drain voltage rises sharply. This rapidly changing voltage generates a displacement current through the device's inherent gate-drain capacitance (also known as Miller capacitance). This current couples from the drain to the gate, and is called the Miller current.

[0041] 2. Neutralization: Injecting equal-sized but opposite-polarity charges simultaneously into the same node so that their electrical effects cancel each other out.

[0042] This application provides an impulse negative charge drive circuit for suppressing crosstalk, and a switching power converter, which will be described in detail in the following embodiments.

[0043] Figure 1 This is a schematic diagram of the structure of the Si driving circuit in related technologies.

[0044] Reference Figure 1The diagram illustrates a silicon (Si) driver circuit used to drive a silicon carbide MOSFET. It includes the silicon driver circuit 101 on the left and the silicon carbide MOSFET 103 on the right. The PWM control signal 111 on the left is transmitted through the driver module 112 via the equivalent internal resistance or on-resistance R. DRV Output gate control signal; the silicon carbide MOSFET 103 on the right includes the SiC MOSFET itself and parasitic capacitance (C). GS Gate-source capacitance, C GD Gate-drain capacitance (also known as Miller capacitance), C DS Drain-source capacitance), gate internal resistance R G There is also the parasitic inductance L, and D, G, and S correspond to the drain node, gate node, and source node of the silicon carbide MOSFET, respectively. When the silicon carbide MOSFET 103 is turned off, the drain voltage rises rapidly, and dv / dt generates a positive crosstalk voltage at the gate through the Miller effect of the silicon carbide MOSFET. When ΔV GS >V GS (th), the power transistor turns on again, causing oscillation, resulting in efficiency loss, and in severe cases, even device damage. Here, ΔV... GS V represents the gate-source voltage variation of a silicon carbide MOSFET. GS (th) represents the turn-on threshold voltage, which is the minimum gate-source voltage required for a silicon carbide MOSFET to switch from off to on.

[0045] Furthermore, the turn-on threshold voltage of silicon carbide MOSFETs decreases with increasing temperature. Therefore, under the influence of gate crosstalk, the risk of oscillation caused by gate crosstalk voltage increases further at high temperatures.

[0046] Currently, crosstalk suppression drive designs mainly fall into two categories: the first is adjusting the equivalent impedance between the gate and source, and the second is using a negative voltage turn-off method. However, the method of adjusting the equivalent impedance between the gate and source in silicon carbide MOSFETs comes at the cost of increased switching losses, switching delays, or increased control complexity.

[0047] Therefore, to prevent false turn-on of silicon carbide MOSFETs, negative voltage drive is a more suitable approach. However, current chip structures supporting negative voltage drive are complex, increasing chip costs.

[0048] To overcome the above-mentioned technical problems, this application provides an impulse negative charge driving circuit for suppressing crosstalk, which will be described in detail below with reference to the accompanying drawings.

[0049] Figure 2 This is a simplified structural diagram of an impulse negative charge driving circuit for suppressing crosstalk provided in one embodiment of this application. Figure 3This is a detailed structural diagram of a crosstalk suppression impulse negative charge driving circuit provided in one embodiment of this application, including: a driving module 201 and an impulse negative charge module 202; the first terminal of the driving module 201 receives an input signal, and the second terminal of the driving module 201 is connected to the gate node of the silicon carbide MOSFET, used to control the turn-on and turn-off of the silicon carbide MOSFET 203 according to the input signal; the first terminal of the impulse negative charge module 202 receives an input signal, the second terminal of the impulse negative charge module 202 is connected to the power supply terminal, the third terminal of the impulse negative charge module 202 is connected to the ground terminal, and the fourth terminal of the impulse negative charge module 202 is connected to the gate node of the silicon carbide MOSFET 203, used to release negative charge to the gate node to neutralize the Miller current when the drain voltage of the silicon carbide MOSFET 203 rises and causes the Miller current to flow back to the gate node during the turn-off process of the silicon carbide MOSFET 203.

[0050] Combination Figure 2 and Figure 3 As shown, the impact negative charge driving circuit 200 may include a driving module 201 and an impact negative charge module 202.

[0051] In some embodiments, the input terminal of the drive module 201 receives an input signal, and the output terminal is connected to the gate node G of the silicon carbide MOSFET 203, for controlling the turn-on and turn-off of the silicon carbide MOSFET 203 according to the PWM control signal; the impulse negative charge module 202 is connected to the input signal, the power supply terminal, the ground terminal and the gate node G respectively, for releasing negative charge to the gate node to neutralize the Miller current when the drain voltage of the silicon carbide MOSFET rises during the turn-off process of the silicon carbide MOSFET 203, causing the Miller current to flow back to the gate node.

[0052] Specifically, the drive module 201, serving as the main control path, typically includes a PWM generator 211, a level shifter, and a power amplifier 212. The PWM generator 211 generates PWM control signals. When the input signal is high, the corresponding PWM control signal is also high, causing the drive module 201 to rapidly raise the gate node voltage to the turn-on voltage (e.g., +18V), fully turning on the silicon carbide MOSFET 203. When the PWM control signal transitions to a low level, the drive module 201 actively pulls the gate node voltage down to the turn-off reference level (typically 0V or ground potential), forcing the device into the turn-off state. Simultaneously, the negative charge module 202, acting as a parallel auxiliary branch, pre-charges the energy storage element (e.g., a dedicated capacitor) through the power supply terminal, establishing a potential difference. During the critical transient of the turn-off process—that is, when the drain voltage of the silicon carbide MOSFET 203 begins to rise sharply and through the gate-drain capacitance (C...)... GDWhen a surge of positive Miller charge violently flows into the gate node, the module rapidly switches its internal switching unit to inject an equal amount of pre-stored negative charge from its energy storage element directly into the gate node via a low-impedance path. This negative charge instantaneously and precisely neutralizes the flowing Miller charge, effectively offsetting the abnormal gate voltage rise (ΔV) that would otherwise occur. GS Interference current. Based on the above circuit, crosstalk voltage is fundamentally suppressed by directly neutralizing the charge at the physical level, preventing the risk of mis-conduction and bridge arm shoot-through; no additional independent negative voltage power supply or complex level shifting circuit is required, simplifying the system architecture and reducing costs; and it only operates within the microsecond-level window of the turn-off transient, avoiding the static losses caused by continuous conduction, and does not affect the normal switching speed, thus improving system reliability while ensuring overall conversion efficiency.

[0053] Reference Figure 4 , Figure 4 This is a detailed structural diagram of an impact negative charge module provided in one embodiment of this application.

[0054] In one possible implementation, the impact negative charge module includes an impact capacitor, a signal receiving unit, and a switch control unit; the first terminal of the impact capacitor is connected to the gate node of the silicon carbide MOSFET; the first terminal of the signal receiving unit receives the input signal, the second terminal of the signal receiving unit is connected to the power supply terminal, the third terminal of the signal receiving unit is connected to the ground terminal, and the fourth terminal of the signal receiving unit is electrically connected to the first terminal of the switch control unit; the second terminal of the switch control unit is connected to the power supply terminal, the third terminal of the switch control unit is connected to the ground terminal, and the fourth terminal of the switch control unit is connected to the second terminal of the impact capacitor for controlling the connection state of the second terminal of the impact capacitor.

[0055] Furthermore, the switch control unit is configured to: when the input signal is at the first level, control the second terminal of the impulse capacitor to be connected to the power supply terminal to precharge the impulse capacitor, thereby establishing a precharge voltage difference between the first and second terminals of the impulse capacitor; when the input signal changes to the second level and Miller current is generated, control the second terminal of the impulse capacitor to be switched from the power supply terminal to the ground terminal.

[0056] Specifically, when the PWM control signal is high (first level), the switch control unit connects to the power supply, allowing the second terminal of the surge capacitor to be connected to the positive voltage of the power supply. This pre-charges the surge capacitor, establishing a stable voltage difference (e.g., 5V) between its upper and lower plates. At this time, the potential of the upper plate (connected to the gate node) is higher than that of the lower plate. When the PWM signal jumps to low (second level) and the drain voltage of the silicon carbide MOSFET begins to rise, at the critical moment when Miller current is generated, the switch control unit quickly disconnects the connection to the power supply and simultaneously connects to the ground, causing the second terminal of the surge capacitor to be instantaneously grounded. Since the capacitor voltage cannot change abruptly, the potential of its first terminal (gate node side) is forcibly pulled low. The charge stored in the capacitor is rapidly released to the gate node in the form of a negative current. This current is neutralized by the positive Miller current flowing back through the gate-drain capacitor, effectively clamping the rise in gate voltage. This method enables localized conversion and release of capacitor energy, achieving negative voltage shutdown without the need for an independent negative voltage power supply. This simplifies the system architecture and reduces costs. Furthermore, the charge release action is precisely synchronized with the occurrence of the Miller effect, achieving dynamic and transient interference suppression and avoiding the increased switching losses or speed reduction caused by traditional series resistor solutions.

[0057] In some embodiments, the switch control unit includes a first switch transistor and a second switch transistor, wherein the first switch transistor is a PMOS transistor and the second switch transistor is an NMOS transistor; the first switch transistor is connected between the power supply terminal and the second terminal of the surge capacitor, and the second switch transistor is connected between the ground terminal and the second terminal of the surge capacitor; when the PWM control signal is at a first level, the first switch transistor is turned on and the second switch transistor is turned off, and the second terminal of the surge capacitor is connected to the power supply terminal; when the PWM control signal is at a second level, the first switch transistor is turned off and the second switch transistor is turned on, and the second terminal of the surge capacitor is switched from the power supply terminal to the ground terminal.

[0058] Specifically, the switching control unit constructs a complementary switching path through a first switching transistor (such as a PMOS transistor) and a second switching transistor (NMOS transistor). When the PWM is high (first level), the first switching transistor is turned on and the second switching transistor is turned off. The power supply charges the second terminal of the surge capacitor through the first switching transistor, raising its potential to the power supply voltage, thereby establishing a stable voltage difference across the capacitor. When the PWM transitions to low (second level), the first switching transistor is turned off to cut off the power supply path, while the second switching transistor is turned on, forcibly pulling the second terminal of the surge capacitor to ground potential. Since the voltage across the capacitor cannot change abruptly, the potential of its first terminal (connected to the gate node) drops instantaneously, and the charge stored in the capacitor is injected into the gate node in the form of a negative transient current. This hardware configuration achieves physical isolation and rapid switching between charging and discharging paths. It can utilize the interlocking characteristics of complementary switches to avoid the risk of shoot-through between power supply and ground, thereby improving system reliability. Furthermore, it can achieve nanosecond-level response speed through direct control of hard switches, ensuring precise synchronization between negative charge release and Miller current backflow in timing. In addition, this structure only requires conventional logic signal drive and does not require additional complex level conversion, maintaining the simplicity and low cost of the overall circuit while achieving efficient neutralization.

[0059] In one possible implementation, the signal receiving unit includes a third switch and a fourth switch; the source of the third switch is connected to a power supply terminal, and the drains of both the third and fourth switches are connected to the gate of the first switch; the gate of the third switch is electrically connected to the gate of the fourth switch; and the source of the fourth switch is connected to ground.

[0060] Specifically, refer to Figure 4 The impact negative charge module includes multiple switching transistors: a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and a fourth switching transistor M4, as well as an impact capacitor C. IM Impact capacitor C IM The first terminal is connected to the gate of the silicon carbide MOSFET, and the surge capacitor C IMThe second terminal is connected to the drain of the first switch M1 and the second switch M2 respectively; the source of the first switch M1 is connected to the power supply terminal, and the gate of the first switch M1 is connected to the gate of the second switch M2; the source of the second switch M2 is connected to the ground terminal; the gates of the third switch M3 and the fourth switch M4 receive the input signal, the source of the third switch M3 is connected to the power supply terminal, the drain of the third switch M3 and the drain of the fourth switch M4 are both connected to the gates of the first switch M1 and the second switch M2, and the source of the fourth switch M4 is connected to the ground terminal; wherein, the third switch M3 and the fourth switch M4 constitute a CMOS inverter, which can realize the inversion of the input signal. When the input is high, the output is low; when the input is low, the output is high; this method has extremely low static power consumption.

[0061] In one possible implementation, the impact negative charge module further includes a timing control circuit; the input terminal of the timing control circuit is electrically connected to the drain of the third switching transistor, and the output terminal of the timing control circuit is electrically connected to the gate of the first switching transistor. After detecting that the input signal changes from the first level to the second level, a timing control signal is generated after a preset delay to control the switch control unit. The timing control signal controls the first switching transistor to turn off and the second switching transistor to turn on, so that the second terminal of the impact capacitor is switched from the power supply terminal to the ground terminal.

[0062] Specifically, the timing control circuit is triggered by the transition edge of the PWM signal (from the first level to the second level). Internally, it uses an RC delay network or a digital counter to generate a precisely settable delay time. This delay matches the time required for the drain voltage of the silicon carbide MOSFET to naturally rise to the point where a significant Miller effect is triggered after the MOSFET is turned off. After the delay, the circuit generates a steep-edge timing control signal to directly drive the switching control unit. This timing control signal ensures that the first switch does not immediately turn off after the turn-off command is issued, but only turns off rapidly at the end of the delay, and synchronously conducts through the second switch, thereby switching the connection of the second terminal of the surge capacitor from the power supply to ground. This method achieves precise synchronization between the negative charge release moment and the Miller current peak moment, avoiding the decrease in suppression effect caused by switching too early (early charge consumption) or too late (untimely suppression). It can adapt to the differences in turn-off characteristics of different types of silicon carbide MOSFETs or operating conditions by preset delay, and can transform complex physical timing judgments into programmable or tunable circuit parameters, improving the anti-interference capability of system noise and overall reliability.

[0063] Figure 5 This is a detailed structural diagram of an impulse negative charge driving circuit 300 for suppressing crosstalk provided in one embodiment of this application.

[0064] Reference Figure 5 As shown, in one possible implementation, the impact negative charge driving circuit 300 further includes a pre-charge circuit 304; the pre-charge circuit 304 is connected between the third terminal of the driving module 301 and the second terminal of the impact negative charge module 302, for supplying power to the driving module 301, and for providing a pre-charge current to the impact capacitor during the conduction of the silicon carbide MOSFET 303, so that the voltage across its terminals reaches a preset value.

[0065] The drive module 301 is the same as in the above embodiment, and may include a PWM generator 311 and a power amplifier 312. The pre-charge circuit 304 may be a low dropout linear regulator (LDO).

[0066] Specifically, the pre-charge circuit 304 typically consists of a controlled current source or a linear regulator with enable control. Its input is connected to the power supply, and its output is directly connected to the second terminal of the surge capacitor. When the system is in operation and the silicon carbide MOSFET 303 is turned on, the pre-charge circuit 304 is activated, injecting charge into the surge capacitor in a constant current manner until the voltage across the capacitor reaches a preset precise value. After charging is complete, the circuit can automatically enter a high-resistance state or a low-power monitoring mode. This method ensures that the surge capacitor is in an energy-saturated and voltage-consistent state before being turned off in each switching cycle, eliminating the problem of insufficient charge reserve caused by process deviations, thereby ensuring the stability and repeatability of the suppression effect. By actively controlling the charging current, the large current surge and power supply noise that may be caused by instantaneous charging directly connected to the power supply are avoided, improving the electromagnetic compatibility of the system. In addition, this circuit decouples the pre-charge process from the main power switch operation, allowing optimization of charging speed and accuracy according to actual needs, enhancing the adaptability of the drive circuit to changes in operating frequency and load, and further improving overall reliability.

[0067] In some embodiments, the power supply terminal is the output terminal of the pre-charge circuit 304, and the preset value is greater than the voltage value of the turn-off drive level output by the drive module 301; wherein, the turn-off drive level is the level output by the second terminal of the drive module 301, which is used to control the turn-off of the silicon carbide MOSFET 303.

[0068] Reference Figure 5As shown, the LDO is used as a dedicated power supply for pre-charging the impulse capacitor, and its output provides a stable and low-noise DC voltage (e.g., 23V). The "preset value" (e.g., 5V) here specifically refers to the precise voltage difference required across the impulse capacitor, which must be greater than the "shutdown drive level" (typically 0V or near ground) applied to the gate node by the drive module during shutdown. During the conduction of the silicon carbide MOSFET303, the LDO charges the impulse capacitor, creating a stable preset voltage difference between its upper plate (connected to the gate node) and lower plate. When the shutdown process is triggered and the lower plate of the capacitor is switched to ground, because the capacitor voltage cannot change abruptly, the potential of its upper plate will instantaneously drop by a negative voltage amplitude equal to the preset value (e.g., from 0V to -5V). By utilizing the high precision and low ripple characteristics of LDOs, this method ensures the consistency and accuracy of the pre-charge voltage each time, thereby guaranteeing the stability and repeatability of the neutralization effect. Furthermore, through the precise voltage difference design between the preset voltage difference and the turn-off level, an equivalent and precisely controllable local negative pressure environment is created without the need for an independent negative pressure power supply, achieving efficient charge neutralization.

[0069] In some embodiments, the impulse negative charge module includes multiple impulse capacitor units connected in parallel, each impulse capacitor unit including an impulse capacitor and its corresponding switching control unit; each impulse capacitor unit is configured to independently release negative charge to the gate node. Specifically, by connecting multiple independent impulse capacitor units in parallel between the power supply terminal, ground terminal, and gate node, each unit includes an independent impulse capacitor and a dedicated switching control unit, and the switching control unit of each unit can receive independent control commands from each other. During operation, the system can selectively trigger one, multiple, or all units to operate synchronously or in a time-sharing manner according to the real-time detected crosstalk intensity or a preset strategy, so that the impulse capacitors of each unit inject the negative charge stored therein into the gate node sequentially or simultaneously. The impulse capacitor unit with this structure achieves programmable and scalable suppression intensity, which can flexibly adapt to silicon carbide MOSFETs with different current levels and different parasitic parameters. By adjusting the number of units in operation, the actual required charge neutralization amount can be matched; and by triggering multiple units in a time-sharing manner, the single large current charge release process can be decomposed into several smaller current releases, reducing the impact of switching transients on the power network and improving electromagnetic compatibility.

[0070] Figure 6 This is a schematic diagram of the operation of an impact negative charge module provided in one embodiment of this application.

[0071] Reference Figure 6 When the PWM control signal is high (first level), the first switch M1 in the switch control unit conducts the path connected to the power supply terminal, causing the surge capacitor C to... IM The second terminal is connected to a positive voltage power supply, thereby impacting the surge capacitor C.IM Pre-charging is performed to establish a stable voltage difference (e.g., 5V) between the upper and lower plates, at which point the surge capacitor C is activated. IM The upper plate (connected to the gate node) has a higher potential than the lower plate; at the critical moment when the PWM signal jumps to a low level (second level) and the drain voltage of the silicon carbide MOSFET begins to rise and Miller current is generated, the first switch M1 in the switch control unit quickly disconnects the connection to the power supply and conducts the path to ground through the second switch M2, causing the surge capacitor C to... IM The second terminal is momentarily grounded. Since the capacitor voltage cannot change abruptly, the surge capacitor C... IM The potential at the first terminal (gate node side) is then forcibly pulled low, impacting the capacitor C. IM The charge stored in the gate is rapidly released to the gate node in the form of a negative current. This current neutralizes the positive Miller current flowing back through the gate-drain capacitance, thereby effectively clamping the rise in gate voltage.

[0072] Figure 7 This is a schematic diagram of the turn-off control of a silicon carbide MOSFET provided in one embodiment of this application.

[0073] Reference Figure 7 As shown, in the initial state, input signal A is high, which, after passing through the driver module, makes the voltage of gate node B high at 18V. The NMOS device is turned off, the PMOS device is turned on, and the surge capacitor C... IM The lower electrode is connected to point C of the LDO via an NMOS device, where the voltage at point C is 23V. The surge capacitor C... IM The upper plate is always connected to the gate node B. Therefore, the surge capacitor... The voltage difference between the plates at this time is =5V. Accumulated charge. for:

[0074]

[0075] At time t0, the input signal A changes from high to low, attempting to turn off the silicon carbide MOSFET. The driver module then causes the voltage at gate node B to decrease from a high level of 18V to 0V.

[0076] At time t1, the silicon carbide MOSFET is turned off, causing the voltage at the drain D to rise rapidly, which in turn increases through the gate-drain capacitance C. GDA large amount of charge flows from the drain to the gate, forming the so-called Miller current effect. Without the impulse negative charge driving circuit provided in this application, the gate voltage would be boosted again by the Miller current, and once the voltage value Vth is reached, the silicon carbide MOSFET would turn on again. However, in the impulse negative charge driving circuit provided in this application, the PMOS device is turned off, the NMOS device is turned on, and the lower plate of the impulse capacitor is grounded. In this way, the negative charge on the upper plate is directly injected into the gate node B. This negative charge neutralizes the positive charge of the Miller current, so that the charge that would otherwise flow entirely into the device R... DRV Large current (i.e., Figure 7 The red dashed line represents a drawback of existing technology, which disappears to almost zero (the effect of this application). Therefore, gate node B is still kept from generating excessively high spike voltages.

[0077] At time t2, after the transient Miller time interval impact, the stored charge is exhausted, and the voltage of gate node B remains at 0V.

[0078] The following describes the impulse negative charge driving circuit for suppressing crosstalk provided in this application through a specific embodiment.

[0079] Example 1

[0080] Based on the crosstalk suppression impulsive negative charge driving circuit provided in this application embodiment, the driving module is composed of a dedicated gate driver chip (such as UCC5350), whose input terminal receives a 100kHz PWM signal from the controller, and whose output terminal is directly connected to the gate of the silicon carbide MOSFET. The impulsive negative charge module is integrated as an external auxiliary circuit next to the driver. Its core is an impulsive capacitor with a capacitance of 1nF, whose upper plate is connected to the gate node; the lower plate is selectively connected to a 23V LDO output terminal or system ground through a complementary switching unit composed of PMOS and NMOS. The working process is as follows: When the PWM is high, the PMOS is on and the NMOS is off. The LDO charges the surge capacitor in constant current mode through a current-limiting resistor (pre-charge circuit) until the voltage difference across its terminals stabilizes at 5V. When the PWM transitions to low, the drive module quickly pulls the gate voltage down to 0V. Simultaneously, a timing control circuit composed of an RC circuit and a Schmitt trigger is triggered. After a preset delay of 40ns (matching the rise time of the silicon carbide MOSFET drain voltage), a control signal is output to turn off the PMOS and turn on the NMOS, instantly grounding the lower plate of the surge capacitor. Since the capacitor voltage cannot change abruptly, the potential of its upper plate (gate node) is forcibly pulled down by approximately 5V to -5V. At this time, the drain voltage of the silicon carbide MOSFET rises sharply, through the C... GDA large Miller current is generated and flows back to the gate. This positive charge flow and the negative charge released by the surge capacitor are precisely neutralized at the gate node, keeping the gate voltage firmly clamped below 0V and completely eliminating the risk of false turn-on. Through a localized, transient charge dynamic balancing mechanism, the inherent crosstalk problem of high-speed switching of silicon carbide MOSFETs is solved efficiently and cost-effectively without relying on an independent negative voltage power supply. Its modular design has strong compatibility, improving system reliability and preventing bridge arm shoot-through while avoiding the increased switching losses caused by traditional active clamping or increased gate resistance schemes, providing key technical support for high-frequency, high-density power supply design.

[0081] This application also provides a switching power converter, including: a switching power transistor, a control circuit, a conversion circuit, and a crosstalk suppression impulsive negative charge drive circuit provided in any embodiment of this application; the switching power transistor is a silicon carbide MOSFET; the output terminal of the impulsive negative charge drive circuit is connected to the gate of the silicon carbide MOSFET for driving the silicon carbide MOSFET; the control circuit is used to generate a PWM control signal and send it to the impulsive negative charge drive circuit; the conversion circuit is connected to the drain of the silicon carbide MOSFET for controlling the conversion of voltage or current.

[0082] In some embodiments, this switching power converter integrates a negative charge impulse drive circuit as the core drive unit into a complete power conversion system. The converter comprises: a silicon carbide MOSFET as a power switch; a control circuit for generating and regulating a pulse width modulation signal; a conversion circuit including inductors, capacitors, and possibly transformers; and the drive circuit of this application. The specific operation of this switching power converter may include: the control circuit generating a PWM signal based on output feedback and sending it to the drive circuit; the drive circuit not only performs conventional switching drive of the silicon carbide MOSFET gate, but also injects a negative charge into the gate during its turn-off transient through a built-in negative charge impulse module, precisely offsetting the interference current generated by the Miller capacitance coupling due to the drastic change in drain voltage. For example, in a 500W DC-DC module, this drive circuit enables the system to operate stably at higher switching frequencies, effectively preventing false turn-on and bridge arm shoot-through caused by crosstalk. This switching power converter inherits all the technical advantages of the drive circuit. It achieves reliable negative voltage shutdown and crosstalk suppression without the need for an independent negative voltage power supply, thereby significantly improving the power density, conversion efficiency and long-term operational reliability of the whole machine. At the same time, it has better cost control capabilities due to its simple and efficient architecture.

[0083] The foregoing has described specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0084] The computer instructions include computer program code, which may be in the form of source code, object code, executable file, or certain intermediate forms. The computer-readable medium may include any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0085] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments of this application.

[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0087] The preferred embodiments disclosed above are merely illustrative of this application. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments of this application. These embodiments are selected and specifically described in this application to better explain the principles and practical applications of the embodiments of this application, thereby enabling those skilled in the art to better understand and utilize this application. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A negative charge driving circuit for suppressing crosstalk, characterized in that, include: Drive module and impact negative charge module; The first end of the driving module receives an input signal, and the second end of the driving module is connected to the gate node of the silicon carbide MOSFET, for controlling the turn-on and turn-off of the silicon carbide MOSFET according to the input signal; The first terminal of the impact negative charge module receives an input signal, the second terminal of the impact negative charge module is connected to a power supply terminal, the third terminal of the impact negative charge module is connected to a ground terminal, and the fourth terminal of the impact negative charge module is connected to the gate node of the silicon carbide MOSFET. It is used to release negative charge to the gate node during the turn-off process of the silicon carbide MOSFET when the drain voltage of the silicon carbide MOSFET rises and causes Miller current to flow back into the gate node, so as to neutralize the Miller current. The impact negative charge module includes an impact capacitor, a signal receiving unit, and a switch control unit; The first end of the impact capacitor is connected to the gate node of the silicon carbide MOSFET; The first end of the signal receiving unit receives the input signal, the second end of the signal receiving unit is connected to the power supply terminal, the third end of the signal receiving unit is connected to the ground terminal, and the fourth end of the signal receiving unit is electrically connected to the first end of the switch control unit. The second terminal of the switch control unit is connected to the power supply terminal, the third terminal of the switch control unit is connected to the ground terminal, and the fourth terminal of the switch control unit is connected to the second terminal of the impact capacitor, which is used to control the connection state of the second terminal of the impact capacitor.

2. The impact negative charge driving circuit according to claim 1, characterized in that, The switch control unit is configured to: When the input signal is at the first level, the second end of the impact capacitor is connected to the power supply terminal to precharge the impact capacitor, thereby establishing a precharge voltage difference between the first and second ends of the impact capacitor. When the input signal changes to the second level and the Miller current is generated, the second terminal of the impulse capacitor is switched from the power supply terminal to the ground terminal.

3. The impact negative charge driving circuit according to claim 2, characterized in that, The switch control unit includes a first switch transistor and a second switch transistor; The drains of both the first and second switching transistors are connected to the second terminal of the surge capacitor; the source of the first switching transistor is connected to the power supply terminal; the gate of the first switching transistor is connected to the gate of the second switching transistor; and the source of the second switching transistor is connected to ground. When the input signal is at the first level, the first switch is turned on and the second switch is turned off, and the second end of the surge capacitor is connected to the power supply terminal. When the input signal is at the second level, the first switch is turned off and the second switch is turned on, and the second terminal of the surge capacitor is switched from the power supply terminal to the ground terminal.

4. The impact negative charge driving circuit according to claim 3, characterized in that, The signal receiving unit includes a third switch and a fourth switch; The source of the third switch is connected to the power supply terminal, and the drains of both the third and fourth switches are connected to the gate of the first switch. The gate of the third switch is electrically connected to the gate of the fourth switch. The source of the fourth switch is connected to the ground terminal.

5. The impact negative charge driving circuit according to claim 4, characterized in that, The impact negative charge module also includes a timing control circuit; The input terminal of the timing control circuit is electrically connected to the drain of the third switching transistor, and the output terminal of the timing control circuit is electrically connected to the gate of the first switching transistor. After detecting that the input signal changes from the first level to the second level, the timing control circuit generates a timing control signal for controlling the switching control unit after a preset delay. The timing control signal controls the first switching transistor to turn off and the second switching transistor to turn on, so that the second terminal of the surge capacitor is switched from the power supply terminal to the ground terminal.

6. The impact negative charge driving circuit according to claim 1, characterized in that, The impact negative charge driving circuit also includes a pre-charging circuit; The pre-charging circuit is connected between the third terminal of the drive module and the second terminal of the impact negative charge module. It is used to power the drive module and to provide a pre-charging current to the impact capacitor during the conduction of the silicon carbide MOSFET, so that the voltage across its terminals reaches a preset value.

7. The impact negative charge driving circuit according to claim 6, characterized in that, The power supply terminal is the output terminal of the pre-charge circuit, and the preset value is greater than the voltage value of the turn-off drive level output by the drive module; wherein, the turn-off drive level is the level output by the second terminal of the drive module, which is used to control the turn-off of the silicon carbide MOSFET.

8. The impact negative charge driving circuit according to claim 1, characterized in that, The impact negative charge module includes multiple impact capacitor units connected in parallel, each impact capacitor unit including an impact capacitor and its corresponding switch control unit; each impact capacitor unit is configured to independently release negative charge to the gate node.

9. A switching power supply converter, characterized in that, include: The switching power transistor, the control circuit, the conversion circuit, and the impulse negative charge driving circuit for suppressing crosstalk as described in any one of claims 1-8; The switching power transistor is a silicon carbide MOSFET; The output terminal of the impact negative charge driving circuit is connected to the gate of the silicon carbide MOSFET and is used to drive the silicon carbide MOSFET. The control circuit is used to generate a PWM control signal and send it to the impact negative charge drive circuit; The conversion circuit is connected to the drain of the silicon carbide MOSFET and is used to control the conversion of voltage or current.

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