Input rail-to-rail high-impedance instrumentation amplifier with synchronous chopped wave and dynamic element matching

Abstract

The invention provides an input rail-to-rail high-impedance instrument amplifier with synchronous matching of chopping waves and dynamic elements, which adopts an AC coupling ripple suppression loop to be combined with a constant gain rail-to-rail input transconductance architecture based on common-mode detection, and is based on a synchronous SCPS method of the chopping waves and the dynamic elements. The influence of dynamic resistance of a switch on input impedance is reduced by synchronously controlling switching logic of a chopping switch and a dynamic element, and meanwhile, an alternating current coupling ripple suppression loop RRL is adopted to realize effective suppression of ripple voltage by offsetting offset current generated by input transconductance and feedback transconductance; rail-to-rail input and constant transconductance are achieved through constant-gain rail-to-rail input transconductance based on common-mode detection, so that the amplification precision is guaranteed; the invention provides an innovative architecture of an alternating current coupling ripple suppression loop and a common-mode detection-based constant gain rail-to-rail input transconductance, and by combining an SCPS technology, the design of an input rail-to-rail high-impedance instrumentation amplifier with synchronous matching of chopped waves and dynamic elements can be realized.

Description

Technical Field

[0001] This invention relates to the field of electronic instrumentation technology, and in particular to an input rail-to-rail high impedance instrumentation amplifier that synchronizes chopper and dynamic element matching. Background Technology

[0002] Instrumentation amplifiers (IAs) are core components in high-precision signal sensing fields such as temperature and bioelectricity, and their performance directly determines the fidelity of signal acquisition. Regarding the core requirements of low noise and low offset, existing technical solutions suffer from the following key bottlenecks:

[0003] (1) Limitations of input impedance in chopper technology: Traditional chopper technology can effectively reduce offset voltage and low-frequency noise interference by separating the signal from the low-frequency noise offset voltage through modulation-demodulation. However, the periodic switching of the input stage chopper switch introduces dynamic resistance, which forms a parallel equivalent impedance with the input signal path, causing a significant decrease in the input impedance of the IA. Although dynamic element matching technology is used to set the chopper frequency to an integer multiple of the dynamic element matching frequency to optimize the gain error, its input impedance improvement effect is limited to doubling the original level. There is an order of magnitude difference between this and the GΩ-level input impedance required by high-impedance signal sources such as biosensors, resulting in impedance mismatch between the signal source and the amplifier, causing signal attenuation and distortion, and failing to meet the impedance matching requirements of high-precision signal acquisition.

[0004] (2) Ripple Suppression Challenges of SCPS Technology: Synchronous Chopping and Port Swapping (SCPS) technology can significantly improve input impedance, but it is necessary to suppress the output ripple of the IA. Traditional solutions suppress ripple by embedding filters in the signal path; however, this solution has the following drawbacks: 1) During the sampling stage of the filter, noise folding is introduced due to the discretization of the signal, causing low-frequency noise to be modulated into the signal bandwidth. 2) Phase shift is introduced at the chopping frequency. When this solution is applied to a closed-loop feedback system, the phase shift superposition will reduce the system phase margin, easily causing self-excited oscillation and circuit instability, requiring additional complex frequency compensation networks. 3) It is difficult to align the chopping frequency, requiring additional complex circuitry to keep the notch filter frequency consistent with the chopping frequency; otherwise, the ripple suppression effect will be reduced.

[0005] Existing technologies cannot simultaneously meet the comprehensive performance requirements of instrumentation amplifiers (IAs) for low noise, low offset, high input impedance, and stable ripple suppression. Therefore, this invention proposes a novel input rail-to-rail high-impedance instrumentation amplifier using chopper and dynamic component matching synchronization technology. It employs an AC-coupled ripple suppression loop to replace the filter to meet the ripple suppression requirements of the chopper and dynamic component matching synchronization technology, thus simultaneously satisfying the IA performance requirements of low noise, low offset, and high input impedance. Furthermore, to expand the input range of the IA and broaden its application scenarios, a constant-gain rail-to-rail input transconductance based on common-mode detection is introduced as both the input and feedback stages of the IA. Summary of the Invention

[0006] This invention proposes an input rail-to-rail high-impedance instrumentation amplifier with synchronized chopping and dynamic component matching. Addressing the core deficiencies of existing technologies, it proposes an innovative architecture of "AC coupling ripple suppression loop + constant gain rail-to-rail input transconductance based on common-mode detection". Relying on the RRL loop to meet the ripple suppression requirements of SCPS, and using the Const_GM unit to achieve rail-to-rail input and constant amplification accuracy, it is possible to design an input rail-to-rail high-impedance instrumentation amplifier with synchronized chopping and dynamic component matching.

[0007] The present invention adopts the following technical solution.

[0008] A rail-to-rail high-impedance instrumentation amplifier (IA) with chopper and dynamic element matching synchronization is disclosed. The instrumentation amplifier IA employs an AC-coupled ripple suppression loop (RRL) combined with a constant-gain rail-to-rail input transconductance based on common-mode detection. SCPS technology is used to achieve rail-to-rail input matching synchronization between chopper and dynamic element. In this architecture, based on the chopper and dynamic element matching synchronization SCPS method, the switching logic of the chopper switch and dynamic element is synchronously controlled to reduce the impact of the switching dynamic resistance on the input impedance, increasing the input impedance of IA to the GΩ level to meet the impedance matching requirements of high-impedance signal sources. Simultaneously, an AC-coupled ripple suppression loop (RRL) replaces the traditional filter, effectively suppressing ripple voltage by canceling the offset current generated by the input transconductance and feedback transconductance without introducing additional noise. Furthermore, constant-gain rail-to-rail input transconductances GM1 and GM2 based on common-mode detection are used to achieve rail-to-rail input and constant transconductance, ensuring amplification accuracy.

[0009] The AC-coupled ripple suppression loop of the described architecture has the following advantages: 1) It operates in continuous mode, eliminating the need for an additional sample-and-hold module, thus reducing chip area and power consumption. Furthermore, the absence of a sampling process eliminates folding noise. 2) The ripple suppression effect is determined by the AC-coupled ripple suppression loop itself, requiring no alignment with the chopping frequency. Therefore, no additional complex circuitry is needed to maintain the notch filter frequency consistent with the chopping frequency, ensuring the desired ripple suppression effect. 3) By reducing the bandwidth of the AC-coupled ripple suppression loop to less than 1 / 10 of the chopping frequency, the loop effectively filters only the ripple frequency components. Simultaneously, the transconductance value of the transconductance unit in the loop is reduced. Based on the positive correlation between transconductance and noise density, the loop's own noise contribution is reduced, ultimately enhancing the ripple suppression effect while avoiding additional interference to the original circuit's noise performance. 4) It does not introduce a phase shift at the chopping frequency. When used in instrumentation amplifiers employing chopping and dynamic component matching synchronization technology, this AC-coupled ripple suppression loop will not affect circuit stability, reducing the difficulty of frequency stability compensation.

[0010] The architecture described above employs a complementary structure of parallel NMOS differential pairs and PMOS differential pairs operating in the subthreshold region, based on common-mode detection and constant-gain rail-to-rail input transconductance. Simultaneously, its bias circuit utilizes constant transconductance technology to achieve GNDA+V. thn To VDDA-|V thp | Input track to track range, where V thn V thp These are the threshold voltages for NMOS and PMOS, respectively.

[0011] The concept and structure of the input rail-to-rail high impedance instrumentation amplifier include the following circuit modules: chopper and dynamic element matching synchronous switch module SCPS, AC coupling ripple suppression loop RRL, input transconductance GM1, feedback transconductance GM2, impedance stage GM_R, output stage GM3, chopper switch CH2, and Miller compensation capacitor C. 1a Miller compensation capacitor C 1b and a resistor voltage divider feedback network.

[0012] The signal input of the rail-to-rail high impedance instrumentation amplifier is as follows: after the external differential signals VIN and VIP are connected, they are modulated into high-frequency signals by the SCPS switching module. This signal is input to the input transconductance GM1, and GM1 converts it into the corresponding current signal.

[0013] The signal amplification and output of the rail-to-rail high-impedance instrumentation amplifier are as follows: GM2 provides feedback transconductance, GM_R converts the current signal into a voltage signal, the Class AB structure GM3 output stage enhances the load-driving capability, and Miller compensation capacitor C... 1a Miller compensation capacitor C 1bTo ensure system stability, the overall gain of the IA is set by a resistor voltage divider feedback network.

[0014] The ripple suppression of the input rail-to-rail high impedance instrumentation amplifier is specifically achieved by: generating a compensation current I in the RRL loop. RRL To offset the offset current I output from GM1 and GM2 GM1 I GM2 To reduce ripple voltage, the Const_GM unit provides a constant transconductance bias for GM1 and GM2, thereby achieving rail-to-rail input range.

[0015] In the input rail-to-rail high impedance instrumentation amplifier, its chopper and dynamic element matching synchronous chopper switching module, through the switching logic of synchronous chopper and dynamic element matching, significantly reduces the impact of the switching dynamic impedance on the input impedance, raising the input impedance to the GΩ level, achieving a high impedance target that is difficult to achieve with existing technologies.

[0016] In the input rail-to-rail high-impedance instrumentation amplifier, its AC coupling ripple suppression loop RRL is one of the core innovations that replaces traditional filters to meet the ripple suppression requirements of SCPS. Its specific circuit connection is as follows: RRL consists of a sensing capacitor C... 3a and C 3b Chopper CH3, RRL_CB cascode buffer, C int Composed of integrating capacitor and RRL_GM for transconductance compensation; power node VDDA is M 2a M 2b M 5a and M 5b The source provides a positive power supply voltage; the output node OUT_AA is connected to M. 2a The drain, OUT_BB is connected to M. 1a The drain and OUT_CC are connected to M. 2b The drain and OUT_DD are also connected to M. 1b The drain; the input node IN+ is connected to C. 3a Coupled to M 8a The drain and input node IN- are connected via C. 3b Coupled to M 8b The drain; common-mode feedback node V CMFB Connect M 8a,b The gate;

[0017] Where M 1a With M 1b M 2a With M 2b This forms a differential input pair, and the bias voltage also controls M. 5a,b The gate potential of M6 is set, and the chopper switch CH1 is connected between the input and M6. 7a,bSignal modulation is achieved between the drain nodes, and the chopper switch CH2 is connected to M. 5a,b Drain and M 6a,b Signal modulation is achieved between source nodes; C int It is an integrating capacitor, one end of which is coupled to M. 7a The source is coupled to M at the other end. 7b Source pole;

[0018] The specific working method of the AC coupling ripple suppression loop (RRL) circuit is as follows: The RRL first passes through C... 3a,b The ripple is converted into a current with a chopping frequency, which, after passing through CH3, is demodulated into a DC current I. CH3 I CH3 In C int Integrating the result yields the corresponding voltage, the final value of which is I. CH3 ×R RRL_CB , where R RRL_CB For RRL_CB in C int The output impedance is measured; ultimately, this voltage is converted to I through the transconductance circuit RRL_GM. RRL ;

[0019] According to Kirchhoff's current law, the offset current I output by GM1 and GM2 GM1 I GM2 The sum of (I) GM1 +I GM2 The compensation current I generated by the RRL loop RRL The current I is obtained by canceling out the negative feedback. CH2 I CH2 After being chopped by CH2, C1 is charged and discharged. Combining parameters such as chopping frequency fch and capacitance value, the reduced ripple voltage is derived as shown in Formula 1 below.

[0020] Formula 1;

[0021] Where f ch R is the chopping frequency. RRL_CB G is the output impedance of RRL_CB. RRL_GM C is the transconductance of RRL_GM, and C3 is the sensing capacitance C. 3a,b The capacitance value is C1, where C1 is the capacitance value of capacitor C1;

[0022] The output of IA is VOUT=V ripple +VOP-VON; Chopper ripples superimposed on the IA output VOUT. ripple The offset voltages, primarily originating from GM1 and GM2, are converted into offset currents via transconductance before passing through the RRL. The chopper then chops this current, and the chopped current, within one chopping cycle, affects the compensation capacitor C. 1a C1b Perform charging and discharging.

[0023] The ripple voltage without RRL is ,

[0024] Where T ch For the chopping period, RRL reduces the chopping ripple. times;

[0025] To suppress the impact of chopper ripple on the output signal VOUT, the RRL bandwidth needs to be less than 1 / 10 of the chopper frequency, therefore C int It is set to several pF to reduce the GBW of the RRL to several hundred Hz, thereby filtering the output signal modulated by CH1; at the same time, to avoid the RRL itself introducing additional noise (especially M) 1a,b M 2a,b The 1 / f noise, after being modulated twice by chopping, will affect the amplifier's low-frequency noise performance. Parameter optimization is needed to balance noise suppression and ripple suppression capabilities; reducing M... 1a,b M 2a,b Transconductance can effectively reduce the noise of the RRL itself, thereby reducing its impact on the original circuit. However, reducing G... M1，2 At the same time, the ripple suppression capability of RRL decreases. Therefore, M 1a,b The same constant gain bias circuit as GM1 is used to bias it. By setting the current values ​​of the two tail currents at the input terminal, it is ensured that GM1 outputs sufficient compensation current while reducing its transconductance, thereby reducing the noise contribution of RRL to IA. In summary, by reducing the RRL bandwidth, increasing the output impedance of RRL_CB, and reducing the transconductance of RRL_GM, the impact on the noise performance of the original circuit can be reduced while effectively suppressing ripple.

[0026] In the rail-to-rail high-impedance instrumentation amplifier, one of the core innovations is the constant gain rail-to-rail input transconductance GM1 and feedback transconductance GM2 based on common-mode detection. This extends the IA input range to rail-to-rail operation. Specifically, it employs parallel NMOS and PMOS differential pairs. The NMOS differential pairs are adapted for low common-mode voltages, while the PMOS differential pairs are adapted for high common-mode voltages. The NMOS transistors have their sources connected to a low potential, and conduction requires the gate-source voltage VGS to be close to the threshold voltage. When the input common-mode voltage approaches GNDA+V... thn When the voltage difference between the gate and source of the NMOS meets the conduction requirements, it operates normally.

[0027] For a PMOS transistor to turn on with its source connected to a high potential, the source-gate voltage VSG must be slightly lower than the threshold voltage. When the input common-mode voltage is close to VDDA-|V thp At that time, the voltage difference between the PMOS source and gate meets the conduction requirements;

[0028] The NMOS differential pair operating in the low common-mode voltage range and the PMOS differential pair operating in the high common-mode voltage range complement each other, and the two work together to achieve GNDA+V. thn To VDDA-|V thp | Rail-to-rail input voltage range;

[0029] The Const_GM module senses the input common-mode voltage level in real time through the common-mode detection unit. When the input common-mode voltage is in the low range, it increases the tail current ratio of the NMOS differential pair.

[0030] When the input common-mode voltage is in the high range, the tail current ratio of the PMOS differential pair is increased to keep the total tail current of the NMOS and PMOS differential pairs constant. Based on the linear relationship between the transconductance and leakage current of the MOS transistor in the subthreshold region, the total transconductance of the differential pair is kept constant in the rail-to-rail input range.

[0031] The specific circuit and connection relationships of the amplifier transconductance section include the constant transconductance unit Const_GM, signal transconductance units GM1 and GM2; the structure of the constant transconductance bias unit Const_GM is as follows: the source of the PMOS transistor M5 is connected to the power supply VDDA, the gate is connected to the bias voltage Vbias, and the drain is the internal current mirror (M). 6a,b —M 9a,b Provides bias;

[0032] The input stage for common-mode detection contains two differential pairs: transistor M 12a M 13a The gate is connected to the positive input VIP, M 12a M 13b The gate is connected to the inverting input VIN; the final output common-mode nodes are VCP and VCN.

[0033] Transconductance GM1 and GM2 adopt the same symmetrical structure: each cell contains a PMOS cascode pair M. 1a M 1b M 2a M 2b NMOS input pair M 1a M 1b The gates are connected to VIP and VIN respectively, and the source is connected to the drain of the tail current source M4 controlled by VCN. The drain is connected to the output terminal of the common-source common-gate load, outputting AA and CC; the PMOS input is connected to M... 2a M 2b The gates are connected to VIP and VIN respectively, the source is connected to the drain of the tail current source M3 controlled by VCP, and the drain is connected to the output terminals of the common source cascode load to output BB and DD.

[0034] The specific operating method of the input transconductance GM1 and feedback transconductance GM2 is as follows: both input transconductance GM1 and feedback transconductance GM2 adopt a complementary structure of parallel NMOS differential pairs and PMOS differential pairs operating in the subthreshold region; at the same time, the bias circuits of GM1 and GM2 use a constant transconductance method to achieve the bias of GM1 and GM2 at GNDA+V. thn To VDDA-|V thp | Remains constant within the range, where V thn V thp These are the threshold voltages for NMOS and PMOS, respectively;

[0035] When the gate-source voltage of a MOSFET is close to its threshold voltage (slightly below the threshold voltage), the drain current formula for a MOSFET operating in the subthreshold region is as shown in Formula 2 below; Formula 3 is obtained by differentiating Formula 2; the input consists of NMOS differential pairs and PMOS differential pairs connected in parallel, therefore, the input transconductance is the transconductance g of the NMOS. mn and the transconductance g of PMOS mp The sum of these two values ​​yields the following formula 4;

[0036] Formula 2;

[0037] Formula 3;

[0038] Formula 4;

[0039] Where V TH V is the threshold voltage of the MOS. T Assuming thermal voltage, according to Equation 4, the transconductance and leakage current of a MOSFET operating in the subthreshold region are linearly related. Therefore, as long as the total current of the input pair remains constant, the total input transconductance remains unchanged. 12a M 12b M 13a M 13b Four input transistor pairs are used to detect the input common-mode voltage and perform I / O based on VIN and VIP. N_ctrl and I P_ctrl The current distribution is such that the current in the two branches is replicated to the tail current source in a certain proportion, so that the tail current I... N_ctrl and I P_ctrl The sum is always a constant; since gm is linearly related to the sum of currents, it remains unchanged in the common-mode range, as shown in Formula 4, so that the transconductance of GM1 and GM2 remains constant in the rail-to-rail input range.

[0040] Instrumentation amplifiers (IAs) are used in scenarios involving the measurement and amplification of high-impedance, weak signal sources, including temperature signals from thermocouples, bioelectrical signals such as electrocardiograms (ECG) and electroencephalograms (EEG), and weak current signals from photodetectors. Furthermore, by employing constant gain rail-to-rail input transconductance based on common-mode detection, IAs can be adapted to GNDA+V. thn To VDDA-|V thp The common-mode voltage input scenario expands the application scenarios of the IA (Integrated Instrumentation Amplifier). Specific applications include thermobridge applications, front-end amplifiers for high-precision digital-to-analog converters, and medical devices such as electrocardiographs, blood pressure monitors, and vital sign monitors. It can serve as a general-purpose circuit in integrated circuits, compatible with various integrated circuit platforms such as Cadence, PSpice, and Hspice. Input chopper switches can be designed in chopper instrumentation amplifiers on various platforms, thereby optimizing the input impedance and chopper ripple noise of the chopper instrument. The impedance GM_R adopts a folded cascode structure. The output stage GM3 adopts a Class AB structure to extend the output voltage range and improve load capacity. Miller compensation is used between the input and output stages to ensure the overall stability of the IA.

[0041] The method of using an instrumentation amplifier includes the following steps;

[0042] Step 1, Signal Input: Connect the pre-processed differential signals such as temperature and bioelectricity to the differential input terminals (VIN, VIP) of the IA; the common-mode voltage of the pre-processed signal must be controlled within GNDA+V. thn To VDDA-|V thp Within the interval, ensure that the input transconductances GM1 and GM2 always operate in a constant transconductance state;

[0043] Step 2, Impedance Boost and Signal Modulation: The synchronous clock signal controls the periodic switching of chopper switches CH1a and CH1b to modulate the input signal; during this process, SCPS technology will cancel the influence of the switch dynamic resistance on the input impedance, so that the IA input impedance reaches the GΩ level.

[0044] Step 3, Signal Amplification and Output: The impedance stage GM_R converts the processed current signal into a voltage signal and transmits it to the output stage GM3; Miller compensation capacitor (C) 1a,b To ensure system stability, the gain of the resistor feedback network is set, ultimately outputting a stable and amplified signal.

[0045] Step 4, Ripple Suppression: The RRL loop generates a compensation current through negative feedback to offset the offset current output by GM1 and GM2, thereby reducing ripple;

[0046] Step 5, Transconductance Constant Control: The input common-mode voltage is detected by the common-mode detection unit Const_GM, and I is allocated accordingly. N_ctrl with I P_ctrlThe signal controls the tail current of the input transconductance, maintaining a constant transconductance within the rail-to-rail input range.

[0047] The advantages of this invention are:

[0048] (1) The AC-coupled ripple suppression loop (RRL) replaces the traditional filter, giving the instrumentation amplifier (IA) the following advantages: 1) Low circuit complexity. The AC-coupled ripple suppression loop does not require frequency alignment or additional calibration circuits. Compared with the traditional filter scheme used in SCPS, the AC-coupled ripple suppression loop of this invention greatly simplifies the circuit design. It reduces chip area and power consumption, improving the product's cost-effectiveness. 2) Low noise. The AC-coupled ripple suppression loop enhances the ripple suppression effect without introducing additional noise through parameter optimization, ensuring the original low noise characteristics of the instrumentation amplifier, achieving dual optimization of ripple and noise, and meeting the stringent requirements of high-precision signal amplification. 3) Optimized ripple suppression. The ripple suppression effect of the AC-coupled ripple suppression loop is determined by the loop characteristics. It does not require frequency alignment or additional calibration circuits, avoiding the performance degradation caused by frequency offset in traditional notch filters. It can work stably under different operating conditions, solving the hidden danger of unstable ripple suppression effect in traditional schemes.

[0049] (2) Wide input range. The constant gain rail-to-rail input transconductance based on common-mode detection achieves GNDA+V thn To VDDA-|V thp |The rail-to-rail input range.

[0050] (3) Overall performance synergistic optimization. SCPS technology breaks through the bottleneck of input impedance improvement through synchronous switching logic, laying the foundation for high impedance signal acquisition; RRL technology replaces the filter in the traditional SCPS technology scheme, suppressing ripple while avoiding the introduction of additional noise and stability problems; the two, together with the constant gain rail-to-rail input transconductance based on common-mode detection, enable IA to achieve GΩ-level input impedance while having low ripple, low noise characteristics and rail-to-rail input capability. SCPS technology solves the core problem of input impedance improvement, while the RRL loop specifically meets the ripple suppression requirements brought by SCPS technology, and the Const_GM unit ensures the amplification accuracy within the rail-to-rail input range through constant transconductance control. The three form a synergistically optimized overall architecture.

[0051] This invention is an innovation in high-precision instrumentation amplifiers with chopper and dynamic element matching synchronization, applicable to a wide range of precision signal amplification and monitoring fields. While retaining the high input impedance advantages of high-precision instrumentation amplifiers with chopper and dynamic element matching synchronization, this invention optimizes noise and chopper ripple, making it suitable for measuring and amplifying high-impedance weak signal sources, including temperature signals from thermocouples, bioelectrical signals such as electrocardiograms (ECG) and electroencephalograms (EEG), and weak current signals from photodetectors. Furthermore, by employing constant gain rail-to-rail input transconductance based on common-mode detection, the IA (Instrumentation Amplifier) ​​can be adapted to GNDA+V (Glass Array of GNDAs). thn To VDDA-|V thp The common-mode voltage input scenario expands the application scenarios of analog-to-analog converters (IA). Specific applications include thermobridge applications, front-end amplifiers for high-precision digital-to-analog converters, and medical equipment such as electrocardiographs, blood pressure monitors, and vital sign monitors.

[0052] This invention relates to an input rail-to-rail high-impedance instrumentation amplifier that synchronizes chopping and dynamic component matching. Its core innovation lies in the synergistic architecture of "SCPS technology + AC coupling ripple suppression loop (RRL) + constant gain rail-to-rail input transconductance based on common-mode detection (GM1, GM2)": SCPS technology overcomes the input impedance bottleneck of traditional chopping techniques, achieving GΩ-level input impedance; RRL replaces traditional filters, achieving stable ripple suppression without noise folding or frequency alignment requirements; and constant gain rail-to-rail input transconductance based on common-mode detection achieves GNDA+V. thn To VDDA-|V thp | Rail-to-rail input range. This invention avoids the ripple suppression defects of traditional filters and simultaneously features high input impedance, low ripple, and GNDA+V. thn To VDDA-|V thp With its rail-to-rail input range, it can be widely used in high-precision signal sensing fields such as temperature and biological sensors.

[0053] This invention, as a general-purpose circuit in integrated circuits, is compatible with multiple integrated circuit platforms such as Cadence, PSpice, and Hspice. It can be used to design input chopper switches in chopper instrumentation amplifiers on various platforms, thereby optimizing the input impedance and chopper ripple noise of the chopper instrument. Attached Figure Description

[0054] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0055] Appendix Figure 1 This is a schematic diagram of a high-precision instrumentation amplifier architecture with novel chopper and dynamic component matching synchronization in an embodiment of the present invention;

[0056] Appendix Figure 2This is a schematic diagram of the specific circuit of the RRL AC coupling ripple suppression loop in an embodiment of the present invention;

[0057] Appendix Figure 3 This is a schematic diagram of the specific circuit of the input stage GM1 and the feedback stage GM2 and their constant gain bias in an embodiment of the present invention. Detailed Implementation

[0058] This example addresses the core shortcomings of existing technologies by proposing an innovative architecture of "AC-coupled ripple suppression loop + constant gain rail-to-rail input transconductance based on common-mode detection." Combined with SCPS technology, it achieves a rail-to-rail high-impedance instrumentation amplifier with synchronized chopper and dynamic element matching. The specific technical solutions are as follows: 1) Based on the synchronized chopper and dynamic element matching (SCPS) technology, the switching logic of the chopper switch and dynamic element is synchronously controlled to reduce the impact of the switch dynamic resistance on the input impedance, increasing the input impedance of the IA to the GΩ level to meet the impedance matching requirements of high-impedance signal sources. 2) An AC-coupled ripple suppression loop (RRL) replaces the traditional filter. This loop effectively suppresses ripple voltage by canceling the offset current generated by the input transconductance and feedback transconductance without introducing additional noise. 3) A constant gain rail-to-rail input transconductance (GM1, GM2) based on common-mode detection achieves rail-to-rail input and constant transconductance, ensuring amplification accuracy.

[0059] like Figure 1 As shown, an input rail-to-rail high-impedance instrumentation amplifier (IA) with chopper and dynamic element matching synchronization is described. The instrumentation amplifier IA employs an AC-coupled ripple suppression loop (RRL) combined with a constant-gain rail-to-rail input transconductance based on common-mode detection. SCPS technology is used to achieve synchronized input rail-to-rail chopper and dynamic element matching. In this architecture, based on the SCPS method, the switching logic of the chopper switch and dynamic element is synchronously controlled to reduce the impact of the switching dynamic resistance on the input impedance, increasing the input impedance of IA to the GΩ level to meet the impedance matching requirements of high-impedance signal sources. Simultaneously, an AC-coupled ripple suppression loop (RRL) replaces the traditional filter, effectively suppressing ripple voltage by canceling the offset current generated by the input transconductance and feedback transconductance without introducing additional noise. Furthermore, constant-gain rail-to-rail input transconductances GM1 and GM2 based on common-mode detection are used to achieve rail-to-rail input and constant transconductance, ensuring amplification accuracy.

[0060] The AC-coupled ripple suppression loop of the described architecture has the following advantages: 1) This AC-coupled ripple suppression loop operates in continuous mode, eliminating the need for a sample-and-hold module. This saves on additional signal paths, reduces chip area and power consumption, and avoids folding noise due to the absence of a sampling process. 2) The ripple suppression effect is determined by the AC-coupled ripple suppression loop itself. It does not require alignment with the chopping frequency, thus eliminating the need for additional complex circuitry to maintain the notch filter frequency consistent with the chopping frequency, ensuring the required ripple suppression effect. 3) By reducing the bandwidth of the AC-coupled ripple suppression loop to a level far below the chopping frequency, the loop effectively filters only the ripple frequency components. Simultaneously, by reducing the transconductance value of the transconductance unit in the loop, and based on the positive correlation between transconductance and noise density, the loop's own noise contribution is reduced. Ultimately, while enhancing the ripple suppression effect, it avoids additional interference to the original circuit's noise performance. 4) Since it does not introduce a phase shift at the chopping frequency, this AC-coupled ripple suppression loop will not affect the stability of the circuit when used in instrumentation amplifiers with chopping and dynamic component matching synchronization technology, reducing the difficulty of frequency stability compensation.

[0061] The architecture described above employs a complementary structure of parallel NMOS differential pairs and PMOS differential pairs operating in the subthreshold region, based on common-mode detection and constant-gain rail-to-rail input transconductance. Simultaneously, its bias circuit utilizes constant transconductance technology to achieve GNDA+V. thn To VDDA-|V thp | Input track to track range, where V thn V thp These are the threshold voltages for NMOS and PMOS, respectively.

[0062] The concept and structure of an input rail-to-rail high impedance instrumentation amplifier are as follows: Figure 1 As shown, the circuit module includes: a chopper and dynamic element matching synchronous switch module SCPS, an AC coupling ripple suppression loop RRL, an input transconductance GM1, a feedback transconductance GM2, an impedance stage GM_R, an output stage GM3, a chopper switch CH2, and a Miller compensation capacitor C. 1a Miller compensation capacitor C 1b and a resistor voltage divider feedback network.

[0063] The signal input to the rail-to-rail high impedance instrumentation amplifier is as follows: external signals VIN and VIP are modulated by the SCPS switching module and then input to GM1. GM1 converts the voltage signal into a current signal.

[0064] The signal amplification and output of the rail-to-rail high-impedance instrumentation amplifier are as follows: GM2 provides feedback transconductance, GM_R converts the current signal into a voltage signal, the Class AB structure GM3 output stage enhances the load-driving capability, and Miller compensation capacitor C... 1a Miller compensation capacitor C 1bTo ensure system stability, the overall gain of the IA is set by a resistor voltage divider feedback network.

[0065] The ripple suppression of the input rail-to-rail high impedance instrumentation amplifier is specifically achieved by: generating a compensation current I in the RRL loop. RRL To offset the offset current I output from GM1 and GM2 GM1 I GM2 To reduce ripple voltage, the Const_GM unit provides a constant transconductance bias for GM1 and GM2, thereby achieving rail-to-rail input range.

[0066] In the input rail-to-rail high impedance instrumentation amplifier, its chopper and dynamic element matching synchronous chopper switching module, through the switching logic of synchronous chopper and dynamic element matching, significantly reduces the impact of the switching dynamic impedance on the input impedance, raising the input impedance to the GΩ level, achieving a high impedance target that is difficult to achieve with existing technologies.

[0067] In the input rail-to-rail high-impedance instrumentation amplifier, the AC coupling ripple suppression loop (RRL) is one of the core innovations that replaces traditional filters to meet the ripple suppression requirements of the SCPS. Its specific circuit connection is as follows: Figure 2 As shown. RRL is caused by the sensing capacitance C. 3a and C 3b Chopper CH3, RRL_CB cascode buffer, C int Composed of integrating capacitor and RRL_GM for transconductance compensation; power node VDDA is M 2a M 2b M 5a and M 5b The source provides a positive power supply voltage; the output node OUT_AA is connected to M. 2a The drain, OUT_BB is connected to M. 1a The drain and OUT_CC are connected to M. 2b The drain and OUT_DD are also connected to M. 1b The drain; the input node IN+ is connected to C. 3a Coupled to M 8a The drain and input node IN- are connected via C. 3b Coupled to M 8b The drain; common-mode feedback node V CMFB Connect M 8a,b The gate;

[0068] Where M 1a With M 1b M 2a With M 2b This forms a differential input pair, and the bias voltage also controls M. 5a,b The gate potential of M6 is set, and the chopper switch CH1 is connected between the input and M6. 7a,bSignal modulation is achieved between the drain nodes, and the chopper switch CH2 is connected to M. 5a,b Drain and M 6a,b Signal modulation is achieved between source nodes; C int It is an integrating capacitor, one end of which is coupled to M. 7a The source is coupled to M at the other end. 7b Source pole;

[0069] The specific working method of the AC coupling ripple suppression loop (RRL) circuit is as follows: The RRL first passes through C... 3a,b The ripple is converted into a current with a chopping frequency, which, after passing through CH3, is demodulated into a DC current I. CH3 I CH3 In C int Integrating the result yields the corresponding voltage, the final value of which is I. CH3 ×R RRL_CB , where R RRL_CB For RRL_CB in C int The output impedance is on; this voltage is converted to I via RRL_GM. RRL ;

[0070] According to Kirchhoff's current law, the offset current I output by GM1 and GM2 GM1 I GM2 The sum of (I) GM1 +I GM2 The compensation current I generated by the RRL loop RRL The current I is obtained by canceling out the negative feedback. CH2 I CH2 After being chopped by CH2, C1 is charged and discharged. Combining parameters such as chopping frequency fch and capacitance value, the reduced ripple voltage is derived as shown in Formula 1 below.

[0071] Formula 1;

[0072] Where f ch R is the chopping frequency. RRL_CB G is the output impedance of RRL_CB. RRL_GM C is the transconductance of RRL_GM, and C3 is the sensing capacitance C. 3a,b The capacitance value is C1, where C1 is the capacitance value of capacitor C1;

[0073] like Figure 1 As shown, the output of IA is VOUT=V ripple +VOP-VON; Chopper ripples superimposed on the IA output VOUT. ripple The offset voltages, primarily originating from GM1 and GM2, are converted into offset currents via transconductance before passing through the RRL. The chopper then chops this current, and the chopped current, within one chopping cycle, affects the compensation capacitor C.1a C 1b Perform charging and discharging.

[0074] The ripple voltage without RRL is ,

[0075] Where T ch For the chopping period, RRL reduces the chopping ripple. times;

[0076] To suppress the impact of chopper ripple on the output signal VOUT, the RRL bandwidth needs to be less than 1 / 10 of the chopper frequency, therefore C int It is set to several pF to reduce the GBW of the RRL to several hundred Hz, thereby filtering the output signal modulated by CH1; at the same time, to avoid the RRL itself introducing additional noise (especially M) 1a,b M 2a,b The 1 / f noise, after being modulated twice by chopping, will affect the amplifier's low-frequency noise performance. Parameter optimization is needed to balance noise suppression and ripple suppression capabilities; reducing M... 1a,b M 2a,b Transconductance can effectively reduce the noise of the RRL itself, thereby reducing its impact on the original circuit. However, reducing G... M1，2 At the same time, the ripple suppression capability of RRL decreases. Therefore, M 1a,b The same constant gain bias circuit as GM1 is used to bias it. By setting the current values ​​of the two tail currents at the input terminal, it is ensured that GM1 outputs sufficient compensation current while reducing its transconductance, thereby reducing the noise contribution of RRL to IA. In summary, by reducing the RRL bandwidth, increasing the output impedance of RRL_CB, and reducing the transconductance of RRL_GM, the impact on the noise performance of the original circuit can be reduced while effectively suppressing ripple.

[0077] In the rail-to-rail high-impedance instrumentation amplifier, one of the core innovations is the constant gain rail-to-rail input transconductance GM1 and feedback transconductance GM2 based on common-mode detection. This extends the IA input range to rail-to-rail operation. Specifically, it employs parallel NMOS and PMOS differential pairs. The NMOS differential pairs are adapted for low common-mode voltages, while the PMOS differential pairs are adapted for high common-mode voltages. The NMOS transistors have their sources connected to a low potential, and conduction requires the gate-source voltage VGS to be close to the threshold voltage. When the input common-mode voltage approaches GNDA+V... thn When the voltage difference between the gate and source of the NMOS meets the conduction requirements, it operates normally.

[0078] For a PMOS transistor to turn on with its source connected to a high potential, the source-gate voltage VSG must be slightly lower than the threshold voltage. When the input common-mode voltage is close to VDDA-|V thp At that time, the voltage difference between the PMOS source and gate meets the conduction requirements;

[0079] The NMOS differential pair operating in the low common-mode voltage range and the PMOS differential pair operating in the high common-mode voltage range complement each other, and the two work together to achieve GNDA+V. thn To VDDA-|V thp | Rail-to-rail input voltage range;

[0080] The Const_GM module senses the input common-mode voltage level in real time through the common-mode detection unit. When the input common-mode voltage is in the low range, it increases the tail current ratio of the NMOS differential pair.

[0081] When the input common-mode voltage is in the high range, the tail current ratio of the PMOS differential pair is increased to keep the total tail current of the NMOS and PMOS differential pairs constant. Based on the linear relationship between the transconductance and leakage current of the MOS transistor in the subthreshold region, the total transconductance of the differential pair is kept constant in the rail-to-rail input range.

[0082] The specific circuit and connection relationship of the transconductance section of the amplifier are as follows: Figure 3 As shown. It includes a constant transconductance unit Const_GM and signal transconductance units GM1 and GM2; the structure of the constant transconductance bias unit Const_GM is as follows: the source of the PMOS transistor M5 is connected to the power supply VDDA, the gate is connected to the bias voltage Vbias, and the drain is an internal current mirror (M). 6a,b —M 9a,b Provides bias;

[0083] The input stage for common-mode detection contains two differential pairs: transistor M 12a M 13a The gate is connected to the positive input VIP, M 12a M 13b The gate is connected to the inverting input VIN; the final output common-mode nodes are VCP and VCN.

[0084] Transconductance GM1 and GM2 adopt the same symmetrical structure: each cell contains a PMOS cascode pair M. 1a M 1b M 2a M 2b NMOS input pair M 1a M 1b The gates are connected to VIP and VIN respectively, and the source is connected to the drain of the tail current source M4 controlled by VCN. The drain is connected to the output terminal of the common-source common-gate load, outputting AA and CC; the PMOS input is connected to M... 2a M 2b The gates are connected to VIP and VIN respectively, the source is connected to the drain of the tail current source M3 controlled by VCP, and the drain is connected to the output terminals of the common source cascode load to output BB and DD.

[0085] The specific operating method of the input transconductance GM1 and feedback transconductance GM2 is as follows: both input transconductance GM1 and feedback transconductance GM2 adopt a complementary structure of parallel NMOS differential pairs and PMOS differential pairs operating in the subthreshold region; at the same time, the bias circuits of GM1 and GM2 use a constant transconductance method to achieve the bias of GM1 and GM2 at GNDA+V. thn To VDDA-|V thp | Remains constant within the range, where V thn V thp These are the threshold voltages for NMOS and PMOS, respectively;

[0086] When the gate-source voltage of a MOSFET is close to its threshold voltage (slightly below the threshold voltage), the drain current formula for a MOSFET operating in the subthreshold region is as shown in Formula 2 below; Formula 3 is obtained by differentiating Formula 2; the input consists of NMOS differential pairs and PMOS differential pairs connected in parallel, therefore, the input transconductance is the transconductance g of the NMOS. mn and the transconductance g of PMOS mp The sum of these two values ​​yields the following formula 4;

[0087] Formula 2;

[0088] Formula 3;

[0089] Formula 4;

[0090] Where V TH V is the threshold voltage of the MOS. T Assuming the thermal voltage, according to Equation 4, the transconductance and leakage current of a MOSFET operating in the subthreshold region have a linear relationship. Therefore, as long as the total current of the input pair remains constant, the total input transconductance remains unchanged. Figure 3 As shown, M 12a M 12b M 13a M 13b Four input transistor pairs are used to detect the input common-mode voltage and perform I / O based on VIN and VIP. N_ctrl and I P_ctrl The current distribution is such that the current in the two branches is replicated to the tail current source in a certain proportion, so that the tail current I... N_ctrl and I P_ctrl The sum is always a constant; since gm is linearly related to the sum of currents, it remains unchanged in the common-mode range, as shown in Formula 4, so that the transconductance of GM1 and GM2 remains constant in the rail-to-rail input range.

[0091] Instrumentation amplifiers (IAs) are used in scenarios involving the measurement and amplification of high-impedance, weak signal sources, including temperature signals from thermocouples, bioelectrical signals such as electrocardiograms (ECG) and electroencephalograms (EEG), and weak current signals from photodetectors. Furthermore, by employing constant gain rail-to-rail input transconductance based on common-mode detection, IAs can be adapted to GNDA+V. thn To VDDA-|V thp The common-mode voltage input scenario expands the application scenarios of the IA (Integrated Instrumentation Amplifier). Specific applications include thermobridge applications, front-end amplifiers for high-precision digital-to-analog converters, and medical devices such as electrocardiographs, blood pressure monitors, and vital sign monitors. It can serve as a general-purpose circuit in integrated circuits, compatible with various integrated circuit platforms such as Cadence, PSpice, and Hspice. Input chopper switches can be designed in chopper instrumentation amplifiers on various platforms, thereby optimizing the input impedance and chopper ripple noise of the chopper instrument. The impedance GM_R adopts a folded cascode structure. The output stage GM3 adopts a Class AB structure to extend the output voltage range and improve load capacity. Miller compensation is used between the input and output stages to ensure the overall stability of the IA.

[0092] The method of using an instrumentation amplifier includes the following steps;

[0093] Step 1, Signal Input: Connect the pre-processed differential signals such as temperature and bioelectricity to the differential input terminals (VIN, VIP) of the IA; the common-mode voltage of the pre-processed signal must be controlled within GNDA+V. thn To VDDA-|V thp Within the interval, ensure that the input transconductances GM1 and GM2 always operate in a constant transconductance state;

[0094] Step 2, Impedance Boost and Signal Modulation: The synchronous clock signal controls the periodic switching of chopper switches CH1a and CH1b to modulate the input signal; during this process, SCPS technology will cancel the influence of the switch dynamic resistance on the input impedance, so that the IA input impedance reaches the GΩ level.

[0095] Step 3, Signal Amplification and Output: The impedance stage GM_R converts the processed current signal into a voltage signal and transmits it to the output stage GM3; Miller compensation capacitor (C) 1a,b To ensure system stability, the gain of the resistor feedback network is set, ultimately outputting a stable and amplified signal.

[0096] Step 4, Ripple Suppression: The RRL loop generates a compensation current through negative feedback to offset the offset current output by GM1 and GM2, thereby reducing ripple;

[0097] Step 5, Transconductance Constant Control: The input common-mode voltage is detected by the common-mode detection unit Const_GM, and I is allocated accordingly. N_ctrl with I P_ctrlThe signal controls the tail current of the input transconductance, maintaining a constant transconductance within the rail-to-rail input range.

Claims

1. A rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization, characterized in that: The instrumentation amplifier IA employs an AC-coupled ripple suppression loop combined with a constant gain rail-to-rail input transconductance architecture based on common-mode detection. Based on the chopper and dynamic element matching synchronization SCPS method, the switching logic of the chopper switch and dynamic element is synchronously controlled to reduce the impact of the switching dynamic resistance on the input impedance. Simultaneously, an AC-coupled ripple suppression loop (RRL) is used to effectively suppress ripple voltage by canceling the offset current generated by the input transconductance and feedback transconductance. Furthermore, a constant gain rail-to-rail input transconductance based on common-mode detection achieves rail-to-rail input and constant transconductance to ensure amplification accuracy.

2. The input rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization according to claim 1, characterized in that: The AC-coupled ripple suppression loop of the architecture reduces the bandwidth of the AC-coupled ripple suppression loop to effectively filter only the ripple frequency components; at the same time, it reduces the transconductance value of the transconductance unit in the loop. Based on the positive correlation between transconductance and noise density, it reduces the noise contribution of the loop itself. While enhancing the ripple suppression effect, it avoids additional interference to the noise performance of the original circuit and does not introduce phase shift at the chopping frequency.

3. The input rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization according to claim 1, characterized in that: The architecture described above, based on common-mode detection and constant-gain rail-to-rail input transconductance, employs a complementary structure of parallel NMOS differential pairs and PMOS differential pairs operating in the subthreshold region. Its bias circuit utilizes constant transconductance technology to achieve GNDA+V. thn To VDDA-|V thp | Input track to track range, where V thn V thp These are the threshold voltages for NMOS and PMOS, respectively.

4. The input rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization according to claim 1, characterized in that: The circuit modules of the input rail-to-rail high-impedance instrumentation amplifier include: a chopper and dynamic element matching synchronous switch module SCPS, an AC coupling ripple suppression loop RRL, input transconductance GM1, feedback transconductance GM2, impedance stage GM_R, output stage GM3, chopper switch CH2, and Miller compensation capacitor C. 1a Miller compensation capacitor C 1b and a resistor voltage divider feedback network.

5. The input rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization according to claim 4, characterized in that: The signal input of the rail-to-rail high impedance instrumentation amplifier is as follows: after the external differential signals VIN and VIP are connected, they are modulated into high-frequency signals by the SCPS switching module. This signal is input to the input transconductance GM1, and GM1 converts it into the corresponding current signal. The signal amplification and output of the rail-to-rail high-impedance instrumentation amplifier are as follows: GM2 provides feedback transconductance, GM_R converts the current signal into a voltage signal, the Class AB structure GM3 output stage enhances the load-driving capability, and Miller compensation capacitor C... 1a Miller compensation capacitor C 1b To ensure system stability, the overall gain of the IA is set by a resistor voltage divider feedback network. The ripple suppression of the input rail-to-rail high impedance instrumentation amplifier is specifically achieved by: generating a compensation current I in the RRL loop. RRL To offset the offset current I output from GM1 and GM2 GM1 I GM2 To reduce ripple voltage, the Const_GM unit provides a constant transconductance bias for GM1 and GM2, thereby achieving rail-to-rail input range.

6. The input rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization according to claim 5, characterized in that: In the input rail-to-rail high impedance instrumentation amplifier, the chopper and dynamic element matching synchronous chopper switch module reduces the impact of the switching dynamic impedance on the input impedance through the switching logic of synchronous chopper and dynamic element matching, thereby increasing the input impedance to the GΩ level.

7. The input rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization according to claim 5, characterized in that: In the input rail-to-rail high-impedance instrumentation amplifier, the specific circuit connection of its AC coupling ripple suppression loop (RRL) is as follows: RRL consists of sensing capacitor C. 3a and C 3b Chopper CH3, RRL_CB cascode buffer, C int Composed of integrating capacitor and RRL_GM for transconductance compensation; power node VDDA is M 2a M 2b M 5a and M 5b The source provides a positive power supply voltage; the output node OUT_AA is connected to M. 2a The drain and OUT_BB are connected to M. 1a The drain and OUT_CC are connected to M. 2b The drain and OUT_DD are also connected to M. 1b The drain; the input node IN+ is connected to C. 3a Coupled to M 8a The drain and input node IN- are connected via C. 3b Coupled to M 8b The drain; common-mode feedback node V CMFB Connect M 8a,b The gate; Where M 1a With M 1b M 2a With M 2b They form a differential input pair, and their bias voltage also controls M. 5a,b The gate potential of M6 is set, and the chopper switch CH1 is connected between the input and M6. 7a,b Signal modulation is achieved between the drain nodes, and the chopper switch CH2 is connected to M. 5a,b Drain and M 6a,b Signal modulation is achieved between source nodes; C int It is an integrating capacitor, one end of which is coupled to M. 7a The source is coupled to M at the other end. 7b Source pole; The specific working method of the AC coupling ripple suppression loop (RRL) circuit is as follows: The RRL first passes through C... 3a,b The ripple is converted into a current with a chopping frequency, which, after passing through CH3, is demodulated into a DC current I. CH3 I CH3 In C int Integrating the result yields the corresponding voltage, the final value of which is I. CH3 ×R RRL_CB , where R RRL_CB For RRL_CB in C int The output impedance is on; this voltage is converted to I via RRL_GM. RRL ; Offset current I output from GM1 and GM2 GM1 I GM2 The sum of these and the compensation current I generated by the RRL loop RRL The current I is obtained by canceling out the negative feedback. CH2 I CH2 After being chopped by CH2, C1 is charged and discharged. Combining the chopping frequency fch and the capacitance value, the reduced ripple voltage is derived as shown in Formula 1 below. Formula 1: Where f ch R is the chopping frequency. RRL_CB G is the output impedance of RRL_CB. RRL_GM C is the transconductance of RRL_GM, and C3 is the sensing capacitance C. 3a,b The capacitance value, C1 is the capacitance value of capacitor C1, I OS The offset current I output by GM1 and GM2 GM1 I GM2 sum; The output of IA is VOUT=V ripple +VOP-VON; Chopper ripples superimposed on the IA output VOUT. ripple The offset voltages derived from GM1 and GM2 are converted into offset currents through transconductance before passing through RRL. The chopper then chops this current, and the chopped current affects the Miller compensation capacitor C within one chopping cycle. 1a C 1b Perform charging and discharging. The ripple voltage without RRL is , Where T ch Let dT be the chopping period, and dT represent the integral variable as time T, C 1a，b For compensation capacitor C 1a，b With the capacitance value, RRL reduces chopper ripple. times; The RRL bandwidth must be lower than the chopping frequency, C int Set to several pF to filter the CH1 modulated output signal; simultaneously, to avoid the RRL itself introducing additional noise, noise suppression and ripple suppression capabilities need to be balanced through parameter optimization; M 1a,b The same constant gain bias circuit as GM1 is used to bias it. By setting the current values ​​of the two tail currents at the input terminal, it is ensured that GM1 outputs sufficient compensation current while reducing its transconductance value, thereby reducing the noise contribution of RRL to IA.

8. The input rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization according to claim 5, characterized in that: In a rail-to-rail high-impedance instrumentation amplifier, the constant gain rail-to-rail input transconductance GM1 and feedback transconductance GM2 based on common-mode detection extend the IA input range to rail-to-rail. Specifically, NMOS and PMOS differential pairs are connected in parallel. The NMOS differential pair is adapted for low common-mode voltage, and the PMOS differential pair is adapted for high common-mode voltage. The source of the NMOS transistor is connected to a low potential, and conduction requires the gate-source voltage VGS to be close to the threshold voltage. When the input common-mode voltage is close to GNDA+V... thn When the voltage difference between the gate and source of the NMOS meets the conduction requirements, it operates normally. For a PMOS transistor to turn on with its source connected to a high potential, the source-gate voltage VSG must be slightly lower than the threshold voltage. When the input common-mode voltage is close to VDDA-|V thp At that time, the voltage difference between the PMOS source and gate meets the conduction requirements; The NMOS differential pair operating in the low common-mode voltage range and the PMOS differential pair operating in the high common-mode voltage range complement each other, and the two work together to achieve GNDA+V. thn To VDDA-|V thp | Rail-to-rail input voltage range; The Const_GM module senses the input common-mode voltage level in real time through the common-mode detection unit. When the input common-mode voltage is in the low range, it increases the tail current ratio of the NMOS differential pair. When the input common-mode voltage is in the high range, the tail current ratio of the PMOS differential pair is increased to keep the total tail current of the NMOS and PMOS differential pairs constant. Based on the linear relationship between the transconductance and leakage current of the MOS transistor in the subthreshold region, the total transconductance of the differential pair is kept constant in the rail-to-rail input range.

9. The input rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization according to claim 8, characterized in that: The amplifier's transconductance section includes a constant transconductance unit Const_GM, signal transconductance units GM1 and GM2. The constant transconductance bias unit Const_GM has the following structure: the source of the PMOS transistor M5 is connected to the power supply VDDA, the gate is connected to the bias voltage Vbias, and the drain is the internal current mirror M. 6a,b —M 9a,b Provide bias; The input stage for common-mode detection contains two differential pairs: transistor M 12a M 13a The gate is connected to the positive input VIP, M 12a M 13b The gate is connected to the inverting input VIN; the final output common-mode nodes are VCP and VCN. Transconductance GM1 and GM2 adopt the same symmetrical structure: each cell contains a PMOS cascode pair M. 1a M 1b M 2a M 2b NMOS input pair M 1a M 1b The gates are connected to VIP and VIN respectively, and the source is connected to the drain of the tail current source M4 controlled by VCN. The drain is connected to the output terminal of the common-source common-gate load, outputting AA and CC; the PMOS input is connected to M... 2a M 2b The gates are connected to VIP and VIN respectively, the source is connected to the drain of the tail current source M3 controlled by VCP, and the drain is connected to the output terminals of the common source cascode load to output BB and DD. The specific operating method of the input transconductance GM1 and feedback transconductance GM2 is as follows: both input transconductance GM1 and feedback transconductance GM2 adopt a complementary structure of parallel NMOS differential pairs and PMOS differential pairs operating in the subthreshold region; at the same time, the bias circuits of GM1 and GM2 use a constant transconductance method to achieve the bias of GM1 and GM2 at GNDA+V. thn To VDDA-|V thp | Remains constant within the range, where V thn V thp These are the threshold voltages for NMOS and PMOS, respectively; When the gate-source voltage of a MOSFET is close to its threshold voltage, the drain current of a MOSFET operating in the subthreshold region is given by Equation 2 below; Equation 3 is obtained by differentiating Equation 2; the input consists of NMOS differential pairs and PMOS differential pairs connected in parallel, therefore, the input transconductance is the transconductance g of the NMOS transistor. mn and the transconductance g of PMOS mp The sum of these two values ​​yields the following formula 4; Formula 2: Formula 3: Formula 4: Where I D VGS is the leakage current of the MOSFET, W is the channel width, L is the channel length of the MOSFET, VGS is the gate-source voltage of the MOSFET, n is a constant >1 determined by the process, gm is the transconductance of the MOSFET, gmn is the transconductance of the NMOS input pair, gmp is the transconductance of the PMOS input pair, and Vm is the transconductance of the PMOS input pair. TH V is the threshold voltage of the MOS. T Assuming thermal voltage, according to Equation 4, the transconductance and leakage current of a MOSFET operating in the subthreshold region have a linear relationship. Keeping the total current of the input pair constant, the total input transconductance remains unchanged. M 12a M 12b M 13a M 13b Four input transistor pairs are used to detect the input common-mode voltage and perform I / O based on VIN and VIP. N_ctrl and I P_ctrl The current distribution is such that the current in the two branches is replicated to the tail current source in a certain proportion, so that the tail current I... N_ctrl and I P_ctrl The sum is always a constant; since gm is linearly related to the sum of currents, it remains unchanged in the common-mode range, as shown in Formula 4, so that the transconductance of GM1 and GM2 remains constant in the rail-to-rail input range.

10. The input rail-to-rail high-impedance instrumentation amplifier with chopper and dynamic element matching synchronization according to claim 9, characterized in that: When the instrumentation amplifier is used for measuring and amplifying high-impedance weak signal sources, the impedance GM_R adopts a folded common-source common-gate structure; the output stage GM3 adopts a Class AB structure to expand the output voltage range and improve the load-driving capability; Miller compensation is used between the input stage and the output stage circuit to ensure the overall stability of the IA. The method of using an instrumentation amplifier includes the following steps; Step 1, Signal Input: Connect the pre-processed differential signals such as temperature and bioelectricity to the differential input terminal of the IA; the common-mode voltage of the pre-processed signal needs to be controlled within GNDA+V. thn To VDDA-|V thp Within the interval, ensure that the input transconductances GM1 and GM2 always operate in a constant transconductance state; Step 2, Impedance Boost and Signal Modulation: The synchronous clock signal controls the periodic switching of chopper switches CH1a and CH1b to modulate the input signal; during this process, SCPS technology will cancel the influence of the switch dynamic resistance on the input impedance, so that the IA input impedance reaches the GΩ level. Step 3, Signal Amplification and Output: The impedance stage GM_R converts the processed current signal into a voltage signal and transmits it to the output stage GM3; the Miller compensation capacitor ensures system stability, the resistor feedback network sets the gain, and finally outputs a stable amplified signal; Step 4, Ripple Suppression: The RRL loop generates a compensation current through negative feedback to offset the offset current output by GM1 and GM2, thereby reducing ripple; Step 5, Transconductance Constant Control: The input common-mode voltage is detected by the common-mode detection unit Const_GM, and I is allocated accordingly. N_ctrl with I P_ctrl The signal controls the tail current of the input transconductance, maintaining a constant transconductance within the rail-to-rail input range.

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