Fault signal latch circuit

Abstract

The invention relates to a fault signal latch circuit, which comprises a latch comparator, the positive input end of which is used for receiving a low-level fault signal and a high-level recovery signal; a positive end voltage lifting output end of the positive end voltage lifting sub-circuit is connected with a positive input end of the latch comparator; a negative end voltage storage and release module of the negative end and output end voltage control sub-circuit is connected with a negative input end of the latch comparator, and an output end voltage control end of the negative end and output end voltage control sub-circuit is connected with an output end of the latch comparator; the anode of the clamping diode is connected with the positive input end and the positive end voltage lifting output end of the latch comparator, and the cathode of the clamping diode is connected with the output end of the latch comparator; the voltage value of the output end voltage control end is larger than the voltage value of the positive end voltage lifting output end, and the voltage value of the positive end voltage lifting output end is larger than the output voltage value of the negative end voltage storage and release module. The cost is increased; and the design complexity is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, and particularly relates to a fault signal latching circuit. BACKGROUND

[0002] The fault signal latching circuit is an electronic circuit for capturing and continuously maintaining a fault state signal, and the core function is to "lock" a transient or short-time fault signal as a stable continuous signal when an overvoltage, undervoltage, overcurrent and the like fault occurs in a system, so as to ensure that a control chip (such as an MCU and a DSP) has enough time to detect the fault and perform a protection action (such as closing a drive and cutting off a power supply).

[0003] The existing fault latching circuit needs to increase an unlocking circuit or output an unlocking signal of a control chip for unlocking after latching, which not only leads to an increase in cost, but also needs to control a power-on timing and an unlocking timing, thereby increasing design complexity. SUMMARY

[0004] The present application provides a fault signal latching circuit, which can solve the problem that the existing fault latching circuit needs to increase an unlocking circuit or output an unlocking signal of a control chip for unlocking after latching, which not only leads to an increase in cost, but also needs to control a power-on timing and an unlocking timing, thereby increasing design complexity.

[0005] In a first aspect, the present application provides a fault signal latching circuit, comprising: A latching comparator, a positive input end of the latching comparator being configured to receive a low-level fault signal and a high-level recovery signal; A positive-end voltage lifting sub-circuit, having a positive-end voltage lifting output end, the positive-end voltage lifting output end being connected to the positive input end of the latching comparator; A negative-end and output-end voltage control sub-circuit, having a negative-end pressure accumulation and release module and an output-end voltage control end, the negative-end pressure accumulation and release module being connected to the negative input end of the latching comparator, and the output-end voltage control end being connected to the output end of the latching comparator; A clamping diode, an anode of the clamping diode being connected to the positive input end of the latching comparator and the positive-end voltage lifting output end, and a cathode of the clamping diode being connected to the output end of the latching comparator; The voltage value of the output end voltage control end is greater than the voltage value of the positive end voltage lifting output end, and the voltage value of the positive end voltage lifting output end is greater than the output voltage value of the negative end storage and discharge voltage module. When the low level fault signal is received, the latch comparator outputs a latch low level fault signal, so that the negative end storage and discharge voltage module discharges and reduces voltage. When the high level recovery signal is received, the voltage of the positive input end of the latch comparator is clamped to a forward clamping voltage through the clamping diode, and when the output voltage value of the negative end storage and discharge voltage module is less than or equal to the forward clamping voltage, a latch high level signal is output.

[0006] In some embodiments, the fault signal latch circuit further comprises a fault detection unit, and the fault detection unit comprises: a first resistor, an input end of which is connected with a target system, for receiving a sampling signal of the target system; a detection comparator, a negative input end of which is connected with an output end of the first resistor, a positive input end of which is connected with an input end of a preset reference voltage, and an output end of which is connected with a positive input end of the latch comparator.

[0007] In some embodiments, the fault detection unit further comprises a first capacitor, one end of which is connected with the output end of the first resistor and the negative input end of the detection comparator, and the other end of which is connected with a circuit ground.

[0008] In some embodiments, the positive end voltage lifting sub-circuit comprises: a second resistor, having a second power supply end and a positive end voltage lifting output end, the second power supply end being connected with a direct current power supply, and the positive end voltage lifting output end being connected with the output end of the detection comparator and the positive input end of the latch comparator; a third resistor, one end of which is connected with the positive end voltage lifting output end, and the other end of which is connected with the circuit ground.

[0009] In some embodiments, the positive end voltage lifting sub-circuit further comprises a second capacitor, which is connected in parallel with the third resistor.

[0010] In some embodiments, the negative end and output end voltage control sub-circuit comprises: a negative end storage and discharge voltage module, having a storage and discharge voltage ground end and a negative end storage and discharge voltage control end, the storage and discharge voltage ground end being connected with the circuit ground, and the negative end storage and discharge voltage control end being connected with the negative input end of the latch comparator; a fifth resistor, one end of which is connected with the negative end storage and discharge voltage control end, and the other end of which is connected with the output end of the latch comparator; a sixth resistor, one end of which is connected with the output end of the latch comparator, and the other end of which is connected with the direct current power supply. In some embodiments, the fault signal latch circuit further comprises a fault detection unit, and the fault detection unit comprises: a first resistor, an input end of which is connected with a target system, for receiving a sampling signal of the target system; a detection comparator, a negative input end of which is connected with an output end of the first resistor, a positive input end of which is connected with an input end of a preset reference voltage, and an output end of which is connected with a positive input end of the latch comparator.

[0007] In some embodiments, the fault detection unit further comprises a first capacitor, one end of which is connected with the output end of the first resistor and the negative input end of the detection comparator, and the other end of which is connected with a circuit ground.

[0008] In some embodiments, the positive end voltage lifting sub-circuit comprises: a second resistor, having a second power supply end and a positive end voltage lifting output end, the second power supply end being connected with a direct current power supply, and the positive end voltage lifting output end being connected with the output end of the detection comparator and the positive input end of the latch comparator; a third resistor, one end of which is connected with the positive end voltage lifting output end, and the other end of which is connected with the circuit ground.

[0009] In some embodiments, the positive end voltage lifting sub-circuit further comprises a second capacitor, which is connected in parallel with the third resistor.

[0010] In some embodiments, the negative end and output end voltage control sub-circuit comprises: a negative end storage and discharge voltage module, having a storage and discharge voltage ground end and a negative end storage and discharge voltage control end, the storage and discharge voltage ground end being connected with the circuit ground, and the negative end storage and discharge voltage control end being connected with the negative input end of the latch comparator; a fifth resistor, one end of which is connected with the negative end storage and discharge voltage control end, and the other end of which is connected with the output end of the latch comparator; a sixth resistor, one end of which is connected with the output end of the latch comparator, and the other end of which is connected with the direct current power supply.

[0011] In some embodiments, the negative end and output end voltage control sub-circuit further comprises a fourth capacitor, one end of the fourth capacitor being connected to the output end of the latch comparator, and the other end of the fourth capacitor being connected to the circuit ground.

[0012] In some embodiments, the negative end pressure accumulation and release module comprises a fourth resistor and a third capacitor connected in parallel.

[0013] In some embodiments, the resistance of the second resistor is equal to the resistance of the sixth resistor, and the resistance of the third resistor is equal to the resistance of the fourth resistor.

[0014] In some embodiments, the fault signal latch circuit further comprises a drive control unit, the drive control unit comprising: a digital signal processor connected to the output end of the latch comparator; a drive AND gate having a first input end, a second input end and an AND gate output end, the first input end being connected to the output end of the latch comparator, the second input end being connected to the drive control signal output end of the digital signal processor, and the AND gate output end being connected to the power tube of the target system.

[0015] Compared with the prior art, the above technical solutions provided by the embodiments of the present application have the following advantages: The fault signal latch circuit provided by the embodiments of the present application ensures that the latch comparator outputs a latched high-level signal in a normal state by making the voltage value of the output end voltage control end greater than the voltage value of the positive end voltage lifting output end, and the voltage value of the positive end voltage lifting output end greater than the output voltage value of the negative end pressure accumulation and release module. By connecting the positive end voltage lifting output end to the positive input end of the latch comparator, connecting the anode of the clamping diode to the positive input end of the latch comparator and the positive end voltage lifting output end, and connecting the cathode of the clamping diode to the output end of the latch comparator, and by using the forward clamping characteristic of the clamping diode and the natural discharge process of the negative end pressure accumulation and release module, when the low-level fault signal is received, the latch comparator flips to output a latched low-level fault signal, and the latch state is continuously maintained by discharging and reducing the voltage through the negative end pressure accumulation and release module. When the high-level recovery signal is received, the voltage of the positive input end of the latch comparator is clamped to the forward clamping voltage by the clamping diode, and when the voltage of the negative end pressure accumulation and release module continuously discharges to be less than or equal to the forward clamping voltage, a latched high-level signal is output, and the unlocking is completed. This can solve the problem of the prior art fault latch circuit, which needs to add an unlocking circuit after latching or output an unlocking signal by a control chip to unlock, which not only increases the cost, but also needs to regulate the power-up timing and unlocking timing, increasing the design complexity. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, the accompanying drawings can obtain other drawings based on these drawings without any creative effort.

[0018] One or more embodiments are illustrated by way of example with reference to the drawings, which are not limiting of the embodiments and which are merely meant to explain the principles of the embodiments. The reference numbers in the drawings indicate elements which functionally correspond to the other elements in the same group. The drawings in the accompanying drawings are not to scale and the dimensions of elements are not intended to correspond to the actual dimensions.

[0019] Fig. 1 A circuit diagram of a fault signal latching circuit provided by an embodiment of the present application; Fig. 2 A circuit voltage schematic diagram at 0-t3 provided by an embodiment of the present application; Fig. 3 A signal flow conversion schematic diagram of a fault signal latching circuit provided by an embodiment of the present application. BRIEF DESCRIPTION OF DRAWINGS 10, positive terminal voltage lifting sub-circuit; 20, negative terminal and output terminal voltage control sub-circuit; 210, negative terminal charge and discharge voltage module; 30, fault detection unit; 40, drive control unit. DETAILED DESCRIPTION

[0021] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the scope of protection of the present application.

[0022] The following disclosure provides a number of different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, reference numerals and / or letters can be repeated in different examples. Such repetition is for the purpose of simplicity and clarity and does not indicate a relationship between the various embodiments and / or arrangements discussed.

[0023] For ease of description, spatial relative terms can be used herein to describe the relative position relationship or movement of one element or feature with respect to another element or feature as shown in the drawings, such as "inner", "outer", "inboard", "outboard", "under", "below", "on", "above", "front", "back", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped over or the posture is changed or the movement state is changed, the directional indications will also change accordingly, for example: the element described as "under" or "below" another element or feature will be subsequently oriented as "above" or "above" another element or feature. Therefore, the example term "below" can include both the upper and lower positions. The device can be additionally oriented (rotated 90 degrees or in other directions) and the spatial relative relationship descriptors used herein are interpreted accordingly.

[0024] The fault signal latching circuit is an electronic circuit for capturing and continuously holding a fault state signal, and the core function is to "lock" the instantaneous or short-time fault signal as a stable continuous signal when the system has an overvoltage, undervoltage, overcurrent, etc. fault, to ensure that the control chip (such as MCU, DSP) has enough time to detect the fault and perform protection actions (such as closing the drive, cutting off the power supply, etc.).

[0025] The existing fault signal latching circuit compares the sampling signal of the system with the preset value through a comparator, and when a fault occurs, the comparator outputs a low-level fault signal. After the control chip detects the fault signal, the drive is closed to protect the system, but the software needs a long time to detect the fault. In order to ensure that the software effectively detects the fault signal, the fault signal often needs to be latched for a period of time, and the existing fault signal latching circuit needs to be unlocked after latching by adding an unlocking circuit or a control chip outputting an unlocking signal, which not only increases the cost, but also needs to control the power-on sequence and the unlocking sequence, increasing the design complexity.

[0026] In order to solve the above technical problems, the embodiments of the present application provide a fault signal latching circuit, as shown in the first aspect of the present application. Figs. 1-3 The fault signal latching circuit comprises: a latch comparator U2, a positive input end of the latch comparator U2 being configured to receive a low-level fault signal and a high-level recovery signal; a positive-end voltage lifting sub-circuit 10, having a positive-end voltage lifting output end, the positive-end voltage lifting output end being connected to the positive input end of the latch comparator U2; a negative-end and output-end voltage control sub-circuit 20, having a negative-end charge and discharge voltage module 210 and an output-end voltage control end, the negative-end charge and discharge voltage module 210 being connected to the negative input end of the latch comparator U2, and the output-end voltage control end being connected to the output end of the latch comparator U2; a clamping diode D1, an anode of the clamping diode D1 being connected to the positive input end of the latch comparator U2 and the positive-end voltage lifting output end, and a cathode of the clamping diode D1 being connected to the output end of the latch comparator U2; wherein a voltage value of the output-end voltage control end is greater than a voltage value of the positive-end voltage lifting output end, and the voltage value of the positive-end voltage lifting output end is greater than an output voltage value of the negative-end charge and discharge voltage module 210, when the low-level fault signal is received, the latch comparator U2 outputs a latch low-level fault signal, so that the negative-end charge and discharge voltage module 210 discharges and reduces voltage, when the high-level recovery signal is received, the voltage of the positive input end of the latch comparator U2 is clamped to a forward clamping voltage through the clamping diode D1, and when the output voltage value of the negative-end charge and discharge voltage module 210 is less than or equal to the forward clamping voltage, a latch high-level signal is output.

[0027] It should be noted that the fault signal latch circuit provided by the embodiments of the present application does not need an additional unlocking circuit (such as a reset chip, a relay) or an unlocking signal of a control chip in the traditional scheme, and automatic unlocking is realized only through the forward clamping characteristics of the clamping diode D1 and the natural discharge of the negative-end charge and discharge voltage module 210, that is, after the low-level fault signal disappears, the high-level recovery signal triggers the clamping diode D1 to conduct, the voltage of the positive input end of the latch comparator U2 is clamped to a forward clamping voltage (or a forward voltage drop VF), and when the negative-end charge and discharge voltage module 210 (a capacitor) is discharged to below (or equal to) the forward clamping voltage, the circuit automatically outputs a high-level recovery normal signal, the additional unlocking element and the timing matching design can be omitted, the number of components is reduced, the hardware cost is reduced, the software and hardware cooperative logic is simplified, and the development cycle is shortened.

[0028] It should be noted that, by clear voltage level design (output voltage control end > positive end voltage lifting output > negative end storage and discharge pressure module 210 output), the high level output of the latch comparator U2 can be stably maintained in normal state to avoid false triggering; when fault occurs, the low level fault signal triggers the latch comparator U2 to immediately output the latch low level fault signal, and at the same time drives the negative end storage and discharge pressure module 210 to discharge and reduce pressure, and the fault state is continuously latched, sufficient time is reserved for software detection of the control chip (such as DSP), and the fault missed detection problem caused by software detection delay is solved; after the fault disappears, no manual intervention or external command is needed, and the circuit relies on the characteristics of the elements to complete the autonomous switching from "fault latching" to "normal output", realizes the automatic recovery of the system, and improves the fault tolerance and operation efficiency of the system.

[0029] In some embodiments, the fault signal latching circuit further comprises a fault detection unit 30, and the fault detection unit 30 comprises: a first resistor R1, an input end of which is connected with the target system and used for receiving a sampling signal of the target system; a detection comparator U1, a negative input end of which is connected with an output end of the first resistor R1, a positive input end of which is connected with an input end of a preset reference voltage, and an output end of which is connected with a positive input end of a latch comparator U2.

[0030] It should be noted that the left end of the first resistor R1 is the input end of the first resistor R1, the right end of the first resistor R1 is the output end of the first resistor R1, and the input end of the preset reference voltage provides a preset reference voltage Vref for the detection comparator U1. The fault detection unit 30 directly connects the sampling signal SS of the target system through the first resistor R1 (sampling and conditioning) and the detection comparator U1, compares it with the preset reference voltage Vref (fault threshold), and automatically generates a low level fault signal or a high level recovery signal, which is directly sent to the positive input end of the latch comparator U2.

[0031] It should be noted that the first resistor R1 can perform voltage division or current limiting conditioning (such as converting high voltage / current signals into a level range that the comparator can withstand) according to the amplitude of the sampling signal SS, to protect the subsequent circuit and improve the sampling accuracy; the input end of the preset reference voltage can be flexibly connected with a reference source (such as a precision voltage stabilizing tube, a DAC output, etc.), so that the fault threshold (such as the threshold of the overvoltage protection) can be flexibly set by changing the reference voltage according to the system requirements, and the circuit is applicable to detection of various fault types such as overvoltage, undervoltage and overcurrent, thereby improving the versatility.

[0032] In some embodiments, the fault detection unit 30 further comprises a first capacitor C1, one end of the first capacitor C1 is connected with the output end of the first resistor R1 and the negative input end of the detection comparator U1, and the other end of the first capacitor C1 is connected with the circuit ground GND.

[0033] It should be noted that the sampling signal SS (such as voltage, current) of the target system often contains high-frequency interference (such as switching noise, electromagnetic radiation, etc.), which may cause the sampling signal SS to exceed or be lower than the preset reference voltage instantaneously, so that the detection comparator U1 is misjudged as "fault" or "recovery"; the first capacitor C1 and the first resistor R1 form an RC low-pass filter circuit, which can effectively attenuate high-frequency noise, so that the signal input to the detection comparator U1 is smoother, only reflecting the real steady state or slowly changing state of the system, and avoiding false triggering caused by instantaneous noise.

[0034] In some embodiments, the positive end voltage lifting sub-circuit 10 comprises: The second resistor R2 has a second power supply end and a positive end voltage lifting output end, the second power supply end is connected with the direct current power supply VDD, and the positive end voltage lifting output end is connected with the output end of the detection comparator U1 and the positive input end of the latch comparator U2; The third resistor R3 has one end connected with the positive end voltage lifting output end and the other end connected with the circuit ground GND.

[0035] It should be noted that the upper end of the second resistor R2 is the second power supply end, the lower end of the second resistor R2 is the positive end voltage lifting output end, the upper end of the third resistor R3 is connected with the positive end voltage lifting output end, and the lower end of the third resistor R3 is connected with the circuit ground GND; the second resistor R2 (connected with the direct current power supply VDD) and the third resistor R3 (connected with the ground) form a voltage dividing circuit, and a stable reference voltage is formed at the positive end voltage lifting output end after voltage division by the direct current power supply VDD .

[0036] It should be noted that the low-level fault signal or high-level recovery signal output by the detection comparator U1 is directly connected to the positive end voltage lifting output end (connected with the voltage dividing node of the second resistor R2 and the third resistor R3): when a fault is detected, the detection comparator U1 outputs a low-level fault signal, which pulls the voltage at the positive input end of the latch comparator U2 to be lower than the voltage at the negative input end of the latch comparator U2, triggering the latch comparator U2 to output a latched low-level fault signal (latched fault); when the fault is recovered, the detection comparator U1 outputs a high-level recovery signal, which directly lifts the node voltage through the high-level driving capability, so that the positive input end of the latch comparator U2 recovers to high level, laying a foundation for subsequent automatic unlocking through the clamping diode D1.

[0037] In some embodiments, the positive end voltage lifting sub-circuit 10 further comprises a second capacitor C2, which is connected in parallel with the third resistor R3.

[0038] It should be noted that the voltage dividing circuit composed of the second resistor R2 and the third resistor R3 provides a reference voltage (i.e. the positive terminal voltage is raised to the output terminal voltage) for the positive input terminal of the latch comparator U2, but the reference voltage may fluctuate due to the DC power supply VDD ripple, circuit noise and the like; after the second capacitor C2 and the third resistor R3 are connected in parallel, an RC filter structure is formed, the high-frequency noise (such as power supply ripple, electromagnetic interference spikes) in the reference voltage is filtered out through the capacitor to ground, and the reference voltage of the positive terminal voltage raised to the output terminal is smoother and more stable.

[0039] It should be noted that the "low-level fault signal" or "high-level recovery signal" output by the detection comparator U1 is directly connected to the positive terminal voltage raised to the output terminal, and there may be edge jitter (high-frequency glitches) when the signal switches (such as the moment of fault occurrence / disappearance). The charge and discharge characteristics of the second capacitor C2 can slow down the signal transition speed, smooth the signal edges, and suppress jitter.

[0040] In some embodiments, the negative terminal and output terminal voltage control sub-circuit 20 includes: The negative terminal and output terminal voltage control sub-circuit 20 includes: The fifth resistor R5 has one end connected to the negative terminal and output terminal voltage control sub-circuit 20 and the other end connected to the output terminal of the latch comparator U2. The sixth resistor R6 has one end connected to the output terminal of the latch comparator U2 and the other end connected to the DC power supply VDD.

[0041] It should be noted that the sixth resistor R6 (connected to the DC power supply VDD) is connected to the output terminal of the latch comparator U2 to provide high-level driving capability for the output terminal of the latch comparator U2; the fifth resistor R5 connects the output terminal of the latch comparator U2 and the negative terminal and output terminal voltage control sub-circuit 20 (the negative input terminal of the latch comparator U2) to form a positive feedback loop: when a fault occurs, the latch comparator U2 outputs a latched low-level fault signal (latched fault), which is passed through the fifth resistor R5 to make the negative terminal and output terminal voltage control sub-circuit 20 discharge through the negative terminal and output terminal voltage control sub-circuit 20 to lower the voltage of the negative input terminal of the latch comparator U2.

[0042] It should be noted that the negative terminal pressure storage and release module 210 (usually a capacitor) dynamically adjusts the voltage of the negative terminal pressure storage and release control end through the charge and discharge characteristics: that is, when fault latching, the latch comparator U2 outputs a low level (i.e. latch low level fault signal), the negative terminal pressure storage and release module 210 discharges through the fifth resistor R5, and the voltage of the negative input end of the latch comparator U2 continues to decrease; when fault recovery, the positive input end of the latch comparator U2 is clamped to the forward voltage drop VF (i.e. forward clamping voltage, such as 0.7V) through the clamping diode D1, at this time the negative terminal pressure storage and release module 210 continues to discharge, and when the voltage of the negative input end of the latch comparator U2 decreases to less than or equal to the forward clamping voltage, the latch comparator U2 flips to output a high level (i.e. latch high level signal) due to "positive input end ≥ negative input end", and the automatic unlocking is completed. This dynamic adjustment enables the voltage of the negative input end of the latch comparator U2 to follow the fault state changes and accurately match the unlocking conditions without external intervention.

[0043] In some embodiments, the negative terminal and output terminal voltage control subcircuit 20 further comprises a fourth capacitor C4, one end of the fourth capacitor C4 being connected to the output end of the latch comparator U2, and the other end of the fourth capacitor C4 being connected to the circuit ground GND.

[0044] It should be noted that the fourth capacitor C4 can filter out high-frequency noise (such as sharp pulses and glitches) generated at the output end of the latch comparator U2 due to circuit switching actions and electromagnetic interference through the "high-frequency grounding" characteristics, so that the output latch signal (low level fault signal or high level recovery signal) is smoother and more stable; and when the latch comparator U2 switches between "low level latching and high level unlocking" states (such as when the output end changes from low level to high level after the fault disappears), the edge of the output signal may be dithered (rapidly high-low jumps) due to circuit parasitic parameters, and the fourth capacitor C4 can delay the level change speed of the output end, smooth the signal edge, and reduce the dithering in the switching process through the charge and discharge characteristics.

[0045] In some embodiments, the negative terminal pressure storage and release module 210 comprises a fourth resistor R4 and a third capacitor C3 connected in parallel.

[0046] It should be noted that the upper ends of the fourth resistor R4 and the third capacitor C3 are the pressure storage and release grounding ends, and the lower ends of the fourth resistor R4 and the third capacitor C3 are the negative terminal pressure storage and release control ends; the third capacitor C3 is the main energy storage and release element, discharges through the fifth resistor R5 during fault latching, and continuously decreases the voltage of the negative terminal pressure storage and release control end; the fourth resistor R4 is connected in parallel with the third capacitor C3 to provide an additional discharge path for the capacitor, avoiding "slow discharge" or "voltage residue" caused by too small capacitor leakage current or too large discharge path impedance; when the fault disappears and enters the unlocking stage, the latch comparator U2 outputs a latch high level signal, at this time the pressure storage and release module needs to charge to restore the voltage of the negative terminal pressure storage and release control end to the initial voltage .

[0047] In some embodiments, the resistance of the second resistor R2 is equal to the resistance of the sixth resistor R6, and the resistance of the third resistor R3 is equal to the resistance of the fourth resistor R4.

[0048] It should be noted that the second resistor R2 and the third resistor R3 form a voltage dividing network of the positive terminal voltage lifting sub-circuit 10, and the reference voltage is The sixth resistor R6, the fifth resistor R5, and the fourth resistor R4 of the negative terminal storage and discharge voltage module 210 form a negative terminal initial voltage network (in a normal state, the latch comparator U2 outputs a high level, and charges the negative terminal through R6 and R5), and the negative terminal initial voltage is When R2=R6 and R3=R4, the voltage dividing ratio of the positive and negative terminals of the latch comparator U2 forms a symmetrical relationship, which is more easily ensured by parameter design that V OUT2-Normal >V INP2-Normal >V INN2-Normal Wherein, the values of the second capacitor C2 and the fourth capacitor C4 need to consider the compatibility of filtering and response time, and can be selected from 100pF to 1nF.

[0049] In some embodiments, the fault signal latching circuit further comprises a driving control unit 40 (or driving control unit 40), which comprises: A digital signal processor connected to the output end of the latch comparator U2; A driving AND gate U3 having a first input end, a second input end, and an AND gate output end, the first input end being connected to the output end of the latch comparator U2, the second input end being connected to the driving control signal output end of the digital signal processor, and the AND gate output end being connected to the power tube of the target system.

[0050] It should be noted that the first input end (1A) of the driving AND gate U3 is connected to the latch signal output by the latch comparator U2 (low level indicating fault, high level indicating normal), and the second input end (1B) of the driving AND gate U3 is connected to the driving control signal (such as PWM signal) output by the DSP; so that only when the "latch signal is high (no fault)" and the "DSP driving control signal is effective (such as PWM high level)", the AND gate output end (1Y) will output the driving signal to the power tube; if the latch signal is low (fault), no matter what driving signal is output by the DSP, the AND gate will output low level, forcibly cutting off the power tube driving, which does not need to be judged by the DSP software, and can instantly cut off the driving when the fault occurs, with a response speed much faster than pure software protection, which can solve the problem of fault expansion caused by software detection delay in traditional solutions.

[0051] It should be noted that the DSP is connected with the output end of the latch comparator U2, and the latch signal state can be detected in real time through software: when a fault occurs, the DSP detects a low-level fault signal, and can perform a protection action (such as turning off the PWM output, cutting off the system power supply, etc.); when normal, the DSP drives the power tube through the output PWM signal and the AND gate, to realize fine control of the speed and voltage of the load, and the double-layer mechanism of “hardware priority cutting off + software subsequent processing” not only ensures the rapid protection (hardware) in the fault moment, but also retains the flexibility of system control (software), and takes into account reliability and functionality.

[0052] It should be noted that, as shown in Fig. 2 , at 0-t1, when no fault occurs, the voltage at the positive input end INP2 of the latch comparator U2 is: ; the voltage at the negative input end INN2 of the latch comparator U2 is: At 0-t1, when no fault occurs, the voltage at the positive input end INP2 of the latch comparator U2 is greater than the voltage at the negative input end INN2 of the latch comparator U2, that is, V INP2-Normal >V INN2-Normal ; the voltage at the output end OUT2 of the latch comparator U2 is ; wherein, in the circuit design, when normal, that is, when no fault occurs, the clamping diode D1 needs to be reverse-biased, so the voltage at the output end OUT2 of the latch comparator U2 needs to be greater than the voltage at the positive input end INP2 of the latch comparator U2, that is, V OUT2-Normal >V INP2-Normal ; in summary, when normal, that is, when no fault occurs, the values of R2, R3, R4, R5 and R6 need to satisfy V OUT2-Normal >V INP2-Normal >V INN2-Normal R2=R6, R3=R4, and C2 and C4 have values compatible with filtering and response time, and can be 100pF~1nF.

[0053] At t1, when a fault is detected, the fault detection unit 30 outputs a low-level fault signal, that is, the positive input end INP2 of the latch comparator U2 is at a low level, at this moment, the voltage at the positive input end INP2 of the latch comparator U2 is lower than the voltage at the negative input end INN2 of the latch comparator U2, resulting in that the latch comparator U2 outputs a low level, at this moment, the third capacitor C3 is discharged through the fourth resistor R4 and the fifth resistor R5, and the voltage at the negative input end INN2 of the latch comparator U2 gradually decreases.

[0054] At t2, the fault disappears, the fault detection unit 30 outputs a high level (i.e. a high level recovery signal), i.e. the positive input end INP2 of the latch comparator U2 is at a high level, and the output end OUT2 of the latch comparator U2 is at a low level, and due to the existence of the clamping diode D1, the clamping diode D1 is forward-biased, and the voltage of the positive input end INP2 of the latch comparator U2 is clamped to the forward voltage drop VF of the clamping diode D1.

[0055] At t3, when the third capacitor C3 continuously discharges, the voltage of the negative input end of the latch comparator U2 is equal to the forward voltage drop VF of the clamping diode D1, i.e. the voltage of the negative input end of the latch comparator U2 is equal to the voltage of the positive input end of the latch comparator U2, the output end of the latch comparator U2 starts to recover to a high level.

[0056] Wherein the time from t1 to t2 is the fault triggering time T-Faults, and the time from t1 to t3 is the fault latch time T-LOCK, and the fault latch time T-LOCK is: Wherein the forward-biased voltage drop VF of the clamping diode D1 is affected by the forward-biased current ID1 and the working temperature, thereby affecting the latch time, the forward-biased current ID1 of the clamping diode D1 is According to the forward-biased current ID1 and the working temperature of the circuit, the forward-biased voltage drop VF of the clamping diode D1 can be determined by referring to the specification book of the clamping diode D1, and considering the worst working temperature, when the forward voltage drop VF of the diode D1 is the largest, the fault latch time T-LOCK is the shortest, and the design requirements can still be met.

[0057] It should be noted that at 0-t1, no fault is triggered, the latch comparator U2 outputs a high level, and the output signal Drive of the AND gate U3 is determined by the PWM signal; at t1-t3, the latch comparator U2 outputs a low level, and the output signal Drive of the AND gate U3 outputs a low level, and the power tube drive is immediately turned off, and after the DSP detects the fault signal, the PWM output is turned off; wherein the fault latch time T-LOCK needs to be greater than the time for the DSP to turn off the PWM output, and the fault latch time T-LOCK can be designed to be greater than 100us, so that when the fault occurs, the power tube drive can be first turned off on the hardware, and the software can detect the fault signal within the fault latch time to turn off the PWM output, thereby realizing the functions of quickly protecting the system and effectively detecting the fault signal, and after the fault disappears and the latch time is reached, the high level can be automatically recovered, without the need for an additional unlocking circuit or unlocking signal.

[0058] It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order

[0059] Although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first", "second", and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

[0060] The above description is merely illustrative of the application and not restrictive. Various modifications can be made to the embodiments described without departing from the spirit or scope of the application. Accordingly, the application is not to be restricted based on the specific examples described above, but is to be defined in the terms of the claims presented below.

Claims

1. A fault signal latching circuit, characterized in that, include: A latch comparator, whose positive input is used to receive low-level fault signals and high-level recovery signals; A positive voltage boosting sub-circuit has a positive voltage boosting output terminal, which is connected to the positive input terminal of the latch comparator. The negative terminal and output terminal voltage control sub-circuit has a negative terminal voltage storage and discharge module and an output terminal voltage control terminal. The negative terminal voltage storage and discharge module is connected to the negative input terminal of the latch comparator, and the output terminal voltage control terminal is connected to the output terminal of the latch comparator. A clamping diode, the anode of which is connected to the positive input terminal and the positive voltage boost output terminal of the latch comparator, and the cathode of which is connected to the output terminal of the latch comparator; Wherein, the voltage value of the output voltage control terminal is greater than the voltage value of the positive voltage boost output terminal, and the voltage value of the positive voltage boost output terminal is greater than the output voltage value of the negative voltage storage module. When the low-level fault signal is received, the latch comparator outputs a latch low-level fault signal, causing the negative voltage storage module to discharge and reduce voltage. When the high-level recovery signal is received, the voltage at the positive input terminal of the latch comparator is clamped to the positive clamp voltage through the clamping diode. When the output voltage value of the negative voltage storage module is less than or equal to the positive clamp voltage, a latch high-level signal is output.

2. The fault signal latching circuit according to claim 1, characterized in that, It also includes a fault detection unit, which comprises: The first resistor has its input terminal connected to the target system and is used to receive the sampling signal of the target system. The detection comparator has its negative input connected to the output of the first resistor, its positive input connected to the input of a preset reference voltage, and its output connected to the positive input of the latch comparator.

3. The fault signal latching circuit according to claim 2, characterized in that, The fault detection unit further includes a first capacitor, one end of which is connected to the output terminal of the first resistor and the negative input terminal of the detection comparator, and the other end of which is connected to the circuit ground.

4. The fault signal latching circuit according to claim 2, characterized in that, The positive terminal voltage boosting sub-circuit includes: The second resistor has a second power supply terminal and the positive voltage boost output terminal. The second power supply terminal is connected to a DC power supply, and the positive voltage boost output terminal is connected to the output terminal of the detection comparator and the positive input terminal of the latch comparator. The third resistor has one end connected to the positive voltage boost output terminal and the other end connected to the circuit ground.

5. The fault signal latching circuit according to claim 4, characterized in that, The positive terminal voltage boosting sub-circuit also includes a second capacitor, which is connected in parallel with the third resistor.

6. The fault signal latching circuit according to claim 4, characterized in that, The voltage control sub-circuit for the negative terminal and the output terminal includes: The negative-terminal storage and discharge module has a storage and discharge voltage grounding terminal and a negative-terminal storage and discharge voltage control terminal. The storage and discharge voltage grounding terminal is connected to the circuit ground, and the negative-terminal storage and discharge voltage control terminal is connected to the negative input terminal of the latch comparator. The fifth resistor has one end connected to the negative terminal of the storage and discharge voltage control terminal and the other end connected to the output terminal of the latch comparator. The sixth resistor has one end connected to the output terminal of the latch comparator and the other end connected to the DC power supply.

7. The fault signal latching circuit according to claim 6, characterized in that, The negative terminal and output terminal voltage control sub-circuit also includes a fourth capacitor, one end of which is connected to the output terminal of the latch comparator, and the other end of which is connected to the circuit ground.

8. The fault signal latching circuit according to claim 6, characterized in that, The negative-end voltage storage and discharge module includes a fourth resistor and a third capacitor connected in parallel.

9. The fault signal latching circuit according to claim 8, characterized in that, The resistance value of the second resistor is equal to the resistance value of the sixth resistor, and the resistance value of the third resistor is equal to the resistance value of the fourth resistor.

10. The fault signal latching circuit according to any one of claims 1-9, characterized in that, It also includes a drive control unit, which includes: A digital signal processor is connected to the output of the latch comparator; The drive AND gate has a first input terminal, a second input terminal, and an AND gate output terminal. The first input terminal is connected to the output terminal of the latch comparator, the second input terminal is connected to the drive control signal output terminal of the digital signal processor, and the AND gate output terminal is connected to the power transistor of the target system.

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