High-speed high-linearity grid voltage bootstrapped switch circuit

Abstract

The invention relates to a high-speed high-linearity gate voltage bootstrapped switch circuit. The high-speed high-linearity gate voltage bootstrapped switch circuit comprises a gate voltage bootstrapped switch main circuit module, an anti-creeping module, a parasitic capacitance reducing module and an acceleration establishment module. The method has the main advantages that the acceleration establishment module is added, the node is charged to the power voltage VDD in advance by the acceleration establishment module, and then the node is continuously charged to VDD + Vin, so that the establishment time can be remarkably shortened, and the sampling accuracy is improved under high-speed sampling. Compared with a traditional scheme, the sampling speed of the grid voltage bootstrapped switch is improved, meanwhile, very high sampling precision can be met, and the high-speed high-precision SAR analog-to-digital converter is suitable for being used in a high-speed high-precision SAR analog-to-digital converter.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design, specifically relating to a high-speed, high-linearity gate voltage bootstrap switching circuit, which is mainly used in successive approximation analog-to-digital converters. Background Technology

[0002] Gate voltage bootstrap switching circuits are widely used in analog-to-digital converters (ADCs), such as the common successive approximation ADC (SAR ADC). In high-performance SAR ADCs, the gate voltage bootstrap switch plays a crucial role, and its accuracy and speed directly affect the accuracy and speed of the ADC.

[0003] A gate-voltage bootstrap switch is a circuit used to transmit external analog signals into an ADC chip for processing. It has two operating phases: sampling and holding. During the sampling phase, the gate-voltage bootstrap switch is open, transmitting the input signal; during the holding phase, the gate-voltage bootstrap switch is closed, holding the voltage value at the moment of shutdown and inputting it into the ADC chip for quantization encoding. Because gate-voltage bootstrap switches maintain high linearity even at high speeds, they are widely used in high-speed, high-linearity mixed-signal circuits.

[0004] Typically, the sampling speed of a gate-voltage bootstrap switch is inversely proportional to its sampling accuracy; that is, the faster the sampling speed, the lower the sampling accuracy. However, when the sampling speed is too fast, the auxiliary circuit may not be able to raise the gate voltage of the main switch to VDD+Vin in time. This causes the main switch to be unable to transmit the input signal with a constant on-resistance, resulting in errors in the signal voltage value during the hold state and reducing the linearity of the entire ADC chip. For example, in high-speed successive approximation analog-to-digital converters, the gate-voltage bootstrap switch may cause input signal distortion, thereby affecting the normal operation of circuits such as quantization and encoding, becoming a major source of low linearity. Improving the sampling speed of the gate-voltage bootstrap switch is of great significance. In a common gate-voltage bootstrap switch, the node Vg7 signal is continuously charged from 0 potential to VDD+Vin when the rising edge of the sampling clock CLKs arrives, allowing the NMOS transistor M7 to smoothly transmit the input signal Vin. However, for high-speed gate-voltage bootstrap switches, this charging process takes a long time, which is not conducive to the complete establishment of the signal, thus limiting the accuracy of the gate-voltage bootstrap switch.

[0005] Meanwhile, the comparator is also a crucial module in SAR ADCs. The latch within the comparator converts the voltage signal to be compared into current signals of varying magnitudes. Based on the difference in current magnitude, the corresponding node potential decreases at different rates. Once a node potential first drops to the turn-on voltage of the pull-up PMOS transistor, the latch immediately enters a positive feedback mechanism, thus distinguishing the voltage difference signal to be compared. Traditional latches reset the output node to the power supply voltage VDD, and then decrease it at different rates to VDD-VDD.TH Then, a positive feedback mechanism is entered. However, the latching time can be reduced by adjusting the reset voltage. For example, the academic paper with DOI number 10.1109 / ISCAS51556.2021.9401172 proposes a high-speed two-stage dynamic comparator. By adjusting the size of the reset transistor PMOS, the output node potential is reset to 1 / 2VDD instead of VDD, which can significantly shorten the latching time and improve the comparison speed. Based on this design idea, this invention patent has made an innovative design on the traditional gate voltage bootstrap switch.

[0006] A search revealed application publication number CN112383292B, which discloses a high-speed, high-linearity gate-voltage bootstrap switching circuit. Traditional gate-voltage bootstrap switching circuits have very limited signal setup time under high-speed sampling. If the sampling speed is too fast, incomplete signal setup can lead to decreased sampling accuracy, significantly limiting the sampling speed of traditional gate-voltage bootstrap switching circuits. While adding a module to reduce parasitic capacitance can improve accuracy, it still doesn't effectively solve the speed problem. By adding an acceleration module, PMOS transistor M16, the signal can be established earlier, shortening the setup time. This allows for a high sampling speed even under high-precision sampling, making this invention highly promising for applications in high-speed, high-linearity analog-to-digital converters. Summary of the Invention

[0007] To address the aforementioned problems with gate-voltage bootstrap switches in high-speed sampling, and drawing upon the design principles of the high-speed comparators mentioned above, this invention proposes a high-speed, high-linearity gate-voltage bootstrap switch circuit that achieves higher sampling accuracy even at high speeds. Furthermore, this circuit is less affected by parasitic capacitance, resulting in higher sampling accuracy.

[0008] The technical solution of the present invention is as follows:

[0009] A high-speed, high-linearity gate voltage bootstrap switching circuit includes: a gate voltage bootstrap switch main circuit module, a leakage current protection module, a parasitic capacitance reduction module, and an accelerated setup module; wherein the gate voltage bootstrap switch main circuit module is connected to the leakage current protection module, the parasitic capacitance reduction module, and the accelerated setup module, respectively.

[0010] The gate voltage bootstrap switch main circuit module charges the bootstrap capacitor and outputs a constant gate-source voltage to the NMOS switching transistor under clock control, enabling the switching transistor to transmit the input signal Vin with a constant on-resistance. The leakage prevention module is used to prevent charge loss at the gate node Vg of the switching transistor during the setup phase. The parasitic capacitance reduction module is used to eliminate the parasitic capacitance between the N-well of the PMOS and the substrate, thereby reducing the parasitic capacitance of the upper-level board node Vtp of the bootstrap capacitor. The setup acceleration module is used to charge node Vg7 in advance to shorten the setup time.

[0011] Furthermore, the gate voltage bootstrap switch main circuit module includes NMOS transistors Min, M2, M4, M6, M7, M8, M9, M11, M12, PMOS transistors M1, M3, M5, and M10, and a bootstrap capacitor Cb. The drain of NMOS transistor Min is connected to one end of the sampling capacitor Cs. The source of NMOS transistor Min is connected to the drain of NMOS transistor M7 and the input signal Vin. The gate of NMOS transistor Min is connected to the gate of PMOS transistor M1, the gate of PMOS transistor M5, the drain of NMOS transistor M8, and... The gate of PMOS transistor M13 is connected to the power supply voltage VDD. The drain of PMOS transistor M1 is connected to the upper stage of bootstrap capacitor Cb, the source of PMOS transistor M10, and the source of PMOS transistor M5. The source of NMOS transistor M2 is connected to ground. The drain of NMOS transistor M2 is connected to the lower stage of bootstrap capacitor Cb, the lower stage of bootstrap capacitor Cbx, the drain of NMOS transistor M14, the source of NMOS transistor M4, the source of NMOS transistor M6, and the source of NMOS transistor M7. The gate of NMOS transistor M2 is connected to the gate of NMOS transistor M12, the gate of PMOS transistor M16, the gate of NMOS transistor M14, the gate of NMOS transistor M9, and PM10. The gate of transistor M15 is connected to the sampling clock inversion signal CKs_F. The source of PMOS transistor M3 is connected to the power supply voltage VDD. The drain of PMOS transistor M3 is connected to the drain of NMOS transistors M4 and M6, the gate of PMOS transistor M5, and the gate of PMOS transistor M10. The gate of PMOS transistor M3 is connected to the gate of NMOS transistor M4 and the sampling clock CKs. The gate of NMOS transistor M6 is connected to the gate of NMOS transistor M7, the drain of NMOS transistor M11, and the drain of PMOS transistor M10. The gate of NMOS transistor M8 is connected to the source of PMOS transistor M15 and the power supply voltage. The source of NMOS transistor M8 is connected to NM... The drains of NMOS transistor M9 and PMOS transistor M15 are connected, the source of NMOS transistor M9 is connected to ground, the gate of NMOS transistor M11 is connected to the power supply voltage VDD, the source of NMOS transistor M11 is connected to the drain of NMOS transistor M12 and the drain of PMOS transistor M16, and the source of NMOS transistor M12 is connected to ground. PMOS transistors M10, M11, and M12 provide gate control signals for NMOS transistors M6 and M7, and can accelerate the establishment of node Vg7, enabling NMOS transistor M7 to smoothly transmit Vin. Cb is a bootstrap capacitor, which is charged by PMOS transistors M1 and M2 until its potential reaches the power supply voltage VDD.Under clock control, the upper-stage voltage Vtp of the bootstrap capacitor is raised to VDD+Vin, and then transmitted to the gate of NMOS transistor Min through PMOS transistor M5. At this time, the gate-source voltage of NMOS transistor Min is constant at VDD, and Vin can be smoothly transmitted with a constant on-resistance. NMOS transistors M8 and M9 are used to turn off NMOS transistor Min. PMOS transistors M3 and M4 are used to control PMOS transistors M5 and M10. NMOS transistor M6 is used to prevent Vsg of PMOS transistor M5 from deviating from VDD, so that the build-up speed of Vg does not change with the input signal.

[0012] Furthermore, the leakage protection module is implemented by a PMOS transistor M15. The source of the PMOS transistor M15 is connected to the gate of the NMOS transistor M8 and the power supply voltage VDD, respectively. The drain of the PMOS transistor M15 is connected to the drain of the NMOS transistor M9 and the source of the NMOS transistor M8, respectively. The gate of the PMOS transistor M15 is connected to the sampling clock inversion signal CKs_F. When the rising edge of the sampling clock CKs arrives, the PMOS transistor M15 turns on and charges node Vd9, causing node Vd9 to rise rapidly to VDD-Vthn, thus turning off the NMOS transistor M8. Vthn is the threshold voltage of the NMOS transistor, preventing charge from flowing to node Vd9 during the setup phase of node Vg.

[0013] Furthermore, the parasitic capacitance reduction module comprises a PMOS transistor M13, an NMOS transistor M14, and a bootstrap capacitor Cbx. The drain of PMOS transistor M13 is connected to the power supply voltage VDD. The source of PMOS transistor M13 is connected to the substrate of PMOS transistor M13, the upper plate of bootstrap capacitor Cbx, the source of PMOS transistor M10, the substrate of PMOS transistor M10, the source of PMOS transistor M1, the substrate of PMOS transistor M1, the source of PMOS transistor M5, and the substrate of PMOS transistor M5. The gate of PMOS transistor M13 is connected to the gate of NMOS transistor Min and the gate of NMOS transistor M14. The drain of transistor M8, the gate of PMOS transistor M1, and the drain of PMOS transistor M5 are connected. The source of NMOS transistor M14 is connected to ground. The drain of NMOS transistor M14 is connected to the lower stage of bootstrap capacitor Cbx, the lower stage of bootstrap capacitor Cb, the drain of NMOS transistor M2, the source of NMOS transistor M4, the source of NMOS transistor M6, and the source of NMOS transistor M7. The gate of NMOS transistor M14 is connected to the sampling clock inversion signal CKs_F, and its connection relationship with PMOS transistors M1, NMOS transistor M2, and bootstrap capacitor Cb is the same. Therefore, the voltages of nodes Vtpx and Vtp change synchronously. At the same time, the substrates of PMOS transistors M1, M5, and M10 are connected to node Vtpx, and the parasitic capacitance of node Vtp eliminates the parasitic capacitance between the N-well of the PMOS transistor and the substrate.

[0014] Furthermore, the accelerated setup module includes a PMOS transistor M16. The source of the PMOS transistor M16 is connected to the power supply voltage. The drain of the PMOS transistor M16 is connected to the drain of the NMOS transistor M12 and the source of the NMOS transistor M11. The gate of the PMOS transistor M16 is connected to the gate of the NMOS transistor M14, the gate of the NMOS transistor M12, the gate of the NMOS transistor M2, and the sampling clock inversion signal CKs_F. When the rising edge of the sampling clock CKs arrives, the PMOS transistor M16 is turned on, charging node Vg7 to VDD in advance, and then continuously charging it to VDD+Vin, thereby accelerating the setup speed.

[0015] Furthermore, during the sampling phase, when the rising edge of the sampling clock CKs arrives, node Vg5 drops from VDD to a low potential. At this time, PMOS transistors M5 and M10 are turned on, and the potential of node Vg7 rises rapidly to VDD, causing NMOS transistors M6 and M7 to turn on. Nodes Vg5 and Vbp gradually rise to Vin, and node Vtp rises to VDD+Vin due to the conservation of capacitor charge. It also continuously charges node Vg7 to VDD+Vin through PMOS transistor M10. At the same time, node Vg is also charged to VDD+Vin through PMOS transistor M5. At this time, NMOS transistor Min is turned on with a constant on-resistance, and the output signal Vout follows the change of the input signal Vin.

[0016] During the hold phase, when the falling edge of the sampling clock CKs arrives, NMOS transistor M9 turns on, causing node Vg to be quickly pulled down to a low potential, resulting in NMOS transistor Min turning off. The output signal Vout remains at the voltage value at the moment of the falling edge. Node Vg5 is raised to VDD by PMOS transistor M3, turning off PMOS transistors M5 and M10. At the same time, PMOS transistors M1 and M2 turn on, charging the bootstrap capacitor Cb to VDD in preparation for the next sampling.

[0017] The advantages and beneficial effects of this invention are as follows:

[0018] In the high-speed, high-linearity gate voltage bootstrap switch circuit proposed in this invention, an acceleration module PMOS transistor M16 is introduced. The source of PMOS transistor M16 is connected to the power supply voltage, and the drain of PMOS transistor M16 is connected to the drain of NMOS transistor M12 and the source of NMOS transistor M11. The gate of PMOS transistor M16 is connected to the gate of NMOS transistor M14, the gate of NMOS transistor M12, the gate of NMOS transistor M2, and the sampling clock inversion signal CKs_F. When the rising edge of the sampling clock CKs arrives, node Vg7 is charged to VDD in advance, and then continuously charged to VDD+Vin, which speeds up the setup speed and effectively solves the problem of low sampling accuracy caused by the gate voltage bootstrap switch due to the high sampling speed. It is very suitable for the sample-and-hold circuit of high-speed, high-precision SAR ADC. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a high-speed, high-linearity gate voltage bootstrap switching circuit according to a preferred embodiment of the present invention.

[0020] Figure 2 This invention provides a preferred embodiment of a high-speed, high-linearity gate voltage bootstrap switching circuit, which establishes key signal curves.

[0021] Figure 3 This invention provides a preferred embodiment of a high-speed, high-linearity gate voltage bootstrap switching circuit, showing the transient waveform simulation of key nodes.

[0022] Figure 4 The present invention provides a preferred embodiment of the input and output transient simulation diagram of a high-speed, high-linearity gate voltage bootstrap switching circuit.

[0023] Figure 5 This invention provides a preferred embodiment of a high-speed, high-linearity gate voltage bootstrap switching circuit and a conventional circuit, along with an FFT analysis diagram of the sampling results. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0025] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0026] In this embodiment, an acceleration module PMOS transistor M16 is introduced. When the rising edge of the sampling control clock CKs arrives, node Vg7 is charged to the power supply voltage VDD in advance through PMOS transistor M16, and then continuously charged to VDD+Vin, which significantly shortens the setup time and improves the sampling accuracy under high-speed sampling.

[0027] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0028] Example

[0029] In specific implementation methods, such as Figure 1 As shown, the complete circuit of the high-speed, high-linearity gate voltage bootstrap switch of the present invention mainly consists of four modules: a gate voltage bootstrap switch main circuit module, a leakage current prevention module, a parasitic capacitance reduction module, and an accelerated setup module. The gate voltage bootstrap switch main circuit module is connected to the leakage current prevention module, the parasitic capacitance reduction module, and the accelerated setup module, respectively.

[0030] The gate voltage bootstrap switch main circuit module charges the bootstrap capacitor and outputs a constant gate-source voltage to the NMOS switching transistor under clock control, enabling the switching transistor to transmit the input signal Vin with a constant on-resistance. The leakage prevention module is used to prevent charge loss at the gate node Vg of the switching transistor during the setup phase. The parasitic capacitance reduction module is used to eliminate the parasitic capacitance between the N-well of the PMOS and the substrate, thereby reducing the parasitic capacitance of the upper-level board node Vtp of the bootstrap capacitor. The setup acceleration module is used to charge node Vg7 in advance to shorten the setup time.

[0031] The gate voltage bootstrap switch main circuit module includes NMOS transistors Min, M2, M4, M6, M7, M8, M9, M11, M12, PMOS transistors M1, M3, M5, and M10, and a bootstrap capacitor Cb. The drain of NMOS transistor Min is connected to one end of the sampling capacitor Cs. The source of NMOS transistor Min is connected to the drain of NMOS transistor M7 and the input signal Vin. The gate of NMOS transistor Min is connected to the gate of PMOS transistor M1, the gate of PMOS transistor M5, the drain of NMOS transistor M8, and the PMOS transistor Cb. The gate of transistor M13 is connected to the ground plane. The source of PMOS transistor M1 is connected to the power supply voltage VDD. The drain of PMOS transistor M1 is connected to the upper stage of bootstrap capacitor Cb, the source of PMOS transistor M10, and the source of PMOS transistor M5. The source of NMOS transistor M2 is connected to ground. The drain of NMOS transistor M2 is connected to the lower stage of bootstrap capacitor Cb, the lower stage of bootstrap capacitor Cbx, the drain of NMOS transistor M14, the source of NMOS transistor M4, the source of NMOS transistor M6, and the source of NMOS transistor M7. The gate of NMOS transistor M2 is connected to the gate of NMOS transistor M12, the gate of PMOS transistor M16, the gate of NMOS transistor M14, the gate of NMOS transistor M9, and the gate of PMOS transistor M16. The gate of transistor M15 is connected to the sampling clock inversion signal CKs_F. The source of PMOS transistor M3 is connected to the power supply voltage VDD. The drain of PMOS transistor M3 is connected to the drain of NMOS transistors M4 and M6, the gate of PMOS transistor M5, and the gate of PMOS transistor M10. The gate of PMOS transistor M3 is connected to the gate of NMOS transistor M4 and the sampling clock CKs. The gate of NMOS transistor M6 is connected to the gate of NMOS transistor M7, the drain of NMOS transistor M11, and the drain of PMOS transistor M10. The gate of NMOS transistor M8 is connected to the source of PMOS transistor M15 and the power supply voltage. The source of NMOS transistor M8 is connected to the NMOS transistor M15 and the sampling clock CKs_F. The drain of S-MOSFET M9 and the drain of PMOS transistor M15 are connected. The source of NMOS transistor M9 is connected to ground. The gate of NMOS transistor M11 is connected to the power supply voltage VDD. The source of NMOS transistor M11 is connected to the drain of NMOS transistor M12 and the drain of PMOS transistor M16. The source of NMOS transistor M12 is connected to ground. PMOS transistors M10, M11, and M12 provide gate control signals for NMOS transistors M6 and M7, and can accelerate the establishment of node Vg7, enabling NMOS transistor M7 to smoothly transmit Vin. Cb is a bootstrap capacitor, which is charged by PMOS transistors M1 and M2 until its potential reaches the power supply voltage VDD.Under clock control, the upper-stage voltage Vtp of the bootstrap capacitor is raised to VDD+Vin, and then transmitted to the gate of NMOS transistor Min through PMOS transistor M5. At this time, the gate-source voltage of NMOS transistor Min is constant at VDD, and Vin can be smoothly transmitted with a constant on-resistance. NMOS transistors M8 and M9 are used to turn off NMOS transistor Min. PMOS transistors M3 and M4 are used to control PMOS transistors M5 and M10. NMOS transistor M6 is used to prevent Vsg of PMOS transistor M5 from deviating from VDD, so that the build-up speed of Vg does not change with the input signal.

[0032] The leakage protection module is implemented by a PMOS transistor M15. The source of the PMOS transistor M15 is connected to the gate of the NMOS transistor M8 and the power supply voltage VDD, respectively. The drain of the PMOS transistor M15 is connected to the drain of the NMOS transistor M9 and the source of the NMOS transistor M8, respectively. The gate of the PMOS transistor M15 is connected to the sampling clock inversion signal CKs_F. When the rising edge of the sampling clock CKs arrives, the PMOS transistor M15 turns on and charges node Vd9, causing node Vd9 to rise rapidly to VDD-Vthn, which turns off the NMOS transistor M8. Vthn is the threshold voltage of the NMOS transistor, preventing charge from flowing to node Vd9 during the setup phase of node Vg.

[0033] The parasitic capacitance reduction module consists of a PMOS transistor M13, an NMOS transistor M14, and a bootstrap capacitor Cbx. The drain of PMOS transistor M13 is connected to the power supply voltage VDD. The source of PMOS transistor M13 is connected to the substrate of PMOS transistor M13, the upper plate of bootstrap capacitor Cbx, the source of PMOS transistor M10, the substrate of PMOS transistor M10, the source of PMOS transistor M1, the substrate of PMOS transistor M1, the source of PMOS transistor M5, and the substrate of PMOS transistor M5. The gate of PMOS transistor M13 is connected to the gate of NMOS transistor Min and the drain of NMOS transistor M8. The gate of PMOS transistor M1 and the drain of PMOS transistor M5 are connected to the N-well of PMOS transistor M14. The source of NMOS transistor M14 is connected to ground. The drain of NMOS transistor M14 is connected to the lower stage of bootstrap capacitor Cbx, the lower stage of bootstrap capacitor Cb, the drain of NMOS transistor M2, the source of NMOS transistor M4, the source of NMOS transistor M6, and the source of NMOS transistor M7. The gate of NMOS transistor M14 is connected to the sampling clock inversion signal CKs_F, and its connection relationship with PMOS transistors M1, NMOS transistor M2, and bootstrap capacitor Cb is the same. Therefore, the voltages of nodes Vtpx and Vtp change synchronously. At the same time, the substrates of PMOS transistors M1, M5, and M10 are connected to node Vtpx, and the parasitic capacitance of node Vtp eliminates the parasitic capacitance between the N-well of the PMOS transistor and the substrate.

[0034] The accelerated setup module includes a PMOS transistor M16. The source of PMOS transistor M16 is connected to the power supply voltage. The drain of PMOS transistor M16 is connected to the drain of NMOS transistor M12 and the source of NMOS transistor M11. The gate of PMOS transistor M16 is connected to the gates of NMOS transistors M14, M12, and M2, as well as the sampling clock inversion signal CKs_F. When the rising edge of the sampling clock CKs arrives, PMOS transistor M16 turns on, charging node Vg7 to VDD in advance, and then continuously charging it to VDD+Vin, thus accelerating the setup speed. Compared to the traditional structure, the setup speed is accelerated by 38ps when node Vg7 reaches 90% of VDD+Vin, improving the overall sampling speed of the gate voltage bootstrap switch.

[0035] Please refer to the key node waveforms of the high-speed, high-linearity gate voltage bootstrap switch during the sampling and holding phase. Figure 3-1 and Figure 3-2 .

[0036] like Figure 3-1 As shown, during the sampling phase, when the rising edge of the sampling clock CKs arrives, node Vg5 drops from VDD to a low potential. At this time, PMOS transistors M5 and M10 are turned on, and the potential of node Vg7 rises rapidly to VDD, causing NMOS transistors M6 and M7 to turn on. Nodes Vg5 and Vbp gradually rise to Vin, and node Vtp rises to VDD+Vin due to the conservation of capacitor charge. It also continuously charges node Vg7 to VDD+Vin through PMOS transistor M10. At the same time, node Vg is also charged to VDD+Vin through PMOS transistor M5. At this time, NMOS transistor Min is turned on with a constant on-resistance, and the output signal Vout follows the change of the input signal Vin.

[0037] During the hold phase, when the falling edge of the sampling clock CKs arrives, NMOS transistor M9 turns on, causing node Vg to be quickly pulled down to a low potential, resulting in NMOS transistor Min turning off. The output signal Vout remains at the voltage value at the moment of the falling edge. Node Vg5 is raised to VDD by PMOS transistor M3, turning off PMOS transistors M5 and M10. At the same time, PMOS transistors M1 and M2 turn on, charging the bootstrap capacitor Cb to VDD in preparation for the next sampling.

[0038] Please refer to the key node waveform of the high-speed, high-linearity gate voltage bootstrap switch sampling one cycle of the input sine signal. Figure 4 .

[0039] Please refer to the FFT analysis graph of the sampling results of the high-speed, high-linearity gate voltage bootstrap switch and the conventional switching circuit at a near Nyquist sampling rate. Figure 5-1 and Figure 5-2 as well as Figure 5-3 .

[0040] like Figure 5-1 As shown, the traditional switching circuit without acceleration and parasitic capacitance reduction modules, with a sampling frequency of 50MHz, an input sine wave frequency of 23.9746MHz, and a sampling capacitor of 650fF, yields an ENOB of 14.26 bits, an SNDR of 87.62dB, an SFDR of 90.16dB, and a THD of -89.83dB when the output waveform is processed by FFT.

[0041] like Figure 5-2 As shown, by adding a parasitic capacitance reduction module to the traditional switching circuit, under the same test conditions, its ENOB is 14.28 bits, SNDR is 87.74 dB, SFDR is 90.91 dB, and THD is -90.58 dB. Compared with the traditional circuit, reducing the parasitic capacitance between the N-well of the PMOS and the substrate improves the output accuracy.

[0042] like Figure 5-3 As shown, this invention adds a parasitic capacitance reduction module and an acceleration module to a traditional switching circuit. Under the same test conditions, it achieves an ENOB of 14.40 bits, an SNDR of 88.49 dB, an SFDR of 92.76 dB, and a THD of -91.62 dB. Compared to traditional switching circuits, this invention's high-speed, high-linearity gate voltage bootstrap switch has better performance indicators, achieving a high sampling rate while meeting high accuracy requirements.

[0043] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high-speed, high-linearity gate voltage bootstrap switching circuit, characterized in that, include: The system includes a gate voltage bootstrap switch main circuit module, a leakage protection module, a parasitic capacitance reduction module, and an accelerated setup module; the gate voltage bootstrap switch main circuit module is connected to the leakage protection module, the parasitic capacitance reduction module, and the accelerated setup module, respectively. The gate voltage bootstrap switch main circuit module charges the bootstrap capacitor and, under clock control, outputs a constant gate-source voltage to the NMOS switching transistor, enabling the switching transistor to transmit the input signal Vin with a constant on-resistance. The leakage protection module is used to prevent charge loss at the gate node Vg of the switching transistor during the setup phase. The parasitic capacitance reduction module is used to eliminate the parasitic capacitance between the N-well of the PMOS and the substrate, thereby reducing the parasitic capacitance of the upper-level board node Vtp of the bootstrap capacitor. The setup acceleration module is used to charge node Vg7 in advance, shortening the setup time.

2. The high-speed, high-linearity gate voltage bootstrap switching circuit according to claim 1, characterized in that, The gate voltage bootstrap switch main circuit module includes NMOS transistors Min, M2, M4, M6, M7, M8, M9, M11, M12, PMOS transistors M1, M3, M5, and M10, and a bootstrap capacitor Cb. The drain of NMOS transistor Min is connected to one end of the sampling capacitor Cs. The source of NMOS transistor Min is connected to the drain of NMOS transistor M7 and the input signal Vin. The gate of NMOS transistor Min is connected to the gate of PMOS transistor M1, the gate of PMOS transistor M5, the drain of NMOS transistor M8, and the PMOS transistor Cb. The gate of transistor M13 is connected to the ground plane. The source of PMOS transistor M1 is connected to the power supply voltage VDD. The drain of PMOS transistor M1 is connected to the upper stage of bootstrap capacitor Cb, the source of PMOS transistor M10, and the source of PMOS transistor M5. The source of NMOS transistor M2 is connected to ground. The drain of NMOS transistor M2 is connected to the lower stage of bootstrap capacitor Cb, the lower stage of bootstrap capacitor Cbx, the drain of NMOS transistor M14, the source of NMOS transistor M4, the source of NMOS transistor M6, and the source of NMOS transistor M7. The gate of NMOS transistor M2 is connected to the gate of NMOS transistor M12, the gate of PMOS transistor M16, the gate of NMOS transistor M14, the gate of NMOS transistor M9, and the gate of PMOS transistor M16. The gate of transistor M15 is connected to the sampling clock inversion signal CKs_F. The source of PMOS transistor M3 is connected to the power supply voltage VDD. The drain of PMOS transistor M3 is connected to the drain of NMOS transistors M4 and M6, the gate of PMOS transistor M5, and the gate of PMOS transistor M10. The gate of PMOS transistor M3 is connected to the gate of NMOS transistor M4 and the sampling clock CKs. The gate of NMOS transistor M6 is connected to the gate of NMOS transistor M7, the drain of NMOS transistor M11, and the drain of PMOS transistor M10. The gate of NMOS transistor M8 is connected to the source of PMOS transistor M15 and the power supply voltage. The source of NMOS transistor M8 is connected to the NMOS transistor M15 and the sampling clock CKs_F. The drain of S-MOSFET M9 and the drain of PMOS transistor M15 are connected. The source of NMOS transistor M9 is connected to ground. The gate of NMOS transistor M11 is connected to the power supply voltage VDD. The source of NMOS transistor M11 is connected to the drain of NMOS transistor M12 and the drain of PMOS transistor M16. The source of NMOS transistor M12 is connected to ground. PMOS transistors M10, M11, and M12 provide gate control signals for NMOS transistors M6 and M7, and can accelerate the establishment of node Vg7, enabling NMOS transistor M7 to smoothly transmit Vin. Cb is a bootstrap capacitor, which is charged by PMOS transistors M1 and M2 until its potential reaches the power supply voltage VDD.Under clock control, the upper-stage voltage Vtp of the bootstrap capacitor is raised to VDD+Vin, and then transmitted to the gate of NMOS transistor Min through PMOS transistor M5. At this time, the gate-source voltage of NMOS transistor Min is constant at VDD, and Vin can be smoothly transmitted with a constant on-resistance. NMOS transistors M8 and M9 are used to turn off NMOS transistor Min. PMOS transistors M3 and M4 are used to control PMOS transistors M5 and M10. NMOS transistor M6 is used to prevent Vsg of PMOS transistor M5 from deviating from VDD, so that the build-up speed of Vg does not change with the input signal.

3. The high-speed, high-linearity gate voltage bootstrap switching circuit according to claim 1, characterized in that, The leakage protection module is implemented by a PMOS transistor M15. The source of the PMOS transistor M15 is connected to the gate of the NMOS transistor M8 and the power supply voltage VDD, respectively. The drain of the PMOS transistor M15 is connected to the drain of the NMOS transistor M9 and the source of the NMOS transistor M8, respectively. The gate of the PMOS transistor M15 is connected to the sampling clock inversion signal CKs_F. When the rising edge of the sampling clock CKs arrives, the PMOS transistor M15 turns on and charges node Vd9, causing node Vd9 to rise rapidly to VDD-Vthn, which turns off the NMOS transistor M8. Vthn is the threshold voltage of the NMOS transistor, preventing charge from flowing to node Vd9 during the setup phase of node Vg.

4. The high-speed, high-linearity gate voltage bootstrap switching circuit according to claim 1, characterized in that, The parasitic capacitance reduction module consists of a PMOS transistor M13, an NMOS transistor M14, and a bootstrap capacitor Cbx. The drain of PMOS transistor M13 is connected to the power supply voltage VDD. The source of PMOS transistor M13 is connected to the substrate of PMOS transistor M13, the upper plate of bootstrap capacitor Cbx, the source of PMOS transistor M10, the substrate of PMOS transistor M10, the source of PMOS transistor M1, the substrate of PMOS transistor M1, the source of PMOS transistor M5, and the substrate of PMOS transistor M5. The gate of PMOS transistor M13 is connected to the gate of NMOS transistor Min and the drain of NMOS transistor M8. The gate of PMOS transistor M1 and the drain of PMOS transistor M5 are connected to the N-well of PMOS transistor M14. The source of NMOS transistor M14 is connected to ground. The drain of NMOS transistor M14 is connected to the lower stage of bootstrap capacitor Cbx, the lower stage of bootstrap capacitor Cb, the drain of NMOS transistor M2, the source of NMOS transistor M4, the source of NMOS transistor M6, and the source of NMOS transistor M7. The gate of NMOS transistor M14 is connected to the sampling clock inversion signal CKs_F, and its connection relationship with PMOS transistors M1, NMOS transistor M2, and bootstrap capacitor Cb is the same. Therefore, the voltages of nodes Vtpx and Vtp change synchronously. At the same time, the substrates of PMOS transistors M1, M5, and M10 are connected to node Vtpx, and the parasitic capacitance of node Vtp eliminates the parasitic capacitance between the N-well of the PMOS transistor and the substrate.

5. The high-speed, high-linearity gate voltage bootstrap switching circuit according to claim 1, characterized in that, The accelerated setup module includes a PMOS transistor M16. The source of the PMOS transistor M16 is connected to the power supply voltage. The drain of the PMOS transistor M16 is connected to the drain of NMOS transistor M12 and the source of NMOS transistor M11. The gate of the PMOS transistor M16 is connected to the gate of NMOS transistor M14, the gate of NMOS transistor M12, the gate of NMOS transistor M2 and the sampling clock inversion signal CKs_F. When the rising edge of the sampling clock CKs arrives, the PMOS transistor M16 is turned on, charging node Vg7 to VDD in advance, and then continuously charging it to VDD+Vin, thereby accelerating the setup speed.

6. The high-speed, high-linearity gate voltage bootstrap switching circuit according to claim 2, characterized in that, During the sampling phase, when the rising edge of the sampling clock CKs arrives, node Vg5 drops from VDD to a low potential. At this time, PMOS transistors M5 and M10 are turned on, and the potential of node Vg7 rises rapidly to VDD, causing NMOS transistors M6 and M7 to turn on. Nodes Vg5 and Vbp gradually rise to Vin, and node Vtp rises to VDD+Vin due to the conservation of capacitor charge. It also continuously charges node Vg7 to VDD+Vin through PMOS transistor M10. At the same time, node Vg is also charged to VDD+Vin through PMOS transistor M5. At this time, NMOS transistor Min is turned on with a constant on-resistance, and the output signal Vout follows the change of the input signal Vin. During the hold phase, when the falling edge of the sampling clock CKs arrives, NMOS transistor M9 turns on, causing node Vg to be quickly pulled down to a low potential, resulting in NMOS transistor Min turning off. The output signal Vout remains at the voltage value at the moment of the falling edge. Node Vg5 is raised to VDD by PMOS transistor M3, turning off PMOS transistors M5 and M10. At the same time, PMOS transistors M1 and M2 turn on, charging the bootstrap capacitor Cb to VDD in preparation for the next sampling.

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