Unibus communication physical layer protocol implementation method suitable for small resistance modulation
By defining and setting the timing synchronization information for single-bus communication, and by adopting specific timing design and transmission methods, the problem of signal distortion under low resistance modulation was solved, and stable and reliable single-bus communication was achieved.
Patent Information
- Application Number
- CN202511483119.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-16
- Publication Date
- 2026-02-13
AI Technical Summary
Existing single-bus communication devices based on low-resistance modulation generate large currents when the switching transistor is switched, resulting in severe signal distortion and poor communication stability and reliability.
Define the timing of transmitting physical signals "1" and "0" in single-bus communication, including the master's synchronization frame header timing START, write 1 timing W1 and write 0 timing W0, and the slave's return 1 timing R1 and return 0 timing R0. Set the protocol to include timing synchronization information between the master and slave. The master uses a similar duty cycle superimposed anchor timing method for downlink commands, and the slave uses an anchor timing continuous backhaul method for uplink data.
It effectively avoids signal misunderstandings or communication interruptions caused by clock asynchrony, improves communication stability and adaptability, reduces signal interference, and enhances communication efficiency.
Smart Images
Figure CN121531036A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic communication technology, and more specifically, to a method for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation. Background Technology
[0002] A typical circuit structure for a single-bus communication device based on low-resistance modulation is as follows: Figure 1 As shown.
[0003] like Figure 1 As shown, the host side consists of the MCU and other communication components. The host sends signals to the single-bus by controlling the switching transistor Pm (with internal resistance Rm) to turn on and off. The slave side is built around a small resistive load Rf (which can be a resistive load such as a heating wire). Communication with the host is achieved by switching the slave side's transistor Ps (with internal resistance Rs) connected in parallel with the small resistor Rf. The switching transistor Pm is a power transistor with an internal resistance in the mΩ range; the switching transistor Ps can be a discrete power transistor or a common MOSFET inside the chip, also with an internal resistance in the mΩ range. The small resistive load Rf is in the range of 0.2Ω. <Rf<2Ω。
[0004] The master transmits information to the slave via switching transistor Pm on and off. When the slave receives a command from the master and begins to respond with data, the master ensures the bus voltage level is high. The slave controls the switching transistor Ps via port R, modulating the returned information into a voltage value on the single bus to return to the master. When transistor Ps is off, the voltage on the single bus is VCC. When the switching transistor Ps is turned on, the voltage on the single bus becomes VCC, where Rf / (Rm+Rf) represents the voltage across the bus. (Rf / / Rs) / (Rm+Rf / / Rs), where Rf / / Rs is the parallel resistance value of Rf and Rs. The master-side receiving circuit decodes the information returned by the slave device by monitoring the voltage changes on the single bus.
[0005] The aforementioned single-bus circuit based on low-resistance modulation generates large currents when both switching transistors Pm and Ps are switched on. When switching transistor Pm is on and switching transistor Ps is off, the current on the single bus is I = VCC / (Rm + Rf), assuming VCC = 3.3V, Rm = 100mΩ, Rf = 1Ω, and I = 3A. This large current leads to severe signal distortion transmitted on the single bus.
[0006] Therefore, for this single-bus communication scenario with low resistive load modulation, it is necessary to design a more stable and reliable physical layer communication protocol. Summary of the Invention
[0007] This invention addresses the technical problems existing in the prior art by providing a method for implementing a physical layer protocol for single-bus communication based on low-resistance modulation, thus solving the communication stability problem under signal distortion conditions and achieving a more stable and reliable single-bus communication effect based on low-resistance modulation.
[0008] According to a first aspect of the present invention, a method for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation is provided, comprising: Define the timing sequence for transmitting physical signals "1" and "0" in single-bus communication, including the master's synchronization frame header timing START, write 1 timing W1 and write 0 timing W0, and the slave's return 1 timing R1 and return 0 timing R0. The single-bus communication physical layer protocol is configured to include timing synchronization information between the master and slave devices; Based on the defined timing and the timing synchronization information, the host uses a method similar to duty cycle superimposed anchor timing for downlink commands, while the slave uses a method of continuous backhaul of anchor timing for uplink data.
[0009] Based on the above technical solution, the present invention can also be improved as follows.
[0010] Optionally, the synchronization frame header timing START includes sequentially set durations of T. START The low level and duration of T W The high level and the low level with a duration of T, the synchronization frame header timing START satisfies the following conditions: T START >4T W T<(1 / 2)T W .
[0011] Optionally, the write-0 timing sequence W0 includes sequentially set durations of T. W0 The high level and the low level with a duration of T, the write 0 timing W0 satisfies the following conditions: (1 / 8)T W <T W0 <(1 / 2)T W .
[0012] Optionally, the write-1 timing sequence W1 includes sequentially set durations of T. W1 The high level and the low level with a duration of T, the write 1 timing W1 satisfies the following conditions: T W <T W1 <(3 / 2)T W .
[0013] Optionally, before the data uplink from the slave device adopts the anchor timing sequence for continuous backhaul, it also includes: After the slave device receives the data return command from the master device, it needs to wait for a time T. wait Where time T wait satisfy: T wait =mT W m is a non-zero positive integer; Define the host receiver circuit initialization time T init ,satisfy: T wait >T init ; During slave standby, the master-side switching transistor Pm remains normally open.
[0014] Optionally, the data uplink from the slave device uses anchor timing sequence for continuous backhaul, including: The slave device sends back the first bit of data according to the master's data return command; After the slave device returns the first bit of data, it automatically continues with the second bit of data until it completes the data reply specified by the data reply instruction sent by the master, or receives the new synchronization frame header timing START sent by the master. During the data return process from the slave device, the host-side switching transistor Pm remains normally open.
[0015] Optionally, the duration of both the return-to-1 timing R1 and the return-to-0 timing R0 is T. bit Duration T bit satisfy: T bit =nT W n is a non-zero positive integer; Specifically, when the timing sequence R1 corresponds to 1 return, the slave-side switch Ps is not turned on; when the timing sequence R0 corresponds to 0 return, the slave-side switch Ps is turned on for a duration of (1 / 8)T. bit Then close.
[0016] According to a second aspect of the present invention, a system for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation is provided, comprising: The definition module is used to define the timing of transmitting physical signals "1" and "0" in single-bus communication, including the master's synchronization frame header timing START, write 1 timing W1 and write 0 timing W0, and the slave's return 1 timing R1 and return 0 timing R0. The synchronization module is used to configure the single-bus communication physical layer protocol to include timing synchronization information between the master and slave devices. The communication module is used to perform downlink commands on the host side using a method similar to duty cycle superimposed anchor timing, and to perform uplink data on the slave side using a method of continuous backhaul of anchor timing, based on the defined timing and the timing synchronization information.
[0017] According to a third aspect of the present invention, an electronic device is provided, including a memory and a processor, wherein the processor is configured to implement the steps of the above-described method for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation when executing a computer management program stored in the memory.
[0018] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, on which a computer management class program is stored, wherein when executed by a processor, the computer management class program implements the steps of the above-described method for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation.
[0019] The present invention provides a method, system, electronic device, and storage medium for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation, which has the following beneficial technical effects: 1. Ensure communication stability: By defining the master's synchronization frame header timing START, write 1 timing W1, write 0 timing W0, and the slave's return 1 timing R1, return 0 timing R0, and setting the protocol to include timing synchronization information between the master and slave, even if there is a large clock deviation between the master and slave, the two can still communicate based on a unified timing rule, effectively avoiding signal misunderstanding or communication interruption caused by clock asynchrony, and improving communication stability.
[0020] 2. Adaptation to Low-Resistance Modulation Scenarios: The host uses a "duty cycle-based anchor timing sequence" method for downlink commands, while the slave uses a "continuous anchor timing sequence transmission" method for uplink data. This design is specifically for single-bus communication scenarios with low-resistance modulation. Low-resistance loads are prone to generating large currents, which may lead to signal distortion. The specific timing design and transmission method can reduce signal interference, ensuring accurate transmission of commands and data in this scenario and improving the protocol's adaptability to low-resistance modulation environments.
[0021] 3. Optimize communication efficiency: The slave's "continuous back transmission" method avoids unnecessary intervals in the data transmission process, and the timing design of the master can also clearly define the instruction boundaries, reduce communication redundancy, and improve the overall efficiency of single-bus communication while ensuring stability.
[0022] This invention employs a duty cycle-based timing anchoring method during downlink communication commands, and continuously transmits uplink data via anchor timing, effectively improving communication stability and efficiency under signal distortion conditions. Attached Figure Description
[0023] Figure 1 This is a typical circuit structure for a single-bus communication device based on low-resistance modulation. Figure 2 A flowchart of a single-bus communication physical layer protocol implementation method suitable for low-resistance modulation provided by the present invention; Figure 3 The single-bus physical layer timing diagram corresponding to the host synchronization frame header timing START, write "0" timing, and write "1" timing provided for the embodiment; Figure 4 A schematic diagram of the single-bus physical layer timing corresponding to the slave device's return to "0" and return to "1" timings provided in the embodiment; Figure 5 This invention provides a system architecture block diagram for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation. Figure 6 A schematic diagram of a possible hardware structure of an electronic device provided by the present invention; Figure 7 This is a schematic diagram of the hardware structure of a possible computer-readable storage medium provided by the present invention. Detailed Implementation
[0024] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.
[0025] based on Figure 1 The typical circuit structure of a single-bus communication device based on low-resistance modulation is shown, such as... Figure 2 As shown, this embodiment of the invention provides a method for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation, the method including the following steps S1~S3: S1 defines the timing of transmitting physical signals "1" and "0" in single-bus communication, including the master's synchronization frame header timing START, write 1 timing W1 and write 0 timing W0, and the slave's return 1 timing R1 and return 0 timing R0. S2, Configure the single-bus communication physical layer protocol to include timing synchronization information between the master and slave devices; S3, based on the defined timing and the timing synchronization information, the host uses a method similar to duty cycle superimposed anchor timing for downlink commands, and the slave uses a method of continuous backhaul of anchor timing for uplink data.
[0026] Understandably, given the deficiencies in the background technology, this invention proposes a method for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation. The communication protocol defines communication commands, which are not described in this invention's embodiments.
[0027] This invention sets a synchronization frame header (i.e., a START frame) before all communication commands issued by the master. By defining the master's synchronization frame header timing START, write 1 timing W1, write 0 timing W0, and the slave's return 1 timing R1, return 0 timing R0, and setting the protocol to include timing synchronization information between the master and slave, even if there is a large clock deviation between the master and slave, they can still communicate based on a unified timing rule. This effectively avoids signal misunderstanding or communication interruption caused by clock asynchrony and improves the stability of master-slave single-bus communication.
[0028] This invention is adapted Figure 1 The diagram illustrates a low-resistance modulation scenario. The master unit uses a "duty cycle-plus-anchor timing sequence" approach for downlink commands, while the slave unit uses a "continuous backhaul of anchor timing sequence" approach for uplink data. This design is specifically tailored for single-bus communication scenarios with low-resistance modulation. Low-resistance loads are prone to generating large currents, which can lead to signal distortion. The specific timing design and transmission method reduce signal interference, ensuring accurate transmission of commands and data in this scenario and improving the protocol's adaptability to low-resistance modulation environments.
[0029] This invention optimizes the efficiency of master-slave single-bus communication. Specifically, the slave's "continuous backhaul" method avoids unnecessary intervals in data transmission, and the master's timing design clearly defines instruction boundaries, reducing communication redundancy. While ensuring stability, it improves the overall efficiency of single-bus communication.
[0030] This invention employs a duty cycle-based timing anchoring method during downlink communication commands, and continuously transmits uplink data via anchor timing, effectively improving communication stability under signal distortion conditions.
[0031] Based on the above technical solution, this embodiment can be further improved as follows.
[0032] In one possible embodiment, such as Figure 3 The diagram shows the single-bus physical layer timings corresponding to the host START frame, writing "0", and writing "1", and the synchronization frame header timings (corresponding to...). Figure 3 The START parameter includes sequentially set durations of T. START The low level and duration of T W The high level and the low level with a duration of T, the synchronization frame header timing START must satisfy the following conditions: T START >4T W T<(1 / 2)T W .
[0033] Understandably, since the duration is T in the START frame... STARTThe low level is the synchronization frame for single-bus communication, therefore the duration T START A high degree of time discrimination is required; in this embodiment, T is taken as T. START >4T W The duration is T. W The high level signal determines the communication rate between the master and slave devices, thus achieving the function of communication handshake.
[0034] In this embodiment, the duration T is used. W As the anchoring reference, duration T START Both duration T and duration T are anchored to duration T W Configure it in this way.
[0035] In one possible embodiment, such as Figure 3 As shown, the write 0 timing sequence W0 includes sequentially set durations of T. W0 A high level and a low level of duration T, when writing 0, the timing W0 satisfies the following conditions: (1 / 8)T W <T W0 <(1 / 2)T W .
[0036] It is understandable that writing a 0 timing sequence is used to anchor the duration T. W The settings are configured in this way, therefore the write 0 timing W0 rate is based on the duration T. W To determine.
[0037] In one possible embodiment, such as Figure 3 As shown, the write-1 timing sequence W1 includes sequentially set durations of T. W1 A high level and a low level of duration T, the write timing W1 satisfies the following conditions: T W <T W1 <(3 / 2)T W .
[0038] It is understandable that writing a 1 timing sequence to anchor the duration T is acceptable. W The settings are configured in this way, therefore the write timing W1 rate is set to the duration T. W To determine.
[0039] In the above embodiments, the relationship between the durations of the synchronization frame header timing START, write 1 timing W1, and write 0 timing in the single-bus communication protocol determines the efficiency of the host's communication command output. Given that the high current, as indicated in the background art, can cause severe signal distortion on a single bus, the host's downlink "0" and "1" are defined using a duty cycle-like approach, with the duty cycle anchored to the time T within the START frame. WThe definition methods of the above embodiments can increase the distinguishability of "0" and "1" in the host downlink, thereby reducing the error rate.
[0040] At the end of the START frame, write 0 timing sequence W0, and write 1 timing sequence W1, a low level of duration T serves to distinguish the frames; therefore, its timing requirement can significantly differentiate the duration T. START Therefore, we can take T < (1 / 2)T. W .
[0041] In one possible embodiment, the slave-side data back-to-physical-layer timing includes a back-to-1 timing sequence R1 and a back-to-0 timing sequence R0. In this embodiment, before the continuous back-to-data transmission using the anchor timing sequence, the slave-side data uplink further includes: After the slave device receives the data return command from the master device, it needs to wait for a time T. wait Where time T wait satisfy: T wait =mT W m is a non-zero positive integer; Define the host receiver circuit initialization time T init ,satisfy: T wait >T init ; During the slave's waiting period, Figure 1 The host-side switch Pm shown is kept normally open.
[0042] Understandably, after receiving a data return command from the master, the slave device needs to wait for a period of time T. wait This allows the host-side receiving circuitry to complete its initialization and preparation. Therefore, the duration T in the START frame is used. w As a timing anchoring reference, and combined with the host receiver circuit initialization time T init Common constraint waiting time T wait Only after the above two constraints are met will the slave device begin data transmission.
[0043] In one possible embodiment, the data uplink from the slave end employs anchored timing sequence continuous backhaul, wherein the continuous data backhaul includes: The slave device sends back the first bit of data according to the master's data return command; After the slave device returns the first bit of data, it automatically continues with the second bit of data until it completes the data reply specified by the data return command sent by the master, or receives a new synchronization frame header timing (START) sent by the master. During the data return process from the slave device, Figure 1 The host-side switch Pm shown is kept normally open.
[0044] Understandably, the slave device's data uplink uses a "continuous backhaul" method to avoid unnecessary intervals in the data transmission process, and the master device's timing design can also clearly define instruction boundaries, reduce communication redundancy, and improve the overall efficiency of single-bus communication while ensuring stability.
[0045] In one possible embodiment, Figure 4 The diagram shows the single-bus physical layer timing corresponding to the slave device returning "0" and "1", as follows: Figure 4 As shown, the duration of both the return-to-1 timing R1 and the return-to-0 timing R0 is T. bit Duration T bit satisfy: T bit =nT W n is a non-zero positive integer; Wherein, corresponding to the return-to-1 timing R1, Figure 1 The slave-side switch Ps shown in the diagram is not turned on; corresponding to the 0-return timing R0, Figure 1 The slave-side switch Ps shown in the figure has an on-time of (1 / 8)T. bit Then close.
[0046] Combination Figure 1 and Figure 4 When corresponding to the return-to-1 timing R1, Figure 1 The slave-side switch Ps shown is not turned on; it is in the off state. The 0-return sequence R0 involves turning on the slave-side switch Ps. When the slave-side switch Ps is turned on, a large current flows through it. Prolonged operation of the switch Ps will cause it to overheat, affecting its lifespan. In this embodiment, the 0-return sequence R0 process involves turning on the switch Ps, and its on-state duration is (1 / 8)T. bit This causes a voltage change of magnitude ΔV to be generated on the single bus for sampling by the host-side receiving circuit, and then the switching transistor Ps is turned off.
[0047] Now combined Figure 3 and Figure 4 The timing diagram illustrates the technical solution of this invention through a specific application scenario.
[0048] In this implementation scenario, communication commands are defined within the communication protocol, but these commands are not described within this scenario. This implementation scenario adds a synchronization frame header (START frame) before each communication command and defines the physical layer timing on the single bus corresponding to protocol "0" and protocol "1" sent by the master, and the physical layer timing on the single bus corresponding to protocol "0" and protocol "1" sent by the slave.
[0049] I. Host side refer to Figure 3The diagram shows the physical layer timing of the single-bus communication, corresponding to the host START frame, writing "0", and writing "1". The single-bus communication physical layer timing on the host side satisfies the following conditions: 1. All communication commands must be preceded by a START frame. The START frame consists of three consecutive parts, including: a duration of T. START The low level lasts for a duration of T. W The high level and the low level for a duration of T.
[0050] 2. Write "0" (corresponding to) Figure 3 The middle W0) consists of two continuous parts, including: a duration of T W0 The high level and the low level for a duration of T.
[0051] 3. Write "1" (corresponding to) Figure 3 W1) consists of two continuous parts, including: a duration of T W1 The high level and the low level for a duration of T.
[0052] 4. In the START frame, the duration is T. START The low level is the synchronization frame for single-bus communication, therefore time T START High time discrimination is required, so take T. START >4 TW The duration afterwards is T. W The high level signal determines the communication rate between the master and slave devices, thus achieving the function of communication handshake.
[0053] The relationship between the durations of each bus is as follows: (1 / 8)T W <T W0 <(1 / 2)T W ;(1 / 2)T W <T W1 <(3 / 2)T W The low-level duration T of the START frame, the write "0", and the write "1" frame tail serves to distinguish between frames. Therefore, the duration T must be sufficient to significantly differentiate between frames. START Therefore, we can take T < (1 / 2)T. W .
[0054] II. Slave Terminal refer to Figure 4 The diagram shows the single-bus physical layer timing for slave data return to "0" and "1". The slave data return physical layer timing defined in this implementation scenario meets the following conditions: 1. After receiving the data return command from the master, the slave device needs to wait for a period of time T. waitThis allows the host-side receiving circuit to complete its initialization and preparation. Assume the initialization and preparation time for the host-side receiving circuit is T. init It must satisfy: T wait =mT W Meanwhile, T wait >T init m is a positive integer that is not zero; in T wait During the waiting time, Figure 1 The host-side switch Pm shown is normally open.
[0055] 2. Waiting time reaches T wait Then, the slave device begins sending data back. During the slave device's data transmission process, Figure 1 The host-side switch Pm shown is normally open.
[0056] 3. The slave device's data return process is continuous. The continuous data return process is defined as follows: after the first bit of data is returned, the second bit of data is automatically returned immediately, until the data return specified in the instruction is completed or the master side sends a START frame.
[0057] 4. Return to 1 (corresponding to) Figure 4 R1) and 0 (corresponding to) Figure 4 The duration of R0 is T. bit T bit =nT W , where n is a non-zero positive integer. The circuit state corresponding to the back-to-1 timing sequence is: Figure 1 The slave-side switch Ps shown is not turned on. The 0-return timing involves... Figure 1 The circuit shown illustrates the turn-on of the switch Ps. When switch Ps is turned on, a large current flows through it. Prolonged operation of switch Ps will cause it to overheat, affecting its lifespan. Therefore, the 0-return timing process defined in this implementation scenario is that switch Ps is turned on for (1 / 8)T. bit The time is used to generate a voltage change of ΔV on the single bus for sampling by the host-side receiving circuit, and then the switching transistor Ps is turned off.
[0058] Figure 5 A system architecture diagram for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation, as provided in an embodiment of the present invention, is shown below. Figure 5 As shown, a single-bus communication physical layer protocol implementation system suitable for low-resistance modulation includes a definition module, a synchronization module, and a communication module, wherein: The definition module is used to define the timing of transmitting physical signals "1" and "0" in single-bus communication, including the master's synchronization frame header timing START, write 1 timing W1 and write 0 timing W0, and the slave's return 1 timing R1 and return 0 timing R0. The synchronization module is used to configure the single-bus communication physical layer protocol to include timing synchronization information between the master and slave devices. The communication module is used to perform downlink commands on the host side using a method similar to duty cycle superimposed anchor timing, and to perform uplink data on the slave side using a method of continuous backhaul of anchor timing, based on the defined timing and the timing synchronization information.
[0059] It is understood that the single-bus communication physical layer protocol implementation system for low resistance modulation provided by the present invention corresponds to the single-bus communication physical layer protocol implementation method for low resistance modulation provided in the foregoing embodiments. The relevant technical features of the single-bus communication physical layer protocol implementation system for low resistance modulation can be referred to the relevant technical features of the single-bus communication physical layer protocol implementation method for low resistance modulation, and will not be repeated here.
[0060] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating an embodiment of the electronic device provided in this invention. For example... Figure 6 As shown, this embodiment of the invention provides an electronic device 600, including a memory 610, a processor 620, and a computer program 611 stored in the memory 610 and executable on the processor 620. When the processor 620 executes the computer program 611, it performs the following steps: Define the timing sequence for transmitting physical signals "1" and "0" in single-bus communication, including the master's synchronization frame header timing START, write 1 timing W1 and write 0 timing W0, and the slave's return 1 timing R1 and return 0 timing R0. The single-bus communication physical layer protocol is configured to include timing synchronization information between the master and slave devices; Based on the defined timing and the timing synchronization information, the host uses a method similar to duty cycle superimposed anchor timing for downlink commands, while the slave uses a method of continuous backhaul of anchor timing for uplink data.
[0061] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. (See diagram below.) Figure 7 As shown, this embodiment provides a computer-readable storage medium 700, on which a computer program 711 is stored. When the computer program 711 is executed by a processor, it performs the following steps: Define the timing sequence for transmitting physical signals "1" and "0" in single-bus communication, including the master's synchronization frame header timing START, write 1 timing W1 and write 0 timing W0, and the slave's return 1 timing R1 and return 0 timing R0. The single-bus communication physical layer protocol is configured to include timing synchronization information between the master and slave devices; Based on the defined timing and the timing synchronization information, the host uses a method similar to duty cycle superimposed anchor timing for downlink commands, while the slave uses a method of continuous backhaul of anchor timing for uplink data.
[0062] This invention provides a method, system, and storage medium for implementing a single-bus communication physical layer protocol suitable for low-resistance modulation. During downlink communication commands, a duty cycle-based timing anchoring method is used, while during uplink data protocols, the anchoring timing is continuously transmitted back, thus solving the communication stability problem under signal distortion conditions. Its main advantages are: 1. Ensure communication stability: By defining the master's synchronization frame header timing START, write 1 timing W1, write 0 timing W0, and the slave's return 1 timing R1, return 0 timing R0, and setting the protocol to include timing synchronization information between the master and slave, even if there is a large clock deviation between the master and slave, the two can still communicate based on a unified timing rule, effectively avoiding signal misunderstanding or communication interruption caused by clock asynchrony, and improving communication stability.
[0063] 2. Adaptation to Low-Resistance Modulation Scenarios: The host uses a "duty cycle-based anchor timing sequence" method for downlink commands, while the slave uses a "continuous anchor timing sequence transmission" method for uplink data. This design is specifically for single-bus communication scenarios with low-resistance modulation. Low-resistance loads are prone to generating large currents, which may lead to signal distortion. The specific timing design and transmission method can reduce signal interference, ensuring accurate transmission of commands and data in this scenario and improving the protocol's adaptability to low-resistance modulation environments.
[0064] 3. Optimize communication efficiency: The slave's "continuous back transmission" method avoids unnecessary intervals in the data transmission process, and the timing design of the master can also clearly define the instruction boundaries, reduce communication redundancy, and improve the overall efficiency of single-bus communication while ensuring stability.
[0065] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0066] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0067] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0068] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0069] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0070] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0071] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A method for implementing a single bus communication physical layer protocol suitable for small resistance modulation, characterized in that, The application relates to a single bus communication physical layer protocol implementation method suitable for small resistance modulation. The application defines the time sequence of transmitting physical signals "1" and "0" in single bus communication, including the time sequence of a host's synchronization frame header (START), the time sequence of writing 1 (W1) and the time sequence of writing 0 (W0), and the time sequence of a slave's returning 1 (R1) and the time sequence of returning 0 (R0); The application sets the time sequence synchronization information of the host and the slave in the single bus communication physical layer protocol; Based on the defined time sequence and the time sequence synchronization information, the host end adopts a mode of superimposing anchor time sequence on duty cycle to downwardly transmit instructions, and the slave end adopts a mode of continuously returning data upwardly by anchor time sequence.
2. The method for implementing the physical layer protocol of one-wire bus communication suitable for small resistance modulation according to claim 1, wherein, The synchronization frame header timing (START) comprises a low level with a duration of T START , a high level with a duration of T W , and a low level with a duration of T, which are arranged successively, the synchronization frame header timing (START) satisfying the following conditions: T START >4T W , T < (1 / 2)T W .
3. The method for implementing the physical layer protocol of one-wire bus communication suitable for small resistance modulation according to claim 2, characterized in that, The write 0 timing (W0) comprises a high level with a duration of T W0 a low level with a duration of T, which are arranged successively in sequence, the write 0 timing (W0) satisfying the following conditions: (1 / 8)T W <T W0 (1 / 2)T W .
4. The method for implementing the physical layer protocol of one-wire bus communication suitable for small resistance modulation according to claim 3, wherein, The write 1 timing (W1) includes a high level with a duration of T W1 a low level with a duration of T, which are arranged in sequence continuously, and the write 1 timing (W1) satisfies the following conditions: T W <T W1 <(3 / 2)T W .
5. The method for implementing the physical layer protocol of single bus communication suitable for small resistance modulation according to claim 2, wherein, Before the slave end adopts the mode of continuously returning data upwardly by anchor time sequence, the application further comprises the following steps: After the slave receives the data-back instruction of the host, it needs to wait for time T wait where time T wait satisfies: T wait =mT W , m is a non-zero positive integer; Definition of the host reception circuit initialization time T init satisfies: T wait >T init ; During the waiting of the slave, the switch tube Pm on the host side keeps open.
6. The method for implementing the physical layer protocol of one-wire bus communication suitable for small resistance modulation according to claim 5, wherein, The application further comprises the following steps: The slave returns the first bit data according to the data returning instruction of the host; After the slave returns the first bit data, the slave automatically connects the second bit data until the data returning instruction specified by the host is completed, or a new synchronization frame header (START) is received by the host; During the data returning of the slave, the switch tube Pm on the host side keeps open.
7. The method for implementing the physical layer protocol of one-wire bus communication suitable for small resistance modulation according to claim 6, wherein, The duration of the return 1 timing (R1) and the return 0 timing (R0) are both T bit , duration T bit satisfies: T bit =nT W , n is a non-zero positive integer; Wherein, when the corresponding back 1 timing (R1), the slave side switch tube Ps is not opened; when the corresponding back 0 timing (R0), the slave side switch tube Ps is opened for (1 / 8) T bit The rear is closed.
8. A system for implementing a single bus communication physical layer protocol suitable for low resistance modulation, characterized by, The application comprises the following steps: A definition module is used to define the time sequence of transmitting physical signals "1" and "0" in single bus communication, including the time sequence of a host's synchronization frame header (START), the time sequence of writing 1 (W1) and the time sequence of writing 0 (W0), and the time sequence of a slave's returning 1 (R1) and the time sequence of returning 0 (R0); A synchronization module is used to set the time sequence synchronization information of the host and the slave in the single bus communication physical layer protocol; A communication module is used to, based on the defined time sequence and the time sequence synchronization information, adopt a mode of superimposing anchor time sequence on duty cycle to downwardly transmit instructions on the host end, and adopt a mode of continuously returning data upwardly by anchor time sequence on the slave end.
9. An electronic device, comprising: The application further comprises a memory and a processor, wherein the processor is used to execute the computer management program stored in the memory to realize the steps of the single bus communication physical layer protocol implementation method suitable for small resistance modulation.
10. A computer-readable storage medium, characterized in that, The application further comprises a memory and a processor, wherein the processor is used to execute the computer management program stored in the memory to realize the steps of the single bus communication physical layer protocol implementation method suitable for small resistance modulation.