MIM capacitor preparation method and MIM capacitor
By using an island structure and a double hard mask sidewall process in MIM capacitor manufacturing, only one photomask is used to define the upper electrode and the lower electrode is patterned by self-alignment. This solves the problems of complexity and high cost of traditional processes and achieves high-yield and low-cost MIM capacitor manufacturing.
Patent Information
- Application Number
- CN202511940435.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-02-13
AI Technical Summary
Traditional MIM capacitor manufacturing processes require multiple photolithography steps, which increases the complexity of the process and the cost of the photomask. Furthermore, the alignment of vias is difficult, which can easily lead to poor contact or open circuit failure.
By employing an island structure and a dual hard mask sidewall process, the upper electrode is defined by a single photomask, and the lower electrode is patterned using the sidewalls and islands for self-alignment. This eliminates the need for a second photomask to define the lower electrode, increasing the contact area and improving the reliability of via connections.
It significantly simplifies the process flow, reduces photomask costs, improves the reliability of through-hole connections, avoids the risk of short circuits between upper and lower electrodes, and improves manufacturing yield.
Smart Images
Figure CN121531728A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, in particular to a MIM capacitor preparation method and a MIM capacitor. BACKGROUND
[0002] In the traditional MIM capacitor manufacturing process, it is usually necessary to define the patterns of the upper electrode and the lower electrode by at least two independent masks: the first mask is used to form the upper electrode structure, and the second mask is used to etch the lower electrode and define its profile, and then the upper and lower electrodes are connected with the interconnection metal layer through a via. This multi-step photolithography scheme not only increases the complexity of the process flow, but also significantly increases the manufacturing cost related to the mask, especially at the advanced process node, the mask cost has become one of the main factors restricting the overall economy of the chip.
[0003] At the same time, in order to realize the reliable connection of the upper and lower electrodes with the interconnection line, the via must be accurately aligned with the electrode area. However, when using sidewall transfer technology or other self-alignment processes, if the lower electrode is indirectly defined by the sidewall, the sidewall width directly affects the available contact area, and too narrow contact window will increase the difficulty of via connection, and even cause failure modes such as poor contact or open circuit. SUMMARY
[0004] The purpose of the present application is to provide a MIM capacitor preparation method and a MIM capacitor which can reduce the number of masks used, simplify the process flow and reduce the manufacturing cost without sacrificing device performance and connection reliability.
[0005] The present application is implemented as follows: In a first aspect, the present application provides a MIM capacitor preparation method, comprising: providing a substrate structure, the substrate structure being sequentially stacked with a lower electrode layer, a dielectric layer, an upper electrode layer and a first hard mask layer; forming a photoresist layer on the first hard mask layer; the photoresist layer has an opening pattern for defining an island structure and an upper electrode structure; using the photoresist layer as a mask, etching the first hard mask layer, the upper electrode layer and the dielectric layer to form a plurality of island structures on the lower electrode layer and an upper electrode structure, the upper electrode structure comprising a first upper electrode and a plurality of second upper electrodes connected with the first upper electrode, a plurality of the island structures being arranged along a first direction, the second upper electrode being between adjacent island structures, the island structures and the first upper electrode being arranged along a second direction, and each island structure having an isolation opening between the first upper electrode and the second upper electrode; the first direction being perpendicular to the second direction; forming a sidewall covering the sidewall of the island structure; Etching the lower electrode layer to form a MIM structure, taking the sidewall and the first hard mask layer as a mask; forming a first metal structure penetrating through the sidewall and connecting with the lower electrode layer.
[0006] As an optional implementation, the forming a first metal structure penetrating through the sidewall and connecting with the lower electrode layer comprises: depositing an upper interlayer dielectric layer on the MIM structure; forming a first via hole on the upper interlayer dielectric layer, the first via hole penetrating through the upper interlayer dielectric layer and the sidewall to the lower electrode layer; depositing a first metal structure connecting with the lower electrode layer in the first via hole.
[0007] As an optional implementation, the first via hole penetrates through the sidewall away from the first upper electrode on the side of the island structure; or, the first via hole penetrates through the sidewall close to the first upper electrode on the side of the island structure.
[0008] As an optional implementation, the method further comprises: forming a second metal structure connecting with the upper electrode layer of the upper electrode structure.
[0009] As an optional implementation, the forming a sidewall covering the sidewall of the island structure comprises: after removing the photoresist layer, depositing a second hard mask layer; the second hard mask layer covers the lower electrode layer and the first hard mask layer; dry etching the second hard mask layer to remove the second hard mask layer on the first hard mask layer, and to remove part of the second hard mask layer on the lower electrode layer, forming the sidewall.
[0010] As an optional implementation, the first metal structure further connects with the island structure.
[0011] In a second aspect, the application provides a MIM capacitor, comprising: a substrate structure, a lower electrode layer arranged on the substrate structure, an upper electrode structure, a plurality of island structures, a sidewall, a first metal structure and a second metal structure arranged on the lower electrode layer; the upper electrode structure and the island structure each comprise a dielectric layer, an upper electrode layer and a first hard mask layer; the upper electrode structure comprises a first upper electrode and a plurality of second upper electrodes connected with the first upper electrode, the plurality of island structures are arranged along a first direction, the second upper electrode is arranged between adjacent island structures, the island structures and the first upper electrode are arranged along a second direction, and each island structure has an isolation opening between the first upper electrode and the second upper electrode; the first direction is perpendicular to the second direction; The lower electrode layer is provided with a side wall on the side of the island structure; the first metal structure penetrates the side wall and is connected with the lower electrode layer; and the second metal structure penetrates the first hard mask layer and is connected with the upper electrode layer of the upper electrode structure.
[0012] As an optional implementation, the method further comprises: a top interlayer dielectric layer covering the first hard mask layer and the side wall. The first metal structure further penetrates the top interlayer dielectric layer on the side wall, and the second metal structure further penetrates the top interlayer dielectric layer on the upper electrode structure.
[0013] As an optional implementation, the sum of the projection areas of the side wall, the upper electrode structure and the plurality of island structures on the substrate structure is equal to the projection area of the lower electrode layer on the substrate structure.
[0014] As an optional implementation, the width of the side wall is equal to the sum of the thickness of the upper electrode layer and the thickness of the dielectric layer.
[0015] The beneficial effects of the present application include: The MIM capacitor preparation method and the MIM capacitor provided by the present application use the island structure and the double hard mask side wall process to perform self-alignment patterning on the lower electrode layer by using the side wall and the island while defining the upper electrode by using only one photomask, thereby eliminating the second photomask specially used for defining the lower electrode in the traditional process, significantly simplifying the process steps and effectively reducing the cost of the photomask; at the same time, the island structure not only provides a stable and increased contact area for the lower electrode, thereby improving the reliability of the via connection, but also maintains a safe distance with the upper electrode layer in the horizontal direction, thereby fundamentally avoiding the risk of short circuit with the upper electrode when filling the via with metal in the subsequent process, so as to reduce the cost while taking into account the device performance and manufacturing yield. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.
[0017] Figure 1 Fig. 1 is a structural schematic diagram of the MIM capacitor of the embodiment of the present application; Figure 2 Fig. 2 is another structural schematic diagram of the MIM capacitor of the embodiment of the present application; Figure 3 Fig. 3 is a state diagram of the MIM capacitor preparation process of the embodiment of the present application; Figure 4Figure 2 is a state diagram of a process for manufacturing a MIM capacitor according to an embodiment of the present application; Figure 5 Figure 3 is a state diagram of a process for manufacturing a MIM capacitor according to an embodiment of the present application; Figure 6 Figure 4 is a state diagram of a process for manufacturing a MIM capacitor according to an embodiment of the present application; Figure 7 Figure 5 is a state diagram of a process for manufacturing a MIM capacitor according to an embodiment of the present application; Figure 8 Figure 6 is a state diagram of a process for manufacturing a MIM capacitor according to an embodiment of the present application; Figure 9 Figure 7 is a state diagram of a process for manufacturing a MIM capacitor according to an embodiment of the present application; Figure 10 Figure 8 is a state diagram of a process for manufacturing a MIM capacitor according to an embodiment of the present application; Figure 11 Figure 9 is a state diagram of a process for manufacturing a MIM capacitor according to an embodiment of the present application; Figure 12 Figure 10 is a state diagram of a process for manufacturing a MIM capacitor according to an embodiment of the present application.
[0018] Figure 1 is a schematic diagram of a MIM capacitor according to an embodiment of the present application; 100 - substrate structure; 101 - lower electrode layer; 102 - dielectric layer; 103 - upper electrode layer; 104 - first hard mask layer; 107 - island structure; 108 - second hard mask layer; 109 - sidewall; 110 - upper interlayer dielectric layer; 111 - first via; 112 - first metal structure; 113 - second via; 114 - second metal structure; 115 - photoresist layer; 116 - upper electrode structure; 117 - first upper electrode; 118 - second upper electrode; Y - first direction; X - second direction. DETAILED DESCRIPTION
[0019] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will be a clear and complete description of the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.
[0020] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.
[0021] It should be noted that similar reference numerals and letters refer to like items throughout the accompanying drawings, and therefore, once an item is defined in one drawing, it is not necessary to further define and explain it in subsequent drawings. In addition, the terms "first", "second", "third", and the like are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.
[0022] In the description of the present application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set", "mount", "connect", "connect" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0023] In the conventional MIM capacitor manufacturing process, it is usually necessary to define the patterns of the upper electrode and the lower electrode by at least two independent masks: the first mask is used to form the upper electrode structure, and the second mask is used to etch the lower electrode and define its profile, and then the upper and lower electrodes are connected with the interconnection metal layer through a via. This multi-step photolithography scheme not only increases the complexity of the process flow, but also significantly increases the manufacturing cost related to the mask, especially at the advanced process node, the mask cost has become one of the main factors restricting the overall economy of the chip.
[0024] At the same time, in order to realize the reliable connection of the upper and lower electrodes and the interconnection line, the via must be accurately aligned with the electrode area. However, when using sidewall transfer technology or other self-alignment process, if the lower electrode is indirectly defined by the sidewall, the sidewall width directly affects the available contact area, and too narrow contact window will increase the difficulty of via connection, and even cause failure modes such as poor contact or open circuit.
[0025] To solve the above technical problems, the present application provides a MIM capacitor preparation method and a MIM capacitor structure.
[0026] The MIM capacitor preparation method provided by the present application can include: As shown in Figure 3 The lower electrode layer 101, the dielectric layer 102 and the upper electrode layer 103 are sequentially stacked on the base structure 100.
[0027] In this embodiment, the materials of the lower electrode layer 101 and the upper electrode layer 103 are the same type of metal material.
[0028] In this embodiment, as shown in Figure 4 A first hard mask layer 104 is deposited on the upper electrode layer 103.
[0029] The first hard mask layer 104 can be made of titanium nitride, tantalum nitride, silicon oxide, or amorphous silicon.
[0030] As shown in FIG. 1C, a photoresist layer 115 is formed on the first hard mask layer 104. The photoresist layer 115 has an opening pattern for defining the island structure 107 and the upper electrode structure 116. Figure 4
[0031] As shown in FIG. 1D, the exposed first hard mask layer 104, the upper electrode layer 103, and the dielectric layer 102 are etched away using the photoresist layer 115 as a mask until the lower electrode layer 101 is exposed, thereby forming a plurality of protruding island structures 107 and the upper electrode structure 116 on the lower electrode layer 101. Figure 5
[0032] As shown in FIG. 1E, the upper electrode structure 116 can include a first upper electrode 117 and a plurality of second upper electrodes 118 connected to the first upper electrode 117. The plurality of island structures 107 are arranged along a first direction Y, and the second upper electrodes 118 are arranged between adjacent island structures 107 along the first direction Y. The island structures 107 and the first upper electrode 117 are arranged along a second direction X, and the island structures 107 are separated from the first upper electrode 117 by a separation opening. Figure 1 Figure 5 Further, as shown in FIG. 1F, a sidewall 109 is formed to cover the sidewalls of the island structures 107. The sidewall 109 also covers part of the exposed lower electrode layer 101.
[0033] As shown in FIG. 1G, the exposed lower electrode layer 101 is etched away using the sidewall 109 and the first hard mask layer 104 as a mask, thereby forming a MIM structure. Figure 7
[0034] As shown in FIG. 1H, a first via 111 is formed in the ILD layer 110. The first via 111 penetrates the ILD layer 110 and the sidewall 109 to the lower electrode layer 101. Figure 7 Figure 8 As shown in FIG. 1I, a first metal structure 112 is deposited in the first via 111. The first metal structure 112 is connected to the lower electrode layer 101.
[0035] In this embodiment, as shown in FIG. 1J, an ILD layer 110 is deposited on the MIM structure. Figure 9
[0036] As shown in FIG. 1K, a first via 111 is formed in the ILD layer 110. The first via 111 penetrates the ILD layer 110 and the sidewall 109 to the lower electrode layer 101. Figure 10 Figure 11 As shown in FIG. 1L, a first metal structure 112 is deposited in the first via 111. The first metal structure 112 is connected to the lower electrode layer 101.
[0037] As shown in FIG. 1M, a second via 113 is formed in the ILD layer 110. The second via 113 penetrates the ILD layer 110 and the sidewall 109 to the lower electrode layer 101. Figure 12
[0038] It should be noted that, along the direction perpendicular to the base structure 100, the island structure 107 and the upper electrode structure 116 each include the dielectric layer 102, the upper electrode layer 103, and the first hard mask layer 104. The first direction Y and the second direction X are both parallel to the plane in which the base structure 100 is located. The first direction Y and the second direction X are perpendicular to each other.
[0039] It should be noted that, by optimizing the patterning process of the MIM capacitor, the embodiment of the present application can complete the definition of the upper electrode layer 103 using only one mask, and at the same time provide a basis for the patterning of the lower electrode layer 101, thereby eliminating the second mask used to define the lower electrode layer 101 in the traditional process.
[0040] Specifically, after the stack of the upper electrode layer 103, the dielectric layer 102, and the lower electrode layer 101 is completed, the embodiment of the present application sets the first hard mask layer 104 on the upper electrode layer 103 and performs single photolithography and etching to the lower electrode layer 101, thereby exposing the lower electrode area with the protruding island structure 107; then, the second hard mask layer 108 is deposited, and the side wall 109 is formed on the side wall of the island structure 107, which, together with the island structure 107, serves as an etching mask to selectively shield the lower electrode layer 101 during the subsequent dry etching and whole-surface etching, thereby defining the final pattern of the lower electrode in a self-aligned manner. Since the pattern of the lower electrode is naturally defined by the side wall 109 and the island structure 107, no additional mask is needed for alignment and exposure, which significantly simplifies the process flow and reduces the cost of the mask.
[0041] It should be emphasized that, in the embodiment of the present application, the island structure 107 plays multiple key roles in the preparation of the MIM capacitor. The island structure 107 is located at a predetermined distance from the upper electrode layer 103 in the horizontal direction, ensuring that the two are physically completely isolated. This distance design ensures that, when the first through-hole 111 is formed through the upper interlayer dielectric layer 110 and the side wall 109, and the first metal structure 112 is filled to connect the lower electrode layer 101, even if there is a certain process offset, since the island structure 107 is far away from the upper electrode layer 103, the first metal structure 112 can effectively avoid accidental contact with the upper electrode layer 103, thereby fundamentally preventing the risk of short circuit between the upper and lower electrodes.
[0042] Secondly, the island structure 107 is considered as a part of the lower electrode, and after the deposition of the second hard mask layer 108, the sidewall of the island structure 107 naturally forms a sidewall 109, which, together with the island structure 107, constitutes a self-aligned etching mask of the pattern of the lower electrode layer 101, so that the lower electrode can be accurately defined without additional masks, significantly simplifying the process and reducing the cost. More importantly, the island structure 107 itself provides a larger and fixed exposed area, creating sufficient and reliable contact windows for subsequent via processes, not only improving the contact area, but also enhancing the process tolerance. The island structure 107 provides a larger contact area for subsequent vias, improving the connection reliability between the lower electrode and the interconnection metal.
[0043] In summary, the island structure 107 ensures electrical isolation through spatial isolation, defines the pattern through self-alignment, and improves connection reliability through geometric optimization, which is the core technical feature of high-yield and low-cost MIM capacitor manufacturing.
[0044] The embodiment of the present application introduces the island structure 107 and the double hard mask sidewall 109 process, which defines the upper electrode using only one mask, and uses the sidewall 109 and the island to self-align the lower electrode layer 101, eliminating the second mask used to define the lower electrode in the traditional process, significantly simplifying the process steps and effectively reducing the mask cost; At the same time, the island structure 107 not only provides a stable and increased contact area for the lower electrode, improving the reliability of the via connection, but also maintains a safe distance with the upper electrode layer 103 in the horizontal direction, fundamentally avoiding the risk of short circuit with the upper electrode during subsequent metal filling of the via, thereby reducing the cost while considering the device performance and manufacturing yield.
[0045] In one embodiment, forming the sidewall 109 covering the sidewall of the island structure 107 can include: Referring to Figure 6 After forming the plurality of island structures 107 and the upper electrode structure 116, and removing the photoresist layer 115, the second hard mask layer 108 is deposited; the second hard mask layer 108 covers the exposed lower electrode layer 101 and the surface of the first hard mask layer 104.
[0046] Further, the second hard mask layer 108 is dry etched to remove the second hard mask layer 108 on the first hard mask layer 104, and to remove part of the second hard mask layer 108 on the lower electrode layer 101, forming the sidewall 109.
[0047] It should be noted that, since the dry etching has anisotropy, the etching direction is mainly vertically downward, and the lateral etching is less. The second hard mask layer 108 on the first hard mask layer 104 and the second hard mask layer 108 on the lower electrode layer 101 have the same thickness and the same etching rate, so they can be etched synchronously. The etching rate at the angle formed by the sidewall of the island structure 107 and the lower electrode layer 101 is slow, and the sidewall 109 close to the sidewall of the island structure 107 can be retained to form a sidewall 109.
[0048] The sidewall 109 shields the lower electrode layer 101 below. In subsequent etching, the area of the lower electrode layer 101 covered by the sidewall 109 is protected, and the other lower electrode layer 101 not covered by the sidewall 109 is exposed.
[0049] As an optional embodiment, the first metal structure 112 connected with the lower electrode layer 101 in the first via hole 111 can include: As shown in Figure 11 , Figure 12 The first metal structure 112 connected with the lower electrode layer 101 and the island structure 107 is deposited in the first via hole 111.
[0050] In the above embodiment, the case that the first metal structure 112 is only connected with the lower electrode layer 101 means that the via hole bottom contact area is limited to the planar part of the lower electrode layer 101, and the island structure 107 is not specially used as a contact enhancement area. Although this connection method can achieve basic electrical connection, the contact area is limited, the via hole alignment accuracy is required, and when the lower electrode pattern is defined by the sidewall 109 self-alignment and the contact window is narrow, there is a risk of increasing contact resistance or connection failure.
[0051] In contrast, the way that the first metal structure 112 is not only connected with the lower electrode layer 101 but also connected with the island structure 107 fully utilizes the island structure 107 as a three-dimensional contact enhancement area protruding from the lower electrode layer 101 and fixed in position. Since the island structure 107 has been formed integrally with the lower electrode layer 101 in the previous photolithography and etching process, its top and sidewall provide a larger exposed area and a more tolerant via hole alignment window. After the first metal structure 112 fills the via hole, it can form an electrical connection with the top of the island structure 107 and the lower electrode layer 101 around it at the same time, significantly increasing the effective contact area, reducing the contact resistance, and improving the process tolerance. More importantly, the island structure 107 and the upper electrode layer 103 maintain a safe distance in the horizontal direction, ensuring that even if the via hole is slightly offset, the first metal structure 112 will not short-circuit with the upper electrode. Therefore, this connection method realizes higher reliability and better electrical connection performance on the premise of ensuring electrical isolation.
[0052] As an optional implementation, the first via hole 111 is formed on the upper interlayer dielectric layer 110, and the first via hole 111 penetrates the upper interlayer dielectric layer 110 and the side wall 109 to the lower electrode layer 101, which can include: As shown in Figure 11 The first via hole 111 penetrates the side wall 109 on the side of the island structure 107 away from the first upper electrode 117.
[0053] It should be noted that, in the embodiment of the present application, the first via hole 111 is arranged to penetrate the side wall 109 on the side of the island structure 107 away from the first upper electrode 117 (i.e. away from the upper electrode region), so as to ensure that the via hole path completely avoids the upper electrode layer 103 and the region directly below it, thereby achieving sufficient isolation of the lower electrode contact point and the upper electrode in physical space. Since the island structure 107 is considered as part of the lower electrode layer 101, and the side of the island structure 107 away from the first upper electrode 117 maintains a safe distance with the upper electrode in the horizontal direction, the side wall 109 region becomes a more optimal via hole opening position.
[0054] When etching to form the first via hole 111, it can accurately pass through the upper interlayer dielectric layer 110 and the side wall 109 on the side, and directly reach the island structure 107 and the connected lower electrode layer 101, to achieve reliable electrical connection. At the same time, since the via hole is located in the region away from the upper electrode, even if there is a process deviation, it will not cause the first metal structure 112 to short circuit with the upper electrode layer 103, thereby significantly improving the electrical isolation and manufacturing yield of the device. This design cleverly utilizes the spatial layout of the island structure 107 and the self-alignment characteristics of the side wall 109, while saving the lower electrode mask, and takes into account the connection reliability and short circuit protection.
[0055] Unlike the above-mentioned implementation, the embodiment of the present application also provides another way, the first via hole 111 is formed on the upper interlayer dielectric layer 110, and the first via hole 111 penetrates the upper interlayer dielectric layer 110 and the side wall 109 to the lower electrode layer 101, which can include: The first via hole 111 penetrates the side wall 109 on the side of the island structure 107 close to the first upper electrode 117.
[0056] In the embodiment of the present application, the first via hole 111 penetrates the side wall 109 on the side of the island structure 107 close to the first upper electrode 117, compared with the above-mentioned "penetrating the side wall 109 on the side away from the first upper electrode 117", the core difference is that the via hole position is closer to the first upper electrode 117 where the upper electrode is located, but still ensures electrical isolation and reliable connection through structural design.
[0057] It should be noted that arranging the via hole close to the first upper electrode 117 can shorten the lateral wiring distance of the lower electrode to the subsequent interconnection metal, which is beneficial to improve the device integration density and signal transmission efficiency. On the other hand, since the island structure 107 itself and the upper electrode layer 103 have a reserved safety distance in the horizontal direction, even if the via hole is located close to the first upper electrode 117, as long as the alignment accuracy is controlled, it can still ensure that the via hole only contacts the island structure 107 and the lower electrode layer 101, and does not touch the upper electrode or the dielectric layer 102 region below it, thereby avoiding short circuit. In addition, the side wall 109 at this position usually has good morphology control in the process, which is beneficial to the uniformity of via hole etching and the integrity of metal filling. Therefore, this embodiment further optimizes the interconnection layout on the basis of maintaining the advantages of self-alignment, mask saving, and short circuit prevention, and is suitable for advanced process scenarios with higher requirements for wiring compactness.
[0058] It should be noted that the first via hole 111 can also be made to penetrate the side wall 109 between adjacent island structures 107 to the lower electrode layer 101 according to needs, that is, a first metal structure 112 connected with the lower electrode layer 101 is arranged between the adjacent island structures 107.
[0059] As an optional embodiment, the first via hole 111 is formed on the upper interlayer dielectric layer 110, the first via hole 111 penetrates the upper interlayer dielectric layer 110 and the side wall 109 to the lower electrode layer 101, and can further include: As shown in Figure 11 , the second via hole 113 is formed on the upper interlayer dielectric layer 110, the second via hole 113 penetrates the upper interlayer dielectric layer 110 and the first hard mask layer 104 on the upper electrode structure 116 to the upper electrode layer 103.
[0060] In this embodiment, the first metal structure 112 connected with the lower electrode layer 101 is deposited in the first via hole 111, and can further include: As shown in Figure 12 , the second metal structure 114 connected with the upper electrode layer 103 is deposited in the second via hole 113.
[0061] It should be noted that the present embodiment simultaneously opens the first via hole 111 and the second via hole 113 in the upper interlayer dielectric layer 110 after forming the MIM capacitor structure, wherein the first via hole 111 penetrates the side wall 109 (preferably located on one side of the island structure 107) to contact the lower electrode layer 101, and the second via hole 113 penetrates the upper interlayer dielectric layer 110 on the upper electrode structure 116 and the first hard mask layer 104 of the upper electrode structure 116, and is directly connected to the upper electrode layer 103; then the first metal structure 112 and the second metal structure 114 are filled in the first via hole 111 and the second via hole 113 respectively, to realize independent and reliable lead-out of the lower electrode and the upper electrode.
[0062] As Figure 1 , Figure 2 and Figure 12 shown, the embodiment of the present application provides a MIM capacitor, which can include: a substrate structure 100, and a lower electrode layer 101 disposed on the substrate structure 100, and an upper electrode structure 116, a plurality of island structures 107, a side wall 109, a first metal structure 112 and a second metal structure 114 located on the lower electrode layer 101; the upper electrode structure 116 and the island structure 107 each include a dielectric layer 102, an upper electrode layer 103 and a first hard mask layer 104; In the embodiment, the upper electrode structure 116 includes a first upper electrode 117 and a plurality of second upper electrodes 118 connected with the first upper electrode 117, the plurality of island structures 107 are arranged along a first direction Y, and the second upper electrode 118 is between adjacent island structures 107, the island structure 107 and the first upper electrode 117 are arranged along a second direction X, and each island structure 107 has an isolation opening between the first upper electrode 117 and the second upper electrode 118; the lower electrode layer 101 is provided with the side wall 109 located on the side surface of the island structure 107; the first metal structure 112 is connected with the lower electrode layer 101 through the side wall 109; and the second metal structure 114 is connected with the upper electrode layer 103 of the upper electrode structure 116 through the first hard mask layer 104.
[0063] It should be noted that the embodiment of the present application integrates an island structure 107 maintaining a horizontal distance with the upper electrode layer 103 on the lower electrode layer 101, and a side wall 109 formed by a second hard mask layer 108 is arranged on the side surface of the island structure 107; after the upper interlayer dielectric layer 110 covers the overall structure, the upper and lower electrodes are respectively realized by two independent through holes. Among them, the first metal structure 112 is connected to the lower electrode layer 101 (including the island structure 107) through the through hole penetrating the side wall 109, and the second metal structure 114 is connected to the upper electrode layer 103 through the through hole penetrating the first hard mask layer 104.
[0064] It should be noted that the island structure 107 is regarded as a part of the lower electrode, not only provides an increased and self-aligned contact area for the first metal structure 112, improves the connection reliability, and the preset distance between the island structure 107 and the upper electrode layer 103 more effectively prevents the upper and lower electrodes from short circuiting due to the through hole offset; the side wall 109 is used as a self-aligned mask during the manufacturing process, and an independent mask required for defining the lower electrode is saved; at the same time, the reserved first hard mask layer 104 provides a precise alignment reference for the second through hole 113, and the upper electrode can be realized without additional photolithography. The overall scheme realizes a high-integration, high-yield and low-cost MIM capacitor structure under the premise of using only one mask.
[0065] As an optional implementation, the MIM capacitor can further include: an upper interlayer dielectric layer 110 covering the first hard mask layer 104 and the sidewall 109.
[0066] In the embodiment, the first metal structure 112 further penetrates the upper interlayer dielectric layer 110 on the sidewall 109, and the second metal structure 114 further penetrates the upper interlayer dielectric layer 110 on the upper electrode structure 116.
[0067] As an optional implementation, the sum of the projection areas of the sidewall 109, the upper electrode structure 116 and the island structure 107 on the base structure 100 is equal to the projection area of the lower electrode layer 101 on the base structure 100.
[0068] It should be noted that, in the manufacturing process, the lower electrode layer 101 is initially deposited in a full surface, and finally, through full surface etching, the lower electrode layer 101 material not covered by the sidewall 109, the island structure 107 and the upper electrode layer 103 is removed, so that only the lower electrode part corresponding to the covered area of the sidewall 109, the island structure 107 and the upper electrode layer 103 is retained. Therefore, the actual pattern of the finally formed lower electrode layer 101 is jointly defined by the upper electrode layer 103, the island structure 107 and the surrounding sidewall 109, and the total projection on the base structure 100 is exactly equal to the area of the original lower electrode layer 101 that is retained. This design not only ensures the high controllability of the lower electrode size and the effective area of the capacitor, but also realizes completely self-aligned pattern transfer, accurately defines the lower electrode boundary without additional masks, and avoids the risk of capacitor value deviation or short circuit caused by over-etching or under-etching, thereby simplifying the process while ensuring the consistency and reliability of the device performance.
[0069] As an optional implementation, the width of the sidewall 109 is equal to the sum of the thickness of the upper electrode layer 103 and the thickness of the dielectric layer 102. The width of the sidewall 109 is greater than the diameter of the via used to form the first metal structure 112.
[0070] It should be noted that, in the conventional MIM capacitor, the thickness of the upper electrode layer 103 and the lower electrode layer 101 is 100-300 nm, and the thickness of the dielectric layer 102 is 20-150 nm. When the width of the sidewall 109 is equal to the sum of the thickness of the upper electrode layer 103 and the thickness of the dielectric layer 102, the width of the sidewall 109 can reach 120-450 nm. The via width of the 28 nm and below technology node is 20-60 nm, and the standard via width of the advanced process (5 nm and below) is about 20-30 nm. In the 3 nm process, the via width of the key layer can be as low as 22 nm, and the reserved width of the lower electrode layer 101 according to the embodiment is much larger than the via width.
[0071] In the embodiments of the present application, the width of the side wall 109 is designed to be equal to the sum of the thickness of the upper electrode layer 103 and the thickness of the dielectric layer 102, which is much larger than the diameter of the via used to form the first metal structure 112 in advanced process nodes (such as 28 nm and below, especially 5 nm and 3 nm nodes) (usually only 20-60 nm, and as low as about 22 nm in 3 nm nodes). This design ensures that when the first via 111 connecting the lower electrode is formed by subsequent etching, even if there is a certain lithography or etching offset, the via can still completely fall within the reserved area of the lower electrode protected by the side wall 109, avoiding the via deviating from the lower electrode or damaging the surrounding dielectric layer 102 due to alignment errors. At the same time, since the side wall 109 itself is composed of a hard mask material, the structure is dense and the edge is vertical, which can serve as a reliable boundary and self-alignment reference for via etching, significantly improving the process window and yield.
[0072] As an optional embodiment, the distance between the island structure 107 and the side surface of the upper electrode layer 103 is greater than the thickness of the side wall 109.
[0073] It should be noted that when the anisotropic etching is performed after depositing the second hard mask layer 108, not only the side wall 109 will be formed on the side wall of the island structure 107, but also another group of side walls 109 will be formed on the side wall of the adjacent upper electrode layer 103; when the distance between the two groups of side walls 109 is greater than twice the thickness of the side wall 109, the two groups of side walls 109 will not merge in space, thereby leaving an independent and clear side wall 109 profile on the side of the island structure 107 close to the upper electrode, forming a local "double side wall 109" region. When the first via 111 is opened in this region, the gap between the double side walls 109 or the side wall 109 of the island structure 107 can be used as a reliable etching window, which not only ensures that the via can stably contact the lower electrode, but also effectively prevents short circuit with the upper electrode during the via etching or metal filling process due to the physical isolation of the side wall 109 on the side wall of the upper electrode. Therefore, by controlling the distance between the island and the upper electrode to be greater than the thickness of the side wall 109, not only a more robust self-alignment patterning is achieved, but also a structural guarantee for high-reliability interconnection is provided.
[0074] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A method for fabricating a MIM capacitor, characterized in that, include: A substrate structure is provided, on which a lower electrode layer, a dielectric layer, an upper electrode layer and a first hard mask layer are sequentially stacked. A photoresist layer is formed on the first hard mask layer; The photoresist layer has an opening pattern for defining the island structure and the upper electrode structure; Using the photoresist layer as a mask, the first hard mask layer, the upper electrode layer, and the dielectric layer are etched to form a plurality of island structures and an upper electrode structure located on the lower electrode layer. The upper electrode structure includes a first upper electrode and a plurality of second upper electrodes connected to the first upper electrode. The plurality of island structures are arranged along a first direction, and a second upper electrode is provided between adjacent island structures. The island structures and the first upper electrode are arranged along a second direction, and each island structure has an isolation opening between the first upper electrode and the second upper electrode. The first direction is perpendicular to the second direction. Forming a sidewall that covers the sidewalls of the island structure; Using the sidewalls and the first hard mask layer as masks, the lower electrode layer is etched to form a MIM structure; A first metal structure is formed that penetrates the sidewall and is connected to the lower electrode layer.
2. The method for preparing a MIM capacitor according to claim 1, characterized in that, The first metal structure forming the first metal structure that penetrates the sidewall and is connected to the lower electrode layer includes: An interlayer dielectric layer is deposited on the MIM structure; A first through-hole is formed on the upper interlayer dielectric layer, and the first through-hole penetrates the upper interlayer dielectric layer and the sidewall to the lower electrode layer; A first metal structure connected to the lower electrode layer is deposited within the first through-hole.
3. The method for preparing a MIM capacitor according to claim 2, characterized in that, The first through hole penetrates the sidewall of the island structure away from the first upper electrode; or, the first through hole penetrates the sidewall of the island structure close to the first upper electrode.
4. The method for preparing a MIM capacitor according to claim 1, characterized in that, The method further includes: A second metal structure is formed that is connected to the upper electrode layer of the upper electrode structure.
5. The method for preparing a MIM capacitor according to claim 1, characterized in that, The sidewalls forming the sidewalls covering the sidewalls of the island structure include: After removing the photoresist layer, a second hard mask layer is deposited; the second hard mask layer covers the lower electrode layer and the first hard mask layer; Dry etching is performed on the second hard mask layer to remove the second hard mask layer on the first hard mask layer and to remove part of the second hard mask layer on the lower electrode layer, thereby forming the sidewall.
6. The method for preparing a MIM capacitor according to claim 1, characterized in that, The first metal structure is also connected to the island structure.
7. A MIM capacitor, characterized in that, include: The substrate structure includes a lower electrode layer disposed on the substrate structure, an upper electrode structure disposed on the lower electrode layer, multiple island structures, sidewalls, a first metal structure, and a second metal structure; the upper electrode structure and the island structures each include a dielectric layer, an upper electrode layer, and a first hard mask layer. The upper electrode structure includes a first upper electrode and a plurality of second upper electrodes connected to the first upper electrode. The plurality of island structures are arranged along a first direction, and a second upper electrode is provided between adjacent island structures. The island structures and the first upper electrode are arranged along a second direction, and each island structure has an isolation opening between itself and the first and second upper electrodes. The first direction is perpendicular to the second direction. The lower electrode layer is provided with a sidewall located on the side of the island structure; The first metal structure penetrates the sidewall and connects to the lower electrode layer; The second metal structure penetrates the first hard mask layer and connects to the upper electrode layer of the upper electrode structure.
8. The MIM capacitor according to claim 7, characterized in that, Also includes: An upper interlayer dielectric layer covers the first hard mask layer and the sidewalls; The first metal structure also penetrates the upper interlayer dielectric layer on the sidewall, and the second metal structure also penetrates the upper interlayer dielectric layer on the upper electrode structure.
9. The MIM capacitor according to claim 7, characterized in that, The sum of the projected areas of the sidewall, the upper electrode structure, and the multiple island structures on the substrate structure is equal to the projected area of the lower electrode layer on the substrate structure.
10. The MIM capacitor according to claim 7, characterized in that, The width of the sidewall is equal to the sum of the thickness of the upper electrode layer and the thickness of the dielectric layer.