Longitudinal conductive gallium nitride-based normally-closed field effect transistor and preparation method thereof

Abstract

The invention discloses a longitudinal conductive gallium nitride-based normally-off field effect transistor and a preparation method thereof, and relates to the technical field of power electronic devices. The structure comprises a substrate, a buffer layer, an i-GaN epitaxial layer, an AlN epitaxial layer, a GaN epitaxial layer, an Al2O3 oxide layer, an n-GaN regrowth layer, an i-GaN regrowth layer, an n +-GaN regrowth layer, an oxide layer, a source electrode arranged on the n +-GaN regrowth layer, a drain electrode arranged on the n-GaN regrowth layer, and a grid electrode arranged on the oxide layer. The influence of the surface state of the gallium nitride material on the breakdown performance of the device is reduced, and the voltage endurance capability of the device can be greatly improved; the device has good threshold voltage regulation and control capability, and can obtain higher output current density theoretically; besides, the grid electrode can be of a circular structure, and the source electrode and the drain electrode can be of an annular structure, so that the source electrode and the drain electrode which are interconnected in a large area can be formed, output current of the device is greatly improved, packaging of the device is facilitated, and the device is more suitable for manufacturing high-voltage power electronic devices.

Description

Technical Field

[0001] This invention relates to the field of power electronic device technology, and in particular to a vertically conductive gallium nitride-based normally off field-effect transistor and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) materials exhibit high electron mobility. High electron mobility (>1200 cm⁻¹) can be achieved at the interface of Al(Ga)N / GaN heterostructures formed through modulated doping. 2 V -1 s -1 High concentration (>1×10) 13 cm -2 Gallium nitride (GaN) exists as a two-dimensional electron gas (2DEG), making it highly suitable for fabricating devices with high current densities. Furthermore, the high electron saturation drift velocity and large bandgap of GaN materials determine that devices possess high cutoff frequencies and breakdown voltages, meeting the requirements of power electronic devices for reduced switching losses and high breakdown voltages. Therefore, the application of GaN in electronic devices has become a research hotspot in recent years, and significant progress has been made.

[0003] Kanamura et al. of Fujitsu Corporation of Japan formed a normally-off AlGaN / GaN MISHFET by etching gate trenches on AlGaN / GaN with an n-GaN / i-AlN / n-GaN cap layer and then depositing an Al2O3 high-k dielectric layer using atomic layer deposition (ALD). The threshold voltage is +3V and the maximum current density is 829mA / mm, achieving both normally-off operation and high-density current output (Reference: Kanamura M, Ohki T, Kikkawa T, Imanishi K, Imada T, Yamada A, and Hara. N. Enhancement-Mode GaN MIS-HEMTs With n-GaN / AlN / n-GaNTriple Cap Layer and High-k Gate Dielectrics. IEEE Electron. Lett., 2010, 31(3):189-191.).

[0004] However, most of the GaN-based electric field-effect transistors currently being developed adopt a lateral conductive structure with the conductive channel located near the semiconductor surface, and the "breakdown voltage" is generally below 800V, which presents a bottleneck in achieving both "high voltage" and "high current" operation at the same time.

[0005] The main method for improving the breakdown voltage of devices is the use of field plate technology. In 2000, Dr. Zhang Naiqian and others at UCSB first used a field plate structure to obtain a GaN-based field-effect transistor device with a breakdown voltage of 570V. Since then, using gate field plate technology, the breakdown voltage of GaN-based devices has been reported to exceed 2000V (Reference: IKEDA N, KAYA S, LI J, et al. High power AlGaN / GaN MIS-HFETs with field plates on Sisubstrates [C] ∥Proc of the 21st ISPSD. Barcelona, ​​Spain, 2009:2512254).

[0006] However, gallium nitride-based devices with lateral conductive structures are always prone to surface breakdown due to the influence of the material's surface states. In a vertical conductive design, the conductive channel is located far from the surface. Therefore, using a vertical conductive structure is highly feasible for achieving ultra-high withstand voltage. Summary of the Invention

[0007] One of the objectives of this invention is to provide a method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor, so that the fabricated device can significantly improve its withstand voltage capability and at the same time have good threshold voltage regulation capability.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: a method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor, comprising the following steps: (A) A buffer layer (2), an i-GaN epitaxial layer (3), an AlN epitaxial layer (4) and a GaN epitaxial layer (5) are grown sequentially on a substrate (1), wherein the AlN epitaxial layer (4) and the GaN epitaxial layer (5) form an AlN / GaN heterojunction.

[0009] (B) An Al2O3 oxide layer (6) is fabricated on the cap layer of the GaN epitaxial layer (5) by atomic layer deposition.

[0010] (C) Photolithography and selective etching are performed by plasma etching, and the etching depth reaches the i-GaN epitaxial layer (3).

[0011] (D) On the i-GaN epitaxial layer (3) in the selectively etched region, an n-GaN regenerated layer (7), an i-GaN regenerated layer (8), and an n-GaN regenerated layer (9) are sequentially formed by secondary epitaxial growth. + -GaN regenerated layer (9).

[0012] (E) The i-GaN regenerated layer (8) and n above the n-GaN regenerated layer (7) + The i-GaN regenerated layer (9) is selectively etched, and the etching depth enters the i-GaN regenerated layer (8) to form a groove structure.

[0013] (F) An oxide layer (10) is formed on the surface of a semiconductor material.

[0014] (G) Photolithography of the drain region pattern, and then selective etching of the semiconductor to the n-GaN regeneration layer (7).

[0015] (H) Photolithography is used to pattern the source and drain regions, and the oxide layer in the source region is removed by wet etching. Then, the drain (12) is fabricated on the n-GaN regenerated layer (7) by electron beam evaporation of metal. + - The source electrode (11) is fabricated on the GaN regenerated layer (9) and an ohmic contact is formed by rapid thermal annealing.

[0016] (I) After photolithography, metal is deposited on the oxide layer (9) to form the gate (13).

[0017] Preferably, in step (B), the thickness of the Al2O3 oxide layer (6) is 5~20 nm.

[0018] More preferably, in step (D), the material of each layer structure formed by the secondary epitaxial growth is selected as GaN-based single-junction heterojunction, GaN-based multi-junction heterojunction, or homojunction containing n-type heavily doped GaN layer.

[0019] More preferably, in step (F), the material of the oxide layer (10) is selected as Al2O3 or a high-K dielectric material.

[0020] More preferably, in step (H), the metal materials of the source (11) and drain (12) are Ti / Al / Ni / Au, Ti / Al / Pt / Au, or Ti / Al / Mo / Au.

[0021] More preferably, in step (I), the metal used in the metal vapor deposition process to form the gate (13) is Ni / Au, Pt / Au, or Pd / Au.

[0022] More preferably, in step (A), the growth temperature of the i-GaN epitaxial layer (3), the AlN epitaxial layer (4) and the GaN epitaxial layer (5) is 1050~1200℃.

[0023] More preferably, in step (A), the buffer layer (2) is an AlN or low-temperature GaN structure layer with a growth temperature of 700~1000℃.

[0024] More preferably, in step (C), the plasma etching method is inductively coupled plasma etching or reactive ion etching.

[0025] In addition, the present invention also provides a vertically conductive gallium nitride-based normally-off field-effect transistor, which is prepared by the above-described method for preparing a vertically conductive gallium nitride-based normally-off field-effect transistor.

[0026] Because the source of the device is located at the n-th epitaxial growth point. + The drain is located on the secondary epitaxially grown n-GaN regenerated layer. When a sufficiently large forward bias voltage is applied to the gate, the n-GaN layer below the gate provides conductive charge for communication. The drain current flows sequentially through the primary grown AlN / GaN heterojunction, the secondary grown n-GaN regenerated layer, and the majority carrier accumulated i-GaN regenerated layer, towards the source. Therefore, Al2O3 becomes the current blocking layer between the drain and source, forming a normally-off device with a vertically conductive structure.

[0027] Compared with the prior art, the present invention has the following technical advantages: (1) The formation of the longitudinal conductive structure reduces the influence of the surface state of gallium nitride material on the breakdown performance of the device and can greatly improve the withstand voltage of the device.

[0028] (2) Before the secondary epitaxial growth, the etching depth of the gate and drain regions reaches the i-GaN epitaxial layer. The n-GaN regenerated layer is connected to the AlN / GaN heterojunction grown in the first stage. When the gate is working, the channel below the gate can be turned on without applying a large gate voltage. At the same time, the threshold voltage is controlled by adjusting the doping concentration of the n-GaN regenerated layer and the etching depth in step C. Therefore, the device has good threshold voltage control capability.

[0029] (3) The conductive channel mainly adopts AlN / GaN heterojunction. Compared with AlN / AlGaN heterojunction, it has a smaller on-resistance and can theoretically obtain a larger output current density.

[0030] (4) The gate can be circular, and the source and drain can be ring-shaped, thus forming a large area of ​​interconnected source and drain electrodes, which greatly improves the output current of the device and facilitates the packaging of the device. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure obtained in step (A) of the process flow of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure obtained in step (B) of the process flow of Embodiment 1 of the present invention; Figure 3This is a schematic diagram of the structure obtained in step (C) of the process flow of Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the structure obtained in step (D) of the process flow of Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the structure obtained in step (E) of the process flow of Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the structure obtained in step (F) of the process flow of Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the structure obtained in step (G) of the process flow of Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of the structure obtained in step (H) of the process flow of Embodiment 1 of the present invention; Figure 9 This is a schematic diagram of the structure obtained in step (I) of the process flow of Embodiment 1 of the present invention (i.e., a schematic diagram of the vertically conductive gallium nitride-based normally off field-effect transistor structure prepared in Embodiment 1). Figure 10 This is a schematic diagram of the transistor structure prepared in Embodiment 2 of the present invention.

[0032] In the picture: 1—Substrate; 2—Buffer layer; 3—i-GaN epitaxial layer 4—AlN epitaxial layer; 5—GaN epitaxial layer; 6—Al2O3 oxide layer 7—n-GaN regenerated layer; 8—i-GaN regenerated layer 9——n + -GaN regenerated layer 10 - Oxide layer 11 - Source electrode 12—Drain; 13—Gate; 14—AlN regenerated layer. Detailed Implementation

[0033] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present invention. Example 1

[0034] Figure 9 The diagram shown is a schematic of the vertically conductive gallium nitride-based normally-off field-effect transistor structure prepared in Example 1. The structure includes a substrate 1, a buffer layer 2, an i-GaN epitaxial layer 3 (unintentionally doped GaN epitaxial layer), an AlN epitaxial layer 4, a GaN epitaxial layer 5, an Al2O3 oxide layer 6, an n-GaN regenerated layer 7, an i-GaN regenerated layer 8, and an n... + -GaN regeneration layer 9, oxide layer 10, set on n +The source 11 is disposed on the GaN regenerated layer 9, the drain 12 is disposed on the n-GaN regenerated layer 7, and the gate 13 is disposed on the oxide layer 10.

[0035] The fabrication process of the aforementioned vertically conductive gallium nitride-based normally-off field-effect transistor is as follows: (A) such as Figure 1 As shown, a buffer layer 2, an i-GaN epitaxial layer 3, an AlN epitaxial layer 4, and a GaN epitaxial layer 5 are sequentially grown on a substrate 1 using metal-organic chemical vapor deposition (MOCVD). The growth temperatures of the i-GaN epitaxial layer 3, AlN epitaxial layer 4, and GaN epitaxial layer 5 are between 1050℃ and 1200℃. The substrate 1 is sapphire, silicon, silicon carbide, or gallium nitride. The buffer layer 2 is an AlN or low-temperature GaN structure layer, grown at a temperature between 700℃ and 1000℃. (B) such as Figure 2 As shown, an Al2O3 oxide layer 6 with a thickness of 10 nm was fabricated on the cap layer of the GaN epitaxial layer 5 by atomic layer deposition.

[0036] (C) such as Figure 3 As shown, photolithography and selective etching are performed using plasma etching, with the etching depth reaching the i-GaN epitaxial layer 3. The etching method used is inductively coupled plasma etching or reactive ion etching, and the gas used is a mixture of Cl2 and BCl3.

[0037] (D) such as Figure 4 As shown, an n-GaN regenerated layer 7, an i-GaN regenerated layer 8, and an n-GaN regenerated layer 9 are sequentially formed on the i-GaN epitaxial layer 3 in the selectively etched region through secondary epitaxial growth. + -GaN regeneration layer 9, the growth conditions for this step are the same as those for step (A).

[0038] (E) such as Figure 5 As shown, the i-GaN regenerated layer 8 and n above the n-GaN regenerated layer 7 + The -GaN regenerated layer 9 is selectively etched, with the etching depth penetrating into the i-GaN regenerated layer 8 to form a groove structure. The etching method used is either inductively coupled plasma etching or reactive ion etching.

[0039] (F) such as Figure 6 As shown, an oxide layer 10 is fabricated in the entire semiconductor region without photolithography by atomic layer deposition or sputtering. The material of the oxide layer 10 is Al2O3 or a high-k dielectric material.

[0040] (G) such as Figure 7As shown, the drain region pattern is etched, and then the semiconductor is selectively etched to the n-GaN regeneration layer 7. The etching method used is either inductively coupled plasma etching or reactive ion etching.

[0041] (H) such as Figure 8 As shown, the source and drain regions are patterned by photolithography, and the oxide layer in the source region is removed by wet etching. Then, the drain 12 is fabricated on the n-GaN regrown layer 7 by electron beam evaporation of metal. + Source electrode 11 is fabricated on GaN regenerated layer 9, and ohmic contacts are formed through rapid thermal annealing. Both source electrode 11 and drain electrode 12 are made of Ti / Al / Ni / Au (four-layer electrode metal).

[0042] (I) If Figure 9 As shown, after photolithography, metal is deposited on oxide layer 9 to form gate 13, thereby fabricating the vertically conductive gallium nitride-based normally off field-effect transistor of Example 1. The metal used in this process is Ni / Au (two-layer electrode metal). Example 2

[0043] like Figure 10 The diagram shows the device structure of Embodiment 2. It is similar to the device structure of Embodiment 1, except that in manufacturing process step D, the n-type material grown via secondary epitaxial growth is... + - Replace GaN regenerated layer 9 with AlN regenerated layer 14.

[0044] Specifically The present invention has provided a detailed description of the vertically structured gallium nitride-based normally-off field-effect transistor and its manufacturing method. In order to make it easier for those skilled in the art to understand the improvements of the present invention compared with the prior art, some of the drawings and descriptions of the present invention have been simplified. The above embodiments are preferred implementations of the present invention. In addition, the present invention can be implemented in other ways. Any obvious substitutions without departing from the concept of the present technical solution are within the protection scope of the present invention.

Claims

1. A method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor, characterized in that, Includes the following steps: (A) A buffer layer (2), an i-GaN epitaxial layer (3), an AlN epitaxial layer (4) and a GaN epitaxial layer (5) are grown sequentially on a substrate (1). (B) An Al2O3 oxide layer (6) is fabricated on the cap layer of the GaN epitaxial layer (5) by atomic layer deposition. (C) Photolithography and selective etching are performed by plasma etching, and the etching depth reaches the i-GaN epitaxial layer (3). (D) On the i-GaN epitaxial layer (3) in the selectively etched region, an n-GaN regenerated layer (7), an i-GaN regenerated layer (8), and an n-GaN regenerated layer (9) are sequentially formed by secondary epitaxial growth. + -GaN regenerated layer (9); (E) The i-GaN regenerated layer (8) and n above the n-GaN regenerated layer (7) + - The GaN regenerated layer (9) is selectively etched, and the etching depth enters the i-GaN regenerated layer (8) to form a groove structure; (F) Fabrication of an oxide layer (10) on the surface of a semiconductor material; (G) Photolithography of the drain region pattern, and then selective etching of the semiconductor to the n-GaN regeneration layer (7). (H) Photolithography is used to pattern the source and drain regions, and the oxide layer in the source region is removed by wet etching. Then, the drain (12) is fabricated on the n-GaN regenerated layer (7) by electron beam evaporation of metal. + - The source electrode (11) is fabricated on the GaN regenerated layer (9), and an ohmic contact is formed by rapid thermal annealing. (I) After photolithography, metal is deposited on the oxide layer (9) to form the gate (13).

2. The method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor according to claim 1, characterized in that: In step (B), the thickness of the Al2O3 oxide layer (6) is 5~20 nm.

3. The method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor according to claim 1, characterized in that: In step (D), the materials selected for each layer structure formed by secondary epitaxial growth are GaN-based single-junction heterojunction, GaN-based multi-junction heterojunction, or homojunction containing n-type heavily doped GaN layers.

4. The method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor according to claim 1, characterized in that: In step (F), the oxide layer (10) is made of Al2O3 or a high-K dielectric material.

5. The method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor according to claim 1, characterized in that: In step (H), the metal materials of the source (11) and drain (12) are Ti / Al / Ni / Au, Ti / Al / Pt / Au, or Ti / Al / Mo / Au.

6. The method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor according to claim 1, characterized in that: In step (I), the metal used in the metal vapor deposition process to form the gate (13) is Ni / Au, Pt / Au, or Pd / Au.

7. The method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor according to claim 1, characterized in that: In step (A), the growth temperature of the i-GaN epitaxial layer (3), AlN epitaxial layer (4) and GaN epitaxial layer (5) is 1050~1200℃.

8. The method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor according to claim 1, characterized in that: In step (A), the buffer layer (2) is an AlN or low-temperature GaN structure layer with a growth temperature of 700~1000℃.

9. The method for fabricating a longitudinally conductive gallium nitride-based normally-off field-effect transistor according to claim 1, characterized in that: In step (C), the plasma etching method is inductively coupled plasma etching or reactive ion etching.

10. A vertically conductive gallium nitride-based normally-off field-effect transistor, characterized in that: It is prepared by the fabrication method of the longitudinally conductive gallium nitride-based normally off field-effect transistor according to any one of claims 1-9.

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