Thin film transistor

Abstract

There is provided a thin film transistor including: a substrate; an active pattern including a first region, a second region, and a channel region; a gate electrode overlapping the channel region; a gate insulating layer between the active pattern and the gate electrode; a first electrode connected to the first region; and a second electrode connected to the second region. The channel region includes first and second boundaries overlapping side surfaces of the gate electrode, and first and second side surfaces spaced apart from each other in the second direction. The active pattern includes curved portions recessed from the first side surface and the second side surface and spaced apart from each other by a first length. One of the curved portions is spaced apart from the first boundary by a second length, and the other of the curved portions is spaced apart from the second boundary by the second length.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0108039, filed on August 13, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments relate to a thin film transistor, a display device including the same, and an electronic device including the same. BACKGROUND

[0003] Recently, as interest in information display has increased, research and development on display devices have been actively conducted. For example, a display device can include a thin film transistor that controls emission of a pixel and a capacitor. The thin film transistor can include a gate electrode, a first electrode, a second electrode, and an active pattern. The shape of the gate electrode can depend on the shape of the active pattern. In the case where the size of the gate electrode increases, it can be desirable to effectively design a planar structure of a channel region of the active pattern within a design margin.

[0004] This BACKGROUND section is intended to provide useful background information to facilitate a better understanding of the techniques. Accordingly, the BACKGROUND section can include ideas, concepts or recognitions not yet known to others who are working on the subject matter disclosed herein. SUMMARY

[0005] Embodiments relate to a thin film transistor having improved performance. For example, the thin film transistor uses a planar structure in which an active pattern includes a curved portion, thereby reducing a surface area of a channel region and improving process variation.

[0006] Embodiments relate to a display device including a thin film transistor having improved performance.

[0007] Embodiments can provide a thin film transistor included in a display device, the thin film transistor including: a substrate; an active pattern disposed on the substrate, the active pattern including a first region, a second region, and a channel region between the first region and the second region; a gate electrode disposed on the active pattern, superposed with the channel region; a gate insulating layer disposed between the active pattern and the gate electrode; a first electrode disposed on the gate insulating layer, connected to the first region; and a second electrode disposed on the gate insulating layer, connected to the second region. The channel region can include a first boundary and a second boundary superposed with side surfaces of the gate electrode and spaced apart from each other in a first direction. The channel region can further include a first side surface and a second side surface spaced apart from each other in a second direction crossing the first direction. The active pattern can include curved portions recessed from the first side surface and the second side surface of the channel region in the second direction and in a direction opposite to the second direction, respectively. The curved portions can be spaced apart from each other by a first length in the first direction. One of the curved portions can be spaced apart from the first boundary by a second length in the first direction, and the other of the curved portions can be spaced apart from the second boundary by the second length in the direction opposite to the first direction. The second length can be equal to or greater than the first length.

[0008] In embodiments, the curved portions can include a first curved portion recessed from the first side surface in the second direction and a second curved portion recessed from the second side surface in a direction opposite to the second direction. The first curved portion can be spaced apart from the second side surface by a third length in the direction opposite to the second direction, and the second curved portion can be spaced apart from the first side surface by the third length in the second direction.

[0009] In embodiments, the third length can be equal to the first length.

[0010] In embodiments, a length of one of the first boundary or the second boundary in the second direction can be equal to a sum of a length of one of the curved portions in the second direction and the third length.

[0011] In embodiments, the channel region can include a first portion adjacent to the first region, a second portion adjacent to the second region, and a third portion between the first portion and the second portion. The first portion can be spaced apart from the first curved portion by the first length in the direction opposite to the first direction, and the second portion can be spaced apart from the second curved portion by the first length in the first direction. The first portion and the second portion can each have a first width in the second direction. The first width can be equal to the third length.

[0012] In embodiments, the third portion can partially surround the curved portions and can have a constant width.

[0013] In an embodiment, the first portion and the second portion can be spaced apart by the same length from a first imaginary line aligned with the second direction. The first imaginary line can be disposed between the first curved portion and the second curved portion and can be spaced apart by the same distance from each of the first curved portion and the second curved portion.

[0014] In an embodiment, the first portion and the second portion can be superposed with a second imaginary line aligned with the first direction. The third portion can include a dummy portion protruding from an area adjacent to the second portion in the second direction. The dummy portion can form the second curved portion together with other portions of the third portion.

[0015] In an embodiment, the dummy portion can have a second width equal to the first length in the first direction and can have a length equal to a length of each of the first curved portion and the second curved portion in the second direction.

[0016] In an embodiment, the curved portion can further include a third curved portion recessed from the first side surface in the second direction. The third curved portion can be parallel to the first curved portion, wherein the second curved portion is disposed between the third curved portion and the first curved portion.

[0017] In an embodiment, the trench region can include a first portion adjacent to the first area, a second portion adjacent to the second area, and a third portion between the first portion and the second portion. The first portion can be spaced apart by the first length from the first curved portion in a direction opposite to the first direction, and the second portion can be spaced apart by the first length from the third curved portion in the first direction. The first portion and the second portion can each have a first width in the second direction. The first width can be equal to the third length.

[0018] In an embodiment, the third portion can partially surround the curved portion and can have a constant width.

[0019] In an embodiment, the first portion and the second portion can be spaced apart by the same length from a first imaginary line aligned with the second direction. The first imaginary line can be disposed between the first curved portion and the third curved portion and can be spaced apart by the same distance from each of the first curved portion and the third curved portion.

[0020] In an embodiment, the third portion can include a dummy portion protruding from an area adjacent to the second portion in a direction opposite to the second direction. The dummy portion can form the third curved portion together with other portions of the third portion.

[0021] In an embodiment, each of the curved portions can have a third width in the first direction in a case where the second length is greater than the first length. In a case where the first length and the second length are equal to each other, each of the curved portions can have a fourth width greater than the third width in the first direction.

[0022] In an embodiment, the thin film transistor can further include a plurality of insulating layers on the gate electrode. The first electrode and the second electrode can be disposed in the same layer on the insulating layers.

[0023] Embodiments can provide a display device including a display element and a thin film transistor providing a driving signal to the display element. The thin film transistor can include a substrate, an active pattern disposed on the substrate, the active pattern including a first region, a second region, and a channel region between the first region and the second region, a gate electrode disposed on the active pattern to overlap the channel region, a gate insulating layer disposed between the active pattern and the gate electrode, a first electrode disposed on the gate insulating layer to be connected to the first region, and a second electrode disposed on the gate insulating layer to be connected to the second region. The channel region can include a first boundary and a second boundary overlapping side surfaces of the gate electrode and spaced apart from each other in a first direction. The channel region can further include a first side surface and a second side surface spaced apart from each other in a second direction crossing the first direction. The active pattern can include curved portions recessed from the first side surface and the second side surface of the channel region in the second direction and in a direction opposite to the second direction, respectively. The curved portions can be spaced apart from each other by a first length in the first direction. One of the curved portions can be spaced apart from the first boundary by a second length in the first direction, and the other of the curved portions can be spaced apart from the second boundary by the second length in the direction opposite to the first direction. The second length can be equal to or greater than the first length.

[0024] Embodiments can provide an electronic device including a processor providing input image data, and a display device displaying an image based on the input image data, the display device including a display element and a thin film transistor providing a driving signal to the display element, wherein the thin film transistor includes a substrate, an active pattern disposed on the substrate, the active pattern including a first region, a second region, and a channel region between the first region and the second region, a gate electrode disposed on the active pattern, the gate electrode being superposed with the channel region, a gate insulating layer disposed between the active pattern and the gate electrode, a first electrode disposed on the gate insulating layer, the first electrode being connected to the first region, and a second electrode disposed on the gate insulating layer, the second electrode being connected to the second region, wherein the channel region includes a first boundary and a second boundary superposed with side surfaces of the gate electrode and spaced apart from each other in a first direction. The channel region can further include a first side surface and a second side surface spaced apart from each other in a second direction crossing the first direction, wherein the active pattern includes curved portions recessed from the first side surface and the second side surface of the channel region in the second direction and in a direction opposite to the second direction, respectively, wherein the curved portions are spaced apart from each other in the first direction by a first length, wherein one of the curved portions is spaced apart from the first boundary in the first direction by a second length, and another of the curved portions is spaced apart from the second boundary in the direction opposite to the first direction by the second length, wherein the second length is equal to or greater than the first length.

[0025] In embodiments, the electronic device can include, but is not limited to, at least one of a flat panel display, a curved display, a computer monitor, a medical monitor, a television, a billboard, an indoor lamp, an outdoor lamp, a signal lamp, a head-up display, a full transparent display, a partial transparent display, a flexible display, a rollable display, a foldable display, a stretchable display, a laser printer, a telephone, a cellular phone, a video phone, a mobile phone, a smart pad, a tablet computer, a phablet, a personal digital assistant (PDA), a wearable device, a smart watch, a navigation device for a vehicle, a laptop computer, a digital camera, a camcorder, a viewfinder, a micro display, a three-dimensional (3D) display, a virtual reality display, an augmented reality display, a vehicle, a head-mounted display device, a video wall having a plurality of displays spliced together, a theater screen, a stadium screen, a light therapy device, and a signboard.

[0026] The curved portions can include a first curved portion recessed from the first side surface in the second direction and a second curved portion recessed from the second side surface in a direction opposite to the second direction, the first curved portion can be spaced apart from the second side surface in the direction opposite to the second direction by a third length, and the second curved portion can be spaced apart from the first side surface in the second direction by the third length.

[0027] The third length can be substantially equal to the first length.

[0028] The channel region can include a first portion adjacent to the first region, a second portion adjacent to the second region, and a third portion disposed between the first portion and the second portion, the first portion can be spaced apart from the first curved portion by a first length in a direction opposite to the first direction, the second portion can be spaced apart from the second curved portion by the first length in the first direction, the first portion and the second portion can each have a first width in the second direction, and the first width can be substantially equal to the third length.

[0029] The third portion can partially surround the curved portion and have a constant width.

[0030] The electronic device can further include a plurality of insulating layers disposed on the gate electrode, wherein the first electrode and the second electrode can be disposed in the same layer on the insulating layers. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other aspects, features, and advantages of embodiments will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a schematic block diagram illustrating an embodiment of a display device.

[0033] Figure 2 is a schematic block diagram illustrating an embodiment of a display panel in Figure 1 .

[0034] Figure 3 is a schematic circuit diagram illustrating an embodiment of a sub-pixel in Figure 2 .

[0035] Figure 4 is a schematic plan view illustrating an embodiment of a display panel in Figure 1 .

[0036] Figure 5 is a schematic cross-sectional view illustrating an embodiment of a display panel in Figure 1 .

[0037] Figure 6 is a schematic cross-sectional view taken along line I-I' in Figure 4 .

[0038] Figures 7 to 14 is a schematic plan view illustrating an embodiment of a thin film transistor.

[0039] Figure 15 is a schematic block diagram illustrating an electronic device including a display device in an embodiment.

[0040] Figure 16 is a schematic diagram illustrating an example in which the electronic device in Figure 15 is a smartphone. is a schematic diagram illustrating an example in which the electronic device in

[0041] Figure 17 is a schematic diagram showing an example in which the electronic device is a tablet computer. Figure 15 DETAILED DESCRIPTION

[0042] The disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. The disclosure may, however, be embodied in different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Various embodiments can be implemented in conjunction with the embodiments described herein. For example, specific shapes, configurations, and properties of the embodiments can be used or implemented in another embodiment.

[0043] In the drawings, the size, thickness, proportion, and dimension of each element can be exaggerated for the sake of description and clarity and thus, is for illustrative purposes only. Identical reference numerals and / or symbols in the drawings denote like elements.

[0044] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] As used herein, the term "about" or "approximately" includes the recited value and means within an acceptable range of deviation for a particular value, as determined by one of ordinary skill in the art, taking into account measurement uncertainty and error associated with measurement of that particular quantity. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0046] In the description and claims, the term "and / or" is intended to mean any combination of the associated listed items, intercalia, "and" and "or". For example, "A and / or B" is understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the conjunctive or disjunctive sense and can be understood to be equivalent to "and / or".

[0047] The phrase "in plan view" means viewing the object from the top, and the phrase "in schematic cross-sectional view" means viewing a cross-section of the object vertically cut from the side. Thus, the expression "in plan view" used herein can mean viewing the object from the top in the third direction DR3 (or z-axis direction). The phrase "in schematic cross-sectional view" means viewing a cross-section of the object vertically cut from the side in the first direction DR1 (or x-axis direction) or the second direction DR2 (or y-axis direction). The third direction DR3 (or z-axis direction) can also be referred to as a "thickness direction".​

[0048] It will be understood that, in the specification, when an element (or components, regions, layers or sections etc.) is referred to as being "formed on", "on", "disposed on", "connected to" or "joined to" another element (or components, regions, layers or sections etc.), it can be directly formed, directly on, directly disposed on, directly connected to or directly joined to the other element (or components, regions, layers or sections etc.), or intervening elements (or components, regions, layers or sections etc.) can be present. It will be understood that the term "connected" or "joined" can include physical or electrical connection or bonding.

[0049] When the terms "comprise", "include", "have" and / or their conjugates are used in the specification, it is to be understood that the stated features, integers, steps, operations, elements, components and / or groups thereof can be included or present but not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0050] The phrase "at least one of A and B" can be construed to mean only A, only B, or any combination of A and B. Further, "at least one of A, B, and C" and "at least one of a group consisting of A, B, and C" can be construed to mean only A, only B, only C, or any combination of A, B, and C.

[0051] For the purpose of this disclosure, the term "and / or" is intended to cover any and all combinations of the terms; e.g., "A and / or B" can be construed to mean "A, B, or A and B". The terms "and" and "or" can be used in either a conjunctive or disjunctive sense and can be understood to mean "and / or", unless otherwise stated.

[0052] Although the terms "first", "second", etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the teachings disclosed.

[0053] Spatially relative terms, such as "under", "below", "lower", "above", "upper", "on", "over", "higher", and "side" (e.g., as in "side wall") can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. Moreover, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0054] Various embodiments will be described hereinafter with reference to the accompanying drawings. It will be appreciated that variations from the shapes and configurations of the illustrations as a result, for example, of manufacturing process, can occur. It should also be understood that the embodiments disclosed herein are not limited to the shapes and configurations of the drawings as shown, but can include deviations in shape that result from, for example, manufacturing processes. As such, the shapes of the regions illustrated in the figures can not reflect actual shapes of the regions of the devices, and are not intended to limit the embodiments disclosed herein.

[0055] Unless otherwise defined or implied herein, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] Figure 1 is a schematic block diagram illustrating an embodiment of a display device DD.

[0057] Referring to Figure 1 The display device DD can include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0058] The display panel DP can include sub-pixels SP. The sub-pixels SP can be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm (where m is an integer greater than 1). The sub-pixels SP can be connected to the data driver 130 through first to n-th data lines DL1 to DLn (where n is an integer greater than 1).

[0059] Each of the sub-pixels SP can include at least one light emitting element that generates light. For example, each of the sub-pixels SP can generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels among the sub-pixels SP can form a pixel PXL (see Figure 4 ).

[0060] The gate driver 120 can be connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 can output a gate signal to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS can include a start signal indicating the start of each frame and a horizontal synchronization signal for outputting a gate signal synchronized with the timing at which a data signal is applied, etc.

[0061] In an embodiment, the first to m-th emission control lines EL1 to ELm can be provided and connected to the sub-pixels SP arranged in a row direction. The gate driver 120 can include an emission control driver that controls the first to m-th emission control lines EL1 to ELm. The emission control driver can operate under the control of the controller 150.

[0062] The gate driver 120 can be disposed at one side of the display panel DP. However, embodiments are not limited thereto. For example, the gate driver 120 can be divided into two or more drivers that are physically and / or logically distinguished from each other. The drivers can be disposed at a first side of the display panel DP and a second side of the display panel DP opposite the first side. As such, the gate driver 120 can be disposed around the display panel DP in various forms according to embodiments.

[0063] The data driver 130 can be connected to the sub-pixels SP arranged in a column direction through the first to n-th data lines DL1 to DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In an embodiment, the data control signal DCS can include a source start pulse, a source shift clock, and a source output enable signal, etc.

[0064] The data driver 130 can apply data signals having gray voltage corresponding to the image data DATA to the first to nth data lines DL1 to DLn using the voltage from the voltage generator 140. In a case where the gate signal is applied to each of the first to mth gate lines GL1 to GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Accordingly, the associated sub-pixel SP can generate light corresponding to the data signal, and an image can be displayed on the display panel DP.

[0065] In an embodiment, the gate driver 120 and the data driver 130 can include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0066] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 can generate a plurality of voltages and provide the generated voltages to components of the display apparatus DD. For example, the voltage generator 140 can receive an input voltage from an external apparatus outside the display apparatus DD, adjust the received voltage, and regulate the adjusted voltage to generate a plurality of voltages.

[0067] The voltage generator 140 can generate a first power voltage VDD and a second power voltage VSS. The generated first power voltage VDD and second power voltage VSS can be supplied to the sub-pixel SP. The first power voltage VDD can have a relatively high voltage level. The second power voltage VSS can have a voltage level lower than the first power voltage VDD. In other embodiments, the first power voltage VDD or the second power voltage VSS can be provided by an external apparatus outside the display apparatus DD.

[0068] The voltage generator 140 can generate various voltages. For example, the voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation to detect electrical characteristics of a transistor and / or a light emitting element of the sub-pixel SP, a reference voltage VREF can be applied to each of the first to nth data lines DL1 to DLn. The voltage generator 140 can generate the reference voltage VREF.

[0069] The controller 150 can control overall operations of the display apparatus DD. The controller 150 can receive input image data IMG and a control signal CTRL from an external apparatus to control an operation of displaying the input image data IMG. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0070] The controller 150 can convert the input image data IMG to be suitable for the display device DD or the display panel DP before outputting the image data DATA. In an embodiment, the controller 150 can align the input image data IMG to be suitable for the row-based sub-pixel SP before outputting the image data DATA.

[0071] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 can be mounted on a single integrated circuit. As Figure 1 indicated in FIG. 1, the data driver 130, the voltage generator 140, and the controller 150 can be included in a driver integrated circuit DIC. The data driver 130, the voltage generator 140, and the controller 150 can be components that are functionally separated from each other in the single driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 can be provided as a component that is separate from the driver integrated circuit DIC.

[0072] The controller 150 can control various operations of the display device DD. For example, the controller 150 can control components such as the data driver 130 and / or the voltage generator 140 to regulate the data signal as well as the first power voltage VDD and the second power voltage VSS.

[0073] Figure 2 is a schematic block diagram illustrating an embodiment of a sub-pixel SP in Figure 1 . In Figure 2 , a sub-pixel SPij is illustrated, which is disposed in an i-th row (where i is an integer between 1 and m, inclusive) and a j-th column (where j is an integer between 1 and n, inclusive) among the sub-pixels SP of Figure 1 .

[0074] Referring to Figure 2 , the sub-pixel SPij can include a sub-pixel circuit SPC and a light emitting element LD.

[0075] The light emitting element LD can be connected between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN can transmit the first power voltage VDD of Figure 1 . The second power voltage node VSSN can transmit the second power voltage VSS of Figure 1 .

[0076] The anode electrode AE of the light emitting element LD can be connected to the first power voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light emitting element LD can be connected to the second power voltage node VSSN. For example, the anode electrode AE of the light emitting element LD can be connected to the first power voltage node VDDN through at least one transistor included in the sub-pixel circuit SPC. Accordingly, a current can flow from the first power voltage node VDDN to the second power voltage node VSSN. The light emitting element LD can emit light corresponding to an amount of the current.

[0077] The sub-pixel circuit SPC can be connected to Figure 1 an i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm of the display panel 100, Figure 1 an i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm of the display panel 100, and Figure 1 a j-th data line DLj among the first data line DL1 to the n-th data line DLn of the display panel 100. The sub-pixel circuit SPC can control the light emitting element LD in response to a signal received through the signal line.

[0078] The sub-pixel circuit SPC can operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi can include one or more sub-gate lines. In an embodiment, as shown in FIG. 2A, the i-th gate line GLi can include a first sub-gate line SGL1 to a third sub-gate line SGL3. The sub-pixel circuit SPC can operate in response to a gate signal received through the first sub-gate line SGL1 to the third sub-gate line SGL3. As such, in a case where the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to a gate signal received through a corresponding sub-gate line. Figure 2 The sub-pixel circuit SPC can operate in response to an emission control signal received through the i-th emission control line ELi. The i-th emission control line ELi can include one or more sub-emission control lines. In an embodiment, as shown in FIG. 2B, the i-th emission control line ELi can include a first sub-emission control line SEL1 and a second sub-emission control line SEL2. As such, in a case where the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to an emission control signal received through a corresponding sub-emission control line.

[0079] Figure 2 The sub-pixel circuit SPC can operate in response to an emission control signal received through the i-th emission control line ELi. The i-th emission control line ELi can include one or more sub-emission control lines. In an embodiment, as shown in FIG. 2B, the i-th emission control line ELi can include a first sub-emission control line SEL1 and a second sub-emission control line SEL2. As such, in a case where the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to an emission control signal received through a corresponding sub-emission control line.

[0080] ​The sub-pixel circuit SPC can receive a data signal through the jth data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one gate signal received through the first to third sub-gate lines SGL1 to SGL3. The sub-pixel circuit SPC can adjust a current flowing from the first power voltage node VDDN to the second power voltage node VSSN through the light emitting element LD based on the stored voltage in response to an emission control signal received through the ith emission control line ELi. Accordingly, the light emitting element LD can generate light having a luminance corresponding to the data signal.

[0081] Figure 3 is a schematic circuit diagram illustrating an embodiment of a sub-pixel SPij in Figure 2 .

[0082] Referring to Figure 3 , the sub-pixel circuit SPC of the sub-pixel SPij can be connected to the ith gate line GLi', the ith emission control line ELi', and the jth data line DLj.

[0083] The sub-pixel circuit SPC can include the first to sixth transistors T1 to T6 and the first and second capacitors C1 and C2.

[0084] The first transistor T1 can be connected between the first power voltage node VDDN and a first node N1. A gate electrode GE of the first transistor T1 can be connected to a second node N2. Accordingly, the first transistor T1 can be turned on according to a voltage level of the second node N2. The first transistor T1 can be referred to as a driving transistor.

[0085] The second transistor T2 can be connected between the jth data line DLj and the second node N2. A gate electrode of the second transistor T2 can be connected to the first sub-gate line SGL1. Accordingly, the second transistor T2 can be turned on in response to a gate signal from the first sub-gate line SGL1. The second transistor T2 can be referred to as a switching transistor.

[0086] The third transistor T3 can be connected between the first node N1 and the second node N2. A gate electrode of the third transistor T3 can be connected to the second sub-gate line SGL2. Accordingly, the third transistor T3 can be turned on in response to a gate signal of the second sub-gate line SGL2.

[0087] The fourth transistor T4 can be connected between the first node N1 and an anode electrode AE of the light emitting element LD. A gate electrode of the fourth transistor T4 can be connected to the second emission control line SEL2. Accordingly, the fourth transistor T4 can be turned on in response to an emission control signal from the second emission control line SEL2.

[0088] The fifth transistor T5 can be connected between the anode electrode AE of the light emitting element LD and an initialization voltage node VINTN. The initialization voltage node VINTN can transmit an initialization voltage. In an embodiment, the initialization voltage can be provided by the voltage generator 140. In other embodiments, the initialization voltage can be provided by an external device of the display device 100. The gate electrode of the fifth transistor T5 can be connected to the third sub-gate line SGL3. Accordingly, the fifth transistor T5 can be turned on in response to a gate signal from the third sub-gate line SGL3. Figure 1

[0089] The sixth transistor T6 can be connected between the first power voltage node VDDN and the first transistor T1. The gate electrode of the sixth transistor T6 can be connected to the first sub-emission control line SEL1. Accordingly, the sixth transistor T6 can be turned on in response to an emission control signal of the first sub-emission control line SEL1.

[0090] The first capacitor C1 can be connected between the second transistor T2 and the second node N2. The second capacitor C2 can be connected between the first power voltage node VDDN and the second node N2.

[0091] Accordingly, the sub-pixel circuit SPC can include the first to sixth transistors T1 to T6 and the first and second capacitors C1 and C2. However, embodiments are not limited to this example. The sub-pixel circuit SPC can be implemented in various forms of circuits each including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC can include two transistors and one capacitor. According to embodiments of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi’ and the number of sub-emission control lines included in the i-th emission control line ELi’ can vary.

[0092] The first to sixth transistors T1 to T6 can be P-type transistors. Each of the first to sixth transistors T1 to T6 can be a thin film transistor (TFT). However, embodiments are not limited to the foregoing. For example, at least one of the first to sixth transistors T1 to T6 can be replaced with an N-type transistor. In an embodiment, the first to sixth transistors T1 to T6 can include amorphous silicon semiconductor, single crystal silicon semiconductor, polycrystalline silicon semiconductor, or oxide semiconductor, etc.

[0093] Each of the first to sixth transistors T1 to T6 can include a source electrode (or first electrode) SE, a drain electrode (or second electrode) DE, and a gate electrode GE.

[0094] ​The light emitting element LD can include an anode electrode AE, a cathode electrode CE, and an emission layer. The emission layer can be disposed between the anode electrode AE and the cathode electrode CE. In a case where emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled at a low level, the fourth transistor T4 and the sixth transistor T6 can be turned on after a voltage of the second node N2 reflects a data signal transmitted through the jth data line DLj. The first transistor T1 can be turned on in response to the voltage of the second node N2, so that a current can flow from the first power voltage node VDDN to the second power voltage node VSSN. The light emitting element LD can emit light corresponding to an amount of the current.

[0095] Figure 4 is a schematic plan view illustrating an embodiment of a display panel DP in Figure 1 .

[0096] Referring to Figure 4 , Figure 1 An embodiment of the display panel DP depicted in FIG. 1A can include a display area DDA and a non-display area NDA. The display panel DP can display an image through the display area DDA. The non-display area NDA can be disposed around or surround the display area DDA.

[0097] The display panel DP can include a substrate SUB, sub-pixels SP, and pads PD.

[0098] The sub-pixels SP can be disposed in the display area DDA on the substrate SUB. The sub-pixels SP can be arranged in a matrix pattern along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, embodiments are not limited to the example. For example, the sub-pixels SP can be arranged in a zigzag pattern on the first direction DR1 and the second direction DR2. For example, the sub-pixels SP can be arranged in a PENTILE ® pattern. In the PENTILE ® pattern, the sub-pixels SP can be approximately aligned along the first direction DR1 and the second direction DR2. The first direction DR1 can correspond to a row direction, and the second direction DR2 can correspond to a column direction.

[0099] Two or more sub-pixels among the sub-pixels SP can form a pixel PXL. For example, three sub-pixels SP can combine to form a pixel PXL.

[0100] Components for controlling the sub-pixels SP can be disposed in the non-display area NDA on the substrate SUB. For example, lines (such as data lines DL, emission control lines SEL, and scan lines ST) connected to the sub-pixels SP can be disposed in the non-display area NDA on the substrate SUB. Figure 1The first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn of the display panel DP can be disposed in the non-display area NDA.

[0101] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 in the display panel DP can be integrated into the non-display area NDA. In an embodiment, the gate driver 120 can be mounted on the display panel DP and positioned in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP.

[0102] The pad PD can be disposed in the non-display area NDA on the substrate SUB. The pad PD can be electrically connected to the sub-pixels SP by the lines. For example, the pad PD can be connected to the sub-pixels SP by the first to n-th data lines DL1 to DLn.

[0103] The pad PD can interface the display panel DP with other components of the display device DD (see Figure 1 ). In an embodiment, the pad PD can provide voltages and signals required for operating components included in the display panel DP from the driver integrated circuit DIC in the display device DD. Figure 1 For example, the first to n-th data lines DL1 to DLn can be connected to the driver integrated circuit DIC through the pad PD. For example, the first and second power voltages VDD and VSS can be supplied from the driver integrated circuit DIC through the pad PD. For example, in the case where the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0104] In an embodiment, a circuit board can be electrically connected to the pad PD using a conductive adhesive component such as an anisotropic conductive film. The circuit board can be a flexible film or a flexible printed circuit board (FPCB) made of a flexible material. The driver integrated circuit DIC can be mounted on the circuit board and electrically connected to the pad PD.

[0105] In an embodiment, the display area DDA can have various shapes. The display area DDA can have a closed-loop shape with linear sides and / or curved sides. For example, the display area DDA can have a shape such as a polygon, a circle, a semi-circle, or an ellipse.

[0106] In an embodiment, the display panel DP can have a planar display surface. In an embodiment, the display panel DP can have an at least partially circular (rounded) display surface. In an embodiment, the display panel DP can be bendable, foldable, or rollable. The display panel DP and / or the substrate SUB can include a material having a flexible property.

[0107] Figure 5 is a schematic cross-sectional view illustrating an embodiment of a display panel DP in Figure 1 .

[0108] Referring to Figure 5 , the display panel DP can include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a thin film encapsulation layer TFE, a color filter layer CFL, and a coating layer OC.

[0109] The substrate SUB can include a semiconductor substrate. For example, the substrate SUB can include a bulk wafer or an epitaxial wafer. The epitaxial wafer can include a layer of crystalline material (i.e., an epitaxial layer) grown on a bulk substrate by an epitaxial process. The substrate SUB is not limited to a bulk wafer or an epitaxial wafer, but can be formed using various types of wafers such as a polished wafer, an annealed wafer, and a silicon-on-insulator (SOI) wafer.

[0110] The pixel circuit layer PCL can be disposed on the substrate SUB and can include circuit elements of a sub-pixel circuit SPC (see Figure 2 ) and at least one insulating layer between the circuit elements. The circuit elements can include at least one transistor and a signal line connected to the at least one transistor.

[0111] The light emitting element layer LDL can include a light emitting element LD (see Figure 2 ) and a pixel definition layer PDL (see Figure 6 ). The light emitting element LD can be disposed in each of the sub-pixels SP. The light emitting element LD can include an anode electrode AE (see Figure 2 ) connected to the at least one transistor, an emission layer, and a cathode electrode CE (see Figure 2 ).

[0112] The thin film encapsulation layer TFE can be disposed on the light emitting element layer LDL. The thin film encapsulation layer TFE can cover the light emitting element layer LDL to prevent oxygen and / or water, etc. from permeating into the light emitting element LD.

[0113] The color filter layer CFL can be disposed on the thin film encapsulation layer TFE. The color filter layer CFL can selectively transmit light emitted from the light emitting element LD in an image display direction (or a front direction) of the display device DD, but is not limited thereto.

[0114] The coating layer OC can be disposed on the color filter layer CFL. The coating layer OC can cover the underlying components including the color filter layer CFL. The coating layer OC can protect the underlying components from foreign substances such as dust.

[0115] Figure 6 is a schematic cross-sectional view taken along the line I-I' in Figure 4 .

[0116] Figure 6 The first transistor T1 among the first to sixth transistors T1 to T6 shown in FIG. 1A will be described. Figure 3

[0117] Referring to FIG. 1A, Figure 6 According to an embodiment, the first transistor T1 can include an active pattern ACT and a gate electrode GE insulated from the active pattern ACT. The first transistor T1 can include a source electrode SE and a drain electrode DE connected to the active pattern ACT. The first transistor T1 can function as a driving thin film transistor.

[0118] Hereinafter, a structure in which components included in the first transistor T1 are stacked will be described.

[0119] A buffer layer BFL can be disposed on the substrate SUB. The buffer layer BFL can reduce or block penetration of foreign substances, moisture, or external air from a lower portion of the substrate SUB, and can provide a flat surface on the substrate SUB.

[0120] The buffer layer BFL can be an inorganic insulating layer including an inorganic material. The buffer layer BFL can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), and silicon oxynitride (SiO x N y ), or can include at least one metal oxide such as aluminum oxide (AlO x ). The buffer layer BFL can include silicon oxide (SiO x ). The buffer layer BFL can have a single layer structure or a multi-layer structure. In the case where the buffer layer BFL has a multi-layer structure, each layer can be formed of the same material or different materials.

[0121] The active pattern ACT can be disposed on the buffer layer BFL. The active pattern ACT can include a source region SA, a drain region DA, and a channel region CA disposed between the source region SA and the drain region DA. The source region SA and the drain region DA can be spaced apart from each other in a first direction DR1 or a second direction DR2 crossing the first direction DR1, with the channel region CA interposed therebetween. The source region SA and the drain region DA of the active pattern ACT can have electrical conductivity by adjusting a carrier concentration in an oxide semiconductor.

[0122] ​The source region SA of the active pattern ACT can be connected to the source electrode SE through a first via hole VIA1. The first via hole VIA1 can pass through the gate insulating layer GISL and the first and second insulating layers ISL1 and ISL2 to expose the source region SA of the active pattern ACT. The drain region DA of the active pattern ACT can be connected to the drain electrode DE through a second via hole VIA2. The second via hole VIA2 can pass through the gate insulating layer GISL and the first and second insulating layers ISL1 and ISL2 to expose the drain region DA of the active pattern ACT.

[0123] The gate insulating layer GISL can be disposed on the active pattern ACT to cover the active pattern ACT. The gate insulating layer GISL can have a single-layer structure or a multi-layer structure including an inorganic insulating material. For example, the inorganic insulating material can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc. Although Figure 6 Although it is shown that the gate insulating layer GISL is formed on the entire surface of the buffer layer BFL and the active pattern ACT, the configuration is not limited thereto. For example, the gate insulating layer GISL can be formed to have the same width as the gate electrode GE through an etching process.

[0124] The gate electrode GE can be disposed on the gate insulating layer GISL and can be overlapped with the active pattern ACT. The gate electrode GE can be insulated from the active pattern ACT by the gate insulating layer GISL. The gate electrode GE can have a single-layer structure or a multi-layer structure including copper (Cu) or a copper alloy, but is not limited thereto. For example, the gate electrode GE can include indium zinc oxide (InZnO), silver (Ag), zinc (Zn), magnesium (Mg), aluminum (Al), or titanium (Ti), etc.

[0125] The gate electrode GE can have a width in the first direction DR1 that is smaller than the total width of the active pattern ACT and equal to the width of the channel region CA of the active pattern ACT. Although Figure 6 Although it is shown that the width of the gate electrode GE is substantially the same as the width of the channel region CA of the active pattern ACT, the configuration is not limited thereto. For example, the gate electrode GE can have a width in the first direction DR1 that is greater than the width of the channel region CA of the active pattern ACT.

[0126] The first insulating layer ISL1 can be disposed on the gate electrode GE. The first insulating layer ISL1 can cover the gate electrode GE. The first insulating layer ISL1 can have a single layer structure or a multi-layer structure including an inorganic insulating material. For example, the inorganic insulating material can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), or the like.

[0127] One or more insulating layers can be further disposed on the first insulating layer ISL1. Although Figure 6 the second insulating layer ISL2 is shown to be disposed on the first insulating layer ISL1, the configuration is not limited thereto. The second insulating layer ISL2 can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), or the like.

[0128] A conductive pattern can be disposed between the first insulating layer ISL1 and the second insulating layer ISL2. The conductive pattern can include an electrode at both ends of the first capacitor C1 and the second capacitor C2 as shown in Figure 3 . For example, the conductive pattern can further include a source electrode and a drain electrode of at least one of the second transistor T2 to the sixth transistor T6 as shown in Figure 3 . Although the conductive pattern can include at least one of copper and a copper alloy, embodiments are not limited thereto. For example, the conductive pattern can include at least one of indium zinc oxide (InZnO), silver (Ag), zinc (Zn), magnesium (Mg), aluminum (Al), titanium (Ti), or the like. An active pattern (or a semiconductor layer) of at least one of the second transistor T2 to the sixth transistor T6 can be further disposed between the first insulating layer ISL1 and the one or more insulating layers.

[0129] A source electrode SE and a drain electrode DE connected to the active pattern ACT can be disposed on the second insulating layer ISL2. A conductive layer CTL can be disposed on the second insulating layer ISL2. For example, the source electrode SE, the drain electrode DE, and the conductive layer CTL can be disposed in the same layer. The conductive layer CTL can function as an electrode of one of the transistors Figure 3 and an anode electrode AE of the light emitting element LD.

[0130] The source electrode SE, the drain electrode DE, and the conductive layer CTL can include a conductive material such as a metal or a conductive oxide. For example, each of the source electrode SE, the drain electrode DE, and the conductive layer CTL can have a single-layer structure or a multi-layer structure including a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0131] A first transistor T1 including the active pattern ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE can be formed. In Figure 6 , the first transistor T1 is illustrated as a coplanar thin film transistor having a top gate structure, but is not limited thereto. For example, the first transistor T1 can have a bottom gate structure. Although Figure 6 , the second transistor T2 to the sixth transistor T6 are not illustrated, at least some of the second transistor T2 to the sixth transistor T6 can have a similar structure to the first transistor T1. Figure 3

[0132] In an embodiment, a bottom conductive layer BML can be disposed between the substrate SUB and the buffer layer BFL. The bottom conductive layer BML can be superposed with the first transistor T1. For example, the bottom conductive layer BML can be disposed adjacent to the substrate SUB and under the first transistor T1. The bottom conductive layer BML can be superposed with the active pattern ACT of the first transistor T1. A constant voltage or a signal can be applied to the bottom conductive layer BML.

[0133] The bottom conductive layer BML can include a metal or a conductive material. For example, the bottom conductive layer BML can have a single-layer structure or a multi-layer structure including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), etc. The bottom conductive layer BML can include a transparent conductive material. For example, the bottom conductive layer BML can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO), etc.

[0134] A passivation layer PSV can be disposed on the source electrode SE, the drain electrode DE, and the conductive layer CTL of the first transistor T1. The passivation layer PSV can have a single-layer structure or a multi-layer structure including an inorganic insulating material. For example, the passivation layer PSV can have a single-layer structure including silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ), or a multi-layer structure in which silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y ​a multi-layer structure in which two or more of the first to third layers are alternately stacked.

[0135] The pixel definition layer PDL and the first light emitting element LD1 including the first anode electrode AE1, the first emission layer EML1, and the cathode electrode CE can be disposed on the passivation layer PSV.

[0136] The first anode electrode AE1 can be formed on the pixel circuit layer PCL of the first sub-pixel SP1. For example, the first anode electrode AE1 can be formed on the insulating layer having a flat surface of the pixel circuit layer PCL by a photolithography process using a mask. The first anode electrode AE1 can be disposed on the passivation layer PSV to be laminated with the conductive layer CTL and can be electrically connected to the conductive layer CTL through the third via hole VIA3 in the passivation layer PSV. For example, the first anode electrode AE1 can be electrically connected to the drain electrode of the fourth transistor T4 and the drain electrode of the fifth transistor T5 as described with reference to FIG. 1. Figure 3

[0137] The first anode electrode AE1 can include a conductive material having reflectivity so that light emitted from the first emission layer EML1 can be reflected and guided toward an image display direction. For example, the conductive material can include a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or an alloy thereof.

[0138] The pixel definition layer PDL can be an organic insulating layer including an organic material. For example, the organic material can include an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin, etc. In an embodiment, the pixel definition layer PDL can include a light absorbing material or be coated with a light absorbing agent so that the pixel definition layer PDL can absorb light introduced from the outside. For example, the pixel definition layer PDL can include a carbon-based black pigment, but is not limited thereto.

[0139] The first emission layer EML1 can be disposed on the first anode electrode AE1 exposed from the pixel definition layer PDL. The cathode electrode CE can be disposed on the first emission layer EML1. The cathode electrode CE can be a thin film metal layer having a thickness that allows light emitted from the first emission layer EML1 to pass therethrough. For example, the cathode electrode CE can include a metal material or a transparent conductive material and have a relatively small thickness.

[0140] The thin film encapsulation layer TFE can be formed over the entire surface of the cathode electrode CE. The thin film encapsulation layer TFE can prevent foreign substances, moisture, or external air from penetrating into the first emission layer EML1 or the cathode electrode CE.

[0141] Figures 7 to 14 ​is a schematic plan view showing an embodiment of a thin film transistor TFT. For convenience of explanation, the thin film transistor TFT is considered as a first transistor T1 of Figure 3 . However, the embodiments are not limited to the example. For example, the thin film transistor TFT can be any one of a second transistor T2 to a sixth transistor T6 of Figure 3 .

[0142] Referring to Figures 7 to 14 , the thin film transistor TFT in the embodiments can include a gate electrode GE, an active pattern (or a semiconductor layer) ACT, a source electrode SE, and a drain electrode DE disposed on a substrate SUB.

[0143] The substrate SUB can include an insulating material such as glass, an organic polymer, or a crystal. The substrate SUB can be made of a material having flexibility to allow the substrate SUB to be bendable or foldable, and can have a single-layer structure or a multi-layer structure. For example, the substrate SUB can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material of the substrate SUB is not limited to the example, and can vary in other embodiments.

[0144] The active pattern ACT can be disposed on the substrate SUB. The active pattern ACT can include a source region SA, a drain region DA, and a channel region CA disposed between the source region SA and the drain region DA. The active pattern ACT can be a semiconductor pattern including polycrystalline silicon, amorphous silicon, an oxide semiconductor, or the like. For example, the channel region CA can be an undoped semiconductor pattern, and thus an intrinsic semiconductor. Each of the source region SA and the drain region DA can be a semiconductor pattern doped with an impurity.

[0145] The channel region CA of the active pattern ACT can be overlapped with the gate electrode GE. The gate electrode GE can be formed of a conductive material (e.g., a metallic material). In the embodiments, the gate electrode GE can serve as a doping prevention layer that prevents the active pattern ACT from being doped with an impurity. Thus, the gate electrode GE can define the channel region CA of the active pattern ACT.

[0146] The source region SA of the active pattern ACT can be overlapped with a source electrode (or a first electrode) SE. The source electrode SE can be disposed on the active pattern ACT, and can cover at least a portion of the active pattern ACT. The source electrode SE can be connected to the source region (hereinafter, also referred to as a first region) SA through a first via VIA1 that passes through a gate insulating layer GISL (see Figure 6 ) and insulating layers ISL1 and ISL2 (see Figure 6 ).

[0147] The drain region DA of the active pattern ACT can be superposed with a drain electrode (or a second electrode) DE. The drain electrode DE can be disposed on the active pattern ACT and can cover at least a portion of the active pattern ACT. The drain electrode DE can be spaced apart from the source electrode SE by a distance in the first direction DR1. The drain electrode DE can be connected to the drain region (hereinafter, also referred to as a second region) DA through a second via hole VIA2 passing through the gate insulating layer GISL and the insulating layers ISL1 and ISL2.

[0148] Referring to Figure 7 The channel region CA of the active pattern ACT can have a first channel length L1T in the first direction DR1 and can have a first channel width W1T in a second direction DR2 crossing the first direction DR1. The gate electrode GE superposed with the channel region CA of the active pattern ACT can have the same first channel length L1T as the channel region CA in the first direction DR1. The gate electrode GE can have a width W1G greater than the first channel width W1T of the channel region CA in the second direction DR2. For example, the shape of the gate electrode GE can be determined based on the first channel length L1T of the channel region CA.

[0149] The channel region CA can include a first boundary BDR11 and a second boundary BDR12 superposed with side surfaces GS11 and GS12 of the gate electrode GE spaced apart from each other in the first direction DR1. The channel region CA can include a first side surface S11 and a second side surface S12 spaced apart from each other in the second direction DR2. The channel region CA can be surrounded by the first boundary BDR11 and the second boundary BDR12 and the first side surface S11 and the second side surface S12.

[0150] Referring to Figure 7 The active pattern ACT can have an even number of curved portions in the channel region CA. In an embodiment, the active pattern ACT can have curved portions CP11 and CP12 respectively concave from the first side surface S11 and the second side surface S12 of the channel region CA in the second direction DR2 and in a direction opposite to the second direction DR2. In the channel region CA, the curved portions CP11 and CP12 can be arranged in a zigzag pattern along the first direction DR1. The curved portions CP11 and CP12 can have the same width W1C.

[0151] For example, the active pattern ACT can include a first curved portion CP11 recessed from the first side surface S11 in the second direction DR2 and a second curved portion CP12 recessed from the second side surface S12 in a direction opposite to the second direction DR2. The first curved portion CP11 and the second curved portion CP12 can be spaced apart from each other by a first length L11 in the first direction DR1. The first curved portion CP11 can be spaced apart from the first boundary BDR11 by a second length L12 in the first direction DR1. The second curved portion CP12 can be spaced apart from the second boundary BDR12 by the second length L12 in a direction opposite to the first direction DR1. The second length L12 can be equal to or greater than the first length L11 between the first curved portion CP11 and the second curved portion CP12. For example, in a case where a size of the gate electrode GE is increased within a design margin, the second length L12 can be greater than the first length L11.

[0152] The first curved portion CP11 and the second curved portion CP12 can have a length L1C in the second direction DR2 that is less than a first channel width W1T of the channel region CA. The first curved portion CP11 can be spaced apart from the second side surface S12 by a third length L13 in a direction opposite to the second direction DR2. The second curved portion CP12 can be spaced apart from the first side surface S11 by the third length L13 in the second direction DR2. The third length L13 can be equal to the first length L11 between the first curved portion CP11 and the second curved portion CP12.

[0153] A sum of the third length L13 and the length L1C of the first curved portion CP11 can be equal to a length W1T of each of the first boundary BDR11 and the second boundary BDR12 in the second direction DR2 (corresponding to the first channel width W1T described earlier). A sum of the third length L13 and the length of the second curved portion CP12 can also be equal to the length W1T of each of the first boundary BDR11 and the second boundary BDR12 in the second direction DR2.

[0154] Referring to Figure 8 The channel region CA of the active pattern ACT can have a first channel length L2T in the first direction DR1 and can have a first channel width W2T in a second direction DR2 that crosses the first direction DR1. The gate electrode GE superposed with the channel region CA of the active pattern ACT can have the same first channel length L2T as the channel region CA in the first direction DR1. For example, a shape of the gate electrode GE can be determined based on the first channel length L2T of the channel region CA. Figure 8 The first channel length L2T in the first direction DR1 can be greater than Figure 7 The first channel length L1T in the first direction DR1. Figure 8 The first channel width W2T in the second direction DR2 can be equal toFigure 7 a first channel width W1T in the first direction DR1.

[0155] The channel region CA can include a first boundary BDR21 and a second boundary BDR22 superposed with side surfaces GS21 and GS22 of the gate electrode GE spaced apart from each other in the first direction DR1. The channel region CA can include a first side surface S21 and a second side surface S22 spaced apart from each other in the second direction DR2. For example, the channel region CA can be surrounded by the first boundary BDR21 and the second boundary BDR22 and the first side surface S21 and the second side surface S22.

[0156] Referring to Figure 8 The active pattern ACT can have an odd number of curved portions in the channel region CA. In an embodiment, the active pattern ACT can have curved portions CP21 to CP23 respectively recessed from the first side surface S21 and the second side surface S22 of the channel region CA in the second direction DR2 and in a direction opposite to the second direction DR2. In the channel region CA, the curved portions CP21 to CP23 can be arranged in a zigzag pattern along the first direction DR1. The curved portions CP21 and CP22 can have the same width W2C.

[0157] For example, the active pattern ACT can include a first curved portion CP21 and a third curved portion CP23 recessed from the first side surface S21 in the second direction DR2 and a second curved portion CP22 recessed from the second side surface S22 in a direction opposite to the second direction DR2. The third curved portion CP23 can be disposed parallel to the first curved portion CP21, with the second curved portion CP22 disposed between the third curved portion CP23 and the first curved portion CP21.

[0158] The first curved portion CP21 to the third curved portion CP23 can be spaced apart from each other by a first length L21 in the first direction DR1. The first curved portion CP21 and the second curved portion CP22 can be spaced apart from each other by the first length L21 in the first direction DR1. The second curved portion CP22 and the third curved portion CP23 can also be spaced apart from each other by the first length L21 in the first direction DR1. The first curved portion CP21 can be spaced apart from the first boundary BDR21 by a second length L22 in the first direction DR1. The third curved portion CP23 can be spaced apart from the second boundary BDR22 by the second length L22 in a direction opposite to the first direction DR1. The second length L22 can be equal to or greater than the first length L21 between the first curved portion CP21 to the third curved portion CP23. For example, in a case where the size of the gate electrode GE is increased within a design margin, the second length L22 can be greater than the first length L21.

[0159] The first curved portion CP21 to the third curved portion CP23 can have a length L2C in the second direction DR2 that is less than the first channel width W2T of the channel region CA. Each of the first curved portion CP21 and the third curved portion CP23 can be spaced apart from the second side surface S22 by a third length L23 in a direction opposite to the second direction DR2. The second curved portion CP22 can be spaced apart from the first side surface S21 by the third length L23 in the second direction DR2. The third length L23 can be equal to the first length L21 between the first curved portion CP21 to the third curved portion CP23.

[0160] Further, a sum of the third length L23 and the length L2C of the first curved portion CP21 can be equal to the length W2T in the second direction DR2 of each of the first boundary BDR21 and the second boundary BDR22 (corresponding to the first channel width W2T described earlier). A sum of the third length L23 and the length of the second curved portion CP22 can be equal to the length W2T in the second direction DR2 of each of the first boundary BDR21 and the second boundary BDR22. A sum of the third length L23 and the length of the third curved portion CP23 can be equal to the length W2T in the second direction DR2 of each of the first boundary BDR21 and the second boundary BDR22.

[0161] In this way, since the channel region CA of the active pattern ACT has a planar structure with curved portions, the current can be induced to flow in a curved shape, thereby increasing the effective channel length of the thin film transistor TFT. Accordingly, the subthreshold swing value representing a change in current below the threshold voltage of the thin film transistor TFT can be reduced, and the mobility value can be increased. However, in a case where an excessive number of curved portions are formed in the channel region CA, the effective channel length can be excessively increased, thus resulting in an increase in power consumption. In consideration of the foregoing, the channel region CA of the active pattern ACT can be designed to have a second length L12 or L22 that is greater than the first length L11 or L21. For example, the channel region CA can not have a curved portion adjacent to the first boundary BDR11 and the second boundary BDR12. Such a design can prevent the effective channel length from being excessively increased, thereby avoiding an excessive or unnecessary increase in power consumption.

[0162] Reference Figure 9FIG. 3B shows an embodiment in which the active pattern ACT can have an even number of curved portions in the channel region CA. In embodiments, the channel region CA of the active pattern ACT can include a first boundary BDR31 and a second boundary BDR32, each of which has a first width W31 in the second direction DR2. The channel region CA of the active pattern ACT can have a length (i.e., a first channel length) L3T in the first direction DR1 and can have a width (i.e., a first channel width) W3T in the second direction DR2.

[0163] The channel region CA can include the first boundary BDR31 and the second boundary BDR32 that overlap the side surfaces GS31 and GS32 of the gate electrode GE that are spaced apart from each other in the first direction DR1. The first boundary BDR31 and the second boundary BDR32 of the channel region CA can have a first width W31. The first width W31 of the first boundary BDR31 and the second boundary BDR32 can be less than the width W3T defined between the first side surface S31 and the second side surface S32 of the channel region CA. Either of the first boundary BDR31 and the second boundary BDR32 can overlap a second imaginary line IL32 that is aligned with (e.g., parallel to) the first direction DR1.

[0164] The active pattern ACT can have curved portions CP31 and CP32 that are recessed from the first side surface S31 and the second side surface S32 of the channel region CA in the second direction DR2 and in a direction opposite to the second direction DR2, respectively. In the channel region CA, the curved portions CP31 and CP32 can be arranged in a zigzag pattern along the first direction DR1.

[0165] For example, the active pattern ACT can include a first curved portion CP31 that is recessed from the first side surface S31 in the second direction DR2 and a second curved portion CP32 that is recessed from the second side surface S32 in a direction opposite to the second direction DR2. The first curved portion CP31 and the second curved portion CP32 can be spaced apart from each other by a first length L31 in the first direction DR1. The first curved portion CP31 can be spaced apart from a first portion PRT31 including the first boundary BDR31 by the first length L31 in the first direction DR1. The second curved portion CP32 can be spaced apart from a second portion PRT32 including the second boundary BDR32 by the first length L31 in a direction opposite to the first direction DR1.

[0166] The first curved portion CP31 can be spaced apart from the second side surface S32 by a third length L33 in a direction opposite to the second direction DR2. The second curved portion CP32 can be spaced apart from the first side surface S31 by the third length L33 in the second direction DR2. The third length L33 can be equal to the first length L31 between the first curved portion CP31 and the second curved portion CP32. Further, the third length L33 can be equal to the first width W31 of each of the first boundary BDR31 and the second boundary BDR32.

[0167] In an embodiment, the channel region CA can include a first portion PRT31 adjacent to the first region SA, a second portion PRT32 adjacent to the second region DA, and a third portion PRT33 between the first portion PRT31 and the second portion PRT32.

[0168] The first portion PRT31 can be spaced apart from the first curved portion CP31 by the first length L31 in a direction opposite to the first direction DR1. The first portion PRT31 can refer to a region defined between the first boundary BDR31 and the third portion PRT33. The second portion PRT32 can be spaced apart from the second curved portion CP32 by the first length L31 in the first direction DR1. The second portion PRT32 can refer to a region defined between the second boundary BDR32 and the third portion PRT33. Either of the first portion PRT31 and the second portion PRT32 can be superposed with a second imaginary line IL32 aligned with the first direction DR1.

[0169] Further, the first portion PRT31 and the second portion PRT32 can be spaced apart from a first imaginary line IL31 aligned with the second direction DR2 by the same fourth length L34. The first portion PRT31 can be spaced apart from the first imaginary line IL31 by the fourth length L34 in a direction opposite to the first direction DR1. The second portion PRT32 can be spaced apart from the first imaginary line IL31 by the fourth length L34 in the first direction DR1. The first imaginary line IL31 can be a single line disposed between the first curved portion CP31 and the second curved portion CP32 and spaced apart from each of the first curved portion CP31 and the second curved portion CP32 by an equal distance.

[0170] The third portion PRT33 can partially surround the first curved portion CP31 and the second curved portion CP32, and can have a constant width L33 (corresponding to the third length L33 described earlier). The width L33 of the third portion PRT33 can be equal to the first width W31 of the first portion PRT31 and the second portion PRT32. The width L33 of the third portion PRT33 can be equal to the first length L31 by which the first curved portion CP31 and the first portion PRT31 are spaced apart from each other in the first direction DR1. The width L33 of the third portion PRT33 can also be equal to the first length L31 by which the second curved portion CP32 and the second portion PRT32 are spaced apart from each other in the first direction DR1.

[0171] Referring to Figure 10 embodiments, the channel region CA of the active pattern ACT can include a first boundary BDR41 and a second boundary BDR42, each of which has a first width W41 in the second direction DR2. The channel region CA of the active pattern ACT can have a length (i.e., a first channel length) L4T in the first direction DR1 and can have a width (i.e., a first channel width) W4T in the second direction DR2.

[0172] The channel region CA can include the first boundary BDR41 and the second boundary BDR42 superposed with side surfaces GS41 and GS42 of the gate electrode GE spaced apart from each other in the first direction DR1. The first boundary BDR41 and the second boundary BDR42 of the channel region CA can have a first width W41. The first width W41 of the first boundary BDR41 and the second boundary BDR42 can be smaller than a width W4T defined between the first side surface S41 and the second side surface S42 of the channel region CA. The first boundary BDR41 and the second boundary BDR42 can be superposed with a second imaginary line IL42 aligned with the first direction DR1.

[0173] The active pattern ACT can have curved portions CP41 to CP43 respectively recessed from the first side surface S41 and the second side surface S42 of the channel region CA in the second direction DR2 and in a direction opposite to the second direction DR2. In the channel region CA, the curved portions CP41 to CP43 can be arranged in a zigzag pattern along the first direction DR1.

[0174] For example, the active pattern ACT can include a first curved portion CP41 and a third curved portion CP43 recessed from the first side surface S41 in the second direction DR2 and a second curved portion CP42 recessed from the second side surface S42 in a direction opposite to the second direction DR2. The third curved portion CP43 can be disposed parallel to the first curved portion CP41, with the second curved portion CP42 disposed between the third curved portion CP43 and the first curved portion CP41.

[0175] The first curved portion CP41 to the third curved portion CP43 can be spaced apart from each other by a first length L41 in the first direction DR1. The first curved portion CP41 can be spaced apart from the first portion PRT41 including the first boundary BDR41 by the first length L41 in the first direction DR1. The second curved portion CP42 can be spaced apart from the first curved portion CP41 by the first length L41 in the first direction DR1. The third curved portion CP43 can be spaced apart from the second portion PRT42 including the second boundary BDR42 by the first length L41 in a direction opposite to the first direction DR1. The third curved portion CP43 can be spaced apart from the second curved portion CP42 by the first length L41 in the first direction DR1.

[0176] Each of the first curved portion CP41 and the third curved portion CP43 can be spaced apart from the second side surface S42 by a third length L43 in a direction opposite to the second direction DR2. The second curved portion CP42 can be spaced apart from the first side surface S41 by the third length L43 in the second direction DR2. The third length L43 can be equal to the first length L41 between the first curved portion CP41 to the third curved portion CP43. Further, the third length L43 can be equal to the first width W41 of each of the first boundary BDR41 and the second boundary BDR42.

[0177] In an embodiment, the channel area CA can include a first portion PRT41 adjacent to the first area SA, a second portion PRT42 adjacent to the second area DA, and a third portion PRT43 between the first portion PRT41 and the second portion PRT42.

[0178] The first portion PRT 41 can be spaced apart from the first curved portion CP 41 by a first length L41 in a direction opposite the first direction DR1. The first portion PRT 41 can refer to an area defined between a first boundary BDR41 and the third portion PRT 43. The second portion PRT 42 can be spaced apart from the third curved portion CP 43 by the first length L41 in the first direction DR1. The second portion PRT 42 can refer to an area defined between a second boundary BDR42 and the third portion PRT 43. The first portion PRT 41 and the second portion PRT 42 can be superimposed with a second imaginary line IL42 aligned with the first direction DR1.

[0179] Further, the first portion PRT 41 and the second portion PRT 42 can be spaced apart from a first imaginary line IL41 aligned with the second direction DR2 by a same fourth length L44. The first portion PRT 41 can be spaced apart from the first imaginary line IL41 by the fourth length L44 in a direction opposite the first direction DR1. The second portion PRT 42 can be spaced apart from the first imaginary line IL41 by the fourth length L44 in the first direction DR1. The first imaginary line IL41 can be a single line disposed between the first curved portion CP 41 and the third curved portion CP 43 and spaced apart from each of the first curved portion CP 41 and the third curved portion CP 43 by an equal distance. The first imaginary line IL41 can be superimposed with the second curved portion CP 42.

[0180] The third portion PRT 43 can partially surround the first curved portion CP 41 to the third curved portion CP 43 and can have a constant width L43 (corresponding to the third length L43 described earlier). The width L43 of the third portion PRT 43 can be equal to the first width W41 of each of the first portion PRT 41 and the second portion PRT 42. The width L43 of the third portion PRT 43 can be equal to the first length L41 by which the first curved portion CP 41 and the first portion PRT 41 are spaced apart from each other in the first direction DR1. The width L43 of the third portion PRT 43 can also be equal to the first length L41 by which the third curved portion CP 43 and the second portion PRT 42 are spaced apart from each other in the first direction DR1. The width L43 of the third portion PRT 43 can be equal to the first length L41 between the first curved portion CP 41 to the third curved portion CP 43.

[0181] In this way, the channel region CA of the active pattern ACT can use a planar structure having the first portion PRT41 and the second portion PRT42 without forming a curved portion adjacent to the first boundary BDR11 and the second boundary BDR12 in which the width of the channel region CA is reduced. Accordingly, the capacitance of the active pattern ACT can be reduced, thereby preventing excessive power consumption. For example, since the active pattern ACT has a planar structure in which the width of the channel region CA is reduced, the characteristics of the thin film transistor TFT can be further enhanced.

[0182] Referring to Figure 11 An embodiment is shown in which the active pattern ACT can have an even number of curved portions in the channel region CA. In the embodiment, the active pattern ACT can include a dummy portion DM51 protruding from the channel region CA in the second direction DR2.

[0183] The channel region CA can include a first portion PRT51 and a second portion PRT52 superposed with a second imaginary line IL52 aligned with the first direction DR1. The channel region CA of the active pattern ACT can include a third portion PRT53 between the first portion PRT51 and the second portion PRT52.

[0184] For example, the third portion PRT53 can include the dummy portion DM51 protruding from a region adjacent to the second portion PRT52 in the second direction DR2. The protruding dummy portion DM51 can not be superposed with the second imaginary line IL52. The dummy portion DM51 together with other portions of the third portion PRT53 can define a second curved portion CP52 adjacent to the second portion PRT52.

[0185] The dummy portion DM51 can have a second width W52 equal to the first length L51 in the first direction DR1, and can have a length L5C equal to the lengths of the first curved portion CP51 and the second curved portion CP52 in the second direction DR2.

[0186] For example, the active pattern ACT can include a first curved portion CP51 recessed from the first side surface S51 in the second direction DR2 and a second curved portion CP52 recessed from the second side surface S52 in a direction opposite the second direction DR2. The first curved portion CP51 and the second curved portion CP52 can be spaced apart from each other by a first length L51 in the first direction DR1. The first curved portion CP51 can be spaced apart from the first portion PRT51 including the first boundary BDR51 by the first length L51 in the first direction DR1. The second curved portion CP52 can be spaced apart from the second portion PRT52 including the second boundary BDR52 by a second width W52 of the dummy portion DM51 in a direction opposite the first direction DR1. The first length L51 can be equal to the second width W52.

[0187] The first curved portion CP51 can be spaced apart from the second side surface S52 by a third length L53 in a direction opposite the second direction DR2. The second curved portion CP52 can be spaced apart from the first side surface S51 by the third length L53 in the second direction DR2. The third length L53 can be equal to the first length L51 between the first curved portion CP51 and the second curved portion CP52. The third length L53 can be equal to the first width W51 of each of the first boundary BDR51 and the second boundary BDR52 in the second direction DR2. The third length L53 can be equal to the second width W52 of the dummy portion DM51.

[0188] In an embodiment, the third portion PRT53 can partially surround the first curved portion CP51 and the second curved portion CP52. For example, the third portion PRT53 can surround the first curved portion CP51 except for a side extending from the first curved portion CP51 along the first side surface S51 in the first direction DR1. The third portion PRT53 can surround the second curved portion CP52 except for a side extending from the second curved portion CP52 along the second side surface S52 in the first direction DR1. The first surface HS51 of the second curved portion CP52 can contact the dummy portion DM51 of the third portion PRT53. The second curved portion CP52 and the dummy portion DM51 can share and contact the first surface HS51.

[0189] As the active pattern ACT has the dummy portion DM51 in the region of the channel region CA adjacent to the second boundary BDR52, process variations can be reduced or minimized. For example, when the dummy portion DM51 is formed on the first surface HS51 of the second curved portion CP52, both the first surface HS51 and the second surface HS52 of the second curved portion CP52 can be uniformly surrounded by the third portion PRT53. Thus, during a process of patterning the active pattern ACT, the first surface HS51 and the second surface HS52 of the second curved portion CP52 can be patterned to the same degree. For example, process variations of the active pattern ACT can be reduced by using the dummy portion DM51 to make the peripheral region of the second curved portion CP52 uniform.

[0190] Referring to Figure 12 embodiments in which the active pattern ACT can have an odd number of curved portions in the channel region CA. In embodiments, the active pattern ACT can include a dummy portion DM61 protruding from the channel region CA in a direction opposite to the second direction DR2.

[0191] The channel region CA can include a first portion PRT61 not overlaid with a second imaginary line IL62 aligned with the first direction DR1 and a second portion PRT62 overlaid with the second imaginary line IL62. The channel region CA of the active pattern ACT can include a third portion PRT63 between the first portion PRT61 and the second portion PRT62.

[0192] The third portion PRT63 can include a dummy portion DM61 protruding from a region adjacent to the second portion PRT62 in a direction opposite to the second direction DR2. The second portion PRT62 can be overlaid with the second imaginary line IL62. The protruding dummy portion DM61 can not be overlaid with the second imaginary line IL62. The dummy portion DM61 together with other portions of the third portion PRT63 can define a third curved portion CP63 adjacent to the second portion PRT62.

[0193] The dummy portion DM61 can have a second width W62 equal to the first length L61 in the first direction DR1 and can have a length L6C equal to lengths of the first curved portion CP61 to the third curved portion CP63 in the second direction DR2.

[0194] For example, the active pattern ACT can include a first curved portion CP61 and a third curved portion CP63 recessed from the first side surface S61 in the second direction DR2 and a second curved portion CP62 recessed from the second side surface S62 in a direction opposite the second direction DR2. The first curved portion CP61 to the third curved portion CP63 can be spaced apart from each other by a first length L61 in the first direction DR1. The first curved portion CP61 can be spaced apart from a first portion PRT61 including the first boundary BDR61 by the first length L61 in the first direction DR1. The third curved portion CP63 can be spaced apart from a second portion PRT62 including the second boundary BDR62 by a second width W62 of a dummy portion DM61 in a direction opposite the first direction DR1. The first length L61 can be equal to the second width W62.

[0195] Each of the first curved portion CP61 and the third curved portion CP63 can be spaced apart from the second side surface S62 by a third length L63 in a direction opposite the second direction DR2. The second curved portion CP62 can be spaced apart from the first side surface S61 by the third length L63 in the second direction DR2. The third length L63 can be equal to the first length L61 between the first curved portion CP61 to the third curved portion CP63. The third length L63 can be equal to a first width W61 of each of the first boundary BDR61 and the second boundary BDR62 in the second direction DR2. The third length L63 can also be equal to the second width W62 of the dummy portion DM61.

[0196] In an embodiment, the third portion PRT63 can partially surround the first curved portion CP61 to the third curved portion CP63. For example, the third portion PRT63 can surround the first curved portion CP61 except for a side extending from the first curved portion CP61 along the first side surface S61 in the first direction DR1. The third portion PRT63 can surround the second curved portion CP62 except for a side extending from the second curved portion CP62 along the second side surface S62 in the first direction DR1. The third portion PRT63 can surround the third curved portion CP63 except for a side extending from the third curved portion CP63 along the first side surface S61 in the first direction DR1. The first surface HS61 of the third curved portion CP63 can contact the dummy portion DM61 of the third portion PRT63. The third curved portion CP63 and the dummy portion DM61 can share and contact the first surface HS61.

[0197] As the active pattern ACT has the dummy portion DM61 in the region of the channel region CA adjacent to the second boundary BDR62, process variation can be reduced or minimized. For example, when the dummy portion DM61 is formed on the first surface HS61 of the third curved portion CP63, both the first surface HS61 and the second surface HS62 of the third curved portion CP63 can be uniformly surrounded by the third portion PRT63. Thus, during a process of patterning the active pattern ACT, the first surface HS61 and the second surface HS62 of the third curved portion CP63 can be patterned to the same degree. For example, process variation of the active pattern ACT can be reduced by using the dummy portion DM61 to make the peripheral region of the third curved portion CP63 uniform.

[0198] In this way, as the channel region CA of the active pattern ACT uses the planar structure having the separate dummy portion DM61 disposed in the region adjacent to the second boundary BDR62, process variation of the active pattern ACT can be reduced or minimized, thereby further enhancing the characteristics of the thin film transistor TFT.

[0199] Referring to Figure 13 , an embodiment in which the active pattern ACT can have an even number of curved portions in the channel region CA is shown. In the embodiment, the channel region CA of the active pattern ACT can have a first channel length L7T in a first direction DR1 and can have a first channel width W7T in a second direction DR2 crossing the first direction DR1.

[0200] For example, the active pattern ACT can include a first curved portion CP71 recessed from a first side surface S71 in the second direction DR2 and a second curved portion CP72 recessed from a second side surface S72 in a direction opposite to the second direction DR2. The first curved portion CP71 and the second curved portion CP72 can be spaced apart from each other by a first length L71 in the first direction DR1. The first curved portion CP71 can be spaced apart from the first boundary BDR71 by the first length L71 in the first direction DR1. The second curved portion CP72 can be spaced apart from the second boundary BDR72 by the first length L71 in a direction opposite to the first direction DR1.

[0201] The first curved portion CP71 and the second curved portion CP72 can have a length L7C in the second direction DR2 that is less than the first channel width W7T of the channel region CA. The first curved portion CP71 can be spaced apart from the second side surface S72 by a third length L73 in a direction opposite to the second direction DR2. The second curved portion CP72 can be spaced apart from the first side surface S71 by the third length L73 in the second direction DR2. The third length L73 can be equal to the first length L71.

[0202] The first curved portion CP71 and the second curved portion CP72 can have the same width W7C in the first direction DR1. The length of the remaining portion of each of the first curved portion CP71 and the second curved portion CP72 except for the fixed region can be equal to the width W7C. The fixed region can refer to a region defined by the first length L71 from the first boundary BDR71 and the second boundary BDR72, respectively, and a region defined by the first length L71 between the first curved portion CP71 and the second curved portion CP72. For example, in a case where the size of the gate electrode GE is increased within a design margin, the first length L71 can remain fixed, and the width W7C of each of the first curved portion CP71 and the second curved portion CP72 can increase. In the channel region CA of the active pattern ACT, as the first channel length L7T increases, the width W7C of each of the first curved portion CP71 and the second curved portion CP72 can also increase.

[0203] Although Figure 7 , Figure 9 , Figure 11 and Figure 13 The active pattern ACT including two curved portions in the channel region CA is illustrated, but embodiments are not limited thereto. For example, the active pattern ACT can further include two additional curved portions between the first curved portion and the second curved portion.

[0204] Referring to Figure 14 , an embodiment in which the active pattern ACT can have an odd number of curved portions in the channel region CA is illustrated. In embodiments, the channel region CA of the active pattern ACT can have a first channel length L8T in a first direction DR1 and can have a first channel width W8T in a second direction DR2 crossing the first direction DR1.

[0205] For example, the active pattern ACT can include a first curved portion CP81 and a third curved portion CP83 recessed from a first side surface S81 in the second direction DR2 and a second curved portion CP82 recessed from a second side surface S82 in a direction opposite to the second direction DR2. The first curved portion CP81 to the third curved portion CP83 can be spaced apart from each other by a first length L81 in the first direction DR1. The first curved portion CP81 can be spaced apart from the first boundary BDR81 by the first length L81 in the first direction DR1. The third curved portion CP83 can be spaced apart from the second boundary BDR82 by the first length L81 in a direction opposite to the first direction DR1.

[0206] The first curved portion CP81 and the second curved portion CP82 can have a length L8C that is smaller than the first channel width W8T of the channel region CA in the second direction DR2. Each of the first curved portion CP81 and the third curved portion CP83 can be spaced apart from the second side surface S82 by a third length L83 in a direction opposite to the second direction DR2. The second curved portion CP82 can be spaced apart from the first side surface S81 by the third length L83 in the second direction DR2. The third length L83 can be equal to the first length L81.

[0207] The first curved portion CP81 to the third curved portion CP83 can have the same width W8C. The length of the remaining portion of each of the first curved portion CP81 to the third curved portion CP83 except for the fixed region can be equal to the width W8C. The fixed region can refer to a region defined by the first length L81 from the first boundary BDR81 and the second boundary BDR82, respectively, and a region of each of which is defined by the first length L81 between the first curved portion CP81 to the third curved portion CP83. For example, in the case where the size of the gate electrode GE is increased within a design margin, the first length L81 can remain fixed, and the width W8C of each of the first curved portion CP81 to the third curved portion CP83 can be increased. In the channel region CA of the active pattern ACT, as the first channel length L8T increases, the width W8C of each of the first curved portion CP81 to the third curved portion CP83 can also increase.

[0208] Although Figure 8 , Figure 10 , Figure 12 and Figure 14 shows the active pattern ACT including three curved portions in the channel region CA, embodiments are not limited thereto. For example, the active pattern ACT can include two additional curved portions in addition to the second curved portion between the first curved portion and the third curved portion.

[0209] In this way, the channel region CA of the active pattern ACT can have a structure in which the curved portions have an increased width without forming a planar structure of the curved portions adjacent to the first boundary BDR11 and the second boundary BDR12. Accordingly, the effective channel length of the thin film transistor TFT can be increased while reducing the capacitance of the active pattern ACT, thereby further enhancing the characteristics of the thin film transistor TFT.

[0210] Figure 15 FIG. 1 is a schematic block diagram illustrating an electronic device 1000 including a display device 1060 according to an embodiment. Figure 16 FIG. 2 is a schematic diagram illustrating the electronic device 1000 shown in FIG. 1 as an example of a smartphone. Figure 15 FIG. 3 is a schematic diagram illustrating the electronic device 1000 shown in FIG. 1 as an example of a tablet PC. Figure 17 FIG. 4 is a schematic diagram illustrating the electronic device 1000 shown in FIG. 1 as an example of a wearable device.Figure 15 The electronic device 1000 shown is a schematic diagram of an example of a tablet computer.

[0211] Reference Figures 15 to 17 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may correspond to... Figure 1 The display device DD shown is an electronic device 1000. The electronic device 1000 may also include various ports for communicating with video cards, sound cards, memory cards, USB devices, or other systems. In embodiments, such as... Figure 16 As shown, the electronic device 2000 can be a smartphone. In an embodiment, as... Figure 17 As shown, electronic device 3000 can be a tablet computer. However, the example is illustrative, and electronic device 1000 is not limited to the example. For example, electronic device 1000 can be a flat panel display, a flexible display, a computer monitor, a medical monitor, a television, a billboard, an indoor light, an outdoor light, a signal light, a head-up display, a fully transparent display, a partially transparent display, a flexible display, a rollable display, a foldable display, a stretchable display, a laser printer, a telephone, a cellular phone, a video phone, a mobile phone, a smart tablet, a tablet computer, a tablet phone, a personal digital assistant (PDA), a wearable device, a smartwatch, a navigation device for a vehicle, a laptop computer, a digital camera, a camcorder, a viewfinder, a microdisplay, a three-dimensional (3D) display, a virtual reality display, an augmented reality display, a vehicle, a head-mounted display, a video wall with multiple displays spliced ​​together, a theater screen, a stadium screen, a light therapy device, or a sign, etc.

[0212] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 can be a microprocessor, central processing unit, or application processor, etc. Processor 1010 can be connected to other components via address buses, control buses, and data buses, etc. In embodiments, processor 1010 can be connected to an expansion bus (such as a peripheral component interconnect (PCI) bus). In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data received from processor 1010.

[0213] The memory device 1020 can store data required for the operation of the electronic device 1000. The memory device 1020 can serve as a working memory and / or a buffer memory of the processor 1010. For example, the memory device 1020 can include one or more volatile memory devices such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0214] The storage device 1030 can store data in response to a control signal or data from the processor 1010. The storage device 1030 can include one or more non-volatile storage components to retain data even in the case of power off of the electronic device 1000. In an embodiment, the storage device 1030 can include a solid state drive (SSD), a hard disk drive (HDD), or a CD-ROM, etc.

[0215] The input / output (I / O) device 1040 can include an input device such as a keypad, a key pad, a touch pad, a touch screen, or a mouse, and an output device such as a speaker or a printer. In an embodiment, the display device 1060 can be integrated with the I / O device 1040.

[0216] The power supply 1050 can supply power required for the operation of the electronic device 1000. For example, the power supply 1050 can include a power management integrated circuit (PMIC). In an embodiment, the power supply 1050 can supply power to the display device 1060.

[0217] The display device 1060 can display an image in response to a control signal or data from the processor 1010. The display device 1060 can be connected to other components through a bus or other communication link.

[0218] In an embodiment, since the channel region CA of the active pattern ACT has a planar structure with a curved portion, a current can be induced to flow in a curved shape, thereby increasing an effective channel length in the thin film transistor TFT while maintaining a limited size. In the case where there is no separate curved portion in an edge region (or a boundary) of the channel region CA, the channel region CA can include a first portion and a second portion having a reduced width, thereby reducing the capacitance of the active pattern ACT. Further, since the channel region CA includes a dummy portion, process variation of the channel region CA can be reduced or minimized.

[0219] Various embodiments can provide a thin film transistor TFT having improved performance and a method of manufacturing a thin film transistor TFT.

[0220] Various embodiments can provide a display device having enhanced performance.

[0221] The effects are not limited by the foregoing and various other effects can be anticipated.

[0222] Embodiments have been disclosed herein and, although the terms are used in the description, they are used and interpreted only in a generic and descriptive sense and not for limitation purposes. In some instances, as will be apparent to one of ordinary skill in the art, features, characteristics or elements described in connection with an embodiment can be used independently of the other embodiments described, or in combination with other elements described in connection with other embodiments, unless expressly stated otherwise. Accordingly, one of ordinary skill in the art will recognize that the embodiments described herein can be varied in form and detail without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A thin film transistor included in a display device, the thin film transistor comprising: a substrate; an active pattern provided over the substrate, the active pattern including a first region, a second region, and a channel region between the first region and the second region; a gate electrode provided over the active pattern so as to overlap the channel region; a gate insulating layer provided between the active pattern and the gate electrode; a first electrode provided on the gate insulating layer and connected to the first region; and a second electrode provided on the gate insulating layer and connected to the second region, wherein the channel region includes a first boundary and a second boundary which overlap side surfaces of the gate electrode and are spaced apart from each other in a first direction, the channel region further includes a first side surface and a second side surface which are spaced apart from each other in a second direction intersecting the first direction, the active pattern includes curved portions which are recessed from the first side surface and the second side surface of the channel region in the second direction and a direction opposite to the second direction, respectively, the curved portions are spaced apart from each other in the first direction by a first length, one of the curved portions is spaced apart from the first boundary in the first direction by a second length, the other of the curved portions is spaced apart from the second boundary in the direction opposite to the first direction by the second length, and the second length is equal to or greater than the first length.

2. The thin film transistor according to claim 1, wherein the curved portions include a first curved portion recessed from the first side surface in the second direction and a second curved portion recessed from the second side surface in the direction opposite to the second direction, the first curved portion is spaced apart from the second side surface in the direction opposite to the second direction by a third length, and the second curved portion is spaced apart from the first side surface in the second direction by the third length. the third length is equal to the first length, and 3. The thin film transistor according to claim 2, wherein, wherein a length of one of the first boundary or the second boundary in the second direction is equal to a sum of a length of one of the curved portions in the second direction and the third length.

4. The thin film transistor according to claim 2, wherein the channel region includes a first portion adjacent to the first region, a second portion adjacent to the second region, and a third portion between the first portion and the second portion, the first portion is spaced apart from the first curved portion in the direction opposite to the first direction by the first length, and the second portion is spaced apart from the second curved portion in the first direction by the first length, the first portion and the second portion each have a first width in the second direction, and the first width is equal to the third length. the third portion partially surrounds the curved portions and has a constant width, and 5. The thin film transistor according to claim 4, wherein, wherein the first portion and the second portion are spaced apart from a first imaginary line aligned with the second direction by the same length, and the third portion is spaced apart from the first imaginary line by the third length. The first imaginary line is disposed between the first curved portion and the second curved portion and is spaced apart from each of the first curved portion and the second curved portion by the same distance.

6. The thin film transistor according to claim 4, wherein the first portion and the second portion are superposed with a second imaginary line aligned with the first direction, the third portion includes a dummy portion protruding from a region adjacent to the second portion in the second direction, and the dummy portion forms the second curved portion together with other portions of the third portion, and wherein the dummy portion has a second width equal to the first length in the first direction, and the dummy portion has a length equal to a length of each of the first curved portion and the second curved portion in the second direction.

7. The thin film transistor according to claim 2, wherein the curved portion further includes a third curved portion recessed from the first side surface in the second direction, and the third curved portion is disposed parallel to the first curved portion, with the second curved portion disposed between the first curved portion and the third curved portion.

8. The thin film transistor according to claim 7, wherein the channel region includes a first portion adjacent to the first region, a second portion adjacent to the second region, and a third portion between the first portion and the second portion, the first portion is spaced apart from the first curved portion by the first length in the direction opposite to the first direction, and the second portion is spaced apart from the third curved portion by the first length in the first direction, the first portion and the second portion each have a first width in the second direction, and the first width is equal to the third length, and wherein the third portion partially surrounds the curved portion and has a constant width.

9. The thin film transistor according to claim 8, wherein the first portion and the second portion are spaced apart by the same length from a first imaginary line aligned with the second direction, and the first imaginary line is disposed between the first curved portion and the third curved portion and is spaced apart from each of the first curved portion and the third curved portion by the same distance, and wherein the third portion includes a dummy portion protruding from a region adjacent to the second portion in the direction opposite to the second direction, and the dummy portion forms the third curved portion together with other portions of the third portion.

10. The thin film transistor according to claim 1, wherein in a case where the second length is greater than the first length, each of the curved portions has a third width in the first direction, and in a case where the first length and the second length are equal to each other, each of the curved portions has a fourth width greater than the third width in the first direction.

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