Array sensor and manufacturing method thereof

Abstract

The invention provides an array sensor and a manufacturing method thereof. The method comprises the following steps: providing a substrate; an interlayer dielectric layer, a TFT located in the interlayer dielectric layer and a first polar plate of a first capacitor are formed on the substrate, and the interlayer dielectric layer comprises a first dielectric layer and a second dielectric layer; forming a second pole plate of a first capacitor on the second dielectric layer; forming a third dielectric layer on the second polar plate of the first capacitor and the second dielectric layer; forming a contact hole penetrating through the third dielectric layer and the second dielectric layer; forming a PIN electrode on the third dielectric layer; a PIN is formed on the PIN electrode; forming an ITO (Indium Tin Oxide) layer on the PIN; and forming a bonding pad, wherein the bonding pad covers part of the side wall of the PIN and the side wall of the ITO layer. According to the invention, the signal-to-noise ratio of the image sensor is improved, and dynamic display and high-quality image are realized, so that the high-PPI flat panel detector is realized.

Description

Technical Field

[0001] This application relates to the field of sensor technology, and in particular to an array sensor and a method for manufacturing the same. Background Technology

[0002] An array sensor is an array of a certain number of sensing units arranged in a specific manner. Each sensing unit can independently sense signals such as light, electromagnetic, and pressure, triggering an electrical response within the unit. This response is detected by an external driving circuit through a specific circuit structure, thereby determining the intensity of the detected signal at the corresponding sensing unit. An array of sensing units can be detected and recorded through the circuit structure, thus forming a two-dimensional distribution information of the sensed signal corresponding to the array of sensing units.

[0003] With the development of display technology, people's requirements for display effects are also increasing. PPI (Pixels Per Inch) is a unit of measurement for screen resolution, used to describe the number of pixels per inch of a display device. The higher the PPI, the more delicate and clear the displayed images and text are. Specifically, PPI is calculated by dividing the horizontal and vertical pixels of the display by the physical width and height of the screen. For example, if a screen has a resolution of 1920×1080 pixels and a screen size of 5 inches, then its PPI can be calculated. With the widespread application of flat panel detectors in medical testing, security inspection, and industrial production, the Modulation Transfer Function (MTF) is one of the core indicators of flat panel detectors. A high PPI array design can improve the detector's MTF, achieving high-quality X-ray images.

[0004] In flat panel detectors or other electronic devices, "FF" usually refers to "Fill Factor". The fill factor is a parameter that represents the ratio of the effective area to the total area of ​​a photodetector (such as a photodiode or solar cell). Specifically, in flat panel detectors, the fill factor describes the proportion of the photosensitive area (the area that can actually sense light) relative to the entire pixel area. A higher fill factor means that more incident light can be captured by the detector and converted into an electrical signal, thereby improving the efficiency and sensitivity of the detector. Conventional array device designs often have the following problems: (1) When the PPI is high, the FF is too low, which directly leads to a significant decrease in detector sensitivity; (2) When the PPI is high, the parasitic capacitance of the PIN diode and the data line increases significantly, which will lead to a significant increase in detector noise and affect the quality of the detector; (3) When the PPI is too high, the storage capacitance of the PIN will decrease, affecting the dynamic range of the detector. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a method for manufacturing an array-type sensor, comprising the steps of: providing a substrate; forming an interlayer dielectric layer on the substrate, and a TFT and a first electrode plate of a first capacitor located within the interlayer dielectric layer, wherein the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer, and the first electrode plate of the first capacitor is connected to the source / drain region of the TFT; forming a second electrode plate of the first capacitor on the second dielectric layer, the first electrode plate and the second electrode plate of the first capacitor being opposite to and parallel to each other in a direction perpendicular to the substrate; forming a third dielectric layer on the second electrode plate of the first capacitor and the second dielectric layer; forming a contact hole penetrating the third dielectric layer and the second dielectric layer; forming a PIN electrode on the third dielectric layer, such that the first electrode plate of the first capacitor is interconnected with the PIN electrode and the source / drain region of the TFT; forming a PIN on the PIN electrode; forming an ITO layer on the PIN; forming a bonding pad, the bonding pad covering a portion of the PIN sidewall and the ITO layer sidewall.

[0006] Optionally, forming an interlayer dielectric layer on the substrate, and the TFT and the first electrode of the first capacitor located within the interlayer dielectric layer, includes the steps of: forming the first dielectric layer on the substrate; forming the source / drain region of the TFT within the first dielectric layer; forming the gate layer of the TFT and the first electrode of the first capacitor on the first dielectric layer and the source / drain region of the TFT, wherein, while forming the gate layer of the TFT, a gate material layer isolated from the gate layer and located on the same layer is formed in the peripheral region of the TFT, serving as the first electrode of the first capacitor; and forming a second dielectric layer on the first dielectric layer, the gate layer of the TFT, and the first electrode of the first capacitor.

[0007] Optionally, the third dielectric layer includes an isolation layer and a dielectric layer, and the contact hole includes a first sub-contact hole and a second sub-contact hole.

[0008] Optionally, forming a third dielectric layer on the second electrode plate and the second dielectric layer of the first capacitor includes the steps of: forming an isolation layer on the second electrode plate and the second dielectric layer of the first capacitor; etching the isolation layer and the second dielectric layer to form a first sub-contact hole interconnected with the first electrode plate of the first capacitor; forming a dielectric layer on the isolation layer; and etching the dielectric layer to form a second sub-contact hole communicating with the first sub-contact hole.

[0009] Optionally, the method for manufacturing the array sensor further includes: after forming the bonding pads, forming a planarization layer covering the bonding pads.

[0010] Optionally, forming a PIN on the PIN electrode includes the steps of forming an N-type material layer, an intrinsic layer, and a P-type material layer on the PIN electrode.

[0011] Optionally, the TFT is a top-gate TFT, and the formation of the TFT includes the steps of: forming a P-type doped layer in the first dielectric layer; forming source / drain regions of the TFT located on both sides of the P-type doped layer; and forming a gate layer of the TFT in the second dielectric layer on top of the P-type doped layer.

[0012] Optionally, the TFT is a bottom-gate TFT, and the formation of the TFT includes the steps of: forming a gate layer of the TFT in the first dielectric layer; forming a P-type doped layer on the gate layer of the TFT and the adjacent region; and forming source / drain regions of the TFT located on both sides of the P-type doped layer.

[0013] The present invention also provides an array-type sensor, comprising: a substrate, and an interlayer dielectric layer and a third dielectric layer formed on the substrate; a TFT located within the interlayer dielectric layer on the substrate; a first capacitor located within the interlayer dielectric layer in the peripheral region of the TFT on the substrate, wherein a first electrode of the first capacitor is located on the same layer as the gate layer of the TFT and interconnected with the source / drain region of the TFT, the first electrode and the second electrode of the first capacitor are arranged opposite to and parallel to each other in a direction perpendicular to the substrate, and an interlayer dielectric layer is provided between the first electrode and the second electrode of the first capacitor; a PIN electrode disposed on the top of the first capacitor and the TFT; a PIN electrode disposed on the PIN electrode, wherein the junction capacitance in the PIN electrode is connected in parallel with the first capacitor; an ITO layer disposed on the PIN electrode; and a bonding pad, wherein the bonding pad covers a portion of the PIN sidewall and the ITO sidewall.

[0014] Optionally, the PIN includes a P-type material layer, a neutral material layer, and an N-type material layer, and the PIN electrode is interconnected with the first electrode of the first capacitor through a contact hole.

[0015] Optionally, the TFT is a top-gate TFT, which includes a P-type doped layer, source / drain regions of the TFT located on both sides of the P-type doped layer, and a gate layer of the TFT located on top of the P-type doped layer.

[0016] Optionally, the TFT is a bottom-gate TFT, which includes a P-type doped layer, source / drain regions of the TFT located on both sides of the P-type doped layer, and a gate layer of the TFT located at the bottom of the P-type doped layer.

[0017] Optionally, the first plate of the first capacitor is interconnected with the source / drain region of the TFT through a contact hole.

[0018] Compared with the prior art, the technical solutions of the embodiments of this disclosure have the following beneficial effects:

[0019] The method for manufacturing an array-type sensor disclosed herein increases the storage capacitance of the array-type sensor by forming a first capacitor that is connected in parallel with the junction capacitance of the PIN; and by isolating the PIN and the TFT with a dielectric layer, the parasitic capacitance between the PIN and the TFT can be reduced. Applying the array-type sensor manufactured by the method disclosed herein to high-PPI flat panel detector products is beneficial for improving the signal-to-noise ratio of the image sensor, achieving dynamic display and high-quality images, thereby realizing a truly high-PPI flat panel detector. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a manufacturing method for an array-type sensor according to an embodiment of the present disclosure;

[0022] Figure 2 This is a schematic diagram of the structure of an array sensor according to an embodiment of the present disclosure. Detailed Implementation

[0023] As mentioned in the background, a high PPI and a very low fill factor in conventional array device designs can lead to a significant decrease in detector sensitivity. First, a low fill factor means a smaller effective area for photoelectric conversion in each pixel, resulting in low incident light utilization and thus reduced overall photoelectric conversion efficiency. Second, due to the small photosensitive area, the generated electrical signal is correspondingly weaker, which affects the detector's signal strength and signal-to-noise ratio, especially under low-light conditions. Furthermore, devices with low fill factors may generate more dark current and noise in non-photosensitive areas, further reducing the signal-to-noise ratio and image quality. For image sensors and X-ray flat panel detectors, a low fill factor leads to a decline in image quality, including reduced resolution and sensitivity. This is particularly detrimental in applications such as medical imaging and precision detection.

[0024] Furthermore, at higher PPI, the parasitic capacitance of PIN diodes and data lines in conventional array designs increases significantly, leading to a marked increase in detector noise and affecting detector quality. Simultaneously, excessively high PPI reduces the storage capacitance of the PIN diodes, impacting the detector's dynamic range.

[0025] Therefore, this disclosure provides an array-type sensor and a method for manufacturing the same, which can enhance the storage capacitance of the array-type sensor and improve the image quality obtained by the image sensor.

[0026] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0027] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Since this invention pertains to electrical devices, connection and interconnection both refer to conductive interconnections. Because the accompanying drawings describe the same device, the same reference numerals denote the same components.

[0028] This disclosure provides an array-type sensor, comprising: a substrate, and an interlayer dielectric layer and a third dielectric layer formed on the substrate; a TFT located within the interlayer dielectric layer on the substrate; a first capacitor located within the interlayer dielectric layer in the peripheral region of the TFT on the substrate, wherein a first electrode of the first capacitor is located on the same layer as the gate layer of the TFT and interconnected with the source / drain region of the TFT, the first electrode and a second electrode of the first capacitor are arranged opposite to and parallel to each other in a direction perpendicular to the substrate, and an interlayer dielectric layer is provided between the first electrode and the second electrode of the first capacitor; a PIN electrode disposed on the top of the first capacitor and the TFT; a PIN electrode disposed on the PIN electrode, wherein the junction capacitance in the PIN electrode is connected in parallel with the first capacitor; an ITO layer disposed on the PIN electrode; and a bonding pad covering a portion of the PIN sidewall and the ITO sidewall.

[0029] Figure 1 A schematic flowchart of a method for manufacturing an array-type sensor according to an embodiment of the present disclosure is shown. Figure 2 A schematic diagram of an array-type sensor according to an embodiment of the present disclosure is shown. The following is in conjunction with… Figure 1 and Figure 2 Specific embodiments of the present invention will be described. The manufacturing method includes the following steps:

[0030] S1: Provide substrate.

[0031] Reference Figure 2 A substrate 100 is provided, and a buffer layer 110 is formed on the substrate 100.

[0032] In this embodiment, the substrate is a glass substrate. In some other embodiments, the substrate may also be a silicon wafer.

[0033] In a thin-film transistor (TFT) structure, a buffer layer is typically formed by depositing different types of materials on the thin film layer. These materials are typically semiconductor materials and insulating materials. In this embodiment, the insulating material used in the buffer layer 110 includes any one or a combination of alumina and silicon oxide, and is deposited on the substrate 100 using techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).

[0034] S2: An interlayer dielectric layer is formed on a substrate, and a TFT and a first electrode of a first capacitor are located within the interlayer dielectric layer, wherein the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer, and the first electrode of the first capacitor is connected to the source / drain region of the TFT.

[0035] In some embodiments, a TFT can be formed by fabricating an active layer of amorphous silicon, metal oxide, or polycrystalline silicon on substrate 100. A TFT is a semiconductor device used to control pixel current and is very common in displays and imaging devices. In flat panel detectors, TFTs can be used to read out and amplify electrical signals generated by photodiodes (such as PIN diodes). In a specific embodiment, polycrystalline silicon can be formed by dehydrogenating a-Si formed by plasma-enhanced chemical vapor deposition (PECVD) and then performing excimer laser crystallization (ELA).

[0036] Specifically, in this embodiment, a first dielectric layer 120 is first deposited on a substrate 100 with a buffer layer 110. Next, a P-type doped layer 210 is formed in the first dielectric layer 120 by plasma source implantation. Then, source / drain regions 220 of the TFT are formed on both sides of the P-type doped layer by source / drain implantation. The source and drain regions are key components in the TFT, used to control the injection and discharge of current, thereby realizing the switching function of the TFT. The materials and fabrication processes of the TFT source and drain regions have a significant impact on the performance and characteristics of the device.

[0037] After forming the source / drain regions 220 of the TFT, a gate material layer is deposited on the first dielectric layer 120 and the P-type doped layer 210. Then, photolithography is used to pattern the gate material to define the gate layer 230 of the TFT; that is, by etching the gate material layer, the gate material layer on top of the P-type doped layer is left as the gate layer 230 of the TFT. Simultaneously, a gate material layer in the peripheral region of the TFT gate layer 230, isolated from the TFT gate layer and located on the same layer, is left to serve as the first electrode 310 of the first capacitor. Then, a second dielectric layer 130 is formed on the first dielectric layer 120, the TFT gate layer 230, and the first electrode 310 of the first capacitor.

[0038] In some embodiments, after the gate layer of the TFT is formed, the substrate is cleaned to remove residual photoresist and etching residues, and possible post-processing steps are performed to improve the surface properties and conductivity of the TFT gate layer.

[0039] In some embodiments, the gate material layer is typically made of a highly conductive material, such as a metal or a conductive oxide. Commonly used gate materials include aluminum (Al), copper (Cu), and indium tin oxide (ITO). In embodiments of this disclosure, the gate material layer is made of molybdenum (Mo).

[0040] In some embodiments, the material of the first dielectric layer may be silicon oxide. The material of the second dielectric layer may be silicon oxide or silicon nitride.

[0041] like Figure 2 As shown in this embodiment, the TFT is a top-gate TFT. In some other embodiments, the TFT may also be a bottom-gate TFT.

[0042] In the structure of a bottom-gate TFT, the gate layer is located at the bottom of the TFT, typically formed by first depositing a metal layer as the gate layer on a glass or other substrate. Subsequently, a gate dielectric layer (such as SiNx or SiO2) and an amorphous silicon active layer are deposited sequentially above the gate layer. In a specific embodiment, the formation steps of the bottom-gate TFT include: forming the gate layer of the TFT in the first dielectric layer; forming a P-type doped layer on the gate layer and adjacent regions of the TFT; and forming source / drain regions of the TFT located on both sides of the P-type doped layer.

[0043] In some embodiments, the TFT is an indium gallium zinc oxide (IGZO) TFT. In other embodiments, the TFT may also be an a-Si TFT or an LTPS TFT.

[0044] S3: A second electrode of a first capacitor is formed on the second dielectric layer, wherein the first electrode and the second electrode of the first capacitor are arranged opposite to each other and parallel in a direction perpendicular to the substrate.

[0045] In this embodiment, a second electrode 320 of the first capacitor is formed on the second dielectric layer 130 at a position corresponding to the first electrode 310 of the first electrode. That is, the first electrode 310 and the second electrode 320 of the first capacitor are arranged opposite to and parallel to each other in a direction perpendicular to the substrate 100. The second electrode 320 of the first capacitor is a metal electrode.

[0046] In some embodiments, the metal electrode used as the second plate of the first capacitor can be a metal such as molybdenum (Mo), copper (Cu), titanium aluminum titanium (Ti / Al / Ti), or ITO.

[0047] S4: A third dielectric layer is formed on the second plate of the first capacitor and the second dielectric layer.

[0048] Reference Figure 2 The third dielectric layer includes an isolation layer 140 and a dielectric layer 150.

[0049] S5: Form a contact hole that penetrates the third dielectric layer and the second dielectric layer.

[0050] In this embodiment of the disclosure, the contact hole includes a first sub-contact hole and a second sub-contact hole.

[0051] Specifically, forming a third dielectric layer on the second electrode of the first capacitor and the second dielectric layer includes the following steps. First, an isolation layer 140 is covered on the second dielectric layer 130 and the second electrode 320 of the first capacitor. The isolation layer 140 is made of silicon oxide or silicon nitride, which ensures electrical isolation and insulation between different metal layers. Then, the isolation layer 140 and the second dielectric layer 130 are etched to form a first sub-contact hole interconnecting with the first electrode 310 of the first capacitor. Next, through deposition and metallization processes, metal electrodes 240 of the TFT source / drain regions are formed in the first sub-contact hole, and the metal electrodes 240 partially cover the isolation layer 140, thereby connecting the metal electrodes 240 of the TFT source / drain regions to the first electrode 310 of the first capacitor.

[0052] In some embodiments, the metal electrodes of the TFT source / drain regions can be commonly used metal materials, including aluminum (Al), copper (Cu), etc.

[0053] In some embodiments, a material with a low dielectric constant can be selected as the isolation layer. The use of a low dielectric constant material can reduce capacitive coupling and signal transmission delay, thereby improving the performance of the integrated circuit. The isolation layer can be formed by PVD or CVD. Using techniques such as CVD or PVD to deposit the selected low dielectric constant material onto the substrate surface ensures that the material uniformly covers the entire substrate surface, and the thickness of the material can be controlled during the fabrication process.

[0054] Next, as Figure 2 As shown, a dielectric layer 150 is formed on the isolation layer 140 and the metal electrodes 240 of the TFT source / drain regions. This dielectric layer, made of an organic resin material, is used to reduce the parasitic capacitance between the PIN and the TFT in the array sensor disclosed herein, which helps to reduce detector noise and improve the detector's signal-to-noise ratio. The dielectric layer 150 is then etched to form a second sub-contact hole communicating with the first sub-contact hole. This second sub-contact hole is used to form the PIN electrode in subsequent steps.

[0055] S6: A PIN electrode is formed on the third dielectric layer, so that the first plate of the first capacitor is interconnected with the PIN electrode and the source / drain region of the TFT.

[0056] First, a PIN electrode 410 is formed in the second sub-contact hole through deposition and metallization processes, and the PIN electrode 410 covers a portion of the dielectric layer 150. Since the second sub-contact hole is filled with the PIN electrode 410, the PIN electrode 410, the metal electrode 240 of the source / drain region of the TFT, and the first electrode plate 310 of the first capacitor are interconnected.

[0057] In the embodiments disclosed herein, such as Figure 2 As shown, the contact hole also includes a third sub-contact hole, through which the first electrode plate 310 of the first capacitor is interconnected with the source / drain region of the TFT.

[0058] S7: A PIN is formed on the PIN electrode.

[0059] Next, an N-type material layer (N-layer) is deposited on the PIN electrode 410. N-type materials are typically semiconductors doped with trivalent elements (such as phosphorus). Then, an intrinsic layer (I-layer) is deposited on top of the N-type material layer. This layer is typically made of pure, undoped semiconductor materials, such as pure silicon (Si), which contains no free carriers. Finally, a P-type material layer (P-layer) is deposited on top of the intrinsic layer. P-type materials are typically semiconductors doped with pentavalent elements (such as boron). The neutral layer is typically used for the light absorption region in optoelectronic devices, while the P-type and N-type layers are used to collect electrons and holes generated after photon absorption and guide them to external circuitry.

[0060] By covering the PIN above the TFT, the detector's open-circuit current (FF) can be increased, thereby improving its detection sensitivity. Simultaneously, by adding a first capacitor in parallel with the junction capacitance in the PIN, they together serve as the storage capacitance of the flat panel detector, which helps to improve the detector's dynamic range. Furthermore, the array sensor provided in this disclosure, by adding a dielectric layer between the TFT and the PIN, reduces the parasitic capacitance between the PIN and the TFT, which helps to reduce detector noise and improve the detector's signal-to-noise ratio.

[0061] S8: An ITO layer is formed on the PIN.

[0062] After forming PIN420, a first ITO layer 430 is deposited on PIN420. Then, the first ITO layer 430 and the N-type material layer, intrinsic layer and P-type material layer in PIN are patterned by etching technology to form the desired structure.

[0063] Indium tin oxide (ITO) is a transparent conductive thin film material commonly used in displays, optoelectronic devices, and other fields. In some embodiments, the ITO layer can be deposited using techniques such as PVD or CVD. PVD is a commonly used method, which involves heating and evaporating an ITO target material in a vacuum environment, then depositing it onto a substrate surface to form a thin film. After the ITO layer is deposited to form a thin film, a transparent conductive layer is formed. ITO has excellent transparency and conductivity, making it ideal for applications such as transparent electrodes.

[0064] In some embodiments, the ITO layer includes a first ITO layer and a second ITO layer.

[0065] S9: Form a bonding pad that covers part of the PIN sidewall and the ITO layer sidewall.

[0066] After forming the ITO layer 430, the bonding pads 160 are then formed, as shown in the reference. Figure 2 The bonding pad 160 covers a portion of the dielectric layer 150, the sidewalls of the PIN electrode 410, the sidewalls of the PIN 420, and the sidewalls of the ITO layer 430.

[0067] In some embodiments, the bonding pads may be made of silicon nitride.

[0068] In this embodiment of the disclosure, after forming the bonding pads 160, the manufacturing method of the array sensor further includes: forming a planarization layer 170 covering the bonding pads, used to planarize the bonding pads 160, facilitating the reliability and stability of subsequent processes.

[0069] The method for manufacturing an array sensor provided in this disclosure flattens the PIN through the planarization layer, which helps to reduce the dark current of the detector and improve the signal-to-noise ratio of the detector.

[0070] In this embodiment of the disclosure, after forming the planarization layer 170, the manufacturing method of the array sensor further includes: forming a second ITO layer 440. (Refer to...) Figure 2 A second ITO layer 440 is deposited on the ITO layer 430.

[0071] Combination Figure 2 In this embodiment of the disclosure, after forming the second ITO layer 440, an insulating layer 180 is used to cover the entire array sensor for encapsulation, preventing the array sensor from coming into contact with external moisture during storage, use, etc., and avoiding moisture entering the PIN diode and other structures and damaging their sensitivity.

[0072] In some embodiments, after forming the insulating layer, a scintillator layer may also be formed on the insulating layer. The scintillator layer is a computed tomography scintillator imaging layer, used in X-ray sensors to convert X-ray energy into visible light or light of other wavelengths. This light is captured by a sensor detector (such as a photodiode or photomultiplier tube) and converted into an electrical signal, thereby forming an image.

[0073] In some embodiments, the scintillator layer is formed by depositing or encapsulating a scintillator material on the photosensitive area of ​​the sensor. The scintillator material is typically a crystal or plastic capable of producing light when X-rays are incident. Common scintillator materials include scintillator plastics, cesium iodide (CsI) crystals, etc.

[0074] In X-ray flat panel detectors, PIN diodes are primarily used to convert incident photon energy into electrical signals. X-rays are converted into visible light as they pass through the scintillator layer. These visible photons are absorbed by the PIN diode, and the photon energy generates electron-hole pairs in the I-layer of the PIN diode. Under the influence of the electric fields in the P-type and N-type regions of the PIN diode, the generated electrons and holes move towards the diode's terminals, respectively, producing a current. This current signal is read by a TFT connected to the PIN diode, amplified, and transmitted to subsequent readout circuitry. This structure enables PIN diodes to perform photoelectric conversion efficiently, exhibiting high sensitivity and high resolution, making them suitable for X-ray flat panel detectors in fields such as medical imaging and industrial inspection.

[0075] The array sensor provided by this invention, by employing a-Si, IGZO, or LTPS TFTs as switching TFTs and adding a first capacitor, which is connected in parallel with the junction capacitance of the PIN as the storage capacitor of the flat panel detector, helps to improve the dynamic range of the detector. Simultaneously, the structure where the PIN covers the TFT helps to improve the detector's open-circuit current (FF) and detection sensitivity; furthermore, by using the PIN to block the TFT channel, it helps to reduce the generation of photogenerated carriers in the TFT and thus reduce detector noise.

[0076] The array-type sensor disclosed herein is used in high PPI flat panel detector products. By adding a first capacitor to expand the storage capacitor, using a dielectric layer to isolate the PIN and TFT, and designing the PIN to cover the TFT, the signal-to-noise ratio of the image sensor can be improved, enabling dynamic display and high-quality images, thereby realizing a truly high PPI flat panel detector.

[0077] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for manufacturing an array-type sensor, characterized in that, Including the following steps: Provide substrate; An interlayer dielectric layer is formed on a substrate, and a TFT and a first electrode of a first capacitor are located within the interlayer dielectric layer. The interlayer dielectric layer includes a first dielectric layer and a second dielectric layer, and the first electrode of the first capacitor is connected to the source / drain region of the TFT. A second electrode of a first capacitor is formed on the second dielectric layer, wherein the first electrode and the second electrode of the first capacitor are arranged opposite to each other and parallel in a direction perpendicular to the substrate. A third dielectric layer is formed on the second electrode plate and the second dielectric layer of the first capacitor; A contact hole is formed that penetrates the third dielectric layer and the second dielectric layer; A PIN electrode is formed on the third dielectric layer, so that the first plate of the first capacitor is interconnected with the PIN electrode and the source / drain region of the TFT; A PIN is formed on the PIN electrode; An ITO layer is formed on the PIN; A bonding pad is formed, which covers a portion of the PIN sidewall and the ITO layer sidewall.

2. The method for manufacturing an array-type sensor as described in claim 1, characterized in that, The step of forming an interlayer dielectric layer on a substrate, and a first electrode plate of a TFT and a first capacitor located within the interlayer dielectric layer, includes the following steps: The first dielectric layer is formed on the substrate; The source / drain regions of the TFT are formed within the first dielectric layer; A gate layer of the TFT and a first electrode of the first capacitor are formed on the first dielectric layer and the source / drain region of the TFT, wherein, while forming the gate layer of the TFT, a gate material layer isolated from the gate layer and located on the same layer is formed in the peripheral region of the TFT, which serves as the first electrode of the first capacitor. The second dielectric layer is formed on the first dielectric layer, the gate layer of the TFT, and the first electrode plate of the first capacitor.

3. The method for manufacturing an array-type sensor as described in claim 1, characterized in that, The third dielectric layer includes an isolation layer and a dielectric layer, and the contact hole includes a first sub-contact hole and a second sub-contact hole.

4. The method for manufacturing an array-type sensor as described in claim 3, characterized in that, The step of forming a third dielectric layer on the second electrode of the first capacitor and the second dielectric layer includes the following steps: An isolation layer is formed on the second electrode plate and the second dielectric layer of the first capacitor; Etch the isolation layer and the second dielectric layer to form a first sub-contact hole that interconnects with the first plate of the first capacitor; A dielectric layer is formed on the isolation layer; The dielectric layer is etched to form a second sub-contact hole that communicates with the first sub-contact hole.

5. The method for manufacturing an array-type sensor as described in claim 1, characterized in that, Also includes: After the bonding pads are formed, a planarization layer is formed to cover the bonding pads.

6. The method for manufacturing an array-type sensor as described in claim 1, characterized in that, The step of forming a PIN on the PIN electrode includes: An N-type material layer, an intrinsic layer, and a P-type material layer are formed on the PIN electrode.

7. The method for manufacturing an array-type sensor as described in claim 2, characterized in that, The TFT is a top-gate TFT, and the formation of the TFT includes the following steps: A P-type doped layer is formed in the first dielectric layer; The source / drain regions of the TFT are formed on both sides of the P-type doped layer; A TFT gate layer is formed in the second dielectric layer on top of the P-type doped layer.

8. The method for manufacturing an array-type sensor as described in claim 1, characterized in that, The TFT is a bottom-gate TFT, and the formation of the TFT includes the following steps: A TFT gate layer is formed in the first dielectric layer; A P-type doped layer is formed on the gate layer and adjacent regions of the TFT; The source / drain regions of the TFT are formed on both sides of the P-type doped layer.

9. An array-type sensor, characterized in that, include: A substrate, and an interlayer dielectric layer and a third dielectric layer formed on the substrate; TFTs located within the interlayer dielectric layer on the substrate; A first capacitor is located in the interlayer dielectric layer of the TFT peripheral region on the substrate. The first electrode of the first capacitor is located in the same layer as the gate layer of the TFT and is interconnected with the source / drain region of the TFT. The first electrode and the second electrode of the first capacitor are arranged opposite to each other and parallel in the direction perpendicular to the substrate. An interlayer dielectric layer is provided between the first electrode and the second electrode of the first capacitor. PIN electrodes disposed on the top of the first capacitor and the TFT; A PIN is disposed on a PIN electrode, wherein the junction capacitance of the PIN is connected in parallel with the first capacitor; The ITO layer located on the PIN; Bonding pads that cover a portion of the PIN sidewall and the ITO sidewall.

10. The array sensor as described in claim 9, characterized in that, The PIN includes a P-type material layer, a neutral material layer, and an N-type material layer, and the PIN electrode is interconnected with the first electrode of the first capacitor through a contact hole.

11. The array sensor as described in claim 9, characterized in that, The TFT is a top-gate TFT, which includes a P-type doped layer, source / drain regions of the TFT located on both sides of the P-type doped layer, and a gate layer of the TFT located on top of the P-type doped layer.

12. The array sensor as described in claim 9, characterized in that, The TFT is a bottom-gate TFT, which includes a P-type doped layer, source / drain regions of the TFT located on both sides of the P-type doped layer, and a gate layer of the TFT located at the bottom of the P-type doped layer.

13. The array sensor as described in claim 9, characterized in that, The first plate of the first capacitor is interconnected with the source / drain region of the TFT through a contact hole.

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