Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: forming a dielectric material stack above a substrate, and the substrate is provided with an array region and a peripheral region; forming accommodating holes of a plurality of capacitor structures in the dielectric material lamination; and forming a capacitor structure in the accommodating holes, the capacitor structure including a plurality of storage capacitors in the array region, each storage capacitor having a first critical dimension at the top surface of the dielectric material stack; and a plurality of dummy capacitors surrounding the storage capacitors, where each dummy capacitor has a second critical dimension at the top surface of the dielectric material stack, where the second critical dimension is less than the first critical dimension and greater than 1 / 3 of the first critical dimension.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing the same, and more particularly to semiconductor devices including a capacitor structure having a high aspect ratio and methods of manufacturing the same. BACKGROUND

[0002] As the manufacturing technology of components continues to move toward miniaturization of component sizes, many challenges arise. For example, in the process of making a capacitor structure having a high aspect ratio, due to some process factors, such as the presence of multiple layers of films between a patterned layer used to define the location of the housing holes of the dummy capacitors and a patterned photoresist used to mask the surrounding area, and / or the presence of a tilt or shift of the sidewall of the outer edge of the patterned photoresist from a predetermined position, the size variation of those openings of the patterned layer exposed by the patterned photoresist at the edge of the array area is large. As a result, based on the etching loading effect, the housing holes of the dummy capacitors formed with a large size tend to extend diagonally at the bottom and contact the housing holes of the storage capacitors, resulting in a short circuit between the dummy capacitors and the storage capacitors formed in the housing holes subsequently, thereby reducing the yield of the semiconductor device. If the problem of large size variation of the housing holes of the dummy capacitors is not improved, more dummy capacitors must be provided to avoid the contact between the dummy capacitors and the storage capacitors with the above-mentioned defects. This will be detrimental to the miniaturization of the semiconductor device. SUMMARY

[0003] According to the semiconductor device and the method of manufacturing the same disclosed in the present disclosure, the problem of large size variation of the housing holes of the dummy capacitors can be improved, thereby reducing the problem of short circuit between the dummy capacitors and the storage capacitors.

[0004] Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including forming a dielectric material stack over a substrate, the substrate having an array area and a surrounding area; forming a plurality of housing holes of capacitor structures in the dielectric material stack; and forming the capacitor structures in the housing holes, and the capacitor structures including a plurality of storage capacitors in the array area, wherein each storage capacitor has a first critical dimension at a top surface of the dielectric material stack; and a plurality of dummy capacitors surrounding the storage capacitors, wherein each dummy capacitor has a second critical dimension at the top surface of the dielectric material stack, wherein the second critical dimension is smaller than the first critical dimension and greater than 1 / 3 of the first critical dimension.

[0005] Some embodiments disclosed herein provide a semiconductor device including a substrate, a dielectric material stack, and a plurality of capacitor structures located within the dielectric material stack. The substrate has an array region and a peripheral region; the dielectric material stack is located above the substrate; and the plurality of capacitor structures are located within the dielectric material stack. The capacitor structures include a plurality of storage capacitors located in the array region, each storage capacitor having a first critical dimension at the top surface of the dielectric material stack; and a plurality of dummy capacitors surrounding these storage capacitors, each dummy capacitor having a second critical dimension at the top surface of the dielectric material stack, wherein the second critical dimension is smaller than the first critical dimension and larger than one-third of the first critical dimension.

[0006] According to the semiconductor device and manufacturing method disclosed herein, the depth and pattern uniformity of the dummy capacitor can be improved, and the depth of the accommodating hole of the dummy capacitor can be controlled to be less than the depth of the accommodating hole of the storage capacitor, so as to avoid short circuits between adjacent capacitor structures and thereby improve the yield of the semiconductor device. Attached Figure Description

[0007] Figure 1 , Figures 2A-2D This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure at some intermediate manufacturing stages.

[0008] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A This is a three-dimensional schematic diagram of a semiconductor device according to some embodiments of the present disclosure at some intermediate manufacturing stages to obtain a patterned sacrificial target layer. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B They are respectively Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A The top view.

[0009] Figure 8 and Figure 9 These are partial top views and cross-sectional views of the receiving holes of the capacitor structure in semiconductor devices according to some embodiments of this disclosure.

[0010] Figure 10 This is a cross-sectional schematic diagram of the capacitor structure in a semiconductor device according to some embodiments of this disclosure.

[0011] List of symbols

[0012] 100: Substrate

[0013] 101: Isolation Structure

[0014] 102: insulating layer

[0015] 104: contact plug

[0016] 106: barrier structure

[0017] 1061, 1062: barrier layer

[0018] 107: metal contact line

[0019] 110: dielectric material stack

[0020] 112: first support layer

[0021] 113: first interlayer insulating layer

[0022] 1131, 1132: sub-insulating layer

[0023] 114: second support layer

[0024] 115: second interlayer insulating layer

[0025] 116: third support layer

[0026] 120: pattern transfer layer

[0027] 122: polysilicon layer

[0028] 124, 134, 154, 154': oxide layer

[0029] 126: sacrificial target layer

[0030] 126': patterned sacrificial target layer

[0031] 126A: array pattern

[0032] 1261: first hole

[0033] 1262: second hole

[0034] 126B: perimeter pattern

[0035] 130': first material stack

[0036] 132: nitride layer

[0037] 134': patterned oxide layer

[0038] 136: sacrificial layer

[0039] 136': patterned sacrificial layer

[0040] 1360: perforation

[0041] 1361, 1362: polysilicon strips

[0042] 138': oxide strip

[0043] 156: photoresist material layer

[0044] 156': patterned photoresist layer

[0045] SP2: spacer

[0046] 150: second material stack

[0047] 152: SOG layer

[0048] 152': SOG strip

[0049] 21: filler

[0050] 30: patterned mask layer

[0051] 30E: opening edge

[0052] 30E1, B1: first edge

[0053] 30E2, B2: second edge

[0054] 30E3, B3: third edge

[0055] 41: first accommodation hole

[0056] 42: second accommodation hole

[0057] 410: capacitance structure

[0058] 410S: storage capacitance

[0059] 410D: dummy capacitance

[0060] 412: lower electrode

[0061] 414: dielectric layer

[0062] 416: upper electrode

[0063] 112a, 132a, 136a, 154a, 21a, 211a, 212a, 213a: top surface

[0064] 42b, 114b: bottom surface

[0065] A1: array region

[0066] A2: peripheral region

[0067] D1, D2, Dc: direction

[0068] 9-9: section line

[0069] C1, C2: Critical dimensions

[0070] d1, d2: Depth

[0071] dp: Vertical distance

[0072] T: Thickness Detailed Implementation

[0073] The following provides different embodiments for implementing different components of the embodiments of the present invention. These are merely examples and are not intended to limit the invention. For example, if the description mentions that a first component is formed on top of a second component, unless specifically excluded, the first and second components may be in direct contact or not. Furthermore, for the purpose of simplicity and clarity, the embodiments of the present invention may use the same or similar element symbols for the same or similar elements in many examples. Moreover, the method for manufacturing the semiconductor device of the present invention can be applied, for example, to DRAM or any semiconductor device having a columnar capacitor structure. In addition, although the cross-sectional views of the embodiments only depict a portion of the array region and the peripheral regions of adjacent portions for illustrative purposes, this disclosure is not limited to the components shown.

[0074] Reference Figure 1 , Figures 2A-2D This illustrates a method for manufacturing the dielectric material stack 110 and the patterned sacrificial layer 136' of a semiconductor device. Figure 1 As shown, substrate 100 includes an array region A1 and a peripheral region A2 adjacent to array region A1. Substrate 100 may contain semiconductor materials, such as silicon, gallium arsenide, gallium nitride, germanium silicide, or combinations thereof. In one embodiment, substrate 100 is a silicon-on-insulator substrate. An isolation structure 101 may be formed in substrate 100 to isolate multiple active regions in substrate 100. In some embodiments, an isolation structure 101 may also be formed between array region A1 and peripheral region A2 in substrate 100. When the semiconductor device is DRAM, various components, such as word lines (not shown) and / or bit lines (not shown), may be formed in substrate 100.

[0075] In this embodiment, an insulating layer 102 may be formed on the substrate 100, and a contact plug 104, for example located in the array region A1, may be formed in the insulating layer 102. The contact plug 104 is used for electrical connection to the active region of the substrate 100. The insulating layer 102 may be a single-layer or multi-layer structure, for example, including an oxide layer and a nitride layer disposed sequentially. In one embodiment, a metal contact wire 107 located in the peripheral region A2 may be formed in the insulating layer 102.

[0076] In some embodiments, a barrier structure 106 may be formed above the contact plug 104. The bottom surface of the barrier structure 106 may completely cover the top surface of the contact plug 104 to prevent etching solution from subsequent processes from seeping into and damaging the contact plug 104 and components within the substrate 100. In this example, the barrier structure 106 includes a first barrier layer 1061 and a second barrier layer 1062. The first barrier layer 1061 covers the sidewalls and bottom surface of the second barrier layer 1062. The first barrier layer 1061 may include, for example, titanium, titanium nitride, tungsten nitride, tantalum, tantalum nitride, or a combination thereof. The second barrier layer 1062 may include, for example, tungsten, copper, other metals with good conductivity, or a combination thereof, to provide a lower resistance value.

[0077] Subsequently, a dielectric material stack 110 is formed over the substrate 100. The dielectric material stack 110 may include a first support layer 112, a first interlayer insulating layer 113, a second support layer 114, a second interlayer insulating layer 115, and a third support layer 116 sequentially formed to cover the insulating layer 102 and the barrier structure 106. By forming mutually separated first support layers 112, second support layers 114, and third support layers 116, the subsequently formed capacitor structure with a high aspect ratio is less prone to collapse. The first support layers 112, second support layers 114, and third support layers 116 may, for example, include silicon nitride. The first interlayer insulating layer 113 and the second interlayer insulating layer 115 may, for example, include an oxide material. The first interlayer insulating layer 113 may include a first insulator layer 1131 and a second insulator layer 1132. The second interlayer insulating layer 115 may include the same material as the second insulator layer 1132.

[0078] In subsequent processes, a capacitor structure will be formed above the contact plug 104 in array region A1. For example, a receiving via is formed in the dielectric material stack 110, and a capacitor structure is formed in the receiving via (e.g., Figure 10 (410). The capacitor structure can be electrically connected to the contact plug 104 via the barrier structure 106. The capacitor structure includes a storage capacitor located in the array region A1 and a dummy capacitor located at the edge of the array region A1. The following describes a method for manufacturing the receiving hole of the capacitor structure of some embodiments.

[0079] like Figure 1As shown, a pattern transfer layer 120, a first material stack 130', a second material stack 150, and a photoresist material layer 156 are sequentially formed above a dielectric material stack 110. The pattern transfer layer 120 may include a polysilicon layer 122, an oxide layer 124, and a sacrificial target layer 126 sequentially formed on a third support layer 116. The sacrificial target layer 126 may be, for example, diamond-like carbon, an amorphous carbon film, a highly selective transparent carbon-containing layer, or other suitable carbon-containing material. In this example, the sacrificial target layer 126 is a spin-on-carbon (SOC) layer. The first material stack 130' may include a nitride layer 132, an oxide layer 134, a sacrificial layer 136, and a plurality of oxide strips 138' sequentially formed on the pattern transfer layer 120. The material of the sacrificial layer 136 includes, for example, polysilicon. The thickness of each material layer in the first material stack 130' is, for example (but not limited to), less than the thickness of each material layer in the pattern transfer layer 120. These oxide strips 138' extending along the first direction D1 can be formed by a self-aligned double patterning (SADP) process. The second material stack 150 includes, for example, a spin-on-glass (SOG) layer 152 and an oxide layer 154 formed sequentially.

[0080] Next, you can proceed as follows: Figures 2A-2D The SADP process is shown. (As shown in the image) Figure 2A As shown, a photoresist material layer 156 is subjected to a photolithography patterning process to form a patterned photoresist layer 156' over an oxide layer 154. The patterned photoresist layer 156' includes a plurality of photoresist strips extending along the direction Dc and spaced apart, and the photoresist strips expose the top surface 154a of the oxide layer 154. Then, referring to... Figure 2B Spacers SP2 are formed on the two opposite sidewalls of each photoresist strip (serving as a mandrel) in the patterned photoresist layer 156'. Then, the patterned photoresist layer 156' is removed. Next, refer to... Figure 2C Using spacer SP2 as an etching mask, the mask pattern is sequentially transferred to the oxide layer 154 and SOG layer 152 below to form oxide layer 154' and SOG strip 152' on oxide strip 138', and expose the top surface 136a of sacrificial layer 136.

[0081] Then, refer to Figure 2Doxide layer 154', SOG strips 152', and oxide strips 138' as etch masks, the underlying sacrificial layer 136 and oxide layer 134 are etched to form a patterned sacrificial layer 136' and a patterned oxide layer 134', with the nitride layer 132 as an etch stop. As a result, the patterned sacrificial layer 136' and the underlying patterned oxide layer 134' expose the top surface 132a of the nitride layer 132.

[0082] Since the patterned oxide layer 134' has the same pattern as the patterned sacrificial layer 136', in the following description and figures, the patterned oxide layer 134' can be omitted and the patterned sacrificial layer 136' can represent itself and the underlying patterned oxide layer 134' if any. In addition, Figures 2A-7A only a portion of the semiconductor device is depicted, the omitted layers and components can be referred to Figure 1 and the above related description. Figures 3B-7B is a top view of the semiconductor device of Figures 3A-7A .

[0083] Referring to Figure 3A , Figure 3B only a portion of the array region Al (as indicated by the dashed line) and a portion of the peripheral region A2 are shown. Among others, Figure 3A is a partial enlarged view of the semiconductor device made according to the steps of Figure 2D In some embodiments, the patterned sacrificial layer 136' includes polysilicon strips 1361 extending along the first direction Dl and polysilicon strips 1362 extending along the direction Dc. These interleaved polysilicon strips 1361, 1362 define a plurality of through-holes 1360. The through-holes 1360 expose the top surface 132a of the nitride layer 132.

[0084] After that, referring to Figure 4A , Figure 4B a fill 21 is formed in the through-holes 1360. The fill 21 fills the through-holes 1360 and contacts the top surface 132a of the nitride layer 132. Further, the fill 21 is different in material from the patterned sacrificial layer 136' and the nitride layer 132. The fill 21 can include an oxide, such as silicon oxide. The top surface 21a of the fill 21 can be substantially coplanar with the top surface 136a of the patterned sacrificial layer 136'.

[0085] After that, according to some embodiments of the disclosure, referring to Figure 5A , Figure 5BA patterned mask layer 30 is formed on the patterned sacrificial layer 136' and the fillers 21. The patterned mask layer 30 exposes the top surfaces 21a of the patterned sacrificial layer 136' and the fillers 21 in the array region Al (corresponding to the locations of the accommodation holes of the dummy capacitors), and covers the patterned sacrificial layer 136' and the fillers 21 in the peripheral region A2.

[0086] Specifically, as shown in FIG. 6, the opening edge 30E of the patterned mask layer 30 includes a first edge 30E1, a second edge 30E2, and a third edge 30E3 connecting the first edge 30E1 and the second edge 30E2. The first edge 30E1 is adjacent to the first edge B1 of the array region Al, for example, located outside the polysilicon strip 1361 closest to the first edge B1. The second edge 30E2 is adjacent to the second edge B2 of the array region Al, for example, located outside the polysilicon strip 1361 closest to the second edge B2. The third edge 30E3 is adjacent to the third edge B3 of the array region Al, for example, located outside the polysilicon strip 1361 closest to the third edge B3. Figure 5A 、 Figure 5B According to some embodiments, the patterned mask layer 30 is formed by a photolithography process. The photomask used in the photolithography process is designed to have a pattern corresponding to the patterned mask layer 30 shown in FIG. 6.

[0087] According to some embodiments, the patterned mask layer 30 is formed by a photolithography process. The photomask used in the photolithography process is designed to have a pattern corresponding to the patterned mask layer 30 shown in FIG. 6. Figure 8 According to some embodiments, the patterned mask layer 30 is formed by a photolithography process. The photomask used in the photolithography process is designed to have a pattern corresponding to the patterned mask layer 30 shown in FIG. 6.

[0088] After that, referring to FIG. 7, the fillers 21 not covered by the patterned mask layer 30 are removed, while the fillers 21 covered by the patterned mask layer 30 are left. The exposed fillers 21 can be removed by a wet etching process without substantially affecting the patterned sacrificial layer 136' and the nitride layer 132. Figure 6A 、 Figure 6B After that, referring to FIG. 7, the fillers 21 not covered by the patterned mask layer 30 are removed, while the fillers 21 covered by the patterned mask layer 30 are left. The exposed fillers 21 can be removed by a wet etching process without substantially affecting the patterned sacrificial layer 136' and the nitride layer 132.

[0089] After that, referring to FIG. 7, the fillers 21 not covered by the patterned mask layer 30 are removed, while the fillers 21 covered by the patterned mask layer 30 are left. The exposed fillers 21 can be removed by a wet etching process without substantially affecting the patterned sacrificial layer 136' and the nitride layer 132. Figure 7A 、 Figure 7BThe pattern is transferred to the underlying sacrificial target layer 126 with the combination of the patterned mask layer 30 and the sacrificial layer 136' as a mask to form a patterned sacrificial target layer 126'. The patterned sacrificial target layer 126' includes an array pattern 126A and a perimeter pattern 126B corresponding to the array region Al and the perimeter region A2, respectively. Specifically, the array pattern 126A includes a plurality of first holes 1261 and a plurality of second holes 1262 surrounding the first holes 1261. Further, the first holes 1261 correspond to locations of the storage capacitor accommodating holes 41 (indicated by Figure 8 ) to be formed in the dielectric material stack 110 later. The second holes 1262 correspond to locations of the dummy capacitor accommodating holes 42 (indicated by Figure 8 ) to be formed in the dielectric material stack 110 later. The second holes 1262 can be adjacent to or abut the perimeter pattern 126B. In the present embodiment, the second holes 1262 are openings having the same or similar size, and the second holes 1262 are smaller than the first holes 1261. The size can refer to shape and / or area and / or width.

[0090] Then, as shown in Figure 8 and Figure 9 , the array pattern 126A and the perimeter pattern 126B of the patterned sacrificial target layer 126' are transferred to the underlying dielectric material stack 110 to form accommodating holes of the capacitor structures (e.g., including the storage capacitors and the dummy capacitors). In the present embodiment, the array pattern 126A and the perimeter pattern 126B of the patterned sacrificial target layer 126' are sequentially transferred to the oxide layer 124, the polysilicon layer 122, and the dielectric material stack 110. Figure 9 is a cross-sectional view of the semiconductor device at an intermediate manufacturing stage taken along the section line 9-9 in Figure 8 . In the present example, the accommodating holes of the capacitor structures formed in the dielectric material stack 110 include a plurality of first accommodating holes 41 in the array region Al and a plurality of second accommodating holes 42 surrounding the first accommodating holes 41. The first accommodating holes 41 and the second accommodating holes 42 correspond to the first holes 1261 and the second holes 1262 of the patterned sacrificial target layer 126', respectively.

[0091] The second accommodating holes 42 can be smaller than the first accommodating holes 41. The second accommodating holes 42 are openings having the same or similar size.

[0092] According to some examples, as shown in Figure 9As shown, the critical dimension C2 of the second accommodation holes 42 at the top surface of the dielectric material stack 110 has a maximum value that is not more than one-tenth of the difference from the minimum value. Alternatively, the difference between the maximum and minimum values of the critical dimension C2 is less than or equal to 10 nm. Alternatively, the uniformity (U% = (maximum - minimum) / 2 * average) of the critical dimension C2 is between 0.5-1 nm.

[0093] Further, the larger the holes of the patterned sacrificial target layer 126', the larger and deeper the openings of the accommodation holes of the subsequently formed capacitor structures. According to the fabrication method of the embodiments, by adjusting the size of the second holes 1262 of the patterned sacrificial target layer 126', the opening and depth of the second accommodation holes 42 can be controlled so that the second accommodation holes 42 reach a predetermined depth in the dielectric material stack 110 that can be well supported.

[0094] In particular, according to some embodiments, the opening size (e.g., critical dimension C2) of the second accommodation holes 42 is smaller than the opening size (e.g., critical dimension C1) of the first accommodation holes 41, and the depth d2 of the second accommodation holes 42 is smaller than the depth d1 of the first accommodation holes 41, as shown. Figure 9 For example, the critical dimension C2 is greater than 1 / 3 of the critical dimension C1 and smaller than the critical dimension C1. The bottom of the second accommodation holes 42 can stop at a position that can be confined by the upper support layer (e.g., the third support layer 116) and the middle support layer (e.g., the second support layer 114).

[0095] In a preferred embodiment, the second accommodation holes 42 can extend through the third support layer 116, the second interlayer dielectric layer 115, and the second support layer 114, and stop in the first interlayer dielectric layer 113. By the fabrication method of the present disclosure, the opening size of the second accommodation holes 42 can be adjusted to control the bottom surface 42b of the second accommodation holes 42 to stop in the first interlayer dielectric layer 113 without extending too much beyond the bottom surface 114b of the second support layer 114. Thus, the distance between the bottom surface 42b of the second accommodation holes 42 and the bottom surface 114b of the second support layer 114 can be smaller than the distance between the bottom surface 42b of the second accommodation holes 42 and the top surface 112a of the first support layer 112.

[0096] In yet another preferred embodiment, the ratio of the vertical distance dp between the bottom surface 42b of each second accommodation hole 42 and the bottom surface 114b of the second support layer 114 to the thickness T of the first interlayer dielectric layer 113 (i.e., the distance between the first support layer 112 and the second support layer 114) is in the range of about 0.01 to about 0.2. In this way, by the confining and supporting effect of the second support layer 114 and the third support layer 116 on the second accommodation holes 42, the second accommodation holes 42 can be prevented from extending obliquely towards the adjacent first accommodation holes 41.

[0097] Furthermore, the second accommodation holes 42 formed according to some embodiments of the present disclosure can have substantially the same or close depth d2. For example, the vertical distance dp from the bottom surface 42b of any two of the second accommodation holes 42 to the bottom surface 114b of the second support layer 114 can have a difference of no more than 30 nm. That is, the second accommodation holes 42 formed according to some embodiments of the present disclosure can have uniform size and depth, which can improve the yield of semiconductor devices.

[0098] Thereafter, referring to Figure 10 , a plurality of capacitor structures 410 are formed. The capacitor structures 410 include storage capacitors 410S corresponding to the first accommodation holes 41 and dummy capacitors 410D corresponding to the second accommodation holes 42. Thus, the storage capacitors 410S are located in the array region Al, and the dummy capacitors 410D are located at the edge of the array region Al. The storage capacitors 410S have a depth dl, and the dummy capacitors 410D have a depth d2. The storage capacitors 410S and the dummy capacitors 410D can have critical dimensions C1 and C2, respectively. The storage capacitors 410S and the dummy capacitors 410D each include a lower electrode 412, a dielectric layer 414, and an upper electrode 416. The lower electrode 412 has, for example, a U-shaped cross section and is in contact with the barrier structure 106. The lower electrode 412 includes, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or a combination thereof. The lower electrode 412 can include the same material as the first barrier layer 1061, such as titanium nitride. The dielectric layer 414 between the lower electrode 412 and the upper electrode 416 includes a dielectric material having a high dielectric constant (e.g., greater than or equal to 3.9). The upper electrode 416 includes a conductive material having good conductivity, such as a silicon-germanium containing conductive material or a combination thereof. After the capacitor structures 410 are formed, other known processes can be performed, such as forming interconnection structures of the peripheral region A2, to complete other components required by the semiconductor device.

[0099] In summary, according to the manufacturing method of semiconductor devices of some embodiments of the present disclosure, the housing holes of the dummy capacitors located at the edge of the array region have a uniform or close size at the top surface of the dielectric material stack and a uniform or close depth in the dielectric material stack. In this way, the dummy capacitors also have a uniform or close critical dimension and a uniform or close depth. Furthermore, according to the manufacturing method of the present disclosure, by adjusting the size of the corresponding holes (e.g., the second holes 1262) of the patterned sacrificial target layer, the opening and depth of the housing holes of the dummy capacitors can be controlled, so that the housing holes have a predetermined opening size and reach a predetermined depth in the dielectric material stack and can be well supported. The smaller the holes of the housing holes of the dummy capacitors, the shallower the depth of the subsequently formed housing holes. According to the present disclosure, the depth of the housing holes of the dummy capacitors is less than the depth of the housing holes of the storage capacitors. The bottom of the housing holes of the dummy capacitors can stop below and close to the intermediate support layer (e.g., the second support layer 114), so that the housing holes are limited and well supported by the top support layer and the intermediate support layer, and are not easy to collapse, bend or skew in the dielectric material stack. Therefore, the present disclosure can avoid the problem that the housing holes of the dummy capacitors are skewed by stress and make improper contact with adjacent housing holes (e.g., the housing holes of the storage capacitors), thereby avoiding short circuit with subsequently formed capacitor structures (e.g., the storage capacitors).

[0100] The present disclosure is suitable for manufacturing miniaturized semiconductor devices to increase the total number of dies on a wafer. Therefore, the present disclosure can reduce the production cost and energy consumption of manufacturing individual ICs, and reduce the production energy consumption of subsequent packaging, thereby reducing carbon emissions in the semiconductor device production process. In addition, since the yield of the semiconductor devices of the present disclosure is improved, the present disclosure provides a green semiconductor technology.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A dielectric material is stacked on top of a substrate, the substrate having an array region and a peripheral region; Multiple accommodating holes for capacitor structures are formed in the dielectric material stack; and The capacitor structure is formed in the receiving hole, and the capacitor structure includes: Multiple storage capacitors are located in the array region, wherein each of the storage capacitors has a first critical dimension at a top surface of the dielectric material stack; and A plurality of dummy capacitors surround the storage capacitor, wherein each of the dummy capacitors has a second critical dimension at the top surface of the dielectric material stack, wherein the second critical dimension is smaller than the first critical dimension and larger than 1 / 3 of the first critical dimension.

2. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, Including: A patterned sacrificial layer containing multiple perforations is formed over the dielectric material stack; Multiple fillers are formed in the perforations, wherein the material of the fillers is different from the material of the patterned sacrificial layer; A patterned mask layer is formed on the patterned sacrificial layer and the filler, and the patterned mask layer exposes the patterned sacrificial layer and the filler located in the array region, and covers the patterned sacrificial layer and the filler located in the peripheral region; Remove the filler exposed by the patterned mask layer; and After removing the filler exposed by the patterned mask layer, the dielectric material stack is etched to transfer the combined pattern of the patterned mask layer and the patterned sacrificial layer into the dielectric material stack, thereby forming the receiving hole of the capacitor structure corresponding to the via in the dielectric material stack.

3. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, Including: A sacrificial target layer is formed between the patterned sacrificial layer and the dielectric material stack; and Using the patterned mask layer and the patterned sacrificial layer as a mask, the sacrificial target layer is etched to form a patterned sacrificial target layer, wherein the patterned sacrificial target layer includes an array pattern and a peripheral pattern corresponding to the array region and the peripheral region, respectively. The combined pattern of the patterned mask layer and the patterned sacrificial layer corresponds to the array pattern and the peripheral pattern.

4. The method for manufacturing a semiconductor device as claimed in claim 2, characterized in that, The top surface of the filler is coplanar with the top surface of the patterned sacrificial layer.

5. The method for manufacturing a semiconductor device as claimed in claim 3, characterized in that, Including: A polycrystalline silicon layer is formed on top of the dielectric material stack; An oxide layer is formed between the polysilicon layer and the sacrificial target layer; and A nitride layer is formed on the sacrificial target layer, wherein the nitride and the sacrificial target layer comprise different materials. The perforation exposes a top surface of the nitride layer. Specifically, the nitride layer, the sacrificial target layer, the oxide layer, the polysilicon layer, and the dielectric material stack are etched sequentially according to the mask.

6. The method for manufacturing a semiconductor device as claimed in claim 5, characterized in that, The material of the filler is different from the materials of the nitride layer and the sacrificial target layer.

7. The method for manufacturing a semiconductor device as claimed in claim 6, characterized in that, The filler comprises an oxide, and the patterned sacrificial layer comprises a polycrystalline silicon.

8. The method for manufacturing a semiconductor device as claimed in claim 2, characterized in that, The opening edge of the patterned mask layer is adjacent to the edge of the array region.

9. The method for manufacturing a semiconductor device as claimed in claim 3, characterized in that, The array pattern of the patterned sacrificial target layer includes: Multiple first holes correspond to the locations of the storage capacitors in the capacitor structure subsequently formed in the dielectric material stack; and Multiple second holes correspond to the positions of dummy capacitors in the capacitor structure subsequently formed in the dielectric material stack, and the second holes are adjacent to the peripheral pattern of the patterned sacrificial target layer, wherein each second hole is smaller than each first hole.

10. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The accommodating hole of the capacitor structure includes: Multiple first receiving holes are located in the array region, and the storage capacitor of the capacitor structure is disposed in the first receiving holes; and A plurality of second receiving holes surround the first receiving hole, and the dummy capacitor of the capacitor structure is disposed in the second receiving holes, wherein each second receiving hole is smaller than each first receiving hole. Each of the second receiving holes has a critical size, wherein the difference between the maximum and minimum values ​​of the critical size does not exceed one-tenth of the average value of the critical size.

11. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The accommodating hole of the capacitor structure includes: Multiple first receiving holes are located in the array region, and the storage capacitor of the capacitor structure is disposed in the first receiving holes; and A plurality of second receiving holes surround the first receiving hole, and the dummy capacitor of the capacitor structure is disposed in the second receiving holes, wherein each second receiving hole is smaller than each first receiving hole. The dielectric material stack includes a first support layer, a second support layer, and a third support layer, wherein the second support layer is located between the first support layer and the third support layer. Each of the second receiving holes passes through the third support layer and the second support layer, extending beyond a bottom surface of the second support layer, and does not contact the first support layer. Each of the first receiving holes passes through the third support layer, the second support layer and the first support layer, and contacts the contact plug below the dielectric material stack.

12. The method of manufacturing a semiconductor device as claimed in claim 11, characterized in that, The ratio of a vertical distance from the bottom surface of each of the second receiving holes to the bottom surface of the second support layer to the distance from the first support layer to the second support layer is in the range of 0.01 to 0.

2.

13. A semiconductor device, characterized in that, include: A substrate having an array region and a peripheral region; A dielectric material stack is located above the substrate; as well as Multiple capacitor structures are located within the dielectric material stack, and the capacitor structures include: Multiple storage capacitors are located in the array region, wherein each of the storage capacitors has a first critical dimension at a top surface of the dielectric material stack; and A plurality of dummy capacitors surround the storage capacitor, wherein each of the dummy capacitors has a second critical dimension at the top surface of the dielectric material stack, wherein the second critical dimension is smaller than the first critical dimension and larger than 1 / 3 of the first critical dimension.

14. The semiconductor device as claimed in claim 13, characterized in that, The difference between the maximum and minimum values ​​of the second critical dimension of the dummy capacitor does not exceed one-tenth of the average value of the second critical dimension.

15. The semiconductor device as claimed in claim 13, characterized in that, The storage capacitor has a first depth in the dielectric material stack, and the dummy capacitor has a second depth in the dielectric material stack, the second depth being less than the first depth.

16. The semiconductor device as claimed in claim 13, characterized in that, The dielectric material stack includes a first support layer, a second support layer, and a third support layer. The second support layer is located between the first support layer and the third support layer. Each of the dummy capacitors passes through the third support layer and the second support layer and extends beyond a bottom surface of the second support layer without contacting the first support layer. Each of the storage capacitors passes through the third support layer, the second support layer, and the first support layer and contacts a contact plug below the dielectric material stack.

17. The semiconductor device as claimed in claim 16, characterized in that, The distance between the bottom surface of each of the dummy capacitors and the bottom surface of the second support layer is less than the distance between the bottom surface of each of the dummy capacitors and the top surface of the first support layer.

18. The semiconductor device as claimed in claim 16, characterized in that, The ratio of a vertical distance from the bottom surface of each of the dummy capacitors to the bottom surface of the second support layer to the distance from the first support layer to the second support layer is in the range of 0.01 to 0.

2.

19. The semiconductor device as claimed in claim 16, characterized in that, The difference in the vertical distance from the bottom surface of any two of the dummy capacitors to the bottom surface of the second support layer does not exceed 30 nm.

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