Integrated device and preparation method of integrated device
By setting capacitor structures on the bottom and sidewalls of the substrate groove and adjusting their length to change the capacitance value, the problem of large space occupied by capacitors is solved, and the integration density of integrated devices is improved.
Patent Information
- Application Number
- CN202411096517.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2026-02-13
AI Technical Summary
In existing technologies, when the capacitance value of the capacitor in a passive filter is large, the area of the metal plate increases, resulting in a larger space occupation and a reduction in the integration density of the passive filter.
By continuously setting the first capacitor structure on the bottom and sidewall of the substrate groove, the capacitance value can be changed by adjusting its length on the sidewall, thereby reducing the space occupied and improving the integration.
While maintaining the capacitance value, the space occupied by the capacitor structure was reduced, improving the integration level and space utilization efficiency of the integrated device.
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Figure CN121531783A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure generally relates to the technical field of radio frequency devices, and particularly relates to an integrated device and a method for manufacturing an integrated device. BACKGROUND
[0002] At present, integrated passive filters as an important part of passive microwave devices are gradually widely used in radio frequency communication systems. In the prior art, the capacitor in the passive filter is usually composed of two layers of metal electrodes and an insulating layer in the metal electrodes (i.e., the capacitor is a Metal-Insulator-Metal structure, abbreviated as MIM structure). Specifically, the capacitor can control its capacitance value by controlling the area of the upper and lower metal electrode plates.
[0003] However, based on the above MIM structure, when the capacitor has a larger capacitance value, the area of the capacitor metal plate also increases accordingly, which leads to an increase in the space ratio of the capacitor arranged on the substrate, thereby reducing the integration of the internal devices of the passive filter. SUMMARY
[0004] In view of the above defects or deficiencies in the prior art, it is desirable to provide an integrated device and a method for manufacturing an integrated device, which can continuously arrange a first capacitor structure on the bottom and sidewall of a groove of a substrate, so as to change the capacitance value of the first capacitor structure by adjusting the length of the first capacitor structure on the sidewall of the groove, thereby reducing the occupied space of the first capacitor structure while ensuring the normal capacitance value of the first capacitor structure, and improving the integration of the integrated device.
[0005] According to a first aspect of the present application, an integrated device is provided, comprising: a substrate, and at least one first capacitor structure and at least one first inductor structure arranged on a first side of the substrate, wherein the first side is provided with a groove;
[0006] The first capacitor structure is continuously arranged on the bottom and sidewall of the groove; the capacitance value of the first capacitor structure is positively correlated with the length of the first capacitor structure on the sidewall of the groove.
[0007] According to a second aspect of the present application, a method for manufacturing an integrated device is provided, the method comprising:
[0008] Based on a preset capacitance value of the first capacitor structure, etching the substrate to form a groove;
[0009] Manufacturing the first capacitor structure on the bottom and sidewall of the groove, and manufacturing the first inductor structure on the side of the substrate provided with the first capacitor structure, to form an integrated device.
[0010] Compared with the capacitor structure arranged in the substrate stack in the prior art, the integrated device and the preparation method of the integrated device provided by the embodiment of the application can improve the integration of the integrated device by arranging the first capacitor structure in the groove on one side of the substrate, and can reduce the space ratio of the first capacitor structure in the integrated device to a certain extent by arranging the first capacitor structure on the bottom and the sidewall of the groove, thereby further improving the integration of the integrated device.
[0011] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS
[0012] Other features, objects, and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments thereof when read in connection with the following drawings:
[0013] Figure 1 A schematic diagram of a conventional passive filter 10 of the application;
[0014] Figure 2 A cross-sectional schematic diagram of an integrated device 20 provided by an embodiment of the application;
[0015] Figure 3 A cross-sectional schematic diagram of an integrated device 20 provided by an embodiment of the application;
[0016] Figure 4 A cross-sectional schematic diagram of an integrated device 20 provided by an embodiment of the application;
[0017] Figure 5 A top view schematic diagram of an integrated device 20 provided by an embodiment of the application;
[0018] Figure 6 A cross-sectional schematic diagram of an integrated device 20 provided by an embodiment of the application;
[0019] Figure 7 A cross-sectional schematic diagram of an integrated device 20 provided by an embodiment of the application;
[0020] Figure 8 A top view schematic diagram of an integrated device 20 provided by an embodiment of the application;
[0021] Figure 9 An equivalent circuit diagram of an integrated device 20 provided by an embodiment of the application;
[0022] Figure 10 A cross-sectional schematic diagram of an integrated device 20 provided by an embodiment of the application;
[0023] Figure 11 Fig. 3 is a top view of the integrated device 20 according to an embodiment of the present application;
[0024] Figure 12 Fig. 7 is a cross-sectional view of the integrated device 20 according to an embodiment of the present application;
[0025] Figure 13 Fig. 8 is a cross-sectional view of the integrated device 20 according to an embodiment of the present application;
[0026] Figure 14 Fig. 9 is a cross-sectional view of the integrated device 20 according to an embodiment of the present application;
[0027] Figure 15 Fig. 2 is a second equivalent circuit diagram of the integrated device 20 according to an embodiment of the present application;
[0028] Figure 16 Fig. 10 is a flow chart of a method for manufacturing the integrated device 20 according to an embodiment of the present application;
[0029] Figure 17 Fig. 11 is a flow chart of a method for manufacturing the first capacitor structure 22 and the first inductor structure 23 according to an embodiment of the present application;
[0030] Figure 18 Fig. 12 is a flow chart of another method for manufacturing the first capacitor structure 22 and the first inductor structure 23 according to an embodiment of the present application;
[0031] In the above figures:
[0032] 10 - passive filter; 11 - substrate; 12 - capacitor; 13 - inductor; 20 - integrated device; 21 - substrate; 22 - first capacitor structure; 23 - first inductor structure; 24 - recess; 221 - first metal layer; 222 - first dielectric layer; 223 - second metal layer; 25 - via; 231 - first conductive line layer; 232 - second dielectric layer; 233 - second conductive line layer; 2321 - first via hole; 701 - via hole; 901 - TGV via hole; 26 - second via hole; 27 - protruding structure; 28 - third dielectric layer; 29 - second capacitor structure; 210 - second inductor structure. DETAILED DESCRIPTION
[0033] The present application will be further described by examples with reference to the drawings. It is to be understood that the following examples are illustrative of specific embodiments of the application. Therefore, the application is not to be construed as being limited to the specific embodiments disclosed herein. In addition, it is to be understood that the terminology used herein is for the purpose of describing the particular embodiments only and is not intended to limit the scope of the application.
[0034] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments. In addition, the term "and / or" in this paper is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. The terms "first" and "second" in the specification and claims of the embodiments of the present application are used to distinguish different objects, not to describe a specific order of the objects.
[0035] At present, integrated passive filters as an important part of passive microwave devices are gradually widely used in radio frequency communication systems. For example, Figure 1 is a schematic diagram of a conventional passive filter 10 of the present application, as Figure 1 shown, the passive filter 10 includes a substrate 11, a capacitor 12 and an inductor 13; wherein the passive filter 10 may, for example, be an LC filter. Specifically, the capacitor 12 in the passive filter 10 is usually composed of two metal electrodes and an insulating layer in the metal electrode (i.e., the capacitor is a Metal-Insulator-Metal structure, abbreviated as MIM structure), so as to control the capacitance value of itself by controlling the area of the upper and lower metal electrode plates.
[0036] However, based on the MIM structure of the capacitor 12 as Figure 1 shown, when the capacitor 12 has a larger capacitance value, the area of the metal plate of the capacitor 12 also increases accordingly, which leads to an increase in the space ratio of the capacitor 12 arranged on the substrate 11, thereby reducing the integration of the passive filter 10.
[0037] Based on this, the present application proposes an integrated device, which can continuously arrange the first capacitor structure on the bottom and sidewall of the groove of the substrate, so as to change the capacitance value of the first capacitor structure by adjusting the length of the first capacitor structure on the sidewall of the groove, thereby reducing the occupied space of the first capacitor structure under the condition of ensuring the normal capacitance value of the first capacitor structure, and improving the integration of the integrated device.
[0038] In an embodiment of the present application, an integrated device 20 is provided. Figure 2 is one of the cross-sectional schematic diagrams of the integrated device 20 provided by the embodiments of the present application, as Figure 2 shown, the integrated device 20 includes a substrate 21, at least one first capacitor structure 22 and at least one first inductor structure 23 arranged on the first side of the substrate 21, wherein the first side is provided with a groove 24. Specifically, the first capacitor structure 23 is continuously arranged on the bottom and sidewall of the groove 24, and the capacitance value of the first capacitor structure 23 is positively correlated with the length of the first capacitor structure 23 on the sidewall of the groove 24.
[0039] In the embodiments of the present application, different types of integrated devices can be formed by connecting the first capacitor structure 22 and the first inductor structure 23 in series or in parallel on the substrate 21 to achieve different filtering functions.
[0040] For example, when the first capacitor structure 22 and the first inductor structure 23 are connected in series, the integrated device 20 can be a high-pass filter or a low-pass filter. Specifically, when one end of the first capacitor structure 22 is grounded and one end of the first inductor structure 23 is connected to the signal input end, the integrated device 20 is a high-pass filter that filters out low-frequency signals and retains high-frequency signals; when one end of the first inductor structure 23 is grounded and one end of the first capacitor structure 22 is connected to the signal input end, the integrated device 20 is a low-pass filter that filters out high-frequency signals and retains low-frequency signals.
[0041] For example, when the first capacitor structure 22 and the first inductor structure 23 are connected in parallel, one end of the first inductor structure 23 is connected to the signal input end and one end of the first capacitor structure 22 is connected to the signal output end, the integrated device 20 can be a band-pass filter or a band-stop filter.
[0042] It should be noted that the number of first capacitor structures 22 and first inductor structures 23 in the integrated device 20 is not limited in the embodiments of the present application.
[0043] For example, the substrate 21, as the substrate of the integrated device 20, can have the characteristics of low expansion coefficient and high surface flatness, and the material thereof can be glass, for example.
[0044] In a possible implementation, any side of the substrate 21 can be determined as the first side, and a groove 24 can be formed on the first side of the substrate 21 to continuously arrange the first capacitor structure 22 on the bottom and the sidewall of the groove 24.
[0045] Compared with the capacitor structure laid flat on one side of the substrate in the prior art, the first capacitor structure 22 is arranged continuously on the bottom and the sidewall of the groove 24 in the embodiments of the present application, so that the first capacitor structure 22 is three-dimensional, thereby reducing the occupied space of the first capacitor structure 22.
[0046] For example, the depth of the groove 24 can be determined according to the capacitance value of the first capacitor structure 22. It should be noted that, in order to improve the integration of the integrated device 20, the first capacitor structure 22 needs to be arranged completely in the groove 24, that is, the depth of the groove 24 is greater than or equal to the length of the first capacitor structure 22 on the sidewall of the groove 24; wherein the length of the first capacitor structure 22 on the sidewall of the groove 24 is specifically the length of the first capacitor structure 22 in the depth direction of the groove 24.
[0047] For example, the capacitance of the first capacitance structure 22 is positively correlated with the length of the first capacitance structure 22 on the sidewall of the recess 24, and thus the capacitance of the first capacitance structure 22 can be changed by adjusting the length of the first capacitance structure 22 on the sidewall of the recess 24.
[0048] Specifically, the length of the first capacitance structure 22 on each sidewall of the recess 24 can be the same or different. For example, Figure 3 is a second cross-sectional view of the integrated device 20 provided by an embodiment of the present application, as shown in Figure 3 When the recess 24 is a regular cube, the length of the first capacitance structure 22 on each sidewall of the recess 24 is the same, i.e., the first capacitance structure 22 is a regular cube consistent with the shape of the recess 24.
[0049] It should be noted that when the first capacitance structure 22 is a regular cube, and the ratio of the length of the first capacitance structure 22 along the depth direction of the recess 24 to the length of the capacitance structure 22 along the vertical direction of the depth direction of the recess 24 (i.e., the width of the first capacitance structure 22) is N, the capacitance of the first capacitance structure 22 is increased by about (2N+1) times compared with the capacitance of a planar capacitance structure with the same cross-sectional area. 2
[0050] For example, the length of the first capacitance structure 22 on at least one sidewall of the recess 24 can be the same as the depth of the recess 24. Specifically, a preset length of the first capacitance structure 22 on the sidewall of the recess 24 can be determined based on the specific capacitance of the first capacitance structure 22, and then the depth of the recess 24 is set based on the preset length. For example, Figure 4 is a third cross-sectional view of the integrated device 20 provided by an embodiment of the present application, as shown in Figure 4 The length of the first capacitance structure 22 on the sidewall of the recess 24 is the same as the depth of the recess 24.
[0051] It should be noted that since the first capacitance structure 22 is a stacked structure, i.e., the first capacitance structure 22 is specifically distributed in multiple layers, the length of the first capacitance structure 22 on the sidewall of the recess 24 described above can be the length of the overlapping part of all layers of the first capacitance structure 22 distributed on the sidewall of the recess 24.
[0052] For example, when one first capacitance structure 22 is arranged on one side of the substrate 21, the orthographic projection shape of the first capacitance structure 22 (i.e., the arrangement shape of the first capacitance structure 22 on the bottom of the recess 24) can be contained in the orthographic projection shape of the recess 24 (i.e., the bottom shape of the recess 24).
[0053] Specifically, the arrangement shape of the first capacitance structure 22 on the bottom of the recess 24 can be the same as or different from the bottom shape of the recess 24. For example, Figure 5 is one of top view schematic diagrams of the integrated device 20 provided by the embodiments of the present application, as shown in Figure 5 It is shown that the orthographic projection shape of the first capacitor structure 22 is consistent with the orthographic projection shape of the groove 24.
[0054] It is to be noted that when the setting shape of the first capacitor structure 22 at the bottom of the groove 24 is contained in the bottom shape of the groove 24, the first capacitor structure 22 set at the bottom and the sidewall of the groove 24 still needs to be continuously set.
[0055] Exemplarily, the orthographic projection shape of the groove 24 is contained in the orthographic projection shape of the first capacitor structure 22.
[0056] Specifically, when one side of the substrate 21 is provided with at least one first capacitor structure 22, in order to ensure the normal connection of the first capacitor structure 22 with other first capacitor structures 22 or with other structures (for example, TGV structures) on the substrate 21, the first capacitor structure 22 can extend to other first capacitor structures 22 or other structures on the substrate 21, so that the orthographic projection shape of the groove 24 can be contained in the orthographic projection shape of the first capacitor structure 22.
[0057] It is to be noted that the orthographic projection shape of the first capacitor structure 22 can also be the orthographic projection shape of the overlapping part between all layers inside the first capacitor structure 22, as the same as the setting length of the first capacitor structure 22 on the sidewall of the groove 24.
[0058] In a possible implementation manner, the first capacitor structure 22 can include a first metal layer 221, a first dielectric layer 222 and a second metal layer 223 which are arranged in a stack. The first metal layer 221 and the second metal layer 223 can be formed by metal copper or metal aluminum wiring; the first dielectric layer 222 can be a silicon nitride (i.e., SiNx) layer or a hafnium oxide (i.e., HfO2) layer; that is, the first metal layer 221, the first dielectric layer 222 and the second metal layer 223 can correspond to the lower electrode metal wiring, the dielectric layer and the upper electrode metal wiring of the capacitor structure respectively.
[0059] Exemplarily, Figure 6 is a fourth cross-sectional schematic diagram of the integrated device 20 provided by the embodiments of the present application, as shown in Figure 6 It is shown that the first metal layer 221 is continuously set at the bottom and the sidewall of the groove 24 away from the substrate 21, the first dielectric layer 222 is correspondingly set at the side of the first metal layer 221 away from the bottom and the sidewall of the groove 24, and the second metal layer 223 is correspondingly set at the side of the first dielectric layer 222 away from the first metal layer 221.
[0060] Specifically, there is an overlapping part between the first metal layer 221, the first dielectric layer 222 and the second metal layer 223; for example, the first metal layer 221, the first dielectric layer 222 and the second metal layer 223 have the same area and shape.
[0061] Compared with the capacitor structure arranged in the substrate stack in the prior art, the integrated device 20 provided by the embodiments of the present application has the following advantages. On the one hand, by arranging the recess 24 on one side of the substrate 21, the first capacitor structure 22 can be arranged in the recess 23, thereby improving the integration of the integrated device 20. On the other hand, by arranging the first capacitor structure 22 on the bottom and the sidewall of the recess 24, the first capacitor structure 22 is three-dimensional, thereby reducing the space ratio of the first capacitor structure 22 in the integrated device 20 to a certain extent, and further improving the integration of the integrated device 20.
[0062] In another embodiment of the present application, other structural distributions of the integrated device 20 and specific distribution modes of the first inductor structure 23 are also provided.
[0063] In a possible implementation manner, the first side of the substrate 21 is further provided with a via hole 25. The via hole 25 is used to arrange the first inductor structure 23.
[0064] For example, the orthographic projection shape of the via hole 25 can be spiral. Correspondingly, the first inductor structure 23 can include the first conductive layer 231, the second dielectric layer 232 and the second conductive layer 233 arranged in a stack.
[0065] Specifically, the first conductive layer 231 and the second conductive layer 233 can be formed by metal copper or metal aluminum wiring. The second dielectric layer 232 can be a PI film layer composed of polyimide, wherein the PI film layer is used to cover the first conductive layer 231, and the thickness range is 3-8 μm.
[0066] It should be noted that the inductance value of the first inductor structure 23 can be controlled by adjusting the position and the number of turns of the first conductive layer 231 and the second conductive layer 233.
[0067] For example, Figure 7 is a fifth cross-sectional schematic view of the integrated device 20 provided by the embodiments of the present application, as Figure 7 As shown in the figure, the first conductive layer 231 is arranged in the via hole 25, the second dielectric layer 232 is arranged on the side of the first conductive layer 231 away from the substrate 21, and the second conductive layer 233 is arranged on the side of the second dielectric layer 232 away from the first conductive layer 231. The arrangement starting point of the second conductive layer 233 is the arrangement end of the first conductive layer 231.
[0068] Specifically, the second dielectric layer 232 is provided with a first through hole 2321, and the first conductive layer 231 and the second conductive layer 233 are connected through the first through hole 2321.
[0069] For example, Figure 8 is a second schematic top view of the integrated device 20 provided by the embodiment of the present application, as shown in the figure, when the orthogonal projection shape of the via 25 is a planar spiral, the orthogonal projection shape of the first conductive layer 231 can be a planar spiral consistent with the via 25, so as to completely arrange the first conductive layer 231 in the via 25; secondly, the first conductive layer 231 and the second conductive layer 233 are connected through the first through hole 2321. Figure 8
[0070] Specifically, when the integrated device 20 is in a distributed structure as shown in Figure 8 , the equivalent circuit diagram of the integrated device 20 can be Figure 9 .
[0071] For example, when the orthogonal projection shape of the via 25 and the first conductive layer 231 are both planar spirals as shown in Figure 8 , the ratio of the wiring width of the first conductive layer 231 to the arrangement interval of the first conductive layer 231 is about 1:1.
[0072] It should be noted that, as shown in Figure 7 , the side of the first conductive layer 231 away from the substrate 21 is also provided with a through hole 701, so as to realize signal connection of the first conductive layer 231 by using the through hole 701.
[0073] Secondly, referring to Figure 7 and Figure 8 , the second dielectric layer 232 is arranged between the first conductive layer 231 and the second conductive layer 233, which can be used to protect the metal wiring of the first conductive layer 231 on the one hand, and can be used as a jumper dielectric layer for the port leading out of the central position of the first conductive layer 231, while avoiding signal interference between the first conductive layer 231 and the second conductive layer 233.
[0074] Optionally, the via 25 can penetrate the substrate 21 along the orthogonal projection direction (that is, the via 25 is a vertical through micro via made on the substrate by TGV technology). Correspondingly, the first inductive structure 23 can be filled in the via 25 to be arranged around the substrate 21.
[0075] Specifically, Figure 10 is a sixth schematic cross-sectional view of the integrated device 20 provided by the embodiment of the present application, as shown in the figure, when the via 25 is a TGV through hole 901, the first inductive structure 23 can be arranged around the substrate 21 with the substrate 21 as a magnetic core. Figure 10
[0076] Secondly, Figure 11 is a top view of the integrated device 20 provided by an embodiment of the present application, as shown in the figure, based on the TGV via hole 901, the first inductance structure 23 can be a 3D spiral structure. Figure 11
[0077] It should be noted that when the material of the substrate 21 is glass, the dielectric constant of the glass is small and the dielectric loss is low, which can effectively avoid the loss of the integrated device 20.
[0078] In another embodiment of the present application, other structural distributions of the integrated device 20 are also provided. For example, the integrated device 20 is also provided with a second via hole 26 penetrating the substrate 21, and a protruding structure 27 is arranged at one end of the second via hole 26 away from the first capacitance structure 22; wherein the second via hole 26 is provided with a metal material, and a third dielectric layer 28 is further arranged between the protruding structure 27 and the substrate 21.
[0079] In the embodiment of the present application, the protruding structure 27 used to complete the packaging of the integrated device 20 can be arranged at the other side away from the first side of the substrate 21, so as to distribute the packaging connection surface and the device surface (i.e. the surface provided with the first capacitance structure 22 and the first inductance structure 23) of the integrated device 20 on both sides of the substrate 21 respectively, thereby effectively improving the heat dissipation of the integrated device 20.
[0080] For example, the second via hole 26 can be a vertical and small via hole made on the substrate 21 by the TGV technology, and the metal copper is filled in the small via hole to form a copper column; and the protruding structure 27 can be a tin cap composed of metal tin.
[0081] For example, the metal copper column in the second via hole 26 and the protruding structure 27 (i.e. the tin cap) can form a bump structure used to package the integrated device 20.
[0082] For example, the third dielectric layer 28 can be a PI film layer composed of polyimide.
[0083] For example, Figure 12 is a cross-sectional view of the integrated device 20 provided by an embodiment of the present application, as shown in the figure, the protruding structure 27 is arranged at one end of the second via hole 26 away from the first capacitance structure 22, and the third dielectric layer 28 which is specifically a PI film layer is further arranged between the second via hole 26 and the protruding structure 27. Figure 12
[0084] It should be noted that in order to ensure the normal connection of the first capacitance structure 22 and the protruding structure 27, the first wire layer 231 in the first capacitance structure 22 has a connection relationship with the metal material filled in the second via hole 26, and based on this, the orthographic projection shape of the groove 24 is within the orthographic projection shape of the first capacitance structure 22.
[0085] For example, when the metal pillar in the second through hole 26 and the first conductive layer 231 are made of the same material (e.g., both are metallic copper), the second through hole 26 can be filled at the same time as the first conductive layer 231 is being prepared.
[0086] In one possible implementation, a metal structure is provided on the side of the third dielectric layer 28 away from the protrusion structure 27.
[0087] In this embodiment, the third dielectric layer 28 can be used to disperse the stress concentration on one side of the integrated device 20 caused by the concentration of blind vias on one side, thereby avoiding the problem of device or wafer warpage.
[0088] For example, the metal structure disposed in the third dielectric layer 28 can be a sheet structure made of copper or silicon.
[0089] Specifically, along the extension direction of the metal structure toward the protrusion 27, the distance between the end of the metal structure near the protrusion 27 and the circumferential edge of the substrate 21 is less than or equal to 100 μm; wherein, the extension direction is the direction perpendicular to the orthographic projection direction.
[0090] For example, Figure 13 This is the eighth cross-sectional schematic diagram of the integrated device 20 provided in the embodiments of this application, as shown below. Figure 13 As shown, a third dielectric layer 28 is disposed on the side of the substrate 21 away from the first side, and a Cu / Si sheet is disposed on the other side of the third dielectric layer 28 away from the protrusion structure 27.
[0091] For example, refer to Figure 13 Along the extension direction of the metal structure toward the protrusion 27, the distance d between the end of the metal structure near the protrusion 27 and the circumferential edge of the substrate 21 is less than or equal to 100 μm; wherein, the extension direction is the direction perpendicular to the orthographic projection direction.
[0092] In another embodiment of this application, other structural distributions of the integrated device 20 are also provided. For example, at least one second capacitor structure 29 and at least one second inductor structure 210 are provided on the second side of the substrate 21 away from the first capacitor structure 22, and the second capacitor structure 29 is continuously disposed on the bottom and sidewall of the groove 24 provided on the second side.
[0093] In this embodiment, the integrated device 20 can be fabricated on both sides by setting a second capacitor structure 29 and a second inductor structure 210 on the other side of the substrate 21, thereby improving the device integration while avoiding substrate warping caused by stress concentration on one side.
[0094] Exemplarily, the second capacitance structure 29 and the second inductance structure 210 can respectively keep consistent with the shape distribution of the first capacitance structure 22 and the first inductance structure 23.
[0095] For example, Figure 14 is a ninth cross-sectional schematic view of the integrated device 20 provided by an embodiment of the present application, as shown in the figure, based on Figure 14 , the recess 24 and the via 25 in a planar spiral shape can be arranged on the second side away from the first side of the substrate 21, and the second capacitance structure 29 can be arranged on the bottom and the sidewall of the recess 24, and the second inductance structure 210 can be arranged on the via 25. Figure 8
[0096] Specifically, when the integrated device 20 has a distribution structure as shown in Figure 14 , the equivalent circuit diagram of the integrated device 20 can be Figure 15 .
[0097] In another embodiment of the present application, a preparation method of the integrated device 20 is also provided. Exemplarily, Figure 16 is a flowchart of the preparation method of the integrated device 20 provided by an embodiment of the present application, as shown in the figure, the method comprises the following steps: Figure 16
[0098] Step 1601, etching the substrate 21 based on a preset capacitance value of the first capacitance structure 22 to form the recess 24.
[0099] In a possible implementation manner, the substrate 21 can be etched based on a preset position and a preset capacitance value of the first capacitance structure 22 to form the recess 24 arranged on the first side of the substrate 21.
[0100] Exemplarily, the substrate 21 can be a glass substrate, and the thickness can be 200 μm.
[0101] Exemplarily, the preset position can be a preset placement position of the first capacitance structure 22 in the integrated device 20, and the depth of the recess 24 along the orthogonal projection direction can be determined according to the preset capacitance value of the first capacitance structure 22.
[0102] Specifically, the setting length of the first capacitance structure 22 on the sidewall of the recess 24 can be determined according to the preset capacitance value of the first capacitance structure 22, and thus the depth of the recess 24 (i.e., the etching depth of the substrate 21) can be determined according to the setting length; wherein the etching depth of the substrate 21 is greater than or equal to the setting length of the first capacitance structure 22 on the sidewall of the recess 24.
[0103] Exemplarily, the substrate 21 can be subjected to a mask processing by using a photolithography mask process, so as to expose the preset positions through the mask. The mask material can be organic PR, PI, Resin, inorganic SiNx, SiOx, SiNO, or metal Cu, Ti, AL, Mo, Ta, etc.
[0104] Exemplarily, the substrate 21 can be etched based on the preset positions exposed by the mask, so as to form the groove 24. It should be noted that the etching depth of the groove 24 is less than the thickness of the substrate 21.
[0105] Optionally, the substrate 21 can be etched after the preset positions are subjected to laser modification by using a laser modification method, so as to form the groove 24.
[0106] Specifically, the substrate 21 can be etched by using a dry etching method, or can be etched by using a wet etching method, which is not limited here. The wet etching of the substrate 21 can be realized by using HF or NaOH solution.
[0107] Exemplarily, after the groove 24 is formed, the substrate 21 can be subjected to a demolding processing, so as to form the substrate 21 with the groove 24.
[0108] It should be noted that when the substrate 21 is etched by using the wet etching method, since the corrosion rates of the material in each direction are the same, the sidewall of the groove 24 can present an arc shape (i.e., the orthographic projection shape of the groove 24 can be a circle), and based on the groove 24 presenting the arc shape, the stress can be dispersed in the preparation process of the integrated device 20, so as to avoid the problem of cracking of the substrate 21 due to stress concentration.
[0109] In one possible implementation, after the groove 24 is formed, the side of the substrate 21 provided with the groove 24 can be etched based on the preset inductance value of the first inductive structure 23, so as to form the via 25.
[0110] Exemplarily, the wiring position and the number of turns of the first inductive structure 23 can be determined according to the preset inductance value of the first inductive structure 23, so as to determine the line width of the first inductive structure 23 based on the wiring position and the number of turns, thereby etching the substrate 21 to form the via 25. The depth of the via 25 along the orthographic projection direction can be consistent with the line width of the first inductive structure 23.
[0111] Exemplarily, the formation method of the via 25 can be the same as that of the groove 24, which will not be described here in detail.
[0112] At step 1602, the first capacitor structure 22 is prepared on the bottom and sidewall of the groove 24, and the first inductor structure 23 is prepared on the side of the substrate 21 where the first capacitor structure 22 is arranged, to form the integrated device 20.
[0113] In a possible implementation, the preparation steps of the first capacitor structure 22 and the first inductor structure 23 can be determined according to the shape of the via 25.
[0114] For example, when the orthographic projection shape of the via 25 is a planar spiral, Figure 17 is a preparation flow diagram of the first capacitor structure 22 and the first inductor structure 23 provided by the embodiment of the present application, as Figure 17 shown, the preparation flow includes the following steps:
[0115] At step 1701, the first wire layer 231 of the first inductor structure 23 is prepared by arranging a wire on the side of the via 25 away from the substrate 21.
[0116] Specifically, on the side of the via 25 away from the substrate 21, the first wire layer 231 of the first inductor structure 23 can be prepared by electroplating in a semi-additive method, through processes such as glue coating, photoetching, development, sputtering seed layer, and electroplating.
[0117] At step 1702, the second dielectric layer 232 is prepared on the side of the first wire layer 231 away from the substrate 21.
[0118] Specifically, the PI film layer composed of polyimide can be prepared on the side of the first wire layer 231 away from the substrate 21 by coating.
[0119] At step 1703, the first metal layer 221 of the first capacitor structure 22 and the second wire layer 233 of the first inductor structure 23 are prepared by arranging a wire on the side of the second dielectric layer 232 and the groove 24 away from the substrate 21; wherein the first wire layer 231, the second dielectric layer 232, and the second wire layer 233 form the first inductor structure 23.
[0120] Specifically, on the side of the second dielectric layer 232 and the groove 24 away from the substrate 21, the first metal layer 221 and the second wire layer 233 can be prepared by a conventional subtractive method, through processes such as sputtering metal, glue coating, photoetching, development, and metal etching.
[0121] It should be noted that, in order to ensure the normal connection of the signal of the first wire layer 231, a through hole 701 can be etched at a certain position of the second dielectric layer 232 corresponding to the first wire layer 231, as Figure 7 shown, to realize the signal connection of the first wire layer 231 through the through hole 701 and the metal wire used to form the first metal layer 221.
[0122] Step 1704, a first dielectric layer 222 is prepared on the side of the first metal layer 221 away from the substrate 21, and a wire is arranged on the side of the first dielectric layer 222 away from the substrate 21 to form a second metal layer 223 of the first capacitor structure 22; wherein the first metal layer 221, the first dielectric layer 222 and the second metal layer 223 form the first capacitor structure 22.
[0123] Specifically, on the side of the first metal layer 221 away from the substrate 21, a conventional subtractive process can be used to prepare the first dielectric layer 222 through sputtering metal, glue coating, photoetching, developing, metal etching and the like; wherein the first dielectric layer 222 can be a SiNx layer or a HfO2 layer.
[0124] For example, when the via 25 is a through hole penetrating the substrate 21 along the orthogonal projection direction, Figure 18 is another preparation flow diagram of the first capacitor structure 22 and the first inductor structure 23 provided by the embodiments of the present application, as shown in the figure, the preparation flow includes the following steps: Figure 18
[0125] Step 1801, a wire is arranged on the side of the recess 24 away from the substrate 21 to form a first metal layer 221.
[0126] Specifically, on the side of the recess 24 away from the substrate 21, a conventional subtractive process can be used to prepare the first metal layer 221 through sputtering metal, glue coating, photoetching, developing, metal etching and the like, and to fill the through hole penetrating the substrate 21 to complete the partial preparation of the first inductor structure 23.
[0127] Step 1802, a first dielectric layer 222 is prepared on the side of the first metal layer 221 away from the substrate 21.
[0128] Specifically, on the side of the first metal layer 221 away from the substrate 21, a conventional subtractive process can be used to prepare the first dielectric layer 222 through PECVD, glue coating, photoetching, developing, etching and the like.
[0129] Step 1803, a wire is arranged on the side of the first dielectric layer 222 away from the substrate 21 and in the via 25 to form a second metal layer 223; wherein the first metal layer 221, the first dielectric layer 222 and the second metal layer 223 form the first capacitor structure 22, and the arrangement of the wire in the via 25 forms the first inductor structure 23.
[0130] Specifically, on the side of the first dielectric layer 222 away from the substrate 21 and the via 25, a semi-additive electroplating process is used, and the second metal layer 223 is prepared by processes such as coating, photolithography, development, sputtering seed layer, and electroplating. The second metal layer 223 can fill the groove 24, or it can have the same shape as the first dielectric layer 222 (i.e., it does not fill the groove 24).
[0131] It should be noted that a metal conductor layer, also known as a redistribution layer (RDL layer), is provided on the side of the first inductor structure 23 away from the substrate 21. For example, an RDL layer composed of a metal layer and an insulating layer can be prepared by damascus process or ordinary semi-additive method.
[0132] In one possible implementation, after forming the first capacitor structure 22 and the first inductor structure 23, a second through hole 26 penetrating the substrate 21 can be prepared on the substrate 21 based on a preset position, and a metal material can be filled in the second through hole 26, and a protrusion structure 27 can be prepared at the end of the second through hole 26 away from the first capacitor structure 22.
[0133] For example, a second through-hole 26 can be fabricated on substrate 21 using TGV technology, and a metal material can be filled into the second through-hole 26 to form a copper pillar within the second through-hole 26.
[0134] For example, a protrusion structure 27 formed by a tin cap can be prepared at the end of the copper pillar away from the first capacitor structure 22 (i.e., the end away from the first side of the substrate 21).
[0135] For example, after forming the protrusion structure 27, a groove 24 and a via 25 can be etched at a preset position on the other side away from the first side of the substrate 21, and a second capacitor structure 29 and a second inductor structure 210 are disposed in the groove 24 and the via 25.
[0136] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the foregoing disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.
Claims
1. An integrated device, comprising: The integrated device comprises: a substrate, and at least one first capacitor structure and at least one first inductor structure arranged on a first side of the substrate, wherein the first side is provided with a groove; the first capacitor structure is continuously arranged on the bottom and sidewall of the groove; the capacitance value of the first capacitor structure is positively correlated with the length of the first capacitor structure on the sidewall of the groove.
2. The integrated device of claim 1, wherein, The length of the first capacitor structure on each sidewall in the groove is the same; wherein the length of the first capacitor structure on the sidewall of the groove is the length of the first capacitor structure along the depth direction of the groove.
3. The integrated device of claim 1 or 2, wherein, The length of the first capacitor structure on at least one sidewall in the groove is the same as the depth of the groove.
4. The integrated device of claim 1, wherein, The orthographic projection shape of the first capacitor structure is the same as the orthographic projection shape of the groove.
5. The integrated device of claim 1, wherein, The orthographic projection shape of the groove is within the orthographic projection shape of the first capacitor structure.
6. The integrated device of any one of claims 1-5, wherein, The first capacitor structure comprises a first metal layer, a first dielectric layer and a second metal layer arranged in a stack, the first metal layer is continuously arranged on the bottom and sidewall of the groove away from the substrate, the first dielectric layer is arranged on the side of the first metal layer away from the bottom and sidewall of the groove, and the second metal layer is arranged on the side of the first dielectric layer away from the first metal layer.
7. The integrated device of claim 1, wherein, The first capacitor structure and the first inductor structure are connected in series or parallel.
8. The integrated device of claim 1, wherein, The first side of the substrate is further provided with a via hole, and the via hole is used to arrange the first inductor structure.
9. The integrated device of claim 8, wherein, The first inductor structure comprises a first wire layer, a second dielectric layer and a second wire layer arranged in a stack, the first wire layer is arranged in the via hole, the second dielectric layer is arranged on the side of the first wire layer away from the substrate, and the second wire layer is arranged on the side of the second dielectric layer away from the first wire layer; wherein the arrangement starting point of the second wire layer is the arrangement end of the first wire layer.
10. The integrated device of claim 9, wherein, The second dielectric layer is provided with a first through hole, and the first wire layer and the second wire layer are connected through the first through hole.
11. The integrated device of claim 8, wherein, The via hole penetrates the substrate along the orthographic projection direction, and the first inductor structure fills the via hole to be arranged around the substrate.
12. The integrated device of any one of claims 1-11, wherein, The integrated device is further provided with a second through hole penetrating the substrate, and a protruding structure is arranged at one end of the second through hole away from the first capacitor structure; wherein a metal material is arranged in the second through hole, and a third dielectric layer is further arranged between the protruding structure and the substrate.
13. The integrated device of claim 12, wherein, The third dielectric layer is provided with a metal structure on the side away from the protruding structure.
14. The integrated device of claim 12 or 13, wherein, The second side of the substrate away from the first capacitor structure is provided with at least one second capacitor structure and at least one second inductor structure, and the second capacitor structure is continuously arranged on the bottom and sidewall of the groove arranged on the second side.
15. A method of fabricating an integrated device, the method comprising: The method comprises: etching the substrate based on the preset capacitance value of the first capacitor structure to form a groove; preparing the first capacitor structure on the bottom and sidewall of the groove, and preparing the first inductor structure on the side of the substrate provided with the first capacitor structure to form an integrated device.
16. The method of claim 15, wherein the method further comprises: The method further comprises: Based on a preset position, a second through hole penetrating through the substrate is prepared on the substrate; A metal material is filled in the second through hole, and a protruding structure is prepared at an end of the second through hole away from the first capacitor structure.