Semiconductor device test structure and semiconductor device evaluation method using the same
By designing the same layer for resistance measurement lines, capacitance measurement lines, and dummy lines in the semiconductor device test structure, the problem of inaccurate resistance and capacitance measurements is solved, and high-precision circuit performance prediction is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-01-14
- Publication Date
- 2026-05-12
AI Technical Summary
In the prior art, the resistance and capacitance measurements of semiconductor device interconnects cannot be accurately extracted due to layout differences, which affects the accuracy of circuit performance prediction.
The same test structure design is adopted, including resistance measurement lines, capacitance measurement lines and dummy lines. The resistance measurement lines and capacitance measurement lines are disposed on the same layer on the semiconductor substrate. The capacitance measurement lines are respectively disposed on both sides of the resistance measurement lines by the first and second capacitance measurement lines. The dummy lines are disposed on adjacent layers. Accurate measurement of resistance and capacitance is achieved by switching the potential of the dummy lines.
This technology enables high-precision measurement of resistance and capacitance in semiconductor device interconnect structures, improves the accuracy of circuit performance simulation prediction, and reduces measurement errors caused by differences in interconnect thickness.
Smart Images
Figure CN121531981B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device testing structure and a method for evaluating semiconductor devices using the structure. Background Technology
[0002] Semiconductor devices and their process conditions are evaluated / verified using semiconductor device test structures. These structures are not directly related to the actual circuit function; their design purpose is to measure specific physical quantities and electrical characteristics. Such test structures are also called test patterns or test chips.
[0003] Currently, resistance and capacitance are measured separately using different test structures. For example... Figures 1-2 As shown, the test structure for resistance measurement consists of resistance measurement line 10 and dummy line 12; as Figures 3-4 As shown, the test structure for capacitance measurement consists of capacitance measurement lines 14 and dummy lines 16 forming a comb-like pattern. However, when different test structures are used to measure resistance and capacitance respectively, even if the connecting lines being measured have the same line width and spacing, they cannot achieve consistency in cross-sectional shape and thickness (shown as Tr and Tc in the figure) due to the density of the surrounding connecting lines and the different layouts of dummy lines 12 and 16. Ideally, the resistance and capacitance of the connecting lines should be extracted under the same layout and thickness, but since this is practically impossible, there is a problem of inaccurate parameter extraction.
[0004] For designs that require high accuracy in layout parasitic extraction (LPE), measurement errors in resistance or capacitance due to differences in interconnect thickness are directly related to simulation results. Therefore, the aforementioned issues are a major cause of decreased accuracy in circuit performance prediction. Summary of the Invention
[0005] The purpose of this invention is to provide a semiconductor device test structure and a semiconductor device evaluation method using the same structure, demonstrating how to achieve accurate measurement of resistance and capacitance in the interconnect structure of a semiconductor device using the same test structure.
[0006] This invention provides a semiconductor device test structure, characterized in that it includes a resistance measurement line, a capacitance measurement line, and a dummy line. The resistance measurement line and the capacitance measurement line are disposed on the same layer on a semiconductor substrate. The resistance measurement line is used to measure the resistance of the connection line; the capacitance measurement line is used to measure the capacitance of the connection line. The capacitance measurement line includes a first capacitance measurement line and a second capacitance measurement line, which are respectively disposed on both sides of the resistance measurement line. The dummy line is disposed on an adjacent layer of the resistance measurement line and the capacitance measurement line.
[0007] In some embodiments, both the first capacitance measurement line and the second capacitance measurement line include a plurality of comb-shaped connecting lines, such that both the first capacitance measurement line and the second capacitance measurement line are comb-shaped patterns.
[0008] In some embodiments, the capacitance measurement line includes two first capacitance measurement lines and two second capacitance measurement lines, the two first capacitance measurement lines are inserted opposite each other, the two second capacitance measurement lines are inserted opposite each other, the two first capacitance measurement lines and the two second capacitance measurement lines are connected to four measurement terminals, and the four measurement terminals are used for four-terminal resistance measurement.
[0009] In some embodiments, the dummy line includes a first dummy line and / or a second dummy line, wherein the first dummy line is disposed in the lower layer of the resistance measurement line and the capacitance measurement line, and / or the second dummy line is disposed in the upper layer of the resistance measurement line and the capacitance measurement line.
[0010] In some embodiments, the first dummy line and / or the second dummy line may be grounded or have a predetermined voltage applied.
[0011] In some embodiments, a third dummy line is further included, which is disposed in an adjacent region outside the first capacitance measurement line and the second capacitance measurement line.
[0012] On the other hand, the present invention also provides a semiconductor device evaluation method, which uses the aforementioned semiconductor device test structure and includes the following steps:
[0013] Resistance measurement using the four-terminal method with resistance measuring wires;
[0014] Capacitance measurement is performed using the resistance measurement lines and capacitance measurement lines.
[0015] In some embodiments, performing capacitance measurement using the resistance measurement line and capacitance measurement line further includes:
[0016] The resistance and capacitance measurement lines are used to measure lateral and vertical capacitance.
[0017] In some embodiments, by switching the potentials of the resistance measurement line, the first dummy line, and the second dummy line, two different capacitance measurement states are formed:
[0018] In the first measurement state, the resistance measurement line, the first dummy line, and the second dummy line are all grounded;
[0019] In the second measurement state, the resistance measurement line, the first dummy line, and the second dummy line are all connected to a predetermined potential;
[0020] In the first measurement state, the first combined value of the lateral capacitance and the vertical capacitance is measured;
[0021] In the second measurement state, a second combined value of the lateral capacitance and the vertical capacitance is measured;
[0022] The lateral capacitance and vertical capacitance are calculated based on the first and second combined values.
[0023] In some embodiments, the lateral capacitance Cl and the vertical capacitance Cv are calculated as follows:
[0024] Cl = (Cap2 - Cap1) / 2;
[0025] Cv=(Cap1-(Nf-1)×2×Cl) / (2×Nf);
[0026] Where Cap1 is the first combined value; Cap2 is the second combined value; and Nf is the number of teeth in each comb pattern in the capacitance measurement line.
[0027] Compared with the prior art, the present invention has the following unexpected technical effects:
[0028] This invention provides a semiconductor device test structure and a semiconductor device evaluation method using the structure. The semiconductor device test structure includes a resistance measurement line, a capacitance measurement line, and a dummy line. The resistance measurement line and the capacitance measurement line are disposed on the same layer on a semiconductor substrate. The resistance measurement line is used to measure the resistance of the interconnect. The capacitance measurement line is used to measure the capacitance of the interconnect. The capacitance measurement line includes a first capacitance measurement line and a second capacitance measurement line, which are respectively disposed on both sides of the resistance measurement line. The dummy line is disposed on an adjacent layer of the resistance measurement line and the capacitance measurement line. The same test structure enables accurate measurement of resistance and capacitance in the interconnect structure of the semiconductor device. Attached Figure Description
[0029] Figure 1 This is a planar diagram of a test structure used for resistance measurement of semiconductor devices in the prior art.
[0030] Figure 2 for Figure 1 A sectional view along line AA.
[0031] Figure 3 This is a planar diagram of a test structure used for capacitance measurement of semiconductor devices in the prior art.
[0032] Figure 4 for Figure 3 Sectional view along line BB.
[0033] Figure 5 This is a plan view of a semiconductor device test structure according to an embodiment of the present invention.
[0034] Figure 6 for Figure 5 A sectional view along line CC.
[0035] Figure 7 This is a plan view of the resistance measurement line and capacitance measurement line in a semiconductor device test structure according to an embodiment of the present invention.
[0036] Figure 8 This is a plan view of the first dummy line in a semiconductor device test structure according to an embodiment of the present invention.
[0037] Figure 9 This is a plan view of the second dummy line in a semiconductor device test structure according to an embodiment of the present invention.
[0038] Figure 10 This is an embodiment of the electrical connection relationship of a semiconductor device test structure according to the present invention.
[0039] Figure 11 This is an illustration of a capacitance measurement method according to an embodiment of the present invention.
[0040] Figure 12 This is an illustration of a capacitance measurement method according to an embodiment of the present invention.
[0041] Explanation of reference numerals in the attached figures:
[0042] 10 - Resistance measurement line; 12 - Dummy line; 14 - Capacitance measurement line; 16 - Dummy line; 20 - Resistance measurement line; 22 - Capacitance measurement line; 22a - First capacitance measurement line; 22b - Second capacitance measurement line; 24 - First dummy line; 26 - Second dummy line; 28 - Third dummy line; 100 - Test structure. Detailed Implementation
[0043] The following will provide a more detailed description of a semiconductor device testing structure and a semiconductor device evaluation method using the structure according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.
[0044] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.
[0045] To make the objectives and features of the present invention more apparent and understandable, specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention.
[0046] Figure 5 This is a plan view of the semiconductor device test structure in this embodiment. Figure 5 As shown, this embodiment provides a semiconductor device test structure 100, including a resistance measurement line 20, a capacitance measurement line 22 (22a, 22b) and a dummy line.
[0047] Figure 6 for Figure 5 A sectional view along line CC. Figure 7 This is a plan view of the resistance measurement lines and capacitance measurement lines in the semiconductor device test structure of this embodiment. Figure 8 This is a plan view of the first dummy line in the semiconductor device test structure of this embodiment. Figure 9 This is a plan view of the second dummy line in the semiconductor device test structure of this embodiment. (See diagram below.) Figures 6-9 As shown, the semiconductor device test structure 100 is used to perform high-precision evaluation of the resistance and capacitance of the interconnects in a semiconductor device.
[0048] Resistance measurement line 20 is a conductive connection used to evaluate the sheet resistance (Rs) of a semiconductor device. Resistance measurement line 20 has a predetermined length and width and is formed along the surface of the semiconductor substrate. Both ends of resistance measurement line 20 are connected to measurement pads (not shown) to enable resistance evaluation via four-terminal measurement.
[0049] The capacitance measurement line 22 is composed of multiple comb-shaped conductive connecting lines, which are interlocked and connected with spacing between them to form a comb-like pattern. The capacitance measurement line 22 includes a first capacitance measurement line 22a and a second capacitance measurement line 22b. In the semiconductor device test structure 100, the first capacitance measurement line 22a and the second capacitance measurement line 22b are respectively arranged in a mirror-symmetrical manner on both sides of the resistance measurement line 20. By combining the resistance measurement line 20 and the capacitance measurement line 22 to perform capacitance measurement, high-precision evaluation of electrostatic capacitance (Cap) can be achieved, especially high-precision evaluation of the lateral capacitance (C1) in the direction parallel to the semiconductor substrate surface and the vertical capacitance component (Cv) in the direction perpendicular to the semiconductor substrate surface.
[0050] In this embodiment, the capacitance measurement line 22 includes two first capacitance measurement lines 22a and two second capacitance measurement lines 22b. Each of the first capacitance measurement lines 22a and the second capacitance measurement line 22b is a comb-shaped pattern composed of Nf comb-like (fin-like) connecting lines. The two first capacitance measurement lines 22a of the comb-shaped pattern are inserted opposite each other, and the two second capacitance measurement lines 22b of the comb-shaped pattern are inserted opposite each other. Therefore, the total number of comb teeth (fins) of the capacitance measurement line 22 is 2Nf, and the number of gaps between the comb teeth (fins) is 2(Nf-1). Of course, the number of comb-like (fin-like) connecting lines in the first capacitance measurement lines 22a and the second capacitance measurement lines 22b can be adjusted appropriately according to actual needs.
[0051] By placing the capacitance measurement line 22 and the resistance measurement line 20 adjacently on the same layer of the semiconductor substrate, the influence of density and surrounding layout on resistance and capacitance measurements can be integrated and unified when the semiconductor device test structure 100 is actually deployed, thereby improving accuracy.
[0052] The dummy lines include a first dummy line 24 and / or a second dummy line 26. Both the first dummy line 24 and / or the second dummy line 26 are conductive connection lines. The first dummy line 24 and the second dummy line 26 are respectively formed in the layer below and the layer above the wiring layer of the resistance measurement line 20 and / or the capacitance measurement line 22 (i.e., the first capacitance measurement line 22a and the second capacitance measurement line 22b). For example, the first dummy line 24 is formed in the layer below (i.e., the lower layer) of the wiring layer of the resistance measurement line 20 and the capacitance measurement line 22 (i.e., the first capacitance measurement line 22a and the second capacitance measurement line 22b); and / or, the second dummy line 26 is formed in the layer above (i.e., the upper layer) of the wiring layer of the resistance measurement line 20 and the capacitance measurement line 22 (i.e., the first capacitance measurement line 22a and the second capacitance measurement line 22b).
[0053] The first dummy line 24 is stacked below the resistance measurement line 20 and the capacitance measurement line 22; and / or, the second dummy line 26 is stacked above the resistance measurement line 20 and the capacitance measurement line 22. That is, at least one of the first dummy line 24 and the second dummy line 26 is present and needs to be stacked with the resistance measurement line 20 and the capacitance measurement line 22. The first dummy line 24 and the second dummy line 26 may be grounded or have a predetermined voltage applied.
[0054] Please continue reading. Figure 5 In order to control the metal density in the evaluation area, a third dummy line 28 can be set in the adjacent area outside the capacitance measurement line 22.
[0055] Figure 10 This illustrates the electrical connection relationships of a semiconductor device test structure according to an embodiment of the present invention. For example... Figure 10 As shown, the resistance measurement line 20, the capacitance measurement line 22, the first dummy line 24, and the second dummy line 26 are electrically connected to each other in a manner that enables the measurement of resistance and capacitance.
[0056] The resistance measuring line 20 is connected at both ends to measuring terminals T1 and T2, and to measuring terminals T3 and T4, respectively. In other words, one end of the resistance measuring line 20 is simultaneously connected to measuring terminals T1 and T2, and the other end is simultaneously connected to measuring terminals T3 and T4. Thus, the resistance measuring line 20 enables high-precision evaluation of sheet resistance using a four-terminal measurement method.
[0057] Measurement terminals T1 and T2 are also connected to the first dummy line 24, and measurement terminals T3 and T4 are also connected to the second dummy line 26. In this way, depending on the measurement conditions, the first dummy line 24 and the second dummy line 26 can be grounded, or maintained at a predetermined voltage, thereby controlling the influence of the surrounding structure on the electric field distribution during capacitance measurement and enabling separate evaluation of lateral and vertical capacitance.
[0058] Furthermore, one comb-shaped pattern of the first capacitance measurement line 22a (top comb-shaped pattern shown in the illustration) and one comb-shaped pattern of the second capacitance measurement line 22b (top comb-shaped pattern shown in the illustration) are connected to the measurement terminal T5 on the same side, respectively. The other comb-shaped pattern of the first capacitance measurement line 22a (bottom comb-shaped pattern shown in the illustration) and the other comb-shaped pattern of the second capacitance measurement line 22b (bottom comb-shaped pattern shown in the illustration) are connected to the measurement terminal T6 on the same side. In this embodiment, the application of a predetermined bias voltage and the switching between floating ground and ground can be achieved during capacitance measurement through the measurement terminals T5 and T6.
[0059] This embodiment also provides a semiconductor device evaluation method for semiconductor device test structures, including the following steps:
[0060] Resistance measurement using the four-terminal method with resistance measuring wires; and
[0061] Capacitance measurement is performed using the resistance measurement lines and capacitance measurement lines.
[0062] The following combination Figures 10-12 The semiconductor device evaluation method for the semiconductor device test structure provided in this embodiment will be described in detail.
[0063] First, perform step one: use the resistance measurement line to perform a four-terminal method resistance measurement, that is, use the first connecting line to evaluate the resistance through a four-terminal measurement method.
[0064] like Figure 10 As shown, this method employs a four-endpoint method with the four endpoints being the measuring ends T1 to T4 connected to the resistance measuring line 20.
[0065] In this design, measuring terminal T1 is connected to a constant current source, and measuring terminal T3 serves as a ground terminal, ensuring a constant current flows between measuring terminals T1 and T3. This allows current to flow through the resistance measuring line 20. Furthermore, measuring terminals T2 and T4 serve as voltage measuring terminals, while measuring terminals T5 and T6 are either floating or grounded, thereby minimizing the influence exerted by other structures besides the resistance measuring line 20, which is the object of measurement.
[0066] The actual effective resistance value of the resistance measuring line 20 can be obtained by measuring the potential difference between the two terminals T2 and T4. Furthermore, it is preferable to use a voltage measuring circuit with an impedance high enough to ensure that no current flows between the two terminals T2 and T4 during measurement.
[0067] Thus, by using the four-endpoint measurement method, the influence of factors such as the contact resistance between the measuring ends T1 to T4 and the resistance measuring line 20 and the measuring device probe can be eliminated, thereby extracting and measuring only the resistance component of the resistance measuring line 20.
[0068] Next, proceed to step two, using the resistance measurement line and capacitance measurement line to perform capacitance measurement. Further, use the first connecting line and the second connecting line to evaluate the lateral capacitance and vertical capacitance.
[0069] Figure 11 This is a diagram illustrating the capacitance measurement method in this embodiment. Figure 11As shown, in the first capacitance measurement setting state (i.e., the first measurement state), one of the comb-shaped patterns of the first capacitance measurement line 22a (the top comb-shaped pattern shown in the figure) and one of the comb-shaped patterns of the second capacitance measurement line 22b (the top comb-shaped pattern shown in the figure) are maintained at a constant potential (e.g., VDD) via the measurement terminal T5. The other comb-shaped pattern of the first capacitance measurement line 22a (the bottom comb-shaped pattern shown in the figure) and the other comb-shaped pattern of the second capacitance measurement line 22b (the bottom comb-shaped pattern shown in the figure) are grounded (GND) via the measurement terminal T6.
[0070] Meanwhile, in the first capacitance measurement setting state, the resistance measurement line 20 is set at a potential such that adjacent connecting lines in the first capacitance measurement line 22a and the second capacitance measurement line 22b do not undergo capacitive coupling. In this embodiment, since the connecting lines (comb-shaped pattern on the bottom side of the figure) adjacent to the resistance measurement line 20 in the first capacitance measurement line 22a and the second capacitance measurement line 22b are grounded (GND), the resistance measurement line 20 is also in a grounded state. Specifically, the resistance measurement line 20 is grounded (GND) from the measurement terminal T1 to the measurement terminal T4. In addition, in the first capacitance measurement setting state, the first dummy line 24 and the second dummy line 26 are also in a grounded state.
[0071] In the first capacitance measurement setting state, the measurement terminals T1 to T4 and T6 are all grounded, and the measurement terminal T5 is kept at a constant potential (such as VDD).
[0072] Figure 12 This is a diagram illustrating the capacitance measurement method in this embodiment. Figure 12 As shown, in the second capacitance measurement setting state (i.e., the second measurement state), one of the comb-shaped patterns of the first capacitance measurement line 22a (the top comb-shaped pattern shown in the figure) and one of the comb-shaped patterns of the second capacitance measurement line 22b (the top comb-shaped pattern shown in the figure) are maintained at a constant potential (e.g., VDD) via the measurement terminal T5. The other comb-shaped pattern of the first capacitance measurement line 22a (the bottom comb-shaped pattern shown in the figure) and the other comb-shaped pattern of the second capacitance measurement line 22b (the bottom comb-shaped pattern shown in the figure) are grounded (GND) via the measurement terminal T6.
[0073] Meanwhile, in the second capacitance measurement setting state, the resistance measurement line 20 is set at a potential such that adjacent connecting lines in the first capacitance measurement line 22a and the second capacitance measurement line 22b do not undergo capacitive coupling. In this embodiment, since the connecting lines (comb-shaped pattern on the bottom side of the figure) adjacent to the resistance measurement line 20 in the first capacitance measurement line 22a and the second capacitance measurement line 22b are grounded (GND), the resistance measurement line 20 is set at a constant potential (e.g., VDD). Specifically, the resistance measurement line 20 is set at a constant potential (e.g., VDD) from the measurement terminal T1 to the measurement terminal T4. In addition, the first dummy line 24 and the second dummy line 26 are also set at a constant potential (e.g., VDD).
[0074] In the second capacitance measurement setting state, the measurement terminals T1 to T5 are kept at a constant potential (such as VDD), and the measurement terminal T6 is in a grounded state.
[0075] Please continue reading. Figure 11 In the first measurement state, the first combined value of the lateral capacitance and the vertical capacitance is measured. Specifically, in the first capacitance measurement setting state, the lateral electrostatic capacitance (lateral capacitance C1) formed between the connecting lines of the first capacitance measurement line 22a and the second capacitance measurement line 22b, and the vertical electrostatic capacitance (vertical capacitance Cv) formed between one of the comb-shaped patterns (top comb-shaped pattern in the illustration) of the first capacitance measurement line 22a and one of the comb-shaped patterns (top comb-shaped pattern in the illustration) of the second capacitance measurement line 22b and the connecting lines of the first dummy line 24 and the second dummy line 26 are measured simultaneously. That is, the vertical electrostatic capacitance Cv formed between one of the comb-shaped patterns (top comb-shaped pattern in the illustration) of the first capacitance measurement line 22a and the connecting lines of the first dummy line 24 and the second dummy line 26 is measured. The vertical electrostatic capacitance (vertical capacitance Cv) between the connecting lines of the first capacitance measurement line 22a; the vertical electrostatic capacitance (vertical capacitance Cv) between one of the comb-shaped patterns (top comb-shaped pattern in the illustration) formed on the first capacitance measurement line 22a and the connecting lines in the second dummy line 26; the vertical electrostatic capacitance (vertical capacitance Cv) between one of the comb-shaped patterns (top comb-shaped pattern in the illustration) formed on the second capacitance measurement line 22b and the connecting lines in the first dummy line 24; the vertical electrostatic capacitance (vertical capacitance Cv) between one of the comb-shaped patterns (top comb-shaped pattern in the illustration) formed on the second capacitance measurement line 22b and the connecting lines in the second dummy line 26.
[0076] The capacitance value measured in the first capacitance measurement setting state is called the capacitance measurement value Cap1 (i.e., the first combined value).
[0077] Please continue reading. Figure 12In the second measurement state, the second combined value of the lateral capacitance and the vertical capacitance is measured. Specifically, in the second capacitance measurement setting state, the lateral electrostatic capacitance (lateral capacitance Cl) formed between the connecting lines in the first capacitance measurement line 22a, the second capacitance measurement line 22b, and the resistance measurement line 20 is measured simultaneously. That is, the lateral electrostatic capacitance (lateral capacitance Cl) between the connecting lines in the first capacitance measurement line 22a and the second capacitance measurement line 22b, between the connecting lines in the first capacitance measurement line 22a and the resistance measurement line 20, and between the connecting lines in the second capacitance measurement line 22b and the resistance measurement line 20 is measured simultaneously.
[0078] The vertical electrostatic capacitance (vertical capacitance Cv) between the other comb pattern (bottom comb pattern shown in the figure) formed on the first capacitance measurement line 22a and the other comb pattern (bottom comb pattern shown in the figure) formed on the second capacitance measurement line 22b and the connecting line in the first dummy line 24 and the second dummy line 26, respectively, is as follows: the vertical electrostatic capacitance (vertical capacitance Cv) formed between the other comb pattern (bottom comb pattern shown in the figure) formed on the first capacitance measurement line 22a and the connecting line in the first dummy line 24; the vertical electrostatic capacitance (vertical capacitance Cv) formed between the other comb pattern (bottom comb pattern shown in the figure) formed on the first capacitance measurement line 22a and the connecting line in the second dummy line 26; the vertical electrostatic capacitance (vertical capacitance Cv) between the other comb pattern (bottom comb pattern shown in the figure) formed on the second capacitance measurement line 22b and the connecting line in the first dummy line 24; and the vertical electrostatic capacitance (vertical capacitance Cv) between the other comb pattern (bottom comb pattern shown in the figure) formed on the second capacitance measurement line 22b and the connecting line in the second dummy line 26.
[0079] The capacitance value measured in the second capacitance measurement setting state is called the capacitance measurement value Cap2 (second combined value).
[0080] Since the comb-shaped pattern of the first capacitance measurement line 22a and the comb-shaped pattern of the second capacitance measurement line 22b each have Nf comb teeth (fins), there are a total of (Nf-1) lateral capacitances formed between adjacent comb teeth.
[0081] Based on the first and second combined values, the lateral capacitance and vertical capacitance are calculated. Specifically, using the capacitance value measured in the first capacitance measurement setting state (capacitance measurement value Cap1) and the capacitance value measured in the second capacitance measurement setting state (capacitance measurement value Cap2), the lateral capacitance Cl and vertical capacitance Cv can be calculated according to the following formulas (1) and (2).
[0082] Cl=(Cap2-Cap1) / 2--------(1);
[0083] Cv=(Cap1-(Nf-1)×2×Cl) / (2×Nf) ------(2).
[0084] As described above, this embodiment, through the semiconductor device test structure 100, enables high-precision evaluation of the resistance (sheet resistance) and capacitance in a semiconductor device by setting the same test structure in different connection states. This allows for optimal design of semiconductor devices with fine interconnect structures and improves their reliability. Furthermore, for designs requiring high accuracy in layout parasitic extraction (LPE), it particularly reduces resistance or capacitance measurement errors caused by differences in interconnect thickness and improves the accuracy of simulation predictions of semiconductor device circuit performance.
[0085] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0086] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A semiconductor device testing structure, characterized in that, The device includes resistance measurement lines, capacitance measurement lines, and dummy lines. The resistance measurement lines and capacitance measurement lines are disposed on the same layer on a semiconductor substrate. The resistance measurement lines are used to measure the resistance of the connecting lines. The capacitance measurement lines are used to measure the capacitance of the connecting lines. The capacitance measurement lines include a first capacitance measurement line and a second capacitance measurement line, which are respectively disposed on both sides of the resistance measurement lines. The dummy lines are disposed on adjacent layers of the resistance measurement lines and the capacitance measurement lines, and are grounded or subjected to a predetermined voltage.
2. The semiconductor device test structure as described in claim 1, characterized in that, The first capacitance measurement line and the second capacitance measurement line both include multiple comb-shaped connecting lines, so that both the first capacitance measurement line and the second capacitance measurement line are comb-shaped patterns.
3. The semiconductor device test structure as described in claim 2, characterized in that, The capacitance measurement line includes two first capacitance measurement lines and two second capacitance measurement lines. The two first capacitance measurement lines are inserted opposite each other, and the two second capacitance measurement lines are inserted opposite each other. The two first capacitance measurement lines and the two second capacitance measurement lines are connected to four measurement terminals. The four measurement terminals are used for four-terminal resistance measurement.
4. The semiconductor device test structure as described in claim 1, characterized in that, The dummy line includes a first dummy line and / or a second dummy line, wherein the first dummy line is disposed in the lower layer of the resistance measurement line and the capacitance measurement line, and / or the second dummy line is disposed in the upper layer of the resistance measurement line and the capacitance measurement line.
5. The semiconductor device test structure as described in claim 4, characterized in that, It also includes a third dummy line, which is set in an adjacent area outside the first capacitance measurement line and the second capacitance measurement line.
6. A method for evaluating semiconductor devices, using the semiconductor device test structure as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Resistance measurement using the four-terminal method with resistance measuring wires; Lateral and vertical capacitance measurements are performed using the resistance and capacitance measurement lines, wherein the lateral capacitance is the lateral electrostatic capacitance between the connecting lines in the capacitance measurement lines, and the vertical capacitance is the vertical electrostatic capacitance between one of the comb-shaped patterns of the capacitance measurement lines and the connecting line in the dummy line.
7. The semiconductor device evaluation method as described in claim 6, characterized in that, By switching the potentials of the resistance measurement line, the first dummy line, and the second dummy line, two different capacitance measurement states are formed: In the first measurement state, the resistance measurement line, the first dummy line, and the second dummy line are all grounded; In the second measurement state, the resistance measurement line, the first dummy line, and the second dummy line are all connected to a predetermined potential; In the first measurement state, the first combined value of the lateral capacitance and the vertical capacitance is measured; In the second measurement state, a second combined value of the lateral capacitance and the vertical capacitance is measured; The lateral capacitance and vertical capacitance are calculated based on the first and second combined values.
8. The semiconductor device evaluation method as described in claim 7, characterized in that, Methods for calculating lateral capacitance Cl and vertical capacitance Cv: Cl = (Cap2 - Cap1) / 2; Cv=(Cap1- (Nf-1)×2×Cl) / (2×Nf); Where Cap1 is the first combined value; Cap2 is the second combined value; and Nf is the number of teeth in each comb pattern in the capacitance measurement line.