Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. The forming method of the semiconductor device comprises the steps that a first semiconductor structure and a second semiconductor structure are stacked, arranged and bonded in the first direction; the first semiconductor structure comprises a device layer and an interconnection layer located between the device layer and the second semiconductor structure in the first direction; the interconnection layer at least comprises a first sub-interconnection layer and a second sub-interconnection layer, and the first sub-interconnection layer is located between the second sub-interconnection layer and the device layer; simultaneously forming a first through hole and a second through hole which extend along the first direction and penetrate through the device layer; forming a first connection structure based on the first through hole, and forming a second connection structure based on the second through hole; the first connection structure penetrates through the first interconnection structure in the first sub-interconnection layer along a first direction and is connected with the second interconnection structure in the second sub-interconnection layer; and the second connection structure penetrates through the first polar plate of the capacitor structure along the first direction and is connected with the third interconnection structure in the first sub-interconnection layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and more particularly to a semiconductor device and a method for forming the same. Background Technology

[0002] In the manufacturing of computing chips, the use of hybrid bonding technology to achieve high-density integration of logic chips and memory chips has become a mainstream trend. Current process routes include face-to-face (F2F) bonding and face-to-back (F2B) bonding. Both of these technologies require the formation of multiple through-silicon vias (TSVs) within the logic chip. The landing layer for these multiple TSVs is typically a single wiring layer, which may lead to high IR drops in power lines or signal lines, and could also cause overload of the wiring layer. All of these issues can reduce the reliability of the computing chip. Therefore, optimizing the TSV landing method has become a pressing problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for forming the same.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows: In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor device, comprising: A first semiconductor structure and a second semiconductor structure are stacked and bonded along a first direction; the first semiconductor structure includes a device layer and an interconnect layer located between the device layer and the second semiconductor structure in the first direction; the interconnect layer includes at least a first sub-interconnect layer and a second sub-interconnect layer, wherein the first sub-interconnect layer is located between the second sub-interconnect layer and the device layer. Simultaneously, a first through-hole and a second through-hole are formed that extend along the first direction and penetrate the device layer; A first connection structure is formed based on the first through-hole, and a second connection structure is formed based on the second through-hole; the first connection structure penetrates the first interconnect structure in the first sub-interconnect layer along the first direction and is connected to the second interconnect structure in the second sub-interconnect layer; the second connection structure penetrates the first electrode plate of the capacitor structure along the first direction and is connected to the third interconnect structure in the first sub-interconnect layer; the capacitor structure is located between the first sub-interconnect layer and the device layer in the first direction.

[0005] In one optional embodiment, the method for forming the semiconductor device further includes: While forming the first through hole and the second through hole, a third through hole is formed that penetrates the device layer along the first direction; While forming the first connection structure and the second connection structure, a third connection structure is formed based on the third through hole; the third connection structure penetrates the second electrode plate of the capacitor structure along the first direction and is connected to the fourth interconnect structure in the first sub-interconnect layer; the first electrode plate and the second electrode plate of the capacitor structure are arranged along the first direction.

[0006] In an optional embodiment, the interconnect layer further includes a third sub-interconnect layer; the third sub-interconnect layer is located between the second semiconductor structure and the second sub-interconnect layer; the method of forming the semiconductor device further includes: While forming the first through hole, the second through hole and the third through hole, a fourth through hole is formed that penetrates the device layer along the first direction; While forming the first connection structure, the second connection structure, and the third connection structure, a fourth connection structure is formed based on the fourth via; the fourth connection structure is connected to the fifth interconnect structure in the third sub-interconnect layer.

[0007] In one optional implementation, the steps of forming the first connection structure based on the first through hole, forming the second connection structure based on the second through hole, forming the third connection structure based on the third through hole, and forming the fourth connection structure based on the fourth through hole include: Performing a first etching operation includes: simultaneously etching the interconnect layer along the first via, the second via, the third via, and the fourth via to form a fifth via, a sixth via, a seventh via, and an eighth via; the bottom of the fifth via exposes the first interconnect structure, the bottom of the sixth via exposes the first electrode plate, the bottom of the seventh via exposes the second electrode plate, and the bottom of the eighth via exposes the dielectric layer in the first sub-interconnect layer; Performing a second etching operation includes: simultaneously etching the interconnect layer along the fifth via, the sixth via, the seventh via, and the eighth via to form a ninth via, a tenth via, an eleventh via, and a twelfth via; the ninth via penetrates the first interconnect structure and exposes the second interconnect structure; the tenth via penetrates the first electrode plate and exposes the third interconnect structure; the eleventh via penetrates the second electrode plate and exposes the fourth interconnect structure; and the twelfth via exposes the fifth interconnect structure.

[0008] In one alternative implementation, prior to performing the second etching operation, the first interconnect structure includes an opening filled with a dielectric material; performing the second etching operation specifically includes: The dielectric material filling the opening is etched to expose the opening, and the dielectric material located between the first interconnect structure and the second interconnect structure is etched along the opening to form a first sub-via exposing the second interconnect structure; the first sub-via communicates with the fifth via and constitutes the ninth via; the size of the first sub-via in the second direction is smaller than the size of the fifth via in the second direction; the second direction is perpendicular to the first direction.

[0009] In one optional embodiment, both the first electrode and the second electrode include a first conductive material, and the first interconnect structure, the second interconnect structure, the third interconnect structure, the fourth interconnect structure, and the fifth interconnect structure all include a second conductive material, wherein the first conductive material is different from the second conductive material; performing the second etching operation specifically includes: The first electrode exposed and the dielectric material located between the first electrode and the third interconnect structure are etched along the sixth via until the third interconnect structure is exposed to form the tenth via; The second electrode exposed along the seventh via and the dielectric material located between the second electrode and the fourth interconnect structure are etched until the fourth interconnect structure is exposed to form the eleventh via.

[0010] In one optional embodiment, the method for forming the semiconductor device further includes: Before performing the first etching operation, an insulating layer is formed covering the inner wall of the first through hole, the inner wall of the second through hole, the inner wall of the third through hole, and the inner wall of the fourth through hole. Performing the first etching operation specifically includes etching the portion of the insulating layer located at the bottom of the first via, the portion located at the bottom of the second via, the portion located at the bottom of the third via, and the portion located at the bottom of the fourth via.

[0011] In an optional embodiment, the steps of forming the first connection structure based on the first through hole, forming the second connection structure based on the second through hole, forming the third connection structure based on the third through hole, and forming the fourth connection structure based on the fourth through hole further include: Meanwhile, a third conductive material is filled into the ninth, tenth, eleventh, and twelfth through holes to form the first connection structure, the second connection structure, the third connection structure, and the fourth connection structure.

[0012] In one optional embodiment, the method for forming the semiconductor device further includes: A redistribution layer and a pad lead-out layer are formed on one side of the device layer opposite to each other along the first direction, away from the interconnect layer; the redistribution layer is located between the device layer and the pad lead-out layer; the pad lead-out layer includes pads coupled to the first connection structure, pads coupled to the second connection structure, pads coupled to the third connection structure, and pads coupled to the fourth connection structure through the redistribution layer.

[0013] In one alternative embodiment, the second semiconductor structure includes a memory array; the device layer includes logic circuitry coupled to the memory array; and the interconnect layer includes a power distribution network and a signal transmission network coupled to the logic circuitry. The first connection structure belongs to the power distribution network or the signal transmission network; the second connection structure and the third connection structure belong to the power distribution network or the signal transmission network; the fourth connection structure belongs to the power distribution network or the signal transmission network.

[0014] In an optional embodiment, the method for forming the semiconductor device further includes: The third semiconductor structure and the second semiconductor structure are stacked and bonded along the first direction; the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure.

[0015] In a second aspect, this disclosure provides a semiconductor device, comprising: A first semiconductor structure and a second semiconductor structure are stacked and bonded along a first direction; the first semiconductor structure includes a device layer and an interconnect layer located between the device layer and the second semiconductor structure in the first direction; the interconnect layer includes at least a first sub-interconnect layer and a second sub-interconnect layer, wherein the first sub-interconnect layer is located between the second sub-interconnect layer and the device layer; A first connection structure and a second connection structure penetrate the device layer along the first direction; the first connection structure penetrates the first interconnect structure in the first sub-interconnect layer along the first direction and is connected to the second interconnect structure in the second sub-interconnect layer; the second connection structure penetrates the first electrode plate of the capacitor structure along the first direction and is connected to the third interconnect structure in the first sub-interconnect layer; the capacitor structure is located between the first sub-interconnect layer and the device layer in the first direction.

[0016] In one optional embodiment, the semiconductor device further includes: A third connection structure extends through the device layer along the first direction; the third connection structure extends through the second electrode of the capacitor structure along the first direction and is connected to the fourth interconnect structure in the first sub-interconnect layer; the first electrode and the second electrode of the capacitor structure are arranged along the first direction.

[0017] In one optional embodiment, the interconnect layer further includes a third sub-interconnect layer; the third sub-interconnect layer is located between the second semiconductor structure and the second sub-interconnect layer; the semiconductor device further includes: A fourth connection structure extends through the device layer along the first direction; the fourth connection structure is connected to a fifth interconnect structure in the third sub-interconnect layer.

[0018] In one optional embodiment, the first connection structure includes a first portion and a second portion connected together; the first portion extends through the device layer along the first direction and through the dielectric layer between the first interconnect structure and the device layer; the second portion extends through the first interconnect structure and is connected to the second interconnect structure; the dimension of the second portion in the second direction is smaller than the dimension of the first portion in the second direction; the second direction is perpendicular to the first direction.

[0019] In one optional embodiment, both the first electrode plate and the second electrode plate include a first conductive material, and the first interconnect structure, the second interconnect structure, the third interconnect structure, the fourth interconnect structure and the fifth interconnect structure all include a second conductive material, wherein the first conductive material is different from the second conductive material.

[0020] In one optional embodiment, the semiconductor device further includes: An insulating layer is located between the first connection structure and the device layer, between the second connection structure and the device layer, between the third connection structure and the device layer, and between the fourth connection structure and the device layer.

[0021] In one optional embodiment, the semiconductor device further includes: A redistribution layer and a pad lead-out layer are located on the side of the device layer opposite each other along the first direction, away from the interconnect layer; the redistribution layer is located between the device layer and the pad lead-out layer; the pad lead-out layer includes pads coupled to the first connection structure, pads coupled to the second connection structure, pads coupled to the third connection structure, and pads coupled to the fourth connection structure through the redistribution layer.

[0022] In one alternative embodiment, the second semiconductor structure includes a memory array; the device layer includes logic circuitry coupled to the memory array; and the interconnect layer includes a power distribution network and a signal transmission network coupled to the logic circuitry. The first connection structure belongs to the power distribution network or the signal transmission network; the second connection structure and the third connection structure belong to the power distribution network or the signal transmission network; the fourth connection structure belongs to the power distribution network or the signal transmission network.

[0023] In one optional embodiment, the semiconductor device further includes: A third semiconductor structure is stacked and bonded to the second semiconductor structure along the first direction; the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure.

[0024] In the technical solution provided in this disclosure, the method for forming a semiconductor device includes simultaneously forming multiple connection structures that penetrate the device layer along a first direction and land on different sub-interconnect layers. The dimensions of the different connection structures in the first direction can be different, and their connection methods with the sub-interconnect layers can also be different. This allows for the simultaneous formation of connection structures suitable for transmitting power supply voltages and connection structures suitable for transmitting data signals / clock signals. On one hand, the simultaneous formation of multiple different connection structures can improve the manufacturing efficiency of semiconductor devices and help save process costs. On the other hand, the connection structures for transmitting power supply voltages and the connection structures for transmitting data signals / clock signals can land on different sub-interconnect layers, which can avoid excessive load and heat concentration on a single sub-interconnect layer, thus helping to distribute the load in the interconnect layer and improve the heat dissipation efficiency of the interconnect layer. Furthermore, the formed transmission paths can include parallel transmission paths and can incorporate decoupling capacitors, which can improve the reliability of electrical signal transmission, thereby improving the reliability of the semiconductor device. Attached Figure Description

[0025] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor device according to an embodiment of this disclosure; Figure 2 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 1 ; Figure 3 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 2 ; Figure 4 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 3 ; Figure 5A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 4 ; Figure 6 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 5 ; Figure 7 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 6 ; Figure 8 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 7 ; Figure 9 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 8 ; Figure 10 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 9 ; Figure 11 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 1 ; Figure 12 This is a top view of the first connection structure provided in an embodiment of the present disclosure; Figure 13 This is a top view of the second and third connection structures provided in the embodiments of this disclosure; Figure 14 This is a top view of the fourth connection structure provided in an embodiment of the present disclosure; Figure 15 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 2 . Detailed Implementation

[0026] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0028] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0029] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] In the manufacturing of computing chips, the use of hybrid bonding technology to achieve high-density integration of logic chips and memory chips has become a mainstream trend. Current process routes include face-to-face (F2F) bonding of logic chips and memory chips and face-to-back (F2B) bonding of logic chips and memory chips. After face-to-face bonding, through-silicon vias (TSVs) can be formed on the back side of the logic chip, and a pad lead-out layer can be formed on the back side of the logic chip. The TSV can land on the wiring layer on the front side of the logic chip and transmit the power and signals received by the pads in the pad lead-out layer to the wiring layer on the front side of the logic chip to provide power and signals to the logic chip and the memory chip. Before face-to-back bonding, TSVs can be formed on the back side of the logic chip. The TSVs can land on the wiring layer on the front side of the logic chip. After the front side of the memory chip and the back side of the logic chip are bonded, a pad lead-out layer can be formed on the wiring layer on the front side of the logic chip. The TSV can transmit the power and signals received by the pads in the pad lead-out layer to the wiring layer on the back side of the logic chip to provide power and signals to the logic chip and the memory chip.

[0032] Both of the aforementioned technical approaches require the formation of multiple TSVs within the logic chip. The landing layer for these multiple TSVs is typically a single routing layer, which may lead to high IR drops in either the power or signal lines, and could also cause overload on that routing layer. All of these factors can reduce the reliability of the computing chip. Therefore, optimizing the TSV landing method has become an urgent problem to be solved.

[0033] The present disclosure provides the following implementation methods.

[0034] This disclosure provides a method for forming a semiconductor device. Figure 1 This is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present disclosure. The method for forming a semiconductor device includes the following steps: Step S1: Stack and bond the first semiconductor structure and the second semiconductor structure along a first direction; the first semiconductor structure includes a device layer and an interconnect layer located between the device layer and the second semiconductor structure in the first direction; the interconnect layer includes at least a first sub-interconnect layer and a second sub-interconnect layer, wherein the first sub-interconnect layer is located between the second sub-interconnect layer and the device layer; Step S2: Simultaneously form a first through-hole and a second through-hole extending along the first direction and penetrating the device layer; Step S3: A first connection structure is formed based on the first through-hole, and a second connection structure is formed based on the second through-hole; the first connection structure penetrates the first interconnect structure in the first sub-interconnect layer along the first direction and is connected to the second interconnect structure in the second sub-interconnect layer; the second connection structure penetrates the first electrode plate of the capacitor structure along the first direction and is connected to the third interconnect structure in the first sub-interconnect layer; the capacitor structure is located between the first sub-interconnect layer and the device layer in the first direction.

[0035] In this embodiment, the method for forming a semiconductor device includes simultaneously forming multiple interconnect structures that penetrate device layers. Different interconnect structures can have different landing methods. For example, a first interconnect structure can penetrate a first interconnect structure in a first sub-interconnect layer and can be connected to a second interconnect structure in a second sub-interconnect layer. A second interconnect structure formed simultaneously with the first interconnect structure can penetrate the first electrode of a capacitor structure and can be connected to a third interconnect structure in the first sub-interconnect layer. Furthermore, the signal transmission paths of interconnect structures with different landing methods can have different functions. For example, a signal transmitted through the first interconnect structure, after reaching the interconnect layer, can be transmitted in parallel using the first interconnect structure in the first sub-interconnect layer and the second interconnect structure in the second sub-interconnect layer. This not only reduces the impedance of the signal transmission path but also avoids overload or uneven heat dissipation in a single sub-interconnect layer. The capacitor structure connected to the second interconnect structure can act as a decoupling capacitor. Therefore, the signal transmission path including the second interconnect structure can have higher anti-interference capability and improve signal integrity. Thus, the semiconductor device formation method provided by this disclosure not only improves the flexibility of setting interconnect structures in semiconductor devices but also improves the reliability of signal transmission using interconnect structures.

[0036] In some embodiments, Figures 2 to 10 This is a schematic diagram of the formation process of a semiconductor device provided in an embodiment of this disclosure. The following will be combined with... Figures 1 to 10 The method for forming the semiconductor device provided in this disclosure is described in detail.

[0037] In some embodiments, refer to Figure 2 Step S1 is executed: the first semiconductor structure 10 and the second semiconductor structure 20 are stacked and bonded along a first direction; the first semiconductor structure 10 includes a device layer 100 and an interconnect layer 110 located between the device layer 100 and the second semiconductor structure 20 in the first direction; the interconnect layer 110 includes at least a first sub-interconnect layer 111 and a second sub-interconnect layer 112, the first sub-interconnect layer 111 being located between the second sub-interconnect layer 112 and the device layer 100. Here, the first direction is taken as the Z direction.

[0038] In some specific examples, the first semiconductor structure 10 and the second semiconductor structure 20 can be bonded using a hybrid bonding process, forming a hybrid bonding layer (not shown in the figure) between the first semiconductor structure 10 and the second semiconductor structure 20. This hybrid bonding layer can include multiple bonding structures. The interconnect structures in the interconnect layer 110 can be coupled to the bonding structures and further coupled to the circuit structures in the second semiconductor structure 20 via the bonding structures. In some specific examples, the device layer 100 can include logic circuitry, and the second semiconductor structure 20 can include a memory array. The logic circuitry can then be coupled to the memory array via the interconnect structures in the interconnect layer 110 and the bonding structures in the hybrid bonding layer.

[0039] It should be noted that, since the processes related to forming the connection structure after step S1 are mainly performed on the side where the first semiconductor structure 10 is located, for the sake of simplicity, Figures 3 to 9 The second semiconductor structure 20 is omitted in both cases.

[0040] In some embodiments, in conjunction with reference Figure 2 and Figure 3 The method for forming a semiconductor device further includes: before performing step S2, thinning the device layer 100 from the side of the first semiconductor structure 10 away from the second semiconductor structure 20, and forming a hard mask layer 201 on the thinned device layer 100. Here, the device layer 100 may include a semiconductor substrate and a circuit structure formed in the semiconductor substrate, and the circuit structure is located on the side closer to the second semiconductor structure 20. The thinning process can remove the portion of the semiconductor substrate where no circuit structure is formed.

[0041] In some embodiments, in conjunction with reference Figure 3 and Figure 4 The method for forming a semiconductor device further includes: forming a patterned mask layer 202 on a hard mask layer 201. The patterned mask layer 202 may include a plurality of opening patterns, each corresponding to the position of a via formed in a subsequent step.

[0042] In some embodiments, in conjunction with reference Figure 4 and Figure 5 Step S2 is executed, and a first via 301 and a second via 302 extending along the first direction and penetrating the device layer 100 are formed. The specific process may include: etching the hard mask layer 201 and the device layer 100 with a patterned mask layer 202 as a mask to form the first via 301 and the second via 302 penetrating the device layer 100 along the first direction.

[0043] In some embodiments, in conjunction with reference Figure 4 and Figure 5The method for forming a semiconductor device further includes forming a third through-hole 303 that penetrates the device layer 100 along a first direction while forming a first through-hole 301 and a second through-hole 302.

[0044] In some embodiments, in conjunction with reference Figure 4 and Figure 5 The method for forming a semiconductor device further includes forming a fourth through-hole 304 that penetrates the device layer 100 along a first direction while forming the first through-hole 301, the second through-hole 302 and the third through-hole 303.

[0045] In some specific examples, the first via 301, the second via 302, the third via 303, and the fourth via 304 all extend into the dielectric layer of the interconnect layer 110 and have the same dimensions in the first direction.

[0046] In some embodiments, in conjunction with reference Figures 5 to 9 Step S3 is executed: a first connection structure 331 is formed based on the first through-hole 301, and a second connection structure 332 is formed based on the second through-hole 302; the first connection structure 331 penetrates the first interconnect structure 1111 in the first sub-interconnect layer 111 along the first direction and is connected to the second interconnect structure 1121 in the second sub-interconnect layer 112; the second connection structure 332 penetrates the first electrode plate 1141 of the capacitor structure 114 along the first direction and is connected to the third interconnect structure 1112 in the first sub-interconnect layer 111; the capacitor structure 114 is located between the first sub-interconnect layer 111 and the device layer 100 in the first direction.

[0047] In some embodiments, in conjunction with reference Figures 5 to 9 The method for forming a semiconductor device further includes: while forming a first connection structure 331 and a second connection structure 332, forming a third connection structure 333 based on a third through-hole 303; the third connection structure 333 penetrates the second electrode 1142 of the capacitor structure 114 along a first direction and is connected to the fourth interconnect structure 1113 in the first sub-interconnect layer 111; the first electrode 1141 and the second electrode 1142 of the capacitor structure 114 are arranged along the first direction.

[0048] In some embodiments, in conjunction with reference Figures 5 to 9 The interconnect layer 110 further includes a third sub-interconnect layer 113; the third sub-interconnect layer 113 is located between the second semiconductor structure 20 and the second sub-interconnect layer 112; the method of forming the semiconductor device further includes: while forming the first connection structure 331, the second connection structure 332 and the third connection structure 333, forming a fourth connection structure 334 based on the fourth via 304; the fourth connection structure 334 is connected to the fifth interconnect structure 1131 in the third sub-interconnect layer 113.

[0049] In some embodiments, forming a first connection structure 331 based on a first through hole 301, forming a second connection structure 332 based on a second through hole 302, forming a third connection structure 333 based on a third through hole 303, and forming a fourth connection structure 334 based on a fourth through hole 304 includes: in conjunction with a reference Figure 5 and Figure 7 The first etching operation includes simultaneously etching the interconnect layer 110 along the first via 301, the second via 302, the third via 303, and the fourth via 304 to form the fifth via 311, the sixth via 312, the seventh via 313, and the eighth via 314; the bottom of the fifth via 311 exposes the first interconnect structure 1111, the bottom of the sixth via 312 exposes the first electrode 1141, the bottom of the seventh via 313 exposes the second electrode 1142, and the bottom of the eighth via 314 exposes the dielectric layer in the first sub-interconnect layer 111. Here, in the first etching operation, the etching along the first via 301 can stop on the first interconnect structure 1111, the etching along the second via 302 can stop on the first electrode 1141, the etching along the third via 303 can stop on the second electrode 1142, and the etching along the fourth via 304 can stop in the dielectric layer of the interconnect layer 110. Therefore, the dimensions of the fifth via 311, the sixth via 312, the seventh via 313, and the eighth via 314 formed by the first etching operation can be different in the first direction.

[0050] In some embodiments, forming a first connection structure 331 based on a first through hole 301, forming a second connection structure 332 based on a second through hole 302, forming a third connection structure 333 based on a third through hole 303, and forming a fourth connection structure 334 based on a fourth through hole 304, further includes: referring to... Figure 7 and Figure 8 The second etching operation includes: simultaneously etching the interconnect layer 110 along the fifth via 311, the sixth via 312, the seventh via 313, and the eighth via 314 to form the ninth via 321, the tenth via 322, the eleventh via 323, and the twelfth via 324; the ninth via 321 penetrates the first interconnect structure 1111 and exposes the second interconnect structure 1121; the tenth via 322 penetrates the first electrode plate 1141 and exposes the third interconnect structure 1112; the eleventh via 323 penetrates the second electrode plate 1142 and exposes the fourth interconnect structure 1113; and the twelfth via 324 exposes the fifth interconnect structure 1131.

[0051] In some embodiments, in conjunction with reference Figure 7 and Figure 8Before performing the second etching operation, the first interconnect structure 1111 includes an opening filled with a dielectric material. The second etching operation specifically includes: etching the dielectric material filling the opening to expose the opening, and etching along the opening between the first interconnect structure 1111 and the second interconnect structure 1121 to form a first sub-via 3212 exposing the second interconnect structure 1121. The first sub-via 3212 communicates with the fifth via 311 and constitutes a ninth via 321. The dimension of the first sub-via 3212 in the second direction is smaller than the dimension of the fifth via 311 in the second direction. The second direction is perpendicular to the first direction. Here, the second direction can be, for example, the X direction.

[0052] In some embodiments, both the first electrode 1141 and the second electrode 1142 include a first conductive material, and the first interconnect structure 1111, the second interconnect structure 1121, the third interconnect structure 1112, the fourth interconnect structure 1113, and the fifth interconnect structure 1131 all include a second conductive material. The first conductive material is different from the second conductive material. (Referring to a reference...) Figure 7 and Figure 8 The second etching operation specifically includes: etching the exposed first electrode 1141 and the dielectric material between the first electrode 1141 and the third interconnect structure 1112 along the sixth via 312 until the third interconnect structure 1112 is exposed to form the tenth via 322; etching the exposed second electrode 1142 and the dielectric material between the second electrode 1142 and the fourth interconnect structure 1113 along the seventh via 313 until the fourth interconnect structure 1113 is exposed to form the eleventh via 323.

[0053] In some specific examples, both the first and second etching operations can be plasma etching (PE).

[0054] In some specific examples, the dielectric material in interconnect layer 110 includes silicon oxide, and the first conductive material included in the first electrode 1141 and the second electrode 1142 may include one of polysilicon, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, germanium, and germanium silicon. The second conductive material included in the first interconnect structure 1111, the second interconnect structure 1121, the third interconnect structure 1112, the fourth interconnect structure 1113, and the fifth interconnect structure 1131 may include one of copper, aluminum, tungsten, titanium, and titanium nitride. In the second etching operation, both the dielectric material and the first conductive material in interconnect layer 110 have a higher etching selectivity than the second conductive material, and the etching rate of the dielectric material is higher than the etching rate of the first conductive material. Therefore, the dielectric material in interconnect layer 110, the first electrode 1141, and the second electrode 1142 can be etched simultaneously, while the first interconnect structure 1111, the second interconnect structure 1121, the third interconnect structure 1112, the fourth interconnect structure 1113, and the fifth interconnect structure 1131 will not be etched.

[0055] In this disclosure embodiment, in conjunction with reference to Figure 7 and Figure 8 In the second etching operation, the etching along the fifth via 311 is based on the opening in the first interconnect structure 1111, and the size of the opening in the first interconnect structure 1111 in the second direction is smaller than the size of the fifth via 311 in the second direction, which will limit the etching rate to a certain extent. The second interconnect structure 1121 located in the second sub-interconnect layer 112 can be used as its etching stop layer. The etching along the sixth via 312 requires etching the first electrode plate 1141 including the first conductive material, and the etching along the seventh via 313 requires etching the second electrode plate 1142 including the first conductive material. Therefore, their etching rates are both low, and the interconnect structures (the third interconnect structure 1112 and the fourth interconnect structure 1113) in the first sub-interconnect layer 111 can be used as their etching stop layers. The etching along the eighth via 314 only requires etching the dielectric layer of the interconnect layer located on the fifth interconnect structure 1131. Therefore, its etching rate is relatively high, and the fifth interconnect structure 1131 in the third sub-interconnect layer 113 can be used as its etching stop layer. Due to differences in etching rates and etching stop layers, the dimensions of the ninth through-hole 321, tenth through-hole 322, eleventh through-hole 323, and twelfth through-hole 324 formed by the second etching operation can be different in the first direction. Specifically, the dimension of the twelfth through-hole 324 in the first direction is larger than that of the ninth through-hole 321 in the first direction, and the dimension of the ninth through-hole 321 in the first direction is larger than that of the tenth through-hole 322 and the eleventh through-hole 323 in the first direction.

[0056] In some embodiments, in conjunction with reference Figure 5 and Figure 6The method for forming a semiconductor device further includes: before performing the first etching operation, forming an insulating layer 305 covering the inner walls of the first through-hole 301, the second through-hole 302, the third through-hole 303, and the fourth through-hole 304; in conjunction with reference to... Figure 6 and Figure 7 The first etching operation specifically includes etching portions of the insulating layer 305 located at the bottom of the first via 301, the bottom of the second via 302, the bottom of the third via 303, and the bottom of the fourth via 304. Here, the insulating layer 305 may, for example, include silicon nitride, which can protect the device layer 100 during the first and second etching operations, preventing damage to the circuit structure within the device layer 100 during these operations.

[0057] In some embodiments, in conjunction with reference Figure 8 and Figure 9 The first connection structure 331 is formed based on the first through hole 301, the second connection structure 332 is formed based on the second through hole 302, the third connection structure 333 is formed based on the third through hole 303, and the fourth connection structure 334 is formed based on the fourth through hole 304. The method further includes filling the ninth through hole 321, the tenth through hole 322, the eleventh through hole 323 and the twelfth through hole 324 with a third conductive material to form the first connection structure 331, the second connection structure 332, the third connection structure 333 and the fourth connection structure 334.

[0058] In some embodiments, in conjunction with reference Figure 9 and Figure 10 The method for forming a semiconductor device further includes: forming a redistribution layer 401 and a pad lead-out layer 402 on one side of the device layer 100 that is away from the interconnect layer 110 along the first direction; the pad lead-out layer 402 includes a pad coupled to a first connection structure 331 through the redistribution layer 401, a pad coupled to a second connection structure 332, a pad coupled to a third connection structure 333, and a pad coupled to a fourth connection structure 334.

[0059] In some embodiments, Figure 11This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure. The semiconductor device can be obtained by the semiconductor device forming method provided in the above embodiments. In the semiconductor device, the second semiconductor structure 20 may include a memory array; the device layer 100 may include logic circuits coupled to the memory array; the interconnect layer 110 may include a power distribution network and a signal transmission network coupled to the logic circuit; the first connection structure 331 may belong to the power distribution network or the signal transmission network; the second connection structure 332 and the third connection structure 333 may belong to the power distribution network or the signal transmission network; the fourth connection structure 334 may belong to the power distribution network or the signal transmission network.

[0060] Here, the power distribution network can be configured to transmit power supply voltage. Specifically, the power distribution network can be coupled to the power pads in the pad lead-out layer 401 through the connection structure, and the power pads can be connected to an external power supply. Then, the power supply voltage provided by the external power supply can be provided to the circuit structure in the semiconductor device through the power pads, the connection structure, and other interconnect structures in the interconnect layer 110. The signal transmission network can be configured to transmit data signals and clock signals. Specifically, the signal transmission network can be coupled to the signal pads in the pad lead-out layer 402 through the connection structure. Then, the data signals / clock signals can be transmitted to the circuit structure in the semiconductor device through the signal pads, the connection structure, and other interconnect structures in the interconnect layer 110.

[0061] In some specific examples, Figure 12 This is a top view of the first connection structure 331 provided in an embodiment of this disclosure. The figure also shows the first interconnect structure 1111 and the second interconnect structure 1121, with some structures shown in perspective. (Refer to reference...) Figure 10 , Figure 11 and Figure 12The first interconnect structure 331 formed by the semiconductor device formation method provided in the above embodiments includes a first part 3311 and a second part 3312 connected together; the first part 3311 penetrates the device layer 100 along a first direction and penetrates the dielectric layer between the first interconnect structure 1111 and the device layer 100, and the bottom of the first part 3311 lands on the first interconnect structure 1111; the second part 3312 penetrates the first interconnect structure 1111 and is connected to the second interconnect structure 1121, then the sidewall of the second part 3312 is connected to the first interconnect structure 1111, and the bottom of the second part 3312 lands on the second interconnect structure 1121. The first connection structure 331 can be simultaneously connected to the first interconnect structure 1111 in the first sub-interconnect layer 111 and the second interconnect structure 1121 in the second sub-interconnect layer 112. The first interconnect structure 1111 and the second interconnect structure 1121 can form a parallel transmission path, which can reduce the overall impedance of the transmission path, reduce the transmission delay of electrical signals, and reduce the load of a single sub-interconnect layer, forming a distributed heat dissipation path and avoiding local overheating. In addition, the parallel transmission paths can serve as redundant transmission paths for each other. When one transmission path fails, the other transmission path can still transmit electrical signals, thereby effectively improving the yield of semiconductor devices.

[0062] Here, the first connection structure 331, the first interconnect structure 1111, and the second interconnect structure 1121 can belong to either a power distribution network or a signal transmission network. When the first connection structure 331, the first interconnect structure 1111, and the second interconnect structure 1121 belong to a power distribution network, the semiconductor device can be powered through parallel transmission paths, which can reduce the impedance of the power distribution network and alleviate problems such as increased power consumption caused by IR drop. When the first connection structure 331, the first interconnect structure 1111, and the second interconnect structure 1121 belong to a signal transmission network, data signals / clock signals can be transmitted through parallel transmission paths, which can improve the reliability of signal transmission. In addition, since the first interconnect structure 1111 and the second interconnect structure 1121 are located in the sub-interconnect layer close to the device layer 100, the transmission path of the signal from the first connection structure 331 to the device layer 100 is shorter, which can reduce signal transmission delay and crosstalk, and further improve the reliability of signal transmission.

[0063] In some specific examples, Figure 13 This illustration provides a top view of the second connection structure 332 and the third connection structure 333 according to embodiments of this disclosure. The figure also shows the first electrode plate 1141, the second electrode plate 1142, the third interconnection structure 1112, and the fourth interconnection structure 1113, with some structures shown in perspective. (Refer to reference...) Figure 10 , Figure 11 and Figure 13The second connection structure 332 and the third connection structure 333 formed by the semiconductor device formation method provided in the above embodiments can respectively penetrate the first electrode 1141 and the second electrode 1142 of the capacitor structure, and can be connected to the third interconnect structure 1112 and the fourth interconnect structure 1113 in the first sub-interconnect layer 111, respectively. One of the second connection structure 332 and the third connection structure 333 can be coupled to the ground pad in the pad lead-out layer 402, and the other can be connected to the power pad or the signal pad. The capacitor structure including the first electrode 1141, the second electrode 1142 and the dielectric layer between the first electrode 1141 and the second electrode 1142 can be used as a decoupling capacitor to bypass noise in the transmission path, which is beneficial to improve signal integrity.

[0064] Here, when the second connection structure 332, the third connection structure 333, the third interconnection structure 1112, and the fourth interconnection structure 1113 belong to a power distribution network, decoupling capacitors can be connected in the power distribution network to improve its decoupling capability and reduce power supply noise. When the second connection structure 332, the third connection structure 333, the third interconnection structure 1112, and the fourth interconnection structure 1113 belong to a signal transmission network, decoupling capacitors can be connected in the signal transmission network to improve the anti-interference capability of high-speed signal lines and enhance the reliability of signal transmission. Furthermore, since the third interconnection structure 1112 and the fourth interconnection structure 1113 are both located in the first sub-interconnection layer 111 close to the device layer 100, the transmission path of the signal from one of the second connection structure 332 and the third connection structure 333 to the device layer 100 is shorter, which can reduce signal transmission delay and further improve the reliability of signal transmission.

[0065] In some specific examples, Figure 14 This is a top view schematic diagram of the fourth connection structure 334 provided in an embodiment of the present disclosure, which also shows a fifth interconnection structure 1131. (Referring to...) Figure 10 , Figure 11 and Figure 14The fourth interconnect structure 334 formed by the semiconductor device formation method provided in the above embodiments is coupled to the fifth interconnect structure 1131 in the third sub-interconnect layer 113. The fourth interconnect structure 334 and the fifth interconnect structure 1131 can belong to a power distribution network, and the interconnect structure in the third sub-interconnect layer 113 can serve as a global power network in the power distribution network. The fourth interconnect structure 334 can be coupled to the power pads in the pad lead-out layer 402, and can directly transmit the power voltage to the global power network, thereby reducing the resistance on the power voltage transmission path. In addition, the fourth interconnect structure 334 and the fifth interconnect structure 1131 can belong to a signal transmission network. The fourth interconnect structure 334 can be coupled to the signal pads in the pad lead-out layer 402, so the transmission path of the signal to the second semiconductor structure 20 can be shorter, which can reduce the delay of the signal transmission to the second semiconductor structure 20.

[0066] In the embodiments of this disclosure, the semiconductor device formation method provided by the above implementation can simultaneously form multiple connection structures that penetrate the device layer along a first direction and land on different sub-interconnect layers. The dimensions of the different connection structures in the first direction can be different, and the connection methods with the sub-interconnect layers can also be different. This allows for the simultaneous formation of connection structures suitable for transmitting power supply voltage and connection structures suitable for transmitting data signals / clock signals. On the one hand, the simultaneous formation of multiple different connection structures can improve the production efficiency of semiconductor devices and help save process costs. On the other hand, the connection structures for transmitting power supply voltage and the connection structures for transmitting data signals / clock signals can land on different sub-interconnect layers, which can avoid excessive load and heat concentration in a single sub-interconnect layer, thus helping to distribute the load in the interconnect layer and improve the heat dissipation efficiency of the interconnect layer. Furthermore, the formed transmission path can include parallel transmission paths and can be connected with decoupling capacitors, which can improve the reliability of electrical signal transmission, thereby improving the reliability of the semiconductor device.

[0067] The above embodiments take the formation of a semiconductor device including a first semiconductor structure and a second semiconductor structure stacked along a first direction as an example, but this disclosure is not limited thereto. The semiconductor device formation method provided by this disclosure can also form a semiconductor device including two or more semiconductor structures stacked along a first direction, and adjacent semiconductor structures can be bonded together by a hybrid bonding process.

[0068] In some embodiments, refer to Figure 15The method for forming a semiconductor device may further include: forming a third semiconductor structure 50 that is stacked and bonded to the second semiconductor structure 20 along a first direction; the second semiconductor structure 20 is located between the first semiconductor structure 10 and the third semiconductor structure 50. Here, the multiple connection structures penetrating the device layer 100 can be formed after stacking and bonding the first semiconductor structure 10, the second semiconductor structure 20, and the third semiconductor structure 50, or the second semiconductor structure 20 and the third semiconductor structure 50 can be stacked and bonded along the first direction after forming the multiple connection structures penetrating the device layer 100. Similarly, a semiconductor device comprising three or more semiconductor structures stacked along the first direction can also be formed, which will not be described in detail here.

[0069] Based on a concept similar to the formation method of the aforementioned semiconductor device, this disclosure also provides a semiconductor device, in conjunction with reference to... Figure 10 and Figure 11 The semiconductor device includes: a first semiconductor structure 10 and a second semiconductor structure 20 stacked and bonded along a first direction; the first semiconductor structure 10 includes a device layer 100 and an interconnect layer 110 located between the device layer 100 and the second semiconductor structure 20 in the first direction; the interconnect layer 110 includes at least a first sub-interconnect layer 111 and a second sub-interconnect layer 112, the first sub-interconnect layer 111 being located between the second sub-interconnect layer 112 and the device layer 100; a first connection structure 331 and a second connection structure 332 penetrating the device layer 100 along the first direction; the first connection structure 331 penetrating the first interconnect structure 1111 in the first sub-interconnect layer 111 along the first direction and connecting to the second interconnect structure 1121 in the second sub-interconnect layer 112; the second connection structure 332 penetrating the first electrode 1141 of a capacitor structure 114 along the first direction and connecting to the third interconnect structure 1112 in the first sub-interconnect layer 111; the capacitor structure 114 being located between the first sub-interconnect layer 111 and the device layer 100 in the first direction.

[0070] In some embodiments, refer to Figure 10 The semiconductor device further includes: a third connection structure 333 that penetrates the device layer 100 along a first direction; the third connection structure 333 penetrates the second electrode 1142 of the capacitor structure 114 along the first direction and is connected to the fourth interconnect structure 1113 in the first sub-interconnect layer 111; the first electrode 1141 and the second electrode 1142 of the capacitor structure 114 are arranged along the first direction.

[0071] In some embodiments, refer to Figure 10The interconnect layer 110 also includes a third sub-interconnect layer 113; the third sub-interconnect layer 113 is located between the second semiconductor structure 20 and the second sub-interconnect layer 112; the semiconductor device also includes a fourth connection structure 334 that extends through the device layer 100 along a first direction; the fourth connection structure 334 is connected to the fifth interconnect structure 1131 in the third sub-interconnect layer 113.

[0072] In some embodiments, in conjunction with reference Figure 10 , Figure 11 and Figure 12 The first connection structure 331 includes a first part 3311 and a second part 3312 connected together; the first part 3311 penetrates the device layer 100 along a first direction and penetrates the dielectric layer between the first interconnect structure 1111 and the device layer 100; the second part 3312 penetrates the first interconnect structure 1111 and is connected to the second interconnect structure 1121; the size of the second part 3312 in the second direction is smaller than the size of the first part 3311 in the second direction; the second direction is perpendicular to the first direction.

[0073] In some embodiments, the first electrode 1141 and the second electrode 1142 both include a first conductive material, and the first interconnect structure 1111, the second interconnect structure 1121, the third interconnect structure 1112, the fourth interconnect structure 1113 and the fifth interconnect structure 1131 all include a second conductive material, wherein the first conductive material is different from the second conductive material.

[0074] In some embodiments, refer to Figure 10 The semiconductor device also includes an insulating layer 305 located between the first connection structure 331 and the device layer 100, between the second connection structure 332 and the device layer 100, between the third connection structure 333 and the device layer 100, and between the fourth connection structure 334 and the device layer 100.

[0075] In some embodiments, refer to Figure 10 The semiconductor device further includes a redistribution layer 401 and a pad lead-out layer 402 located on the side of the device layer 100 opposite each other along the first direction, away from the interconnect layer 110; the pad lead-out layer 402 includes pads coupled to the first connection structure 331 through the redistribution layer 401, pads coupled to the second connection structure 332, pads coupled to the third connection structure 333, and pads coupled to the fourth connection structure 334.

[0076] In some embodiments, refer to Figure 11The second semiconductor structure 20 includes a memory array; the device layer 100 includes logic circuits coupled to the memory array; the interconnect layer 110 includes a power distribution network and a signal transmission network coupled to the logic circuits; the first connection structure 331 belongs to the power distribution network or the signal transmission network; the second connection structure 332 and the third connection structure 333 belong to the power distribution network or the signal transmission network; and the fourth connection structure 334 belongs to the power distribution network or the signal transmission network.

[0077] In some embodiments, refer to Figure 15 The semiconductor device also includes a third semiconductor structure 50 that is stacked and bonded to the second semiconductor structure 20 along a first direction; the second semiconductor structure 20 is located between the first semiconductor structure 10 and the third semiconductor structure 50.

[0078] It should be noted that the semiconductor device provided in this disclosure can be obtained by the semiconductor device formation method in any of the above embodiments, and the semiconductor device can achieve the same effects as the semiconductor device formation method provided in the above embodiments.

[0079] The semiconductor device provided in this disclosure includes a TSV that connects multiple layers of metal (e.g., a first connection structure 331), a TSV that connects to a lower layer of metal and a decoupling capacitor (e.g., a second connection structure 332 and a third connection structure 333), and a TSV that connects to a higher layer of metal (e.g., a fourth connection structure 334).

[0080] In some specific examples, in conjunction with reference Figure 11 and Figure 12For the multilayer metal TSV that connects across layers, i.e. the first connection structure 331, it can be connected to the interconnect structure in the first sub-interconnect layer 111 and the interconnect structure in the second sub-interconnect layer 112 at the same time. Here, the first sub-interconnect layer 111 may include lower layer metal (e.g., M1 or M2), and the second sub-interconnect layer 112 may include higher layer metal (e.g., M7 or M8). This connection method achieves several advantages. First, it enables three-dimensional current distribution. For example, the interconnect structures in the first sub-interconnect layer 111 and the second sub-interconnect layer 112, which are simultaneously connected to the first connection structure 331, can form parallel transmission paths, thereby reducing the overall impedance of the transmission path (by approximately 40%) and decreasing the transmission delay of electrical signals. Second, it enables redundancy and fault tolerance. The parallel transmission paths can serve as redundant transmission paths for each other. When one transmission path fails, the other transmission path can still transmit electrical signals, thus effectively improving the yield of semiconductor devices. Third, it enables distributed heat dissipation paths. For example, the lower metal layer connected to the sidewall of the second part 3312 of the first connection structure can dissipate local hot spot heat, while the higher metal layer connected to the bottom of the second part 3312 can be used for global heat dissipation. Fourth, it enables electrothermal decoupling. Through multi-layer parallel conductive paths, the mutual interference between power supply noise and thermal stress can be avoided.

[0081] In some specific examples, in conjunction with reference Figure 11 and Figure 13 For the TSVs connected to the lower metal layer and decoupling capacitors, namely the second connection structure 332 and the third connection structure 333, they can penetrate the plates of the capacitor structure 114 and connect to the interconnect structure in the first sub-interconnect layer 111. Here, the first sub-interconnect layer 111 may include a lower metal layer (e.g., M1 or M2) close to the device layer 100. This connection method can, on the one hand, minimize the signal transmission path. For example, when high-speed signal lines (such as clock buses and data buses) are connected to the TSV through the lower metal layer, the signal transmission path can be minimized, thereby reducing the RC delay of signal transmission. On the other hand, since the lower metal layer is close to the transistors in the device layer, the coupling capacitance between signal lines can be reduced, thereby reducing signal crosstalk. Furthermore, since a decoupling capacitor is connected in the signal transmission path, the anti-interference capability of the signal lines can be improved, which is beneficial to improving signal integrity. In some specific examples, refer to the reference... Figure 11 and Figure 14For the TSV connected to the higher-layer metal, i.e., the fourth connection structure 334, it is connected to the interconnect structure in the third sub-interconnect layer 113. Here, the third sub-interconnect layer 113 may include a higher-layer metal (e.g., M7 or M8) located away from the device layer 100. The fourth connection structure 334 may be coupled to the power pads in the pad lead-out layer 402. The interconnect structure in the third sub-interconnect layer 113 can serve as a global power network in the power distribution network. Through this connection method, the power supply voltage can be directly transmitted to the global power network, thereby reducing the resistance on the power supply voltage transmission path.

[0082] In summary, in the embodiments of this disclosure, the semiconductor device may include a variety of TSVs connected to different metal layers and having different functions, which can effectively improve the efficiency of signal transmission, the anti-interference ability and integrity of signals in the semiconductor device, and help improve the reliability of the semiconductor device.

[0083] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0084] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A first semiconductor structure and a second semiconductor structure are stacked and bonded along a first direction; the first semiconductor structure includes a device layer and an interconnect layer located between the device layer and the second semiconductor structure in the first direction; the interconnect layer includes at least a first sub-interconnect layer and a second sub-interconnect layer, wherein the first sub-interconnect layer is located between the second sub-interconnect layer and the device layer. Simultaneously, a first through-hole and a second through-hole are formed that extend along the first direction and penetrate the device layer; A first connection structure is formed based on the first through-hole, and a second connection structure is formed based on the second through-hole; the first connection structure penetrates the first interconnect structure in the first sub-interconnect layer along the first direction and is connected to the second interconnect structure in the second sub-interconnect layer; the second connection structure penetrates the first electrode plate of the capacitor structure along the first direction and is connected to the third interconnect structure in the first sub-interconnect layer; the capacitor structure is located between the first sub-interconnect layer and the device layer in the first direction.

2. The method for forming a semiconductor device according to claim 1, characterized in that, The method for forming the semiconductor device further includes: While forming the first through hole and the second through hole, a third through hole is formed that penetrates the device layer along the first direction; While forming the first connection structure and the second connection structure, a third connection structure is formed based on the third through hole; the third connection structure penetrates the second electrode plate of the capacitor structure along the first direction and is connected to the fourth interconnect structure in the first sub-interconnect layer; the first electrode plate and the second electrode plate of the capacitor structure are arranged along the first direction.

3. The method for forming a semiconductor device according to claim 2, characterized in that, The interconnect layer further includes a third sub-interconnect layer; the third sub-interconnect layer is located between the second semiconductor structure and the second sub-interconnect layer; the method for forming the semiconductor device further includes: While forming the first through hole, the second through hole and the third through hole, a fourth through hole is formed that penetrates the device layer along the first direction; While forming the first connection structure, the second connection structure, and the third connection structure, a fourth connection structure is formed based on the fourth via; the fourth connection structure is connected to the fifth interconnect structure in the third sub-interconnect layer.

4. The method for forming a semiconductor device according to claim 3, characterized in that, The process of forming the first connection structure based on the first through hole, forming the second connection structure based on the second through hole, forming the third connection structure based on the third through hole, and forming the fourth connection structure based on the fourth through hole includes: Performing a first etching operation includes: simultaneously etching the interconnect layer along the first via, the second via, the third via, and the fourth via to form a fifth via, a sixth via, a seventh via, and an eighth via; the bottom of the fifth via exposes the first interconnect structure, the bottom of the sixth via exposes the first electrode plate, the bottom of the seventh via exposes the second electrode plate, and the bottom of the eighth via exposes the dielectric layer in the first sub-interconnect layer; Performing a second etching operation includes: simultaneously etching the interconnect layer along the fifth via, the sixth via, the seventh via, and the eighth via to form a ninth via, a tenth via, an eleventh via, and a twelfth via; the ninth via penetrates the first interconnect structure and exposes the second interconnect structure; the tenth via penetrates the first electrode plate and exposes the third interconnect structure; the eleventh via penetrates the second electrode plate and exposes the fourth interconnect structure; and the twelfth via exposes the fifth interconnect structure.

5. The method for forming a semiconductor device according to claim 4, characterized in that, Prior to performing the second etching operation, the first interconnect structure includes openings filled with a dielectric material; Performing the second etching operation specifically includes: The dielectric material filling the opening is etched to expose the opening, and the dielectric material located between the first interconnect structure and the second interconnect structure is etched along the opening to form a first sub-via exposing the second interconnect structure; the first sub-via communicates with the fifth via and constitutes the ninth via; the size of the first sub-via in the second direction is smaller than the size of the fifth via in the second direction; the second direction is perpendicular to the first direction.

6. The method for forming a semiconductor device according to claim 4, characterized in that, Both the first electrode and the second electrode include a first conductive material, and the first interconnect structure, the second interconnect structure, the third interconnect structure, the fourth interconnect structure, and the fifth interconnect structure all include a second conductive material. The first conductive material is different from the second conductive material. Performing the second etching operation specifically includes: The first electrode exposed and the dielectric material located between the first electrode and the third interconnect structure are etched along the sixth via until the third interconnect structure is exposed to form the tenth via; The second electrode exposed along the seventh via and the dielectric material located between the second electrode and the fourth interconnect structure are etched until the fourth interconnect structure is exposed to form the eleventh via.

7. The method for forming a semiconductor device according to claim 4, characterized in that, The method for forming the semiconductor device further includes: Before performing the first etching operation, an insulating layer is formed covering the inner wall of the first through hole, the inner wall of the second through hole, the inner wall of the third through hole, and the inner wall of the fourth through hole. Performing the first etching operation specifically includes etching the portion of the insulating layer located at the bottom of the first via, the portion located at the bottom of the second via, the portion located at the bottom of the third via, and the portion located at the bottom of the fourth via.

8. The method for forming a semiconductor device according to claim 4, characterized in that, The method of forming the first connection structure based on the first through hole, forming the second connection structure based on the second through hole, forming the third connection structure based on the third through hole, and forming the fourth connection structure based on the fourth through hole further includes: Meanwhile, a third conductive material is filled into the ninth, tenth, eleventh, and twelfth through holes to form the first connection structure, the second connection structure, the third connection structure, and the fourth connection structure.

9. The method for forming a semiconductor device according to claim 3, characterized in that, The method for forming the semiconductor device further includes: A redistribution layer and a pad lead-out layer are formed on one side of the device layer opposite to each other along the first direction, away from the interconnect layer; the redistribution layer is located between the device layer and the pad lead-out layer; the pad lead-out layer includes pads coupled to the first connection structure, pads coupled to the second connection structure, pads coupled to the third connection structure, and pads coupled to the fourth connection structure through the redistribution layer.

10. The method for forming a semiconductor device according to claim 3, characterized in that, The second semiconductor structure includes a memory array; the device layer includes logic circuitry coupled to the memory array; the interconnect layer includes a power distribution network and a signal transmission network coupled to the logic circuitry. The first connection structure belongs to the power distribution network or the signal transmission network; the second connection structure and the third connection structure belong to the power distribution network or the signal transmission network; the fourth connection structure belongs to the power distribution network or the signal transmission network.

11. The method for forming a semiconductor device according to claim 1, characterized in that, The method for forming the semiconductor device further includes: The third semiconductor structure and the second semiconductor structure are stacked and bonded along the first direction; the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure.

12. A semiconductor device, characterized in that, include: A first semiconductor structure and a second semiconductor structure are stacked and bonded along a first direction; the first semiconductor structure includes a device layer and an interconnect layer located between the device layer and the second semiconductor structure in the first direction; the interconnect layer includes at least a first sub-interconnect layer and a second sub-interconnect layer, wherein the first sub-interconnect layer is located between the second sub-interconnect layer and the device layer; A first connection structure and a second connection structure penetrate the device layer along the first direction; the first connection structure penetrates the first interconnect structure in the first sub-interconnect layer along the first direction and is connected to the second interconnect structure in the second sub-interconnect layer; the second connection structure penetrates the first electrode plate of the capacitor structure along the first direction and is connected to the third interconnect structure in the first sub-interconnect layer; the capacitor structure is located between the first sub-interconnect layer and the device layer in the first direction.

13. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes: A third connection structure extends through the device layer along the first direction; the third connection structure extends through the second electrode of the capacitor structure along the first direction and is connected to the fourth interconnect structure in the first sub-interconnect layer; the first electrode and the second electrode of the capacitor structure are arranged along the first direction.

14. The semiconductor device according to claim 13, characterized in that, The interconnect layer further includes a third sub-interconnect layer; the third sub-interconnect layer is located between the second semiconductor structure and the second sub-interconnect layer; the semiconductor device further includes: A fourth connection structure extends through the device layer along the first direction; the fourth connection structure is connected to a fifth interconnect structure in the third sub-interconnect layer.

15. The semiconductor device according to claim 12, characterized in that, The first connection structure includes a first part and a second part connected together; the first part extends through the device layer along the first direction and through the dielectric layer between the first interconnect structure and the device layer; the second part extends through the first interconnect structure and is connected to the second interconnect structure; the size of the second part in the second direction is smaller than the size of the first part in the second direction; the second direction is perpendicular to the first direction.

16. The semiconductor device according to claim 14, characterized in that, Both the first electrode plate and the second electrode plate include a first conductive material, and the first interconnect structure, the second interconnect structure, the third interconnect structure, the fourth interconnect structure and the fifth interconnect structure all include a second conductive material, wherein the first conductive material is different from the second conductive material.

17. The semiconductor device according to claim 14, characterized in that, The semiconductor device further includes: An insulating layer is located between the first connection structure and the device layer, between the second connection structure and the device layer, between the third connection structure and the device layer, and between the fourth connection structure and the device layer.

18. The semiconductor device according to claim 14, characterized in that, The semiconductor device further includes: A redistribution layer and a pad lead-out layer are located on the side of the device layer opposite each other along the first direction, away from the interconnect layer; the redistribution layer is located between the device layer and the pad lead-out layer; the pad lead-out layer includes pads coupled to the first connection structure, pads coupled to the second connection structure, pads coupled to the third connection structure, and pads coupled to the fourth connection structure through the redistribution layer.

19. The semiconductor device according to claim 14, characterized in that, The second semiconductor structure includes a memory array; the device layer includes logic circuitry coupled to the memory array; the interconnect layer includes a power distribution network and a signal transmission network coupled to the logic circuitry. The first connection structure belongs to the power distribution network or the signal transmission network; the second connection structure and the third connection structure belong to the power distribution network or the signal transmission network; the fourth connection structure belongs to the power distribution network or the signal transmission network.

20. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes: A third semiconductor structure is stacked and bonded to the second semiconductor structure along the first direction; the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure.

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