Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a first dielectric layer located on a substrate and covering a first electrode layer; the first capacitor lamination layer is located on the first dielectric layer of the first capacitor region and the second capacitor region, and the first capacitor lamination layer comprises a second electrode layer, a third electrode layer located on the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer; the first conductive plug is located in the first capacitor region and is electrically connected with the first electrode layer; the second conductive plug is located in the first capacitor region and is electrically connected with the third electrode layer; the third conductive plug is located in the second capacitor region and is electrically connected with the second electrode layer; the fourth conductive plug is located in the second capacitance area and electrically connected with the third electrode layer and the first electrode layer. According to the invention, the capacitor with low withstand voltage value and high capacitance density can be formed, and the capacitor with high withstand voltage value and low capacitance density can also be formed, so that the requirements of forming capacitors with different types and performance parameters on the substrate are met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in materials and design have led to generation after generation of integrated circuits. Each generation features smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of fabricating and manufacturing integrated circuits, requiring similar developments in IC fabrication and manufacturing to achieve these advancements. Throughout the development of integrated circuits, functional density (the number of interconnect devices per chip area) has gradually increased, while geometric dimensions (the smallest components that can be manufactured using specific processes) have gradually decreased.

[0003] One type of capacitor is the metal-insulator-metal (MIM) capacitor, which is commonly used in mixed-signal devices and logic devices such as embedded memories and radio frequency devices. MIM capacitors are typically used to store charge in a variety of semiconductor devices.

[0004] However, the performance of MIM capacitors still needs to be improved. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a first capacitor region and a second capacitor region; a first electrode layer located on the substrate of the first capacitor region and the second capacitor region; a first dielectric layer located on the substrate and covering the first electrode layer; a first capacitor stack located on the first dielectric layer of the first capacitor region and the second capacitor region, wherein the first capacitor stack includes a second electrode layer and a third electrode layer located on the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer; a first conductive plug located in the first capacitor region and electrically connected to the first electrode layer; a second conductive plug located in the first capacitor region and electrically connected to the third electrode layer; a third conductive plug located in the second capacitor region and electrically connected to the second electrode layer; and a fourth conductive plug located in the second capacitor region and electrically connected to both the third electrode layer and the first electrode layer.

[0007] Optionally, the first capacitor region includes a first connection region and a second connection region, and a first sub-capacitor region located between the first connection region and the second connection region; the second capacitor region includes a third connection region and a fourth connection region, and a second sub-capacitor region located between the third connection region and the fourth connection region; the first electrode layer in the first capacitor region is located on the substrate of the first connection region and the first sub-capacitor region and exposes the top of the substrate of the second connection region; the first electrode layer in the second capacitor region is located on the substrate of the second sub-capacitor region and the fourth connection region and exposes the top of the substrate of the third connection region; the second electrode layer in the first capacitor region is located on top of the first electrode layer of the first sub-capacitor region and exposes the top of the first electrode layer of the first connection region and the top of the substrate of the second connection region; the third electrode layer in the first capacitor region is located on the first electrode layer of the first sub-capacitor region. The top of the second electrode layer and the top of the base of the second connection region are exposed, as are the tops of the first electrode layer of the first connection region; the second electrode layer in the second capacitor region is located at the top of the first electrode layer of the second sub-capacitor region and the top of the base of the third connection region, and exposes the top of the first electrode layer of the fourth connection region; the third electrode layer in the second capacitor region is located at the top of the second electrode layer of the second sub-capacitor region and the top of the first electrode layer of the fourth connection region, and exposes the top of the second electrode layer of the third connection region; the first conductive plug is electrically connected to the exposed first electrode layer of the first connection region; the second conductive plug is electrically connected to the third electrode layer at the top of the base of the second connection region; the third conductive plug is electrically connected to the exposed second electrode layer of the third connection region; and the fourth conductive plug is electrically connected to the first and third electrode layers of the fourth connection region.

[0008] Optionally, the semiconductor structure further includes: an interlayer dielectric layer located on the substrate of the first capacitor region and the second capacitor region, and covering the first capacitor stack; a first conductive plug penetrating the interlayer dielectric layer and the first electrode layer of the first connection region, and the sidewall of the first conductive plug being electrically connected to the first electrode layer; a second conductive plug penetrating the interlayer dielectric layer and the third electrode layer of the second connection region, and the sidewall of the second conductive plug being electrically connected to the third electrode layer; a third conductive plug penetrating the interlayer dielectric layer and the second electrode layer of the third connection region, and the sidewall of the third conductive plug being electrically connected to the second electrode layer; and a fourth conductive plug penetrating the interlayer dielectric layer, the third electrode layer and the first electrode layer of the fourth connection region, and the sidewall of the fourth conductive plug being electrically connected to the third electrode layer and the first electrode layer.

[0009] Optionally, the substrate includes a device structure layer and a back-end interconnect layer located on and electrically connected to the device structure layer. The back-end interconnect layer includes a bottom dielectric layer and one or more metal layers located in the bottom dielectric layer, with the topmost metal layer serving as the top metal layer. The first conductive plug is also electrically connected to the top metal layer, the second conductive plug is also electrically connected to the top metal layer, the third conductive plug is also electrically connected to the top metal layer, and the fourth conductive plug is also electrically connected to the top metal layer.

[0010] Optionally, the substrate may also include an etch stop layer located on the bottom dielectric layer and covering the top metal layer, and a top dielectric layer located on the etch stop layer.

[0011] Optionally, the semiconductor structure further includes an interconnect layer located on the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, and the interconnect layer is electrically connected to the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, respectively.

[0012] Optionally, the second dielectric layer is made of the same material as the first dielectric layer.

[0013] Optionally, the material of the first dielectric layer includes hafnium oxide, aluminum oxide, or zirconium oxide; the material of the second dielectric layer includes hafnium oxide, aluminum oxide, or zirconium oxide.

[0014] Optionally, the material of the first electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; the material of the second electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; and the material of the third electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0015] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including a first capacitor region and a second capacitor region; forming a first electrode layer on the substrate of the first capacitor region and the substrate of the second capacitor region; forming a first dielectric layer covering the first electrode layer on the substrate; after forming the first dielectric layer, forming a first capacitor stack on the first dielectric layer of the first capacitor region and the second capacitor region, the first capacitor stack including a second electrode layer and a third electrode layer located on the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer; forming a first conductive plug electrically connected to the first electrode layer in the first capacitor region, forming a second conductive plug in the first capacitor region, the second conductive plug being electrically connected to the third electrode layer; forming a third conductive plug electrically connected to the second electrode layer in the second capacitor region, and forming a fourth conductive plug electrically connected to the third electrode layer and the first electrode layer in the second capacitor region.

[0016] Optionally, in the step of providing the substrate, the first capacitor region includes a first connection region and a second connection region, and a first sub-capacitor region located between the first connection region and the second connection region; the second capacitor region includes a third connection region and a fourth connection region, and a second sub-capacitor region located between the third connection region and the fourth connection region; in the step of forming the first electrode layer, the first electrode layer in the first capacitor region is located on the substrate of the first connection region and the first sub-capacitor region and exposes the top of the substrate of the second connection region; the first electrode layer in the second capacitor region is located on the substrate of the second sub-capacitor region and the fourth connection region and exposes the top of the substrate of the third connection region; in the step of forming the first capacitor stack, the second electrode layer in the first capacitor region is located on top of the first electrode layer of the first sub-capacitor region and exposes the top of the first electrode layer of the first connection region and the top of the substrate of the second connection region; the third electrode layer in the first capacitor region is located on top of the second electrode layer of the first sub-capacitor region and the top of the substrate of the second connection region. The first conductive plug is electrically connected to the exposed first electrode layer of the first connection region at the top of the substrate of the second sub-capacitor region; the second electrode layer of the second capacitor region is located at the top of the first electrode layer of the second sub-capacitor region and the top of the substrate of the third connection region, and exposes the top of the first electrode layer of the fourth connection region; the third electrode layer of the second capacitor region is located at the top of the second electrode layer of the second sub-capacitor region and the top of the first electrode layer of the fourth connection region, and exposes the top of the second electrode layer of the third connection region; in the step of forming the first conductive plug, the first conductive plug is electrically connected to the exposed first electrode layer of the first connection region; in the step of forming the second conductive plug, the second conductive plug is electrically connected to the third electrode layer at the top of the substrate of the second connection region; in the step of forming the third conductive plug, the third conductive plug is electrically connected to the exposed second electrode layer of the third connection region; in the step of forming the fourth conductive plug, the fourth conductive plug is electrically connected to the first electrode layer and the third electrode layer of the fourth connection region.

[0017] Optionally, the step of forming the first electrode layer includes: forming a first electrode material layer on the substrate of the first capacitor region and the second capacitor region; removing the first electrode material layer on the second connection region and the third connection region, and using the remaining first electrode material layer located on the first connection region and the first sub-capacitor region, and located on the second sub-capacitor region and the fourth connection region as the first electrode layer.

[0018] Optionally, the step of forming the first capacitor stack includes: forming a second electrode material layer on top of the first electrode layer in the first connection region and the first sub-capacitor region, on top of the substrate of the second connection region, on top of the substrate of the third connection region, and on top of the first electrode layer in the second sub-capacitor region and the fourth connection region; removing the second electrode material layer on top of the substrate of the first connection region and the second connection region, and on top of the substrate of the fourth connection region, and using the remaining second electrode material layer on top of the first electrode layer in the first sub-capacitor region, on top of the substrate of the third connection region, and on top of the first electrode layer in the second sub-capacitor region as the second electrode layer; forming a second dielectric layer covering the second electrode layer; after forming the second dielectric layer, forming a third electrode material layer on top of the second electrode layer and the first electrode layer on the substrate, removing the third electrode material layer in the first connection region and the fourth connection region, and using the remaining third electrode material layer on top of the first sub-capacitor region and the second connection region, and on top of the second sub-capacitor region and the fourth connection region as the third electrode layer, and the second electrode layer, the second dielectric layer, and the third electrode layer constitute the first capacitor stack.

[0019] Optionally, after forming the first capacitor stack and before forming the first conductive plug, second conductive plug, third conductive plug, and fourth conductive plug, the forming method further includes: forming an interlayer dielectric layer covering the first capacitor stack on the substrate of the first capacitor region and the second capacitor region; the step of forming the first conductive plug and the second conductive plug includes: forming a first opening penetrating the interlayer dielectric layer and the first electrode layer in the first connection region; forming a second opening penetrating the interlayer dielectric layer and the third electrode layer in the second connection region; filling the first opening and the second opening with conductive material, using the conductive material in the first opening as the first conductive plug, and electrically connecting the sidewall of the first conductive plug to the first electrode layer. The conductive material in the second opening serves as the second conductive plug, and the sidewall of the second conductive plug is electrically connected to the third electrode layer; the steps of forming the third conductive plug and the fourth conductive plug include: forming a third opening in the third connection region that penetrates the interlayer dielectric layer and the first electrode layer; forming a fourth opening in the fourth connection region that penetrates the interlayer dielectric layer, the third electrode layer and the first electrode layer; filling the third opening and the fourth opening with conductive material, using the conductive material in the third opening as the third conductive plug, and the sidewall of the third conductive plug being electrically connected to the first electrode layer, and using the conductive material in the fourth opening as the fourth conductive plug, and the sidewall of the fourth conductive plug being electrically connected to the third electrode layer and the first electrode layer.

[0020] Optionally, the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug are formed in the same step.

[0021] Optionally, in the step of providing the substrate, the substrate includes a device structure layer and a back-end interconnect layer located on and electrically connected to the device structure layer, the back-end interconnect layer including a bottom dielectric layer and one or more metal layers located in the bottom dielectric layer, and the topmost metal layer is used as the top metal layer; in the step of forming the first conductive plug and the second conductive plug, the first conductive plug is also electrically connected to the top metal layer, and the second conductive plug is also electrically connected to the top metal layer; in the step of forming the third conductive plug and the fourth conductive plug, the third conductive plug is also electrically connected to the top metal layer, and the fourth conductive plug is also electrically connected to the top metal layer.

[0022] Optionally, in the step of providing the substrate, the substrate further includes an etch stop layer located on the bottom dielectric layer and covering the top metal layer, and a top dielectric layer located on the etch stop layer.

[0023] Optionally, after forming the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, the method for forming the semiconductor structure further includes: forming an interconnect layer on the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, wherein the interconnect layer is electrically connected to the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, respectively.

[0024] Optionally, the second dielectric layer is made of the same material as the first dielectric layer.

[0025] Optionally, the material of the first dielectric layer includes hafnium oxide, aluminum oxide, or zirconium oxide; the material of the second dielectric layer includes hafnium oxide, aluminum oxide, or zirconium oxide.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0027] The semiconductor structure provided in this embodiment of the invention includes a first capacitor stack located on a first dielectric layer of a first capacitor region and a second capacitor region. The first capacitor stack includes a second electrode layer, a third electrode layer located on the second electrode layer, and a second dielectric layer located between the second and third electrode layers. A first conductive plug is located in the first capacitor region and electrically connected to the first electrode layer. A second conductive plug is located in the first capacitor region and electrically connected to the third electrode layer. A third conductive plug is located in the second capacitor region and electrically connected to the second electrode layer. A fourth conductive plug is located in the second capacitor region and electrically connected to both the third and first electrode layers. In other words, in the first capacitor region, capacitors can be formed between adjacent electrode layers (i.e., between the first and second electrode layers, and between the second and third electrode layers). Since the first conductive plug in the first capacitor region is electrically connected to the first electrode layer, and the second conductive plug is electrically connected to the third electrode layer, the capacitors in the first capacitor region are connected in series, increasing the total capacitance in the first capacitor region. The reduced capacitance value helps to lower the capacitance density of the first capacitor region. Furthermore, the series connection of capacitors in the first capacitor region increases the withstand voltage of the first capacitor region, thereby improving its withstand voltage performance. Correspondingly, in the second capacitor region, capacitors can be formed between adjacent electrode layers (i.e., between the first and second electrode layers, and between the second and third electrode layers). Since the third conductive plug in the second capacitor region is electrically connected to the second electrode layer, and the fourth conductive plug is electrically connected to both the third and first electrode layers, the capacitors in the second capacitor region are connected in parallel, increasing the total capacitance value in the second capacitor region. This helps to increase the capacitance density of the second capacitor region. Moreover, the parallel connection of capacitors in the second capacitor region reduces the withstand voltage of the first capacitor region. Therefore, the embodiments of the present invention can form both capacitors with low withstand voltage and high capacitance density, and capacitors with high withstand voltage and low capacitance density, satisfying the need to form capacitors of different types and performance parameters on a substrate.

[0028] In the semiconductor structure formation method provided by this invention, a first capacitor stack is formed on a first dielectric layer of a first capacitor region and a second capacitor region. The first capacitor stack includes a second electrode layer, a third electrode layer located on the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer. A first conductive plug electrically connected to the first electrode layer is formed in the first capacitor region. A second conductive plug is formed in the first capacitor region and electrically connected to the third electrode layer. A third conductive plug electrically connected to the second electrode layer is formed in the second capacitor region. A fourth conductive plug electrically connected to both the third electrode layer and the first electrode layer is formed in the second capacitor region. That is, in the first capacitor region, capacitors can be formed between adjacent electrode layers (i.e., between the first electrode layer and the second electrode layer, and between the second electrode layer and the third electrode layer). Since the first conductive plug in the first capacitor region is electrically connected to the first electrode layer, and the second conductive plug is electrically connected to the third electrode layer, the capacitors in the first capacitor region are connected in series, making the first electrode layer... The reduction in the total capacitance value in the first capacitor region helps to lower the capacitance density of the first capacitor region. Furthermore, the series connection of capacitors in the first capacitor region increases the withstand voltage of the first capacitor region, thereby improving its withstand voltage performance. Correspondingly, in the second capacitor region, capacitors can be formed between adjacent electrode layers (i.e., between the first and second electrode layers, and between the second and third electrode layers). Since the third conductive plug in the second capacitor region is electrically connected to the second electrode layer, and the fourth conductive plug is electrically connected to both the third and first electrode layers, the capacitors in the second capacitor region are connected in parallel, increasing the total capacitance value in the second capacitor region. This helps to increase the capacitance density of the second capacitor region. Moreover, the parallel connection of capacitors in the second capacitor region reduces the withstand voltage of the first capacitor region. Therefore, the embodiments of the present invention can form capacitors with both low withstand voltage and high capacitance density, as well as capacitors with high withstand voltage and low capacitance density, satisfying the need to form capacitors of different types and performance parameters on a substrate. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0030] Figures 2 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0031] As can be seen from the background technology, the performance of current semiconductor structures needs to be improved.

[0032] To address the technical problem, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including a first capacitor region and a second capacitor region; a first electrode layer located on the substrate of the first capacitor region and the second capacitor region; a first dielectric layer located on the substrate and covering the first electrode layer; a first capacitor stack located on the first dielectric layer of the first capacitor region and the second capacitor region, wherein the first capacitor stack includes a second electrode layer and a third electrode layer located on the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer; a first conductive plug located in the first capacitor region and electrically connected to the first electrode layer; a second conductive plug located in the first capacitor region and electrically connected to the third electrode layer; a third conductive plug located in the second capacitor region and electrically connected to the second electrode layer; and a fourth conductive plug located in the second capacitor region and electrically connected to both the third electrode layer and the first electrode layer.

[0033] The semiconductor structure provided in this embodiment of the invention includes a first capacitor stack located on a first dielectric layer of a first capacitor region and a second capacitor region. The first capacitor stack includes a second electrode layer, a third electrode layer located on the second electrode layer, and a second dielectric layer located between the second and third electrode layers. A first conductive plug is located in the first capacitor region and electrically connected to the first electrode layer. A second conductive plug is located in the first capacitor region and electrically connected to the third electrode layer. A third conductive plug is located in the second capacitor region and electrically connected to the second electrode layer. A fourth conductive plug is located in the second capacitor region and electrically connected to both the third and first electrode layers. In other words, in the first capacitor region, capacitors can be formed between adjacent electrode layers (i.e., between the first and second electrode layers, and between the second and third electrode layers). Since the first conductive plug in the first capacitor region is electrically connected to the first electrode layer, and the second conductive plug is electrically connected to the third electrode layer, the capacitors in the first capacitor region are connected in series, increasing the total capacitance in the first capacitor region. The reduced capacitance value helps to lower the capacitance density of the first capacitor region. Furthermore, the series connection of capacitors in the first capacitor region increases the withstand voltage of the first capacitor region, thereby improving its withstand voltage performance. Correspondingly, in the second capacitor region, capacitors can be formed between adjacent electrode layers (i.e., between the first and second electrode layers, and between the second and third electrode layers). Since the third conductive plug in the second capacitor region is electrically connected to the second electrode layer, and the fourth conductive plug is electrically connected to both the third and first electrode layers, the capacitors in the second capacitor region are connected in parallel, increasing the total capacitance value in the second capacitor region. This helps to increase the capacitance density of the second capacitor region. Moreover, the parallel connection of capacitors in the second capacitor region reduces the withstand voltage of the first capacitor region. Therefore, the embodiments of the present invention can form both capacitors with low withstand voltage and high capacitance density, and capacitors with high withstand voltage and low capacitance density, satisfying the need to form capacitors of different types and performance parameters on a substrate.

[0034] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] refer to Figure 1 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0036] The semiconductor structure includes: a substrate 200, including a first capacitor region 200a and a second capacitor region 200b; a first electrode layer 210 located on the substrate 200 of the first capacitor region 200a and the second capacitor region 200b; a first dielectric layer 215 located on the substrate 200 and covering the first electrode layer 210; and a first capacitor stack 240 located on the first dielectric layer 215 of the first capacitor region 200a and the second capacitor region 200b, wherein the first capacitor stack 240 includes a second electrode layer 220 and a third electrode layer 230 located on the second electrode layer 220. The first conductive plug 280 is located in the first capacitor region 200a and is electrically connected to the first electrode layer 210; the second conductive plug 287 is located in the first capacitor region 200a and is electrically connected to the third electrode layer 230; the third conductive plug 282 is located in the second capacitor region 200b and is electrically connected to the second electrode layer 220; and the fourth conductive plug 283 is located in the second capacitor region 200b and is electrically connected to the third electrode layer 230 and the first electrode layer 210.

[0037] It should be noted that the first capacitor stack 240 is located on the first dielectric layer 215 of the first capacitor region 200a and the second capacitor region 200b, and the first capacitor stack 240 includes a second electrode layer 220 and a third electrode layer 230 located on the second electrode layer 220, and a second dielectric layer 225 located between the second electrode layer 220 and the third electrode layer 230. The first conductive plug 280 is located in the first capacitor region 200a and is electrically connected to the first electrode layer 210. The second conductive plug 287 is located in the first capacitor region 200a and is electrically connected to the third electrode layer 230. The third conductive plug 282 is located in the second capacitor region 200b. Furthermore, it is electrically connected to the second electrode layer 220. The fourth conductive plug 283 is located in the second capacitor region 200b and is electrically connected to the third electrode layer 230 and the first electrode layer 210. That is to say, in the first capacitor region 200a, capacitors can be formed between adjacent electrode layers (i.e., between the first electrode layer 210 and the second electrode layer 220, and between the second electrode layer 220 and the third electrode layer 230). Since the first conductive plug 280 in the first capacitor region 200a is electrically connected to the first electrode layer 210, and the second conductive plug 287 is electrically connected to the third electrode layer 230, the capacitors in the first capacitor region 200a are interconnected. The series connection reduces the total capacitance in the first capacitor region 200a, which helps to lower the capacitance density of the first capacitor region 200a. Furthermore, the series connection of the capacitors in the first capacitor region 200a increases its withstand voltage, thereby improving its withstand voltage performance. Correspondingly, in the second capacitor region 200b, capacitors can be formed between adjacent electrode layers (i.e., between the first electrode layer 210 and the second electrode layer 220, and between the second electrode layer 220 and the third electrode layer 230). Since the third conductive plug 282 in the second capacitor region 200b is electrically connected to the second electrode layer 220... The fourth conductive plug 283 is electrically connected to the third electrode layer 230 and the first electrode layer 210. Therefore, the capacitors in the second capacitor region 200b are connected in parallel, which increases the total capacitance value in the second capacitor region 200b and is beneficial to increasing the capacitance density of the second capacitor region 200b. Furthermore, the parallel connection of the capacitors in the second capacitor region 200b can reduce the withstand voltage value of the first capacitor region 200a. Thus, the embodiments of the present invention can form capacitors with low withstand voltage and high capacitance density, as well as capacitors with high withstand voltage and low capacitance density, satisfying the need to form capacitors of different types and performance parameters on the substrate 200.

[0038] The substrate 200 is used to provide a process platform for the formation of semiconductor structures.

[0039] In this embodiment, the substrate 200 includes a device structure layer and a back-end interconnect layer 290 located on and electrically connected to the device structure layer. The back-end interconnect layer 290 includes a bottom dielectric layer 201 and one or more metal layers located in the bottom dielectric layer 201, and the topmost metal layer is used as the top metal layer 205.

[0040] The device structure layer is formed through front-end device fabrication processes. In specific implementations, the device structure layer may include a substrate and a device structure located on the substrate. The device structure may include MOS transistors, such as NMOS transistors and PMOS transistors.

[0041] As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide, and the substrate may also be other types of substrates such as silicon-on-insulator or germanium-on-insulator.

[0042] In this embodiment, the back-end interconnect layer 290 includes a bottom dielectric layer 201 and one or more metal layers located in the bottom dielectric layer 201, and the topmost metal layer is used as the top metal layer 205.

[0043] The bottom dielectric layer 201 is used to achieve isolation between metal layers. Specifically, the bottom dielectric layer 201 is an inter-metal dielectric (IMD).

[0044] The bottom dielectric layer 201 is made of a dielectric material. As an example, the bottom dielectric layer 201 is made of silicon oxide.

[0045] In this embodiment, adjacent metal layers are electrically connected to each other so that the electrical properties of the device structure in the device structure layer can be brought out through one or more metal layers. Specifically, adjacent metal layers are electrically connected through a via interconnect structure located between them; the electrical properties of the device structure in the device structure layer are brought out through the top metal layer 205.

[0046] Specifically, the metal layer is made of a conductive material. In this embodiment, the metal layer material includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0047] It should be noted that the first capacitor region 200a and the second capacitor region 200b are used to form capacitors, respectively.

[0048] Specifically, in this embodiment, capacitors of different types and performance parameters are formed in the first capacitor region 200a and the second capacitor region 200b, respectively.

[0049] In this embodiment, the first capacitor region 200a includes a first connection region II and a second connection region I, and a first sub-capacitor region 200C located between the first connection region II and the second connection region I. The second capacitor region 200b includes a third connection region IV and a fourth connection region III, and a second sub-capacitor region 200D located between the third connection region IV and the fourth connection region III.

[0050] Specifically, the first connection area II is the area forming the first conductive plug 280, the second connection area I is the area forming the second conductive plug 287, the third connection area IV is the area forming the third conductive plug 282, and the fourth connection area III is the area forming the fourth conductive plug 283.

[0051] The first sub-capacitor region 200C and the second sub-capacitor region 200D are used as regions for forming the MIM capacitor region.

[0052] In this embodiment, the substrate 200 further includes an etch stop layer 202 located on the bottom dielectric layer 201 and covering the top metal layer 205, and a top dielectric layer 203 located on the etch stop layer 202.

[0053] It should be noted that the etching stop layer 202 is used to define the etching stop position in the steps of setting the first conductive plug 280, the second conductive plug 287, the third conductive plug 282 and the fourth conductive plug 283, so as to reduce the probability of damage to the top metal layer 205. At the same time, it also helps to improve the bottom height consistency of the first conductive plug 280, the second conductive plug 287, the third conductive plug 282 and the fourth conductive plug 283.

[0054] As an example, the etch stop layer 202 is made of silicon nitride. In other embodiments, the etch stop layer may also be made of other materials that have high etch selectivity with the substrate material, such as one or more of silicon nitride, aluminum oxide, aluminum nitride, and NDC (nitride-doped carbon).

[0055] It should be noted that the top dielectric layer 203 is used to achieve electrical isolation between the top metal layer 205 and the first electrode layer 210, thereby reducing the risk of leakage current between the top metal layer 205 and the first electrode layer 210.

[0056] Specifically, the material of the top dielectric layer 203 is a dielectric material. As an example, the material of the top dielectric layer 203 is silicon oxide.

[0057] Specifically, the first electrode layer 210 is used as the electrode plate of the MIM capacitor.

[0058] The material of the first electrode layer 210 is a conductive material. As an example, the material of the first electrode layer 210 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0059] In this embodiment, the first electrode layer 210 in the first capacitor region 200a is located on the substrate 200 of the first connection region II and the first sub-capacitor region 200C and exposes the top of the substrate 200 of the second connection region I. The first electrode layer 210 in the second capacitor region 200b is located on the substrate 200 of the second sub-capacitor region 200D and the fourth connection region III and exposes the top of the substrate 200 of the third connection region IV.

[0060] Specifically, the first electrode layer 210 in the first capacitor region 200a is located on the base 200 of the first connection region II and the first sub-capacitor region 200C and is exposed on the top of the base 200 of the second connection region I, so that the first conductive plug 280 can be electrically connected to the first electrode layer 210. At the same time, the first electrode layer 210 in the first capacitor region 200a is exposed on the top of the base 200 of the second connection region I, providing space for the third electrode layer 230 to be disposed on the top of the base 200 of the second connection region I.

[0061] It should be noted that the first dielectric layer 215 is used as an insulating layer in the formation of the MIM capacitor. Specifically, the first dielectric layer 215 located in the first capacitor region 200a is used to isolate the first electrode layer 210 and the subsequently formed second electrode layer 220, and the first dielectric layer 215 located in the second capacitor region 200b is used to isolate the first electrode layer 210 and the subsequently formed second electrode layer 220.

[0062] Specifically, the first dielectric layer 215 conformally covers the first electrode layer 210 and the substrate 200.

[0063] As an example, the material of the first dielectric layer 215 is an insulating dielectric material.

[0064] In this embodiment, the material of the first dielectric layer 215 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide.

[0065] As an example, the material of the first dielectric layer 215 includes one or more of hafnium oxide, aluminum oxide, and zirconium oxide.

[0066] It should be noted that in the first capacitor region 200a, capacitors can be formed between adjacent electrode layers (i.e., between the first electrode layer 210 and the second electrode layer 220, and between the second electrode layer 220 and the third electrode layer 230). After the first conductive plug 280 and the second conductive plug 287 are subsequently formed, since the first conductive plug 280 is electrically connected to the first electrode layer 210 and the second conductive plug 287 is electrically connected to the third electrode layer 230 in the first capacitor region 200a, the capacitors in the first capacitor region 200a are connected in series, which reduces the total capacitance value in the first capacitor region 200a. This helps to reduce the capacitance density of the first capacitor region 200a. Furthermore, the series connection of the capacitors in the first capacitor region 200a can improve the withstand voltage value of the first capacitor region 200a, thereby improving the withstand voltage performance of the first capacitor region 200a. Correspondingly, in the second capacitor region 200b, capacitors can be formed between adjacent electrode layers (i.e., between the first electrode layer 210 and the second electrode layer 220, and between the second electrode layer 220 and the third electrode layer 230). Capacitors can be formed between layer 210 and the second electrode layer 220, and between the second electrode layer 220 and the third electrode layer 230. After the third conductive plug 282 and the fourth conductive plug 283 are subsequently formed, since the third conductive plug 282 in the second capacitor region 200b is electrically connected to the second electrode layer 220, and the fourth conductive plug 283 is electrically connected to the third electrode layer 230 and the first electrode layer 210, the capacitors in the second capacitor region 200b are connected in parallel, which increases the total capacitance value in the second capacitor region 200b and is beneficial to increasing the capacitance density of the second capacitor region 200b. Furthermore, the parallel connection of the capacitors in the second capacitor region 200b can reduce the withstand voltage value of the first capacitor region 200a. Thus, this embodiment can form capacitors with low withstand voltage and high capacitance density, as well as capacitors with high withstand voltage and low capacitance density, satisfying the need to form capacitors of different types and performance parameters on the substrate 200.

[0067] In this embodiment, the second electrode layer 220 in the first capacitor region 200a is located on top of the first electrode layer 210 in the first sub-capacitor region 200C, and exposes the top of the first electrode layer 210 in the first connection region II and the top of the substrate 200 in the second connection region I. The third electrode layer 230 in the first capacitor region 200a is located on top of the second electrode layer 220 in the first sub-capacitor region 200C and the top of the substrate 200 in the second connection region I, and exposes the top of the first electrode layer 210 in the first connection region II.

[0068] Specifically, the second electrode layer 220 in the first capacitor region 200a exposes the top of the first electrode layer 210 in the first connection region II and the top of the base 200 in the second connection region I, so that the second electrode layer 220 in the first capacitor region 200a is not electrically connected to the first conductive plug 280 and the second conductive plug 287, thereby making the first conductive plug 280 electrically connected only to the first electrode layer 210 and the second conductive plug 287 electrically connected only to the third electrode layer 230, thereby enabling the capacitors in the first capacitor region 200a to be connected in series with each other.

[0069] In this embodiment, the second electrode layer 220 in the second capacitor region 200b is located on top of the first electrode layer 210 in the second sub-capacitor region 200D and on top of the substrate 200 of the third connection region IV, and exposes the top of the first electrode layer 210 of the fourth connection region III. The third electrode layer 230 in the second capacitor region 200b is located on top of the second electrode layer 220 in the second sub-capacitor region 200D and on top of the first electrode layer 210 of the fourth connection region III, and exposes the top of the second electrode layer 220 of the third connection region IV.

[0070] It should be noted that the second electrode layer 220 in the second capacitor region 200b exposes the top of the first electrode layer 210 in the fourth connection region III, providing space for the third electrode layer 230 disposed in the fourth connection region III, so that the third electrode layer 230 can be located on top of the first electrode layer 210 in the fourth connection region III, enabling the third conductive plug 282 to be electrically connected to the second electrode layer 220, and enabling the fourth conductive plug 283 to be electrically connected to the third electrode layer 230 and the first electrode layer 210, thereby enabling the capacitors in the second capacitor region 200b to be connected in parallel with each other.

[0071] The second electrode layer 220 is used as the electrode plate of the MIM capacitor.

[0072] Specifically, the material of the second electrode layer 220 is a conductive material. As an example, the material of the second electrode layer 220 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0073] It should be noted that the second dielectric layer 225 is used as an insulating layer in the MIM capacitor.

[0074] Specifically, the second dielectric layer 225 located in the first capacitor region 200a is used to isolate the second electrode layer 220 and the third electrode layer 230, and the second dielectric layer 225 located in the second capacitor region 200b is used to isolate the second electrode layer 220 and the third electrode layer 230.

[0075] As an example, the material of the second dielectric layer 225 is an insulating dielectric material.

[0076] In this embodiment, the material of the second dielectric layer 225 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide.

[0077] As an example, the material of the second dielectric layer 225 includes one or more of hafnium oxide, aluminum oxide, and zirconium oxide.

[0078] In this embodiment, the second dielectric layer 225 and the first dielectric layer 215 are made of the same material. In other embodiments, the second dielectric layer and the first dielectric layer may be made of different materials.

[0079] The third electrode layer 230 is used as the electrode plate of the MIM capacitor.

[0080] Specifically, the material of the third electrode layer 230 is a conductive material. As an example, the material of the third electrode layer 230 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0081] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 260, which is located on the substrate 200 of the first capacitor region 200a and the second capacitor region 200b, and covers the first capacitor stack 240.

[0082] Specifically, the interlayer dielectric layer 260 provides a process basis for setting the first conductive plug 280, the second conductive plug 287, the third conductive plug 282 and the fourth conductive plug 283, and at the same time, it provides electrical isolation between the first conductive plug 280, the second conductive plug 287, the third conductive plug 282 and the fourth conductive plug 283.

[0083] It should be noted that the material of the interlayer dielectric layer 260 is a dielectric material. As an example, the material of the interlayer dielectric layer 260 is silicon oxide.

[0084] Specifically, the first conductive plug 280 in the first capacitor region 200a is electrically connected to the first electrode layer 210, and the second conductive plug 287 is electrically connected to the third electrode layer 230. Therefore, the capacitors in the first capacitor region 200a are connected in series, which reduces the total capacitance value in the first capacitor region 200a, thus helping to reduce the capacitance density of the first capacitor region 200a. Furthermore, the series connection of the capacitors in the first capacitor region 200a can increase the withstand voltage value of the first capacitor region 200a, thereby improving the withstand voltage performance of the first capacitor region 200a. Correspondingly, in the second capacitor region 200b, the third conductive plug 282 is electrically connected to the second electrode layer 220, and the fourth conductive plug 283 is electrically connected to the third electrode layer 230 and the first electrode layer 210. Therefore, the capacitors in the second capacitor region 200b are connected in parallel, which increases the total capacitance value in the second capacitor region 200b and is beneficial to increasing the capacitance density of the second capacitor region 200b. Furthermore, the parallel connection of the capacitors in the second capacitor region 200b can reduce the withstand voltage value of the first capacitor region 200a.

[0085] In this embodiment, the first conductive plug 280 is electrically connected to the first electrode layer 210 of the exposed first connection area II, the second conductive plug 287 is electrically connected to the third electrode layer 230 on the top of the substrate 200 of the second connection area I, the third conductive plug 282 is electrically connected to the second electrode layer 220 of the exposed third connection area IV, and the fourth conductive plug 283 is electrically connected to the first electrode layer 210 and the third electrode layer 230 of the fourth connection area III.

[0086] Specifically, the first conductive plug 280 is electrically connected to the first electrode layer 210 of the exposed first connection area II, and the second conductive plug 287 is electrically connected to the third electrode layer 230 on the top of the substrate 200 of the second connection area I, which enables the capacitors in the first capacitor area 200a to be connected in series.

[0087] The third conductive plug 282 is electrically connected to the exposed second electrode layer 220 of the third connection region IV, and the fourth conductive plug 283 is electrically connected to the first electrode layer 210 and the third electrode layer 230 of the fourth connection region III, enabling the capacitors in the second capacitor region 200b to be connected in parallel.

[0088] In this embodiment, the first conductive plug 280 also penetrates the top dielectric layer 203 and the etch stop layer 202, and the second conductive plug 287 also penetrates the top dielectric layer 203 and the etch stop layer 202. The etch stop layer 202 can define the etch stop position during the formation of the first conductive plug 280 and the second conductive plug 287, thereby reducing the probability of the process of forming the first conductive plug 280 and the second conductive plug 287 damaging the top metal layer 205 and improving the depth consistency of the bottom of the first conductive plug 280 and the second conductive plug 287.

[0089] In this embodiment, the third conductive plug 282 also penetrates the top dielectric layer 203 and the etch stop layer 202, and the fourth conductive plug 283 also penetrates the top dielectric layer 203 and the etch stop layer 202. The etch stop layer 202 can define the etch stop position during the formation of the third conductive plug 282 and the fourth conductive plug 283, thereby reducing the probability of the process of forming the third conductive plug 282 and the fourth conductive plug 283 damaging the top metal layer 205 and improving the depth consistency of the bottom of the third conductive plug 282 and the fourth conductive plug 283.

[0090] In this embodiment, the first conductive plug 280 penetrates the interlayer dielectric layer 260 and the first electrode layer 210 of the first connection region II, and the sidewall of the first conductive plug 280 is electrically connected to the first electrode layer 210; the second conductive plug 287 penetrates the interlayer dielectric layer 260 and the third electrode layer 230 of the second connection region I, and the sidewall of the second conductive plug 287 is electrically connected to the third electrode layer 230; the third conductive plug 282 penetrates the interlayer dielectric layer 260 and the second electrode layer 220 of the third connection region IV, and the sidewall of the third conductive plug 282 is electrically connected to the second electrode layer 220; the fourth conductive plug 283 penetrates the interlayer dielectric layer 260, the third electrode layer 230 and the first electrode layer 210 of the fourth connection region III, and the sidewall of the fourth conductive plug 283 is electrically connected to the third electrode layer 230 and the first electrode layer 210.

[0091] In this embodiment, the first conductive plug 280 is also electrically connected to the top metal layer 205, and the second conductive plug 287 is also electrically connected to the top metal layer 205, thereby realizing the electrical connection between the first conductive plug 280 and the first electrode layer 210 and the top metal layer 205, and realizing the electrical connection between the second conductive plug 287 and the third electrode layer 230 and the top metal layer 205.

[0092] Specifically, the first conductive plug 280 and the second conductive plug 287 are made of conductive materials.

[0093] In this embodiment, the materials of the first conductive plug 280 and the second conductive plug 287 include one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0094] In this embodiment, the third conductive plug 282 is also electrically connected to the top metal layer 205, and the fourth conductive plug 283 is also electrically connected to the top metal layer 205, thereby realizing the electrical connection between the third conductive plug 282 and the second electrode layer 220 and the top metal layer 205, and realizing the electrical connection between the fourth conductive plug 283 and the third electrode layer 230, the first electrode layer 210 and the top metal layer 205.

[0095] Specifically, the third conductive plug 282 and the fourth conductive plug 283 are made of conductive materials.

[0096] In this embodiment, the materials of the third conductive plug 282 and the fourth conductive plug 283 include one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0097] In this embodiment, the semiconductor structure further includes an interconnect layer 290 located on the first conductive plug 280, the second conductive plug 287, the third conductive plug 282, and the fourth conductive plug 283, and the interconnect layer 290 is electrically connected to the first conductive plug 280, the second conductive plug 287, the third conductive plug 282, and the fourth conductive plug 283, respectively.

[0098] It should be noted that the interconnect layer 290 is used to enable the first conductive plug 280, the second conductive plug 287, the third conductive plug 282 and the fourth conductive plug 283 to be electrically connected to the external circuit structure, so that the first conductive plug 280, the second conductive plug 287, the third conductive plug 282 and the fourth conductive plug 283 can be connected to the potential through the interconnect layer 290.

[0099] In this embodiment, the material of the interconnect layer 290 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0100] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 2 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0101] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0102] refer to Figure 2 A substrate 100 is provided, including a first capacitor region 100a and a second capacitor region 100b.

[0103] Substrate 100 is used to provide a process platform for the formation of subsequent semiconductor structures.

[0104] In this embodiment, the substrate 100 includes a device structure layer (not shown) and a back interconnect layer (not shown) located on and electrically connected to the device structure layer. The back interconnect layer includes a bottom dielectric layer 101 and one or more metal layers located in the bottom dielectric layer 101, and the topmost metal layer is used as the top metal layer 105.

[0105] The device structure layer is formed through front-end device fabrication processes. In specific implementations, the device structure layer may include a substrate and a device structure located on the substrate. The device structure may include MOS transistors, such as NMOS transistors and PMOS transistors.

[0106] As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide, and the substrate may also be other types of substrates such as silicon-on-insulator or germanium-on-insulator.

[0107] The back-end interconnect layer is formed using a back-end interconnect process.

[0108] In this embodiment, the back-end interconnect layer includes a bottom dielectric layer 101 and one or more metal layers located in the bottom dielectric layer 101, and the topmost metal layer is designated as the top metal layer 105.

[0109] The bottom dielectric layer 101 is used to achieve isolation between metal layers. Specifically, the bottom dielectric layer 101 is an inter-metal dielectric (IMD).

[0110] The bottom dielectric layer 101 is made of a dielectric material. As an example, the bottom dielectric layer 101 is made of silicon oxide.

[0111] In this embodiment, adjacent metal layers are electrically connected to each other so that the electrical properties of the device structure in the device structure layer can be brought out through one or more metal layers. Specifically, adjacent metal layers are electrically connected through a via interconnect structure located between them; the electrical properties of the device structure in the device structure layer are brought out through the top metal layer 105.

[0112] Specifically, the metal layer is made of a conductive material. In this embodiment, the metal layer material includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0113] It should be noted that the first capacitor region 100a and the second capacitor region 100b are used to form capacitors, respectively.

[0114] Specifically, in this embodiment, capacitors of different types and performance parameters are formed in the first capacitor region 100a and the second capacitor region 100b, respectively.

[0115] In this embodiment, the first capacitor region 100a includes a first connection region II and a second connection region I, and a first sub-capacitor region located between the first connection region II and the second connection region I. The second capacitor region 100b includes a third connection region IV and a fourth connection region III, and a second sub-capacitor region located between the third connection region IV and the fourth connection region III.

[0116] Specifically, the first connection region II is the region where the first conductive plug is subsequently formed, the second connection region I is the region where the second conductive plug is subsequently formed, the third connection region IV is the region where the third conductive plug is subsequently formed, and the fourth connection region III is the region where the fourth conductive plug is subsequently formed.

[0117] The first and second sub-capacitor regions are used as areas for the subsequent formation of the MIM capacitor region.

[0118] In this embodiment, the substrate 100 further includes an etch stop layer 102 located on the bottom dielectric layer 101 and covering the top metal layer 105, and a top dielectric layer 103 located on the etch stop layer 102.

[0119] It should be noted that the etching stop layer 102 is used to define the etching stop position in the subsequent steps of forming the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, so as to reduce the probability of damage to the top metal layer 105. At the same time, it also helps to improve the bottom height consistency of the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug.

[0120] As an example, the etch stop layer 102 is made of silicon nitride. In other embodiments, the etch stop layer may also be made of other materials that have high etch selectivity with the substrate material, such as one or more of silicon nitride, aluminum oxide, aluminum nitride, and NDC (nitride-doped carbon).

[0121] It should be noted that the top dielectric layer 103 is used to achieve electrical isolation between the top metal layer 105 and the first electrode layer, thereby reducing the risk of leakage current between the top metal layer 105 and the first electrode layer.

[0122] Specifically, the material of the top dielectric layer 103 is a dielectric material. As an example, the material of the top dielectric layer 103 is silicon oxide.

[0123] refer to Figure 3 A first electrode layer 110 is formed on the substrate 100 of the first capacitor region 100a and the substrate 100 of the second capacitor region 100b.

[0124] Specifically, the first electrode layer 110 is used as the electrode plate of the subsequently formed MIM capacitor.

[0125] The material of the first electrode layer 110 is a conductive material. As an example, the material of the first electrode layer 110 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0126] In this embodiment, in the step of forming the first electrode layer 110, the first electrode layer 110 in the first capacitor region 100a is located on the substrate 100 of the first connection region II and the first sub-capacitor region and exposes the top of the substrate 100 of the second connection region I, and the first electrode layer 110 in the second capacitor region 100b is located on the substrate 100 of the second sub-capacitor region and the fourth connection region III and exposes the top of the substrate 100 of the third connection region IV.

[0127] Specifically, the first electrode layer 110 in the first capacitor region 100a is located on the base 100 of the first connection region II and the first sub-capacitor region and is exposed on the top of the base 100 of the second connection region I, so that the first conductive plug formed subsequently can be electrically connected to the first electrode layer 110. At the same time, the first electrode layer 110 in the first capacitor region 100a is exposed on the top of the base 100 of the second connection region I, providing space for the formation of the third electrode layer on the top of the base 100 of the second connection region I.

[0128] In this embodiment, the step of forming the first electrode layer 110 includes: forming a first electrode material layer on the substrate 100 of the first capacitor region 100a and the second capacitor region 100b; removing the first electrode material layer on the second connection region I and the third connection region IV, and using the remaining first electrode material layer located on the first connection region II and the first sub-capacitor region, and located on the second sub-capacitor region and the fourth connection region III as the first electrode layer 110.

[0129] As an example, the process for forming the first electrode material layer includes either physical vapor deposition or chemical vapor deposition.

[0130] In this embodiment, an anisotropic dry etching process is used to remove the first electrode material layer on the second connection region I and the third connection region IV.

[0131] refer to Figure 4 A first dielectric layer 115 covering the first electrode layer 110 is formed on the substrate 100.

[0132] It should be noted that the first dielectric layer 115 is used as an insulating layer in the formation of the MIM capacitor. Specifically, the first dielectric layer 115 located in the first capacitor region 100a is used to isolate the first electrode layer 110 and the subsequently formed second electrode layer, and the first dielectric layer 115 located in the second capacitor region 100b is used to isolate the first electrode layer 110 and the subsequently formed second electrode layer.

[0133] Specifically, the first dielectric layer 115 conformally covers the first electrode layer 110 and the substrate 100.

[0134] As an example, the material of the first dielectric layer 115 is an insulating dielectric material.

[0135] In this embodiment, the material of the first dielectric layer 115 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide.

[0136] As an example, the material of the first dielectric layer 115 includes one or more of hafnium oxide, aluminum oxide, and zirconium oxide.

[0137] In this embodiment, the process for forming the first dielectric layer 115 includes chemical vapor deposition or atomic layer deposition.

[0138] refer to Figures 5 to 7 After forming the first dielectric layer 115, a first capacitor stack 140 is formed on the first dielectric layer 115 of the first capacitor region 100a and the second capacitor region 100b. The first capacitor stack 140 includes a second electrode layer 120 and a third electrode layer 130 located on the second electrode layer 120, and a second dielectric layer 125 located between the second electrode layer 120 and the third electrode layer 130.

[0139] It should be noted that in the first capacitor region 100a, capacitors can be formed between adjacent electrode layers (i.e., between the first electrode layer 110 and the second electrode layer 120, and between the second electrode layer 120 and the third electrode layer 130). After the first conductive plug and the second conductive plug are subsequently formed, since the first conductive plug in the first capacitor region 100a is electrically connected to the first electrode layer 110 and the second conductive plug is electrically connected to the third electrode layer 130, the capacitors in the first capacitor region 100a are connected in series, which reduces the total capacitance value in the first capacitor region 100a. This helps to reduce the capacitance density of the first capacitor region 100a. Furthermore, the series connection of the capacitors in the first capacitor region 100a can improve the withstand voltage value of the first capacitor region 100a, thereby improving the withstand voltage performance of the first capacitor region 100a. Correspondingly, in the second capacitor region 100b, capacitors can be formed between adjacent electrode layers (i.e., between the first electrode layer 110 and the second electrode layer 120, and between the second electrode layer 120 and the third electrode layer 130). Capacitors can be formed between layer 110 and the second electrode layer 120, and between the second electrode layer 120 and the third electrode layer 130. After the third conductive plug and the fourth conductive plug are subsequently formed, since the third conductive plug in the second capacitor region 100b is electrically connected to the second electrode layer 120, and the fourth conductive plug is electrically connected to the third electrode layer 130 and the first electrode layer 110, the capacitors in the second capacitor region 100b are connected in parallel, which increases the total capacitance value in the second capacitor region 100b and is beneficial to increasing the capacitance density of the second capacitor region 100b. Furthermore, the parallel connection of the capacitors in the second capacitor region 100b can reduce the withstand voltage value of the first capacitor region 100a. Thus, this embodiment can form capacitors with low withstand voltage and high capacitance density, as well as capacitors with high withstand voltage and low capacitance density, satisfying the need to form capacitors of different types and performance parameters on the substrate 100.

[0140] In this embodiment, in the step of forming the first capacitor stack 140, the second electrode layer 120 in the first capacitor region 100a is located on top of the first electrode layer 110 in the first sub-capacitor region, and exposes the top of the first electrode layer 110 in the first connection region II and the top of the substrate 100 in the second connection region I; the third electrode layer 130 in the first capacitor region 100a is located on top of the second electrode layer 120 in the first sub-capacitor region and the top of the substrate 100 in the second connection region I, and exposes the top of the first electrode layer 110 in the first connection region II; the second electrode layer 120 in the second capacitor region 100b is located on top of the first electrode layer 110 in the second sub-capacitor region and the top of the substrate 100 in the third connection region IV, and exposes the top of the first electrode layer 110 in the fourth connection region III; the third electrode layer 130 in the second capacitor region 100b is located on top of the second electrode layer 120 in the second sub-capacitor region and the top of the first electrode layer 110 in the fourth connection region III, and exposes the top of the second electrode layer 120 in the third connection region IV.

[0141] Specifically, the second electrode layer 120 in the first capacitor region 100a exposes the top of the first electrode layer 110 in the first connection region II and the top of the base 100 in the second connection region I, so that the second electrode layer 120 in the first capacitor region 100a is not electrically connected to the subsequently formed first conductive plug and second conductive plug, so that the first conductive plug is only electrically connected to the first electrode layer 110 and the second conductive plug is only electrically connected to the third electrode layer 130, thereby enabling the capacitors in the first capacitor region 100a to be connected in series with each other.

[0142] It should be noted that the second electrode layer 120 in the second capacitor region 100b exposes the top of the first electrode layer 110 in the fourth connection region III, providing space for the third electrode layer 130 formed in the fourth connection region III, so that the third electrode layer 130 can be located on top of the first electrode layer 110 in the fourth connection region III. After the third conductive plug and the fourth conductive plug are subsequently formed, the third conductive plug can be electrically connected to the second electrode layer 120, and the fourth conductive plug can be electrically connected to the third electrode layer 130 and the first electrode layer 110, thereby enabling the capacitors in the second capacitor region 100b to be connected in parallel with each other.

[0143] In this embodiment, the step of forming the first capacitor stack 140 includes: forming a second electrode material layer on the top of the first electrode layer 110 of the first connection region II and the first sub-capacitor region, the top of the substrate 100 of the second connection region I, the top of the substrate 100 of the third connection region IV, and the top of the first electrode layer 110 of the second sub-capacitor region and the fourth connection region III; removing the second electrode material layer on the top of the substrate 100 of the first connection region II and the second connection region I, and the top of the substrate 100 of the fourth connection region III, leaving the remaining first electrode material layer on the top of the first electrode layer 110 of the first sub-capacitor region, the top of the substrate 100 of the third connection region IV, and the first electrode layer of the second sub-capacitor region. The second electrode material layer at the top of layer 110 serves as the second electrode layer 120; a second dielectric layer 125 is formed covering the second electrode layer 120; after the second dielectric layer 125 is formed, a third electrode material layer is formed on the substrate 100, located on top of the second electrode layer 120 and the first electrode layer 110; the third electrode material layers of the first connection region II and the fourth connection region III are removed, and the remaining third electrode material layers located in the first sub-capacitor region and the second connection region I, as well as the second sub-capacitor region and the fourth connection region III, serve as the third electrode layer 130, and the second electrode layer 120, the second dielectric layer 125 and the third electrode layer 130 constitute the first capacitor stack 140.

[0144] The second electrode layer 120 is used as the electrode plate of the MIM capacitor.

[0145] Specifically, the material of the second electrode layer 120 is a conductive material. As an example, the material of the second electrode layer 120 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0146] In this embodiment, the process of removing the second electrode material layer from the top of the first connection region II and the second connection region I substrate 100, and the top of the fourth connection region III substrate 100, includes anisotropic dry etching process.

[0147] It should be noted that the second dielectric layer 125 is used as an insulating layer in the MIM capacitor.

[0148] Specifically, the second dielectric layer 125 located in the first capacitor region 100a is used to isolate the second electrode layer 120 and the third electrode layer 130, and the second dielectric layer 125 located in the second capacitor region 100b is used to isolate the second electrode layer 120 and the third electrode layer 130.

[0149] As an example, the material of the second dielectric layer 125 is an insulating dielectric material.

[0150] In this embodiment, the material of the second dielectric layer 125 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide.

[0151] As an example, the material of the second dielectric layer 125 includes one or more of hafnium oxide, aluminum oxide, and zirconium oxide.

[0152] In this embodiment, the second dielectric layer 125 and the first dielectric layer 115 are made of the same material. In other embodiments, the second dielectric layer and the first dielectric layer may be made of different materials.

[0153] The third electrode layer 130 is used as the electrode plate of the MIM capacitor.

[0154] Specifically, the material of the third electrode layer 130 is a conductive material. As an example, the material of the third electrode layer 130 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0155] In this embodiment, the process for removing the third electrode material layer of the first connection region II and the fourth connection region III includes an anisotropic dry etching process.

[0156] refer to Figure 8After forming the first capacitor stack 140 and before forming the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, the forming method further includes forming an interlayer dielectric layer 160 covering the first capacitor stack 140 on the substrate 100 of the first capacitor region 100a and the second capacitor region 100b.

[0157] Specifically, the interlayer dielectric layer 160 provides a process basis for the subsequent formation of the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, and at the same time, it provides electrical isolation between the subsequently formed first conductive plug, second conductive plug, third conductive plug, and fourth conductive plug.

[0158] It should be noted that the material of the interlayer dielectric layer 160 is a dielectric material. As an example, the material of the interlayer dielectric layer 160 is silicon oxide.

[0159] As an example, a chemical vapor deposition process is used to form an interlayer dielectric layer 160.

[0160] refer to Figure 9 A first conductive plug 180 electrically connected to the first electrode layer 110 is formed in the first capacitor region 100a. A second conductive plug 181 is formed in the first capacitor region 100a and electrically connected to the third electrode layer 130. A third conductive plug 182 electrically connected to the second electrode layer 120 is formed in the second capacitor region 100b. A fourth conductive plug 183 electrically connected to the third electrode layer 130 and the first electrode layer 110 is formed in the second capacitor region 100b.

[0161] Specifically, in the first capacitor region 100a, the first conductive plug 180 is electrically connected to the first electrode layer 110, and the second conductive plug 181 is electrically connected to the third electrode layer 130. Therefore, the capacitors in the first capacitor region 100a are connected in series, which reduces the total capacitance value in the first capacitor region 100a, thus reducing the capacitance density of the first capacitor region 100a. Furthermore, the series connection of the capacitors in the first capacitor region 100a increases the withstand voltage value of the first capacitor region 100a, thereby improving its withstand voltage performance. Correspondingly, in the second capacitor region 100b, the third conductive plug 182 is electrically connected to the second electrode layer 130. Layer 120 is electrically connected, and the fourth conductive plug 183 is electrically connected to the third electrode layer 130 and the first electrode layer 110. Therefore, the capacitors in the second capacitor region 100b are connected in parallel, which increases the total capacitance value in the second capacitor region 100b and is beneficial to increasing the capacitance density of the second capacitor region 100b. Furthermore, the parallel connection of the capacitors in the second capacitor region 100b can reduce the withstand voltage value of the first capacitor region 100a. Thus, the embodiments of the present invention can form capacitors with low withstand voltage and high capacitance density, as well as capacitors with high withstand voltage and low capacitance density, satisfying the need to form capacitors of different types and performance parameters on the substrate 100.

[0162] In this embodiment, the first conductive plug 180 is electrically connected to the first electrode layer 110 of the exposed first connection area II, the second conductive plug 181 is electrically connected to the third electrode layer 130 on the top of the substrate 100 of the second connection area I, the third conductive plug 182 is electrically connected to the second electrode layer 120 of the exposed third connection area IV, and the fourth conductive plug 183 is electrically connected to the first electrode layer 110 and the third electrode layer 130 of the fourth connection area III.

[0163] Specifically, the first conductive plug 180 is electrically connected to the first electrode layer 110 of the exposed first connection area II, and the second conductive plug 181 is electrically connected to the third electrode layer 130 on the top of the substrate 100 of the second connection area I, which enables the capacitors in the first capacitor area 100a to be connected in series.

[0164] The third conductive plug 182 is electrically connected to the exposed second electrode layer 120 of the third connection region IV, and the fourth conductive plug 183 is electrically connected to the first electrode layer 110 and the third electrode layer 130 of the fourth connection region III, enabling the capacitors in the second capacitor region 100b to be connected in parallel.

[0165] In this embodiment, the steps of forming the first conductive plug 180 and the second conductive plug 181 include: forming a first opening penetrating the interlayer dielectric layer 160 and the first electrode layer 110 in the first connection region II; forming a second opening penetrating the interlayer dielectric layer 160 and the third electrode layer 130 in the second connection region I; filling the first opening and the second opening with conductive material, using the conductive material in the first opening as the first conductive plug 180, and the sidewall of the first conductive plug 180 being electrically connected to the first electrode layer 110; using the conductive material in the second opening as the second conductive plug 181, and the sidewall of the second conductive plug 181 being electrically connected to the third electrode layer 130.

[0166] In this embodiment, the steps of forming the third conductive plug 182 and the fourth conductive plug 183 include: forming a third opening in the third connection region IV that penetrates the interlayer dielectric layer 160 and the first electrode layer 110; forming a fourth opening in the fourth connection region III that penetrates the interlayer dielectric layer 160, the third electrode layer 130, and the first electrode layer 110; filling the third opening and the fourth opening with conductive material, using the conductive material in the third opening as the third conductive plug 182, and the sidewall of the third conductive plug 182 being electrically connected to the first electrode layer 110; using the conductive material in the fourth opening as the fourth conductive plug 183, and the sidewall of the fourth conductive plug 183 being electrically connected to the third electrode layer 130 and the first electrode layer 110.

[0167] In this embodiment, the first conductive plug 180, the second conductive plug 181, the third conductive plug 182, and the fourth conductive plug 183 are formed in the same step.

[0168] Specifically, the first conductive plug 180, the second conductive plug 181, the third conductive plug 182 and the fourth conductive plug 183 are formed in the same step, which can reduce the number of process steps and reduce process costs.

[0169] It should be noted that, in this embodiment, during the steps of forming the first conductive plug 180 and the second conductive plug 181, the first conductive plug 180 also penetrates the top dielectric layer 103 and the etch stop layer 102, and the second conductive plug 181 also penetrates the top dielectric layer 103 and the etch stop layer 102. The etch stop layer 102 can define the etch stop position during the formation of the first conductive plug 180 and the second conductive plug 181, thereby reducing the probability of the process of forming the first conductive plug 180 and the second conductive plug 181 damaging the top metal layer 105 and improving the depth consistency of the bottom of the first conductive plug 180 and the second conductive plug 181.

[0170] It should also be noted that, in this embodiment, during the steps of forming the third conductive plug 182 and the fourth conductive plug 183, the third conductive plug 182 also penetrates the top dielectric layer 103 and the etch stop layer 102, and the fourth conductive plug 183 also penetrates the top dielectric layer 103 and the etch stop layer 102. The etch stop layer 102 can define the etch stop position during the formation of the third conductive plug 182 and the fourth conductive plug 183, thereby reducing the probability of the process of forming the third conductive plug 182 and the fourth conductive plug 183 damaging the top metal layer 105 and improving the depth consistency of the bottom of the third conductive plug 182 and the fourth conductive plug 183.

[0171] In this embodiment, during the steps of forming the first conductive plug 180 and the second conductive plug 181, the first conductive plug 180 is also electrically connected to the top metal layer 105, and the second conductive plug 181 is also electrically connected to the top metal layer 105, thereby realizing the electrical connection between the first conductive plug 180 and the first electrode layer 110 and the top metal layer 105, and realizing the electrical connection between the second conductive plug 181 and the third electrode layer 130 and the top metal layer 105.

[0172] In this embodiment, during the steps of forming the third conductive plug 182 and the fourth conductive plug 183, the third conductive plug 182 is also electrically connected to the top metal layer 105, and the fourth conductive plug 183 is also electrically connected to the top metal layer 105, thereby realizing the electrical connection between the third conductive plug 182 and the second electrode layer 120 and the top metal layer 105, and realizing the electrical connection between the fourth conductive plug 183 and the third electrode layer 130, the first electrode layer 110 and the top metal layer 105.

[0173] Specifically, the first conductive plug 180 and the second conductive plug 181 are made of conductive materials.

[0174] In this embodiment, the materials of the first conductive plug 180 and the second conductive plug 181 include one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0175] Specifically, the third conductive plug 182 and the fourth conductive plug 183 are made of conductive materials.

[0176] In this embodiment, the materials of the third conductive plug 182 and the fourth conductive plug 183 include one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0177] refer to Figure 10After forming the first conductive plug 180, the second conductive plug 181, the third conductive plug 182, and the fourth conductive plug 183, the method for forming the semiconductor structure further includes forming an interconnect layer 190 on the first conductive plug 180, the second conductive plug 181, the third conductive plug 182, and the fourth conductive plug 183, wherein the interconnect layer 190 is electrically connected to the first conductive plug 180, the second conductive plug 181, the third conductive plug 182, and the fourth conductive plug 183, respectively.

[0178] It should be noted that the interconnect layer 190 is used to enable the first conductive plug 180, the second conductive plug 181, the third conductive plug 182 and the fourth conductive plug 183 to be electrically connected to the external circuit structure, so that the first conductive plug 180, the second conductive plug 181, the third conductive plug 182 and the fourth conductive plug 183 can be connected to the potential through the interconnect layer 190.

[0179] In this embodiment, the step of forming the interconnect layer 190 includes: forming an interconnect material layer on top of the interlayer dielectric layer 160, the first conductive plug 180, the second conductive plug 181, the third conductive plug 182, and the fourth conductive plug 183; performing patterning processing on the interconnect material layer, retaining the interconnect material layer located on top of the first conductive plug 180, the second conductive plug 181, the third conductive plug 182, and the fourth conductive plug 183, and using the interconnect material layer located on top of the first conductive plug 180, the second conductive plug 181, the third conductive plug 182, and the fourth conductive plug 183 as the interconnect layer 190.

[0180] In this embodiment, the process for patterning the interconnect material layer includes anisotropic dry etching.

[0181] In this embodiment, the material of the interconnect layer 190 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0182] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first capacitor region and a second capacitor region; The first electrode layer is located on the substrate of the first capacitor region and the second capacitor region; A first dielectric layer is located on the substrate and covers the first electrode layer; The first capacitor stack is located on the first dielectric layer of the first capacitor region and the second capacitor region, and the first capacitor stack includes a second electrode layer and a third electrode layer located on the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer. The first conductive plug is located in the first capacitor region and is electrically connected to the first electrode layer; The second conductive plug is located in the first capacitor region and is electrically connected to the third electrode layer; The third conductive plug is located in the second capacitor region and is electrically connected to the second electrode layer; The fourth conductive plug is located in the second capacitor region and is electrically connected to the third electrode layer and the first electrode layer.

2. The semiconductor structure as described in claim 1, characterized in that, The first capacitor region includes a first connection region and a second connection region, and a first sub-capacitor region located between the first connection region and the second connection region; the second capacitor region includes a third connection region and a fourth connection region, and a second sub-capacitor region located between the third connection region and the fourth connection region. The first electrode layer in the first capacitor region is located on the base of the first connection region and the first sub-capacitor region and exposes the top of the base of the second connection region; the first electrode layer in the second capacitor region is located on the base of the second sub-capacitor region and the fourth connection region and exposes the top of the base of the third connection region. The second electrode layer in the first capacitor region is located on top of the first electrode layer in the first sub-capacitor region and exposes the top of the first electrode layer in the first connection region and the top of the base of the second connection region. The third electrode layer in the first capacitor region is located on top of the second electrode layer in the first sub-capacitor region and the top of the base of the second connection region and exposes the top of the first electrode layer in the first connection region. The second electrode layer in the second capacitor region is located on top of the first electrode layer in the second sub-capacitor region and on top of the base of the third connection region, and exposes the top of the first electrode layer of the fourth connection region. The third electrode layer in the second capacitor region is located on top of the second electrode layer in the second sub-capacitor region and on top of the first electrode layer of the fourth connection region, and exposes the top of the second electrode layer of the third connection region. The first conductive plug is electrically connected to the first electrode layer of the exposed first connection area; The second conductive plug is electrically connected to the third electrode layer on top of the substrate of the second connection area; The third conductive plug is electrically connected to the second electrode layer of the exposed third connection area; The fourth conductive plug is electrically connected to the first electrode layer and the third electrode layer of the fourth connection region.

3. The semiconductor structure as described in claim 2, characterized in that, The semiconductor structure further includes: an interlayer dielectric layer located on the substrate of the first capacitor region and the second capacitor region, and covering the first capacitor stack; The first conductive plug penetrates the interlayer dielectric layer and the first electrode layer of the first connection area, and the sidewall of the first conductive plug is electrically connected to the first electrode layer. The second conductive plug penetrates the interlayer dielectric layer and the third electrode layer of the second connection area, and the sidewall of the second conductive plug is electrically connected to the third electrode layer; The third conductive plug penetrates the interlayer dielectric layer and the second electrode layer of the third connection region, and the sidewall of the third conductive plug is electrically connected to the second electrode layer. The fourth conductive plug penetrates the interlayer dielectric layer, the third electrode layer, and the first electrode layer of the fourth connection region, and the sidewall of the fourth conductive plug is electrically connected to the third electrode layer and the first electrode layer.

4. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a device structure layer and a back-end interconnect layer located on and electrically connected to the device structure layer. The back-end interconnect layer includes a bottom dielectric layer and one or more metal layers located in the bottom dielectric layer, with the topmost metal layer serving as the top metal layer. The first conductive plug is also electrically connected to the top metal layer, and the second conductive plug is also electrically connected to the top metal layer; The third conductive plug is also electrically connected to the top metal layer, and the fourth conductive plug is also electrically connected to the top metal layer.

5. The semiconductor structure as described in claim 4, characterized in that, The substrate further includes an etch stop layer located on the bottom dielectric layer and covering the top metal layer, and a top dielectric layer located on the etch stop layer.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an interconnect layer located on the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, and the interconnect layer is electrically connected to the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, respectively.

7. The semiconductor structure as described in claim 1, characterized in that, The second dielectric layer is made of the same material as the first dielectric layer.

8. The semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer includes hafnium oxide, aluminum oxide, or zirconium oxide; The material of the second dielectric layer includes hafnium oxide, aluminum oxide, or zirconium oxide.

9. The semiconductor structure as described in claim 1, characterized in that, The material of the first electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; The material of the second electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; The material of the third electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

10. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a first capacitor region and a second capacitor region; A first electrode layer is formed on the substrate of the first capacitor region and on the substrate of the second capacitor region; A first dielectric layer covering the first electrode layer is formed on the substrate; After the first dielectric layer is formed, a first capacitor stack is formed on the first dielectric layer of the first capacitor region and the second capacitor region. The first capacitor stack includes a second electrode layer and a third electrode layer located on the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer. A first conductive plug electrically connected to the first electrode layer is formed in the first capacitor region, and a second conductive plug is formed in the first capacitor region, the second conductive plug being electrically connected to the third electrode layer. A third conductive plug electrically connected to the second electrode layer is formed in the second capacitor region, and a fourth conductive plug electrically connected to the third electrode layer and the first electrode layer is formed in the second capacitor region.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing the substrate, the first capacitor region includes a first connection region and a second connection region, and a first sub-capacitor region located between the first connection region and the second connection region; the second capacitor region includes a third connection region and a fourth connection region, and a second sub-capacitor region located between the third connection region and the fourth connection region. In the step of forming the first electrode layer, the first electrode layer in the first capacitor region is located on the substrate of the first connection region and the first sub-capacitor region and exposes the top of the substrate of the second connection region; the first electrode layer in the second capacitor region is located on the substrate of the second sub-capacitor region and the fourth connection region and exposes the top of the substrate of the third connection region. In the step of forming the first capacitor stack, the second electrode layer in the first capacitor region is located on top of the first electrode layer in the first sub-capacitor region, and exposes the top of the first electrode layer in the first connection region and the top of the base of the second connection region; the third electrode layer in the first capacitor region is located on top of the second electrode layer in the first sub-capacitor region and the top of the base of the second connection region, and exposes the top of the first electrode layer in the first connection region; the second electrode layer in the second capacitor region is located on top of the first electrode layer in the second sub-capacitor region and the top of the base of the third connection region, and exposes the top of the first electrode layer in the fourth connection region; the third electrode layer in the second capacitor region is located on top of the second electrode layer in the second sub-capacitor region and the top of the first electrode layer in the fourth connection region, and exposes the top of the second electrode layer in the third connection region. In the step of forming the first conductive plug, the first conductive plug is electrically connected to the first electrode layer of the exposed first connection area; In the step of forming the second conductive plug, the second conductive plug is electrically connected to the third electrode layer on top of the substrate of the second connection region; In the step of forming the third conductive plug, the third conductive plug is electrically connected to the second electrode layer of the exposed third connection region; In the step of forming the fourth conductive plug, the fourth conductive plug is electrically connected to the first electrode layer and the third electrode layer of the fourth connection region.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the first electrode layer includes: forming a first electrode material layer on the substrate of the first capacitor region and the second capacitor region; removing the first electrode material layer on the second connection region and the third connection region, and using the remaining first electrode material layer located on the first connection region and the first sub-capacitor region, and located on the second sub-capacitor region and the fourth connection region as the first electrode layer.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the first capacitor stack includes: forming a second electrode material layer on top of the first electrode layer of the first connection region and the first sub-capacitor region, on top of the substrate of the second connection region, on top of the substrate of the third connection region, and on top of the first electrode layer of the second sub-capacitor region and the fourth connection region; removing the second electrode material layer on top of the substrate of the first connection region and the second connection region, and on top of the substrate of the fourth connection region, and the remaining second electrode material layer located on top of the first electrode layer of the first sub-capacitor region, on top of the substrate of the third connection region, and on top of the first electrode layer of the second sub-capacitor region as the second electrode layer; A second dielectric layer is formed covering the second electrode layer; After the second dielectric layer is formed, a third electrode material layer is formed on the substrate at the top of the second electrode layer and the first electrode layer. The third electrode material layers in the first connection region and the fourth connection region are removed. The remaining third electrode material layers in the first sub-capacitor region and the second connection region, as well as the second sub-capacitor region and the fourth connection region, are used as the third electrode layer. The second electrode layer, the second dielectric layer and the third electrode layer constitute the first capacitor stack.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the first capacitor stack and before forming the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, the forming method further includes: forming an interlayer dielectric layer covering the first capacitor stack on the substrate of the first capacitor region and the second capacitor region. The steps of forming the first conductive plug and the second conductive plug include: forming a first opening in the first connection region that penetrates the interlayer dielectric layer and the first electrode layer; forming a second opening in the second connection region that penetrates the interlayer dielectric layer and the third electrode layer; filling the first opening and the second opening with conductive material, using the conductive material in the first opening as the first conductive plug, and electrically connecting the sidewall of the first conductive plug to the first electrode layer; using the conductive material in the second opening as the second conductive plug, and electrically connecting the sidewall of the second conductive plug to the third electrode layer. The steps of forming the third conductive plug and the fourth conductive plug include: forming a third opening in the third connection region that penetrates the interlayer dielectric layer and the first electrode layer; forming a fourth opening in the fourth connection region that penetrates the interlayer dielectric layer, the third electrode layer, and the first electrode layer; filling the third opening and the fourth opening with conductive material, using the conductive material in the third opening as the third conductive plug, and electrically connecting the sidewall of the third conductive plug to the first electrode layer; using the conductive material in the fourth opening as the fourth conductive plug, and electrically connecting the sidewall of the fourth conductive plug to the third electrode layer and the first electrode layer.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug are formed in the same step.

16. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing the substrate, the substrate includes a device structure layer and a back-end interconnect layer located on and electrically connected to the device structure layer, the back-end interconnect layer including a bottom dielectric layer and one or more metal layers located in the bottom dielectric layer, and the topmost metal layer is used as the top metal layer; In the steps of forming the first conductive plug and the second conductive plug, the first conductive plug is also electrically connected to the top metal layer, and the second conductive plug is also electrically connected to the top metal layer. In the steps of forming the third conductive plug and the fourth conductive plug, the third conductive plug is also electrically connected to the top metal layer, and the fourth conductive plug is also electrically connected to the top metal layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, In the step of providing the substrate, the substrate further includes an etch stop layer located on the bottom dielectric layer and covering the top metal layer, and a top dielectric layer located on the etch stop layer.

18. The method for forming a semiconductor structure as described in claim 10, characterized in that, After forming the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, the method for forming the semiconductor structure further includes: forming an interconnect layer on the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, wherein the interconnect layer is electrically connected to the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug, respectively.

19. The method for forming a semiconductor structure as described in claim 10, characterized in that, The second dielectric layer is made of the same material as the first dielectric layer.

20. The method for forming a semiconductor structure as described in claim 10, characterized in that, The material of the first dielectric layer includes hafnium oxide, aluminum oxide, or zirconium oxide; The material of the second dielectric layer includes hafnium oxide, aluminum oxide, or zirconium oxide.

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