Treatment method after TGV large square plate electroplating and TGV large square plate electroplating equipment

Abstract

The invention discloses a treatment method for a TGV large square plate after electroplating and TGV large square plate electroplating equipment. The treatment method for the TGV large square plate after electroplating comprises the following steps that S10, a to-be-treated substrate after TGV electroplating is obtained; s20, cutting the electroplated substrate to be processed into a plurality of independent wafers according to a preset cutting mode; and S30, deplating the plurality of cut wafers, wherein the deplated wafers are used for bonding to form a bonding structure and a semiconductor device. By cutting the electroplated substrate and then performing fine deplating, the processes of chemically and mechanically polishing the electroplated substrate, grinding and thinning a plating layer and the like are replaced, so that the edge effect when the substrate is processed into a wafer is avoided, the deplating uniformity is ensured, and the phenomenon that the wafer is damaged due to microcracks and stress concentration points possibly appearing on the substrate when the plating layer is mechanically polished and ground is avoided. And meanwhile, the phenomenon of over-corrosion / under-corrosion by adopting a chemical mode is avoided, and the electrical property, the mechanical reliability and the long-term service life of the product are remarkably improved.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor manufacturing and TGV advanced packaging manufacturing, and particularly to a method for processing TGV large square plates after electroplating and TGV large square plate electroplating equipment. Background Technology

[0002] TGV (Through Glass Via) plating is an advanced technology for forming conductive vias on glass substrates. It enables vertical electrical interconnection by creating vias on glass substrates and filling them with conductive materials (such as copper) through electroplating.

[0003] In existing technologies, after electroplating large TGV glass substrates, a thick, uneven copper plating layer remains on the surface. This layer requires a series of treatments to obtain a usable interconnect structure, typically including cleaning and drying, chemical mechanical polishing (CMP), plating thinning by grinding, fabrication of wiring layers, and dicing into individual chip devices. CMP removes excess copper through the synergistic effect of chemical etching and mechanical grinding, resulting in a globally flat surface. Plating thinning involves grinding to reduce the thickness of the substrate, exposing the copper pillars. Because glass substrates are brittle, these processes are highly susceptible to substrate breakage, cracking, or warping under mechanical stress, leading to a significant decrease in product yield. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defects in the prior art that the plating treatment of the substrate after electroplating is prone to causing the substrate to crack, fissure or warp, resulting in a significant decrease in product yield. The present invention provides a method for treating TGV large square plates after electroplating and TGV large square plate electroplating equipment.

[0005] The present invention solves the above-mentioned technical problems through the following technical solution:

[0006] A method for processing TGV large square plates after electroplating, the method comprising the following steps:

[0007] S10. Obtain the substrate to be processed after TGV electroplating;

[0008] S20 cuts the electroplated substrate into multiple independent wafers according to a preset cutting method;

[0009] S30. The diced wafers are stripped of their plating, and the stripped wafers are used for bonding to form bonding structures and semiconductor devices.

[0010] In this solution, the pre-cutting and subsequent fine stripping of the electroplated substrate replaces the previous steps of cleaning, drying, chemical mechanical polishing, thinning the plating layer, fabricating wiring layers, and cutting into individual chip devices. This avoids edge effects during wafer fabrication, ensures uniform stripping, and prevents microcracks and stress concentrations that may occur during mechanical polishing and plating. It also avoids over-etching / under-etching issues caused by chemical methods, significantly improving the product's electrical performance, mechanical reliability, and long-term lifespan. This "divide and conquer" approach isolates risks; the failure of a single wafer does not affect other wafers, resulting in a significantly improved overall yield. Furthermore, the cutting process proactively discards defective edge areas of the electroplated substrate, achieving pre-screening of quality.

[0011] Preferably, the following steps are included before step S10:

[0012] The circuit unit layout and process reference markings are preset on the substrate to be processed before electroplating.

[0013] In this solution, the above settings are used to achieve precise collaborative positioning and array arrangement algorithms for subsequent wafer dicing by utilizing preset circuit units and process reference marks. The resulting wafers can be directly adapted to existing wafer manufacturing equipment, thereby improving production line efficiency.

[0014] Preferably, step S20 further includes the following step:

[0015] When cutting the substrate to be processed, multiple independent wafers are cut and formed according to a preset circuit unit layout and process reference mark array, and each cut wafer includes at least one circuit unit.

[0016] In this solution, the above settings maximize the arrangement of effective circuit units on the substrate, reducing material waste.

[0017] Preferably, the wafer includes a flat-edge wafer and a notched wafer, and the step of dicing the substrate to be processed further includes the following steps:

[0018] The flat-edge wafers maintain a consistent flat-edge angle orientation; the notch-angle wafers maintain a consistent notch-angle orientation.

[0019] In this solution, the above settings facilitate the rapid positioning of the cut wafer within the substrate to be processed, and its clamping and stripping.

[0020] Preferably, the cutting method for cutting the substrate to be processed includes laser cutting.

[0021] In this solution, the above settings are used to effectively cut the substrate to be processed and form multiple independent wafers.

[0022] Preferably, step S30 further includes the following step:

[0023] When stripping the wafer, electrochemical stripping is used. The positive terminal of the power supply of the electrochemical stripping equipment is connected to the wafer to be stripped, and the negative terminal of the electrochemical stripping equipment is connected to the anode of the electroplating chamber of the electrochemical stripping equipment. The stripping is performed in constant current mode or pulse mode.

[0024] In this solution, the above settings are used to thin the plating layer by stripping. At this time, the shape to be stripped is a circular wafer instead of a substrate with sharp edges, so as to eliminate the current accumulation effect caused by sharp edges, making the stripping more uniform and reliable, and the yield rate higher.

[0025] Preferably, the wafer is further subjected to the following steps during the stripping process:

[0026] The voltage and resistance of the wafer are monitored in real time using a voltage and resistance testing device. When the voltage and resistance of the wafer increase to a preset value, the wafer deplating is terminated.

[0027] In this solution, the above settings are used to monitor the wafer stripping process in real time and terminate the stripping process in a timely manner, which effectively improves the mass transfer process of the electrolyte in the diffusion layer, thereby obtaining better uniformity and a smoother stripped surface, and further improving the wafer quality.

[0028] A TGV large square plate electroplating equipment, wherein the TGV large square plate electroplating equipment processes the substrate to be processed using the post-TGV large square plate electroplating processing method described above.

[0029] In this solution, the above-mentioned processing method after electroplating of TGV large square plates can replace the traditional processing method and obtain wafers of better quality.

[0030] Preferably, the TGV large square plate electroplating equipment further includes a clamp for picking up and placing multiple independent wafers formed after the substrate to be processed is cut.

[0031] In this solution, the above settings are used to effectively pick up and place wafers for electroplating.

[0032] Preferably, the TGV large square plate electroplating equipment includes a cutting section, which includes a laser cutting end.

[0033] In this solution, the above settings are used to effectively cut the substrate and form multiple independent wafers.

[0034] The significant advantages of this invention are as follows: By cutting the electroplated substrate before fine stripping, this invention replaces the processes of cleaning, drying, chemical mechanical polishing, thinning the plating layer, fabricating wiring layers, and cutting into individual chip devices. This avoids edge effects during wafer fabrication, ensures uniform plating removal, and prevents microcracks and stress concentration points that may occur during mechanical polishing and plating. It also avoids over-etching / under-etching phenomena using chemical methods, significantly improving the electrical performance, mechanical reliability, and long-term lifespan of the product. The "divide and conquer" approach of cutting before stripping isolates risks; the failure of a single wafer does not affect other wafers, significantly improving overall yield. Furthermore, the cutting process can proactively discard defective edge areas of the electroplated substrate, achieving pre-screening of quality. Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating a preferred embodiment of the processing method for TGV large square plates after electroplating.

[0036] Figure 2 This is a schematic diagram of the structure of the substrate to be processed according to a preferred embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of the structure of a substrate to be cut according to a preferred embodiment of the present invention.

[0038] Figure 4 This is a cross-sectional view of a wafer according to a preferred embodiment of the present invention.

[0039] Figure 5 This is a cross-sectional view of a wafer after deplating according to a preferred embodiment of the present invention.

[0040] Figure 6 This is a schematic diagram of wafer bonding according to a preferred embodiment of the present invention.

[0041] Explanation of reference numerals in the attached figures:

[0042] Through-hole 1; Substrate to be processed 2; Wafer 21; Flat-edge wafer 211; Notched wafer 212; Plating layer 3. Detailed Implementation

[0043] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments described herein.

[0044] This embodiment provides a method for processing TGV large square plates after electroplating, specifically as follows: Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6As shown, the post-electroplation treatment method for TGV large square plates includes the following steps:

[0045] S10. Obtain the substrate 2 to be processed after TGV electroplating;

[0046] S20. Cut the electroplated substrate 2 into multiple independent wafers 21 according to a preset cutting method;

[0047] S30. The diced wafers 21 are stripped of their plating, and the stripped wafers 21 are used for bonding to form bonding structures and semiconductor devices.

[0048] Specifically, the substrate 2 to be processed is a glass substrate. In this embodiment, the substrate 2 to be processed is square, with a size of 510 x 515 cm as an example. In step S10, the substrate 2 to be processed is electroplated using the existing TGV technology, so that through-holes 1 are opened on the substrate 2 and a relatively thick, uneven electroplated layer is formed on the surface of the substrate 2. The plating layer 3 is a copper layer, to facilitate the next step of the process after electroplating. It can be understood that the plating layer 3 can effectively fill the through-holes 1 during electroplating. Further, in step S20, the substrate 2 to be processed with the relatively thick, uneven electroplated layer is cut according to a preset cutting method to form multiple independent wafers 21. At the same time, in step S30, the wafers 21 are stripped of plating. The wafers 21 are stripped of plating independently to avoid edge effects and ensure the uniformity of plating stripping.

[0049] In this embodiment, instead of the processes of cleaning, drying, chemical mechanical polishing, thinning the plating layer 3, fabricating wiring layers, and cutting into individual chip devices, the electroplated substrate 2 is cut and then finely stripped. This avoids microcracks and stress concentration points that may occur on the substrate 2 during mechanical polishing and plating. It also avoids over-etching / under-etching caused by the lack of precise control in the chemical etching process, significantly improving the electrical performance, mechanical reliability, and long-term lifespan of the product. The stripped wafer 21 can be directly used for bonding and forming bonding structures and semiconductor devices. The "divide and conquer" approach of cutting before stripping isolates risks; the failure of a single wafer 21 does not affect other wafers 21, significantly improving the overall yield of the TGV large-format board after electroplating. Furthermore, the cutting process can proactively discard defective areas at the edges of the electroplated substrate 2, achieving pre-screening of quality.

[0050] Furthermore, in this embodiment, the following steps are included before step S10:

[0051] Before electroplating, the circuit unit layout and process reference markings are preset on the substrate 2 to be processed. The circuit unit layout and process reference markings are existing layout and marking methods, which are not improved in this embodiment. Instead, they are preset before electroplating on the substrate 2 to directly expose the copper pillars within the through-holes 1 after cutting and stripping the plating. It should be noted that the copper pillars are pillars formed within the through-holes 1 after the plating layer 3 is stripped, and their function is to conduct electricity. Simultaneously, the preset circuit unit layout and process reference markings also guide the cutting process. This allows for precise collaborative positioning and array arrangement algorithms for subsequent wafer dicing 21, determining the dicing array, with a preferred circular dicing shape. The resulting wafer 21 can be directly adapted to existing wafer manufacturing equipment, improving production line efficiency.

[0052] In this embodiment, step S20 further includes the following step:

[0053] When dicing the substrate 2 to be processed, multiple independent wafers 21 are formed according to a preset circuit unit layout and process reference mark array. Each diced wafer 21 includes at least one circuit unit (not shown in the figure). The center of each wafer 21 is located using the global process reference mark (e.g., a crosshair reference mark) on the mother board, i.e., the substrate 2 to be processed, as the origin of the coordinate system. This ensures that after dicing, each wafer 21 can contain one or more complete and usable circuit units to the maximum extent. By including at least one circuit unit on each wafer 21 when dicing according to the preset circuit unit layout and process reference marks, the effective circuit units on the substrate 2 to be processed are maximized, reducing material waste.

[0054] In this embodiment, wafer 21 includes a flat-edge wafer 211 and a notched wafer 212, and the following steps are also included when dicing the substrate 2 to be processed:

[0055] The flat-edge angle orientation of flat-edge wafer 211 remains consistent; the notch angle orientation of notched wafer 212 remains consistent.

[0056] Specifically, wafer 21 includes flat wafers 211 and notched wafers 212. Flat wafers are also called flat wafers, and notched wafers are also called notched wafers. For flat wafers 211 and notched wafers 212, the length and angular orientation of their flat edges need to be determined during dicing. For example, the angle between the flat edge and a certain edge of the substrate 2 to be processed. The angular orientation of all flat wafers, i.e., their orientation, should be consistent to facilitate the quick determination of the relative position of each flat wafer 211 in the substrate 2 to be processed during dicing. For notched wafers 212, the angular orientation of their notches, i.e., their orientation, also needs to be determined during dicing. For example, the angle between the line from the center of the notch to the edge of the substrate 2 and a certain edge of the substrate 2 to be processed, so that the diced wafers 21 can be quickly positioned in the substrate 2 to be processed, clamped, and stripped.

[0057] In this embodiment, the cutting method for cutting the substrate 2 to be processed includes laser cutting.

[0058] In this embodiment, step S30 further includes the following step:

[0059] When stripping the plating from wafer 21, jigs corresponding to flat-edge wafer 211 and notched wafer 212 are used for handling. By using different jigs to handle different wafers 21, the flat-edge wafer 211 and notched wafer 212 can be effectively distinguished.

[0060] In this embodiment, step S30 further includes the following step:

[0061] Electrochemical stripping is used when stripping the plating on wafer 21. The positive terminal of the electrochemical stripping equipment is connected to the wafer 21, and the negative terminal is connected to the anode of the plating chamber. Stripping is performed using a constant current mode or a pulse mode. The electrochemical stripping equipment is a standard stripping setup, and this embodiment does not improve upon it. By "breaking down" the substrate 2 into multiple independent wafers 21, the plating layer 3 is thinned using a stripping method. At this point, the wafer 21 to be stripped is circular instead of the substrate 2 with sharp edges, thus eliminating the current concentration effect caused by sharp edges. This results in more uniform and reliable stripping with a higher yield. This embodiment uses a pulse mode for stripping. By adjusting the pulse's on-time, off-time, and peak current, the mass transfer process of the electrolyte in the diffusion layer can be effectively improved, thereby obtaining better uniformity and a smoother stripped surface.

[0062] In this embodiment, the following steps are also included when stripping the plating on wafer 21:

[0063] A voltage and resistance testing device is used to detect the voltage and resistance of wafer 21 in real time. When the voltage and resistance of wafer 21 increase to the preset value, the deplating of wafer 21 is terminated.

[0064] Specifically, the voltage and resistance testing equipment is a conventional device used to detect resistance and voltage. This embodiment does not modify it. By real-time detection of the resistance and voltage during the stripping process of wafer 21, the stripping can be terminated in a timely manner, effectively improving the mass transfer process of the electrolyte in the diffusion layer, thereby obtaining better uniformity and a smoother stripped surface, further improving the quality of wafer 21. It is understood that when the stripping is not yet complete, the surface of wafer 21 has a thick, uneven electroplated layer. The plating layer 3 is a copper layer, and copper has high conductivity, resulting in low resistance and low voltage on wafer 21. When the stripping is complete, the plating layer 3 is thinned to the preset thickness, at which point the resistance increases, and the voltage increases accordingly. By detecting the resistance and voltage of wafer 21, the completion of the stripping can be determined in a timely manner, and the constant current mode or pulse mode in electrochemical stripping can be used to cut off the power in a timely manner to terminate the stripping. Compared with the lag in terminating the stripping during chemical stripping, this avoids the phenomenon of over-corrosion / under-corrosion caused by the inability to precisely control the corrosion process, significantly improving the electrical performance, mechanical reliability, and long-term life of the product.

[0065] This embodiment also provides a TGV large square plate electroplating equipment. The TGV large square plate electroplating equipment uses the above-mentioned processing method for the TGV large square plate electroplating to process the substrate 2 to be processed, so as to replace the traditional processing method by stripping multiple independent wafers 21 after the substrate 2 to be processed is cut, and to obtain wafers 21 with better quality.

[0066] Furthermore, in this embodiment, the TGV large-format plate electroplating equipment also includes a fixture (not shown in the figure), which is used to pick up and place multiple independent wafers 21 formed after the substrate 2 to be processed is cut. The fixture is configured with multiple types of wafers 21, including flat-edge wafers 211 and notched wafers 212. Different fixtures are used to pick up and place the corresponding flat-edge wafers 211 and notched wafers 212 to transfer the cut wafers 21 for stripping, and remove them after stripping. It is understood that the fixture is a fixture from the prior art, and this embodiment does not improve upon it.

[0067] In this embodiment, the TGV large square plate electroplating equipment includes a cutting section (not shown in the figure), which includes a laser cutting end. The substrate 2 to be processed is effectively cut using laser cutting to form multiple independent wafers 21. The cutting section can be a laser cutting device from the prior art; this embodiment does not improve upon it, and will not be described in detail here.

[0068] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.

Claims

1. A method for treating TGV large square plates after electroplating, characterized in that, The post-electroplating treatment method for the TGV large square plate includes the following steps: S10. Obtain the substrate to be processed after TGV electroplating; S20. Cut the electroplated substrate into multiple independent wafers according to a preset cutting method; S30. The diced wafers are stripped of their plating, and the stripped wafers are used for bonding to form bonding structures and semiconductor devices.

2. The method for processing TGV large square plates after electroplating as described in claim 1, characterized in that, The following steps are included before step S10: The circuit unit layout and process reference markings are preset on the substrate to be processed before electroplating.

3. The method for treating TGV large square plates after electroplating as described in claim 2, characterized in that, Step S20 also includes the following steps: When cutting the substrate to be processed, multiple independent wafers are cut and formed according to a preset circuit unit layout and process reference mark array, and each cut wafer includes at least one circuit unit.

4. The method for treating TGV large square plates after electroplating as described in claim 3, characterized in that, The wafer includes flat-edge wafers and notched wafers, and the process of dicing the substrate to be processed further includes the following steps: The flat-edge wafers maintain a consistent flat-edge angle orientation; the notch-angle wafers maintain a consistent notch-angle orientation.

5. The method for treating TGV large square plates after electroplating as described in claim 3, characterized in that, When cutting the substrate to be processed, the cutting method includes laser cutting.

6. The method for processing TGV large square plates after electroplating as described in claim 1, characterized in that, Step S30 also includes the following steps: When stripping the wafer, electrochemical stripping is used. The positive terminal of the power supply of the electrochemical stripping equipment is connected to the wafer to be stripped, and the negative terminal of the electrochemical stripping equipment is connected to the anode of the electroplating chamber of the electrochemical stripping equipment. The stripping is performed in constant current mode or pulse mode.

7. The method for treating TGV large square plates after electroplating as described in claim 6, characterized in that, The process of stripping the plating from the wafer also includes the following steps: The voltage and resistance of the wafer are monitored in real time using a voltage and resistance testing device. When the voltage and resistance of the wafer increase to a preset value, the wafer deplating is terminated.

8. A TGV large square plate electroplating equipment, characterized in that, The TGV large square plate electroplating equipment uses the post-electroplating treatment method for TGV large square plates as described in any one of claims 1-7 to process the substrate to be processed.

9. The TGV large square plate electroplating equipment as described in claim 8, characterized in that, The TGV large square plate electroplating equipment also includes a clamp, which is used to pick up and place multiple independent wafers formed after the substrate to be processed is cut.

10. The TGV large square plate electroplating equipment as described in claim 8, characterized in that, The TGV large square plate electroplating equipment includes a cutting section, which includes a laser cutting end.

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