Array substrate, driving method of liquid crystal display and display device

Abstract

The invention provides an array substrate, a driving method of a liquid crystal display and a display device, the array substrate comprises a plurality of pixel units, the plurality of pixel units are arranged in an array, and each pixel unit comprises at least three sub-pixels which are different in light emitting color and adjacent in position; the plurality of grid line groups respectively correspond to the plurality of rows of pixel units, each grid line group comprises a plurality of grid lines extending along the row direction, the number of the grid lines included in the grid line groups is the same as the number of sub-pixels in the pixel units, one grid line in one grid line group is connected with the sub-pixels which are located in the same row and emit light of the same color; the array substrate comprises a plurality of columns of pixel units, and a plurality of data line groups respectively corresponding to the plurality of columns of pixel units, each data line group comprises one or more parallel data lines extending along the column direction, and all the sub-pixels in a single pixel unit are connected with the data lines in the same data line group.

Description

Array substrate, driving method of liquid crystal display and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to an array substrate, a driving method of a liquid crystal display and a display device. BACKGROUND

[0002] Current display can include liquid crystal display, OLED (Organic Light-Emitting Diode) display, and no matter which display, array substrate will be used. Among them, a plurality of gate lines and a plurality of data lines are formed on the array substrate, wherein the gate line is used to provide a scanning signal, and the data line is used to provide a data signal. The scanning signal is used to turn on the thin film transistor located at the pixel, so that the data signal provided by the data line is given to the sub-pixel, such as the pixel electrode of the sub-pixel. Generally speaking, the data line is driven by a data driving chip, and a data driving chip has a plurality of output channels, and one output channel corresponds to driving one data line. Among them, the data driving chip is related to the manufacturing cost of the display.

[0003] SUMMARY

[0004] Based on the content of the background art, the present disclosure provides an array substrate, a driving method of a liquid crystal display and a display device.

[0005] The first aspect of the present disclosure provides an array substrate, comprising:

[0006] a plurality of pixel units, the plurality of pixel units are arranged in an array, each of the pixel units comprises at least three sub-pixels with different emitting colors and adjacent positions;

[0007] a plurality of gate line groups corresponding to a plurality of rows of the pixel units, the gate line group comprises a plurality of gate lines extending along the row direction, the number of the gate lines included in the gate line group is the same as the number of the sub-pixels in the pixel unit, wherein one of the gate lines in one of the gate line groups is connected to the sub-pixels located in the same row and emitting the same color light; and

[0008] a plurality of data line groups corresponding to a plurality of columns of the pixel units, the data line group comprises one or more parallel data lines extending along the column direction, and all the sub-pixels in a single pixel unit are connected to the data line in the same data line group.

[0009] In an exemplary embodiment, the data line group comprises one data line, and the orthogonal projection of the data line on the substrate substrate is located between the orthogonal projections of two adjacent pixel units on the substrate substrate.

[0010] In an example embodiment, multiple pixel units in the same column are connected with data lines in the same data line group.

[0011] In an example embodiment, two pixel units in the same column and adjacent to each other are connected with data lines in two adjacent data line groups respectively.

[0012] In an example embodiment, the data line comprises a first end and a second end, and the data line group comprises multiple parallel data lines;

[0013] In an example embodiment, the first ends of the multiple data lines in the data line group are connected with each other, and / or the second ends of the multiple data lines are connected with each other.

[0014] In an example embodiment, the array substrate comprises a display area and a peripheral area, and multiple pixel units are located in the display area.

[0015] The peripheral area comprises a fan-out area, a transition area and a load area, the load area is arranged close to the display area, the fan-out area is located on a side of the transition area away from the display area, the transition area is located between the fan-out area and the load area, and the fan-out area comprises multiple data leads.

[0016] In an example embodiment, the multiple data lines in the data line group are connected with each other at one end close to the fan-out area, and the connection point is located on a side of the load area close to the transition area, and the data leads are connected with the connection point of the multiple data lines in the data line group after being routed along the transition area.

[0017] In an example embodiment, multiple sub-pixels comprised in the pixel unit are adjacent in the row direction, and the data line group comprises multiple parallel data lines, and the adjacent two data lines in the same data line group are separated by one or two columns of the sub-pixels.

[0018] In an example embodiment, the multiple data lines comprised in the array substrate are located in at least two different film layers.

[0019] In an example embodiment, the data line group comprises multiple parallel data lines, and two adjacent data line groups are located in different film layers respectively.

[0020] In an example embodiment, multiple sub-pixels in the pixel unit are adjacent in the row direction, and the multiple gate lines in the gate line group are arranged into multiple rows in a display order, and the display order is used to represent a scanning order of the multiple rows of the sub-pixels.

[0021] Among the plurality of gate lines connected with the plurality of sub-pixels in one pixel unit, the gate line at the front of the display sequence is connected with the sub-pixel emitting target color light in the pixel unit, and the target color light is color light other than red light.

[0022] In an exemplary embodiment, the gate line at the front of the display sequence is connected with the sub-pixel emitting blue light in the pixel unit.

[0023] In an exemplary embodiment, the array substrate further comprises:

[0024] A plurality of signal lines are arranged at intervals along the column direction and are staggered with the plurality of data line groups on the array substrate; wherein the orthographic projection of the signal line on the substrate substrate is located between the orthographic projections of the adjacent two sub-pixels on the substrate substrate.

[0025] Among the plurality of signal lines, there are signal lines connected with the common electrode of the array substrate and / or signal lines connected with the touch signal line of the array substrate.

[0026] In an exemplary embodiment, the plurality of signal lines are located in at least two different film layers; and / or, the signal lines are arranged in different layers from the data lines.

[0027] In an exemplary embodiment, the signal line is overlapped with the common electrode or the touch signal line through a via hole;

[0028] The orthographic projection of the via hole on the substrate substrate is located within the orthographic projection of the gate line group on the substrate substrate, and does not overlap with the orthographic projection of the gate line on the substrate substrate.

[0029] In an exemplary embodiment, the sub-pixel comprises a thin film transistor, and

[0030] A common electrode layer, the orthographic projection of the common electrode layer on the substrate substrate covers the area where the sub-pixel is located;

[0031] A pixel electrode is located on the side of the common electrode layer away from the substrate substrate and is connected with the drain of the thin film transistor;

[0032] The orthographic projection of the pixel electrode on the substrate substrate overlaps with the orthographic projection of the source of the thin film transistor on the substrate substrate, and / or overlaps with the orthographic projection of the gate of the thin film transistor on the substrate substrate.

[0033] In an exemplary embodiment, the sub-pixel comprises a thin film transistor, the thin film transistor comprises:

[0034] an active layer comprising a channel region and a source region and a drain region located on opposite sides of the channel region;

[0035] a gate layer, a projection of the gate layer on the substrate substrate covering a projection of the channel region on the substrate substrate;

[0036] wherein a projection of an edge of the channel region on the substrate substrate close to the data line is parallel to an edge of the substrate substrate.

[0037] In an exemplary embodiment, a projection of the channel region on the substrate substrate comprises a letter.

[0038] In an exemplary embodiment, the data line group comprises one data line, the data line being connected to a plurality of the sub-pixels in the pixel unit respectively; wherein the data line comprises a first branch connected to a first sub-pixel, and a second branch connected to the first branch and a second sub-pixel respectively.

[0039] wherein the second branch comprises a plurality of bends, and the second sub-pixel is adjacent to the first sub-pixel.

[0040] In an exemplary embodiment, a projection of the first branch and the second branch on the substrate substrate is substantially U-shaped, and the sub-pixel comprises a thin film transistor.

[0041] wherein the first branch and the second branch overlap with an active layer of the thin film transistor.

[0042] A second aspect of the present disclosure provides a driving method of a liquid crystal display, wherein the liquid crystal display comprises the array substrate of any one of the exemplary embodiments of the first aspect, and the driving method comprises:

[0043] in a lighting period of lighting the sub-pixels located in the same row, sequentially outputting driving scanning signals to a plurality of gate lines in the same gate line group according to a driving timing sequence;

[0044] and outputting corresponding data voltages to the data lines in each of the data line groups when outputting the driving scanning signals to the gate lines, and inputting data voltages with opposite polarities to two adjacent data line groups in each of the lighting periods, so that the polarities of the data voltages input by the same data line group in two adjacent lighting periods are the same.

[0045] A third aspect of the present disclosure provides a display device, comprising the array substrate of any one of the first aspect.

[0046] The array substrate provided by the present disclosure comprises a plurality of pixel units arranged in an array, each pixel unit comprising at least three sub-pixels of different light-emitting colors and adjacent to each other; a plurality of gate line groups corresponding to a plurality of rows of pixel units respectively, each gate line group comprising a plurality of gate lines extending in a row direction, and a gate line in the gate line group being connected to sub-pixels of the same color in the same row; and a plurality of data line groups corresponding to a plurality of columns of pixel units respectively, each data line group comprising one or more parallel data lines extending in a column direction, and all sub-pixels in a single pixel unit being connected to data lines in the same data line group. Since one row of pixel units can share one gate line group, and the number of gate lines in the gate line group is the same as the number of sub-pixels in the pixel unit, the sub-pixels of the same color in one row of sub-pixels are driven by the same gate line. In this way, for a single pixel unit, the number of gate lines required by the pixel unit is more than the number of data line groups, and one output channel of an output data signal can be shared by a plurality of sub-pixels, so that the number of output channels for providing data signals to the sub-pixels can be reduced to at least one third of the original number. Compared with the conventional one output channel driving one sub-pixel of a light-emitting color, the number of output channels can be greatly reduced, thereby reducing the demand for data driving chips, and thus the cost of the display can be reduced.

[0047] The above description is only a summary of the technical solutions of the present disclosure. In order to enable a clearer understanding of the technical means of the present disclosure, the contents of the specification can be implemented, and in order to enable the above and other purposes, features and advantages of the present disclosure to be more apparent and easy to understand, the specific embodiments of the present disclosure are described below.

[0048] Brief Description of Drawings

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or related art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0050] FIG. 1 shows a schematic diagram of the area distribution of the array substrate proposed in an embodiment of the present disclosure;

[0051] FIGS. 2 and 3 respectively show schematic diagrams of the pixel design of two array substrates;

[0052] FIGS. 4-6 respectively show schematic diagrams of the pixel design of three other different array substrates provided in embodiments of the present disclosure;

[0053] FIG. 7 shows a layout design schematic diagram of an array substrate provided in an embodiment of the present disclosure in a peripheral region of a display region;

[0054] FIG. 8 shows a layout design schematic diagram of a partial region in FIG. 7;

[0055] FIGS. 9-12 respectively show pixel design schematic diagrams of two other different array substrates provided in embodiments of the present disclosure;

[0056] FIG. 13 shows a schematic diagram of a display screen having a black and white boundary screen;

[0057] FIGS. 14, 15a, 15b and 16 respectively show wiring structure schematic diagrams of four other array substrates;

[0058] FIG. 17 shows a partial structure schematic diagram in a cross-sectional direction of the array substrate shown in FIG. 16;

[0059] FIG. 18 shows a wiring layout of an array substrate;

[0060] FIG. 19 shows a wiring schematic diagram of an array substrate;

[0061] FIG. 20 shows a layout design schematic diagram of the array substrate in FIG. 19;

[0062] FIG. 21 shows a cross-sectional structure schematic diagram in an A-A direction of the array substrate shown in FIG. 20;

[0063] FIG. 22 shows a cross-sectional structure schematic diagram in a B-B direction of the array substrate shown in FIG. 20;

[0064] FIG. 23 shows an enlarged schematic diagram of a dashed box region of the array substrate in FIG. 20;

[0065] FIG. 24 shows a wiring layout of an array substrate in an embodiment;

[0066] FIG. 25 shows an enlarged schematic diagram of a connection structure between a data line and a pixel unit in FIG. 24;

[0067] FIG. 26 shows a layout of the array substrate shown in FIG. 5;

[0068] FIG. 27 shows a layout of the array substrate shown in FIG. 15b;

[0069] FIG. 28 shows a step flow schematic diagram of a driving method of a liquid crystal display;

[0070] FIG. 29 shows waveforms of S1 & S2 and G1-G3 when the array substrate A displays a blue screen (B255);

[0071] Explanation of reference signs: 10, display area; 20, peripheral area; 21, load area; 22, transition area; 23, fan-out area; S, data line group; G, gate line group; 30, signal line; 30a, signal line connected with touch signal line; 30b, signal line connected with common electrode; L1-L3, film layer; 40, common electrode layer; 50, pixel electrode; 101, gate; 102, drain; 103, source; 104, channel area; 1041, first edge; 1042, second edge; 1031, first branch; 1032, second branch; 70, connection line; 80, data lead; 301, via hole; Sa, first data line; Sb, second data line; 61, first line segment; 62, second line segment; 63, third line segment; 64, connection point.

[0072] DETAILED DESCRIPTION

[0073] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0074] In the related art, taking a liquid crystal display as an example, the liquid crystal display includes an array substrate and a color film substrate arranged in a box, and liquid crystal is arranged between the array substrate and the color film substrate. When display driving is performed, a gate line provides a scanning signal, a data line provides a data signal, and a sub-pixel at the intersection of the activated gate line and data line is charged, so as to drive the liquid crystal to deflect, and then to pass through or not to pass through the light of a backlight plate, so as to realize display. The liquid crystal display occupies a dominant position in the field of flat panel display, and currently needs to reduce the cost of the liquid crystal display. As described in the background art, the cost of the liquid crystal display is mainly related to a data driving chip.

[0075] Therefore, the present disclosure proposes an array substrate adopting a new wiring design of data lines and gate lines, which is mainly used to reduce the number of data driving chips. The specific design idea is to reduce the number of output channels of output data signals and increase the number of gate lines, so that one output channel can correspond to the driving of a plurality of sub-pixels emitting light of different colors.

[0076] Referring to FIG. 1, FIG. 2, and FIG. 3, FIG. 1 shows a schematic diagram of the area distribution of the array substrate proposed in an embodiment of the present disclosure, and FIG. 2 and FIG. 3 respectively show schematic diagrams of the top pixel design of two kinds of array substrates. As shown in FIG. 1-FIG. 3, the array substrate in the present embodiment mainly includes:

[0077] a plurality of pixel units arranged in an array, each pixel unit comprising at least three adjacent sub-pixels;

[0078] a plurality of gate line groups G corresponding to the plurality of rows of pixel units respectively, each gate line group G comprising a plurality of gate lines extending in a row direction, the number of gate lines included in each gate line group G being the same as the number of sub-pixels in a pixel unit, and a gate line in a gate line group G being connected to sub-pixels in the same row that emit light of the same color; and

[0079] a plurality of data line groups S corresponding to the plurality of columns of pixel units respectively, each data line group S comprising a plurality of data lines extending in a column direction, and all sub-pixels in a single pixel unit being connected to data lines in the same data line group S.

[0080] In some embodiments, each data line group S comprises one data line or a plurality of parallel data lines.

[0081] In some embodiments, the array substrate can be used in a liquid crystal display or an OLED display.

[0082] In some embodiments, the array substrate comprises a display region 10 and a peripheral region 20 surrounding the display region. In some embodiments, the peripheral region 20 comprises a fan-out region 23, a transition region 22, and a load region 21. The load region 21 is located adjacent to the display region, the transition region 22 is located on a side of the load region 21 away from the display region, and the fan-out region 23 is located on a side of the transition region 22 away from the display region. In some embodiments, a binding region is further provided on a side of the fan-out region away from the display region. The binding region can be located on a front surface of the array substrate or a back surface of the array substrate. In some embodiments, a data driving chip and a gate driving chip are mounted in the binding region, and gate line leads and data leads are arranged in the fan-out region. One data lead is connected to one output pin of the data driving chip, and a plurality of gate lines are connected to the gate driving chip. In some embodiments, one data lead is connected to a data line in one data line group S, so that data signals output by the data driving chip are transmitted to the data line group S. The transition region is used to connect the leads in the fan-out region to the display region, and the load region is provided with a gate driving circuit to drive the gate lines to scan.

[0083] As shown in FIGS. 2 and 3, the array substrate can comprise a plurality of pixel units arranged in an array, and each pixel unit can comprise a plurality of sub-pixels. The plurality of sub-pixels can also be arranged in rows and columns on the array substrate. It should be noted that the sub-pixel described in the present embodiment can be a combination of a thin film transistor and a pixel electrode connected to the drain of the thin film transistor. For example, when the array substrate is used in a liquid crystal display, the sub-pixel can comprise a thin film transistor and a pixel electrode connected to the drain of the thin film transistor. When the array substrate is used in an OLED display, the sub-pixel can comprise a thin film transistor and an anode connected to the drain of the thin film transistor.

[0084] The plurality of sub-pixel arrays are arranged, specifically, the plurality of sub-pixels can be arranged into multiple rows and multiple columns, specifically, the plurality of sub-pixels can be arranged according to the required light-emitting colors, for example, the sub-pixels emitting the same color light are arranged into a column, and the sub-pixels emitting different color lights are arranged in the row direction in an interlaced manner, so that the light-emitting colors corresponding to every two adjacent sub-pixels in a row are different, which is shown in FIGS. 2 and 3. This arrangement can also be referred to as a longitudinal pixel arrangement. It should be noted that in the longitudinal pixel arrangement, the lateral dimension of the sub-pixel is less than the longitudinal dimension, for example, the lateral-to-longitudinal ratio of the sub-pixel is a first ratio. Of course, in other embodiments, the sub-pixels emitting the same color light can also be arranged into a row, and the sub-pixels emitting different color lights can be arranged in the column direction in an interlaced manner, so that the light-emitting colors corresponding to every two adjacent sub-pixels in a column are different, which can also be referred to as a transverse pixel arrangement. It should be noted that in the transverse pixel arrangement, the lateral dimension of the sub-pixel is greater than the longitudinal dimension, for example, the lateral-to-longitudinal ratio of the sub-pixel is a second ratio, wherein the first ratio is less than the second ratio. As shown in subsequent FIG. 4.

[0085] In the present example, each pixel unit can include at least three adjacent sub-pixels, wherein the light-emitting colors corresponding to the three adjacent sub-pixels are different for one pixel unit. In the longitudinal pixel arrangement, the multiple sub-pixels in one pixel unit are adjacent in the row direction, and in the transverse pixel arrangement, the multiple sub-pixels in one pixel unit are adjacent in the column direction. Taking FIGS. 2 and 3 as examples, in the longitudinal pixel arrangement, the light-emitting colors of the sub-pixels in the same column are the same, and the light-emitting colors of every two adjacent sub-pixels in a row are different, so that the adjacent three columns of sub-pixels in a row of sub-pixels can constitute one pixel unit, and the three sub-pixels in one pixel unit are a red light-emitting sub-pixel R, a green light-emitting sub-pixel G, and a blue light-emitting sub-pixel B, respectively.

[0086] The plurality of sub-pixel arrays are arranged, specifically, the plurality of sub-pixels can be arranged into multiple rows and multiple columns, specifically, the plurality of sub-pixels can be arranged according to the required light-emitting colors, for example, the sub-pixels emitting the same color light are arranged into a column, and the sub-pixels emitting different color lights are arranged in the row direction in an interlaced manner, so that the light-emitting colors corresponding to every two adjacent sub-pixels in a row are different, which is shown in FIGS. 2 and 3. This arrangement can also be referred to as a longitudinal pixel arrangement. It should be noted that in the longitudinal pixel arrangement, the lateral dimension of the sub-pixel is less than the longitudinal dimension, for example, the lateral-to-longitudinal ratio of the sub-pixel is a first ratio. Of course, in other embodiments, the sub-pixels emitting the same color light can also be arranged into a row, and the sub-pixels emitting different color lights can be arranged in the column direction in an interlaced manner, so that the light-emitting colors corresponding to every two adjacent sub-pixels in a column are different, which can also be referred to as a transverse pixel arrangement. It should be noted that in the transverse pixel arrangement, the lateral dimension of the sub-pixel is greater than the longitudinal dimension, for example, the lateral-to-longitudinal ratio of the sub-pixel is a second ratio, wherein the first ratio is less than the second ratio. As shown in subsequent FIG. 4.

[0087] Specifically, for the same gate line group, one gate line in the gate line group can be connected with the sub-pixels located in one row and emitting the same color light. For example, as shown in FIGS. 2 and 3, one gate line group includes three gate lines, and different gate lines are connected with the sub-pixels of different light emitting colors in one row of sub-pixels. It should be noted that the connection between the gate line and the sub-pixel actually means that the gate line is connected with the gate electrode of the thin film transistor of the sub-pixel. Generally, the gate electrode and the gate line are in different layers, and at least one film layer is included between the gate electrode of the thin film transistor and the gate line. Therefore, the connection mode between the gate line and the gate electrode can be that the gate line is connected with the gate electrode through a via hole formed in each film layer.

[0088] The display panel further includes a plurality of data line groups, each of which can correspond to a plurality of pixel units in the column direction. The plurality of data lines in each data line group extend in the column direction. The gate lines and the data lines can be orthogonal or substantially orthogonal to each other. The intersection position of the gate lines and the data lines can be the position of the thin film transistor of the sub-pixel. Specifically, the plurality of data lines can be divided into a plurality of data line groups. One data line group can include one data line or a plurality of parallel data lines. The parallel means that the plurality of data lines in the data line group are connected to the same output channel, for example, the same pin of the data driving chip, so that the data signals on the plurality of data lines in the same data line group are the same at the same time.

[0089] In the case where the data line group includes a plurality of parallel data lines, the number of data lines included in one data line group can be less than or equal to the number of sub-pixels in the pixel unit, or can be greater than the number of sub-pixels in the pixel unit.

[0090] In the embodiment, all the sub-pixels in one pixel unit are connected to the same data line group. For example, as shown in FIG. 2, in the case where the data line group includes one data line, the thin film transistors of the three sub-pixels in one pixel unit are connected in parallel to the one data line.

[0091] For example, in the case where the data line group includes a plurality of data lines, the thin film transistors of all the sub-pixels in one pixel unit can be connected to the plurality of data lines in the same data line group. For example, two sub-pixels in one pixel unit are connected to the same data line in one data line group, and the remaining sub-pixel is connected to another data line in the data line group. For example, as shown in FIG. 3, the data line group includes parallel data lines. The sub-pixel B is connected to one data line in the data line group S1, and the sub-pixel R and the sub-pixel G are connected in parallel to another data line in the data line group S1.

[0092] In the case that the data line group includes a plurality of data lines in parallel, the plurality of data lines in parallel can reduce the resistance of the data line group, thereby reducing the driving power consumption of the data driving chip, and reducing the wiring difficulty between the thin film transistor of the sub-pixel and the data line.

[0093] In some embodiments, in the case that the data line group includes one data line, the data line can be shared by three sub-pixels in the pixel unit, that is, one data line drives three sub-pixels. In this embodiment, the data line needs to be connected to the three sub-pixels respectively, which can also be understood as that the thin film transistors of the three sub-pixels in the pixel unit are connected in parallel to the same data line.

[0094] In this embodiment, in the case that the data line group includes one data line, the orthogonal projection of the data line on the substrate can be located between the orthogonal projections of the adjacent two pixel units on the substrate.

[0095] In the case that the data line group includes one data line, the data line can be located between the adjacent two pixel units, for example, the orthogonal projection of the data line in each data line group on the substrate is located between the orthogonal projections of the adjacent two pixel units on the substrate. For example, as shown in FIG. 2, the data line can be located between the sub-pixel R and the sub-pixel B, so as to avoid occupying the wiring space between the sub-pixels of the pixel unit, thereby expanding the area of the sub-pixel. When applied to a liquid crystal display, the area of the pixel electrode of the sub-pixel can be appropriately increased; when applied to an OLED display, the aperture ratio of the sub-pixel can be appropriately increased. In the case that the area of the sub-pixel is increased, the light emitting area of the sub-pixel can be increased, thereby realizing high-resolution design.

[0096] The technical scheme of the embodiment can reduce the number of output channels of the output data signal, thereby reducing the demand for the data driving chip, and thus reducing the cost of the display. In the case that the data line group includes a plurality of data lines in parallel, the parallel connection can reduce the resistance, reduce the driving power consumption of the array substrate, and reduce the wiring difficulty between the data line and the sub-pixel. In the case that the data line group includes one data line, the data line can be located in the gap between the two pixel units, thereby increasing the light emitting area of the sub-pixel, and realizing high-resolution design.

[0097] In some embodiments, the array substrate can be arranged in a longitudinal pixel arrangement, in which the same column of the array substrate includes a plurality of sub-pixels emitting the same color light, and two adjacent sub-pixels in the same row emit different color light; or the array substrate can be arranged in a horizontal pixel arrangement, in which the same row of the array substrate includes a plurality of sub-pixels emitting the same color light, and two adjacent sub-pixels in the same column emit different color light.

[0098] In some embodiments, the array substrate can be arranged in a longitudinal pixel arrangement, in which the same column of the array substrate includes a plurality of sub-pixels emitting the same color light, and two adjacent sub-pixels in the same row emit different color light; or the array substrate can be arranged in a horizontal pixel arrangement, in which the same row of the array substrate includes a plurality of sub-pixels emitting the same color light, and two adjacent sub-pixels in the same column emit different color light.

[0099] In order to match the polarity inversion, in one embodiment, the plurality of pixel units in the same column can be connected to the data lines in the same data line group. In this case, no matter whether the data line group includes one data line or multiple data lines, the plurality of sub-pixels in the same column can be connected to the same data line. In this embodiment, please continue to refer to FIG. 2 and FIG. 3, the data lines connected by the plurality of sub-pixels in the same column can be located in the same data line group.

[0100] In some embodiments, the array substrate can be arranged in a longitudinal pixel arrangement, in which the same column of the array substrate includes a plurality of sub-pixels emitting the same color light, and two adjacent sub-pixels in the same row emit different color light; or the array substrate can be arranged in a horizontal pixel arrangement, in which the same row of the array substrate includes a plurality of sub-pixels emitting the same color light, and two adjacent sub-pixels in the same column emit different color light.

[0101] In the case that the plurality of sub-pixels in the pixel unit are adjacent in the row direction, the sub-pixels in the same column correspond to the same light-emitting color, and if the data line group includes a plurality of data lines, one data line in the data line group can connect the sub-pixels on one column or more columns, and for each data line in the data line group, the plurality of sub-pixels connected by the data line are in the same column. Taking FIG. 3 as an example, the data line group S1 includes two data lines, one data line in the two data lines connects the sub-pixel R in the same column and the sub-pixel G in the same column, and the other data line connects the sub-pixel B in the same column. Similarly, in one driving period, the polarities of the data voltages input on the two data lines in the data line group S1 are the same, the polarities of the data voltages input on the two data lines in the data line group S2 are the same, and the polarities of the data voltages input by the data line group S1 and the data line group S2 are opposite, so that column inversion is realized in the same frame of picture.

[0102] In another embodiment in which polarity inversion is realized, one data line group can drive two adjacent pixel units in the column direction to realize dot inversion driving, which can refer to that in the same frame of display picture, the polarities of the data voltages on every two adjacent pixel units are opposite.

[0103] Please refer to FIG. 4, FIG. 5 and FIG. 6, FIG. 4 shows a wiring diagram of an array substrate in horizontal pixel arrangement, and FIG. 5 and FIG. 6 respectively show wiring diagrams of array substrates in vertical pixel arrangement.

[0104] As shown in FIG. 4, the plurality of sub-pixels in the same row can emit light of the same color, and the two adjacent sub-pixels in the same column can emit light of different colors, which can also be understood as that the plurality of sub-pixels included in the pixel unit are adjacent in the column direction, and the sub-pixels in one pixel unit in the same column and adjacent to each other are connected to one data line group, and the sub-pixels in the other pixel unit are connected to another adjacent data line group.

[0105] In this embodiment, the data line group includes one data line, and the two adjacent pixel units in the same column are respectively connected to two adjacent data lines, specifically, as shown in FIG. 4, the two adjacent sub-pixels of the same light-emitting color in the same column can be respectively connected to two different data lines, and the two data lines are adjacent data lines, and the plurality of sub-pixels in the same pixel unit are connected to the same data line. For example, as shown in FIG. 4, the two adjacent sub-pixels R are respectively connected to the data line S1 and the data line S2, and the sub-pixel R, the sub-pixel G and the sub-pixel B in the same pixel unit are all connected to the data line S1.

[0106] With the array substrate, the polarity of the data voltage on the same data line can be kept unchanged during the driving of one frame of display picture, and the polarity of each two adjacent pixel units in the whole picture can be reversed through the connection between the data line and the pixel unit.

[0107] As shown in FIGS. 5-6, the plurality of sub-pixels in the same column correspond to the same light-emitting color, and each two adjacent sub-pixels in the same row have different light-emitting colors, i.e., the plurality of sub-pixels in the pixel unit are adjacent in the row direction, and in the case where the two pixel units in the same column and adjacent to each other are connected with the data lines in the two adjacent data line groups respectively, the two sub-pixels in the same column and adjacent to each other are connected with the data lines in the two adjacent data line groups respectively in the embodiment.

[0108] As shown in FIGS. 5 and 6, the plurality of sub-pixels in the same column are cross-connected with the data lines in the two adjacent data line groups.

[0109] As shown in FIG. 5, the data line group includes one data line, the one data line can be connected with the plurality of sub-pixels in the same pixel unit, and the two sub-pixels in the same column and adjacent to each other are connected with the two adjacent data lines respectively. When the plurality of sub-pixels on the array substrate are driven, in the driving period of the first row of sub-pixels, the data line S2 drives the pixel unit on the second column of the first row, and in the scanning period of the second row of sub-pixels, the data line S2 drives the pixel unit on the first column of the second row. That is, for the same data line group, the data line group drives the pixel units in different columns in the lighting period of the adjacent two rows.

[0110] In the data line group, as shown in FIG. 6, the data line group includes a plurality of parallel data lines, and the plurality of data lines in the same data line group are connected to a plurality of sub-pixels in the same pixel unit. In an example, for the same data line in the same data line group, the number of sub-pixels connected by the data line in the nth row is different from the number of sub-pixels connected by the data line in the (n+1)th row. Taking FIG. 6 as an example, the data line group S2 includes two data lines, and one data line of the data line group S2 is connected to the sub-pixel R and the sub-pixel G in the second column pixel unit in the first row, and is connected to three sub-pixels in the first column pixel unit in the second row; and then is connected to the sub-pixel R and the sub-pixel G in the second column pixel unit in the third row. Similarly, for the other data line in the data line group S2, the data line is connected to the sub-pixel B in the second column pixel unit in the first row, is not connected to any sub-pixel in the second row, and is connected to the sub-pixel B in the second column pixel unit in the third row. In this example, since the data line group includes a plurality of data lines, and the data line group needs to be connected to the pixel units on two columns in an interlaced manner, the arrangement and wiring between the data line and the sub-pixel can be facilitated when the data line is connected to different numbers of sub-pixels in different rows, and specifically, the wiring requirement can be simplified.

[0111] Similarly, the plurality of sub-pixels in the same column are cross-connected to the sub-pixels in the adjacent two data line groups, and the polarity of the data voltage on the same data line can be kept unchanged during the driving process of one frame of display picture, and the polarity of every adjacent two pixel units in the whole picture can be opposite through the cross-connection relationship between the data line and the pixel unit, so that the driving logic during the point inversion can be simplified.

[0112] In some embodiments, when the data line group includes a plurality of parallel data lines, the plurality of data lines in the same data line group are connected in parallel, and specifically, the data line includes a first end and a second end, the first ends of the plurality of data lines in the data line group are connected to each other, and / or the second ends of the plurality of data lines are connected to each other.

[0113] Referring to FIGS. 7 and 8, FIG. 7 shows a wiring schematic diagram of an array substrate in a display area and a peripheral area in an embodiment of the present disclosure, and FIG. 8 shows an enlarged schematic diagram of a part of the layout shown in FIG. 7. As shown in FIGS. 7 and 8, the array substrate includes a display area 10 and a peripheral area 20, and the peripheral area 20 can be provided with a fan-out area 23, a transition area 22 and a load area 21. The load area is arranged close to the display area, the fan-out area is located on a side of the transition area away from the display area, and the transition area is located between the fan-out area and the load area. A plurality of data leads 80 are arranged in the fan-out area, each data lead 80 can be connected to one output pin of a data driving chip, and one data lead is connected to one data line group S.

[0114] In this embodiment, the first end of the data line can refer to the end close to the data lead, specifically, any end of the plurality of data lines in the same data line group can be connected to each other, for example, the first ends of the plurality of data lines are connected to each other and then connected to the data lead, or the second ends of the plurality of data lines are connected to each other. As shown in FIG. 3, it is shown that the ends of the plurality of data lines are connected to each other. In some other examples, the first ends of the data lines in the same data line group are connected to each other and the second ends are connected to each other, in this case, it can be referred to as the first end and the second end of the data line being connected.

[0115] When the first end and / or the second end of the plurality of data lines in the same data line group are connected to each other, the equivalent resistance of the data line can be further reduced, thereby reducing the driving power consumption.

[0116] Continuing to combine FIGS. 7 and 8, the plurality of data lines in the data line group are connected in parallel at the end close to the data lead, and then connected to the data lead. Specifically, the connection point 64 at which the plurality of data lines in the data line group are connected to each other can be located between the load area and the transition area, such as the side of the load area close to the transition area, or the transition area, as shown in the circle in FIG. 8. Wherein, the wiring of the plurality of data lines in the same data line group can be slightly different to facilitate the connection between the data lines. For example, in some examples, the data line group can include at least one first data line Sa, which includes a first line segment 61 extending in the column direction and a second line segment 62 extending in the row direction, and the first line segment 61 can be connected to a second data line Sb other than the first data line in the first data line group, and the second line segment 62 is connected to the data lead through a third line segment 63 bent towards the peripheral area.

[0117] Wherein, in the case that the data line group includes two parallel data lines, it can include one first data line Sa, that is, one first data line with a bending portion; in the case that the data line group includes three parallel data lines, it can include two first data lines Sa, that is, it can include two first data lines with a bending portion. The remaining second data lines in the data line group extend in the column direction and can not have a bending.

[0118] Wherein, as shown in FIGS. 7 and 8, the first data line Sa includes a first line segment 61 extending in the column direction and a second line segment 62 extending in the row direction, and the first line segment and the second line segment are connected through a bending portion, wherein the first line segment can be connected to a second data line other than the first data line in the first data line group, and the second line segment is connected to the data lead through a third line segment bent towards the peripheral area, and the connection between the second line segment and the second data line is located at the side of the load area close to the transition area.

[0119] In an embodiment, the data lead line can extend along or substantially along the row direction, and the data lead line can be connected with the data line group through a connecting line 70, one end of the connecting line 70 can be connected with the data lead line 80, and the other end can be connected with the third line segment 63. In this way, in the case where the data line group includes a plurality of parallel data lines, the plurality of data lines can be connected with each other at one end close to the data lead line, and then connected with the connecting line, thereby realizing the connection with the data lead line. It should be noted that, as shown in FIG. 7, the connecting line 70 can extend along the column direction.

[0120] In the plurality of data lead lines, due to the limited wiring space of the data lead lines, the plurality of data lead lines can be located in at least two film layers, for example, two adjacent data lead lines can be located in different film layers, so as to avoid short circuit between the data lead lines. The plurality of data lines can be located in the same layer, so that when the data lead line is connected with the data line through the connecting line, the plurality of data lead lines can be connected to the same layer through the via at the position connected with the connecting line, thereby enabling the plurality of data lines to be arranged in the same layer.

[0121] Of course, the data line and the data lead line connected with the data line can also be arranged in the same layer, so that the plurality of data lines can be located in at least two film layers.

[0122] In the plurality of data lead lines, due to the limited wiring space of the data lead lines, the plurality of data lead lines can be located in at least two film layers, for example, two adjacent data lead lines can be located in different film layers, so as to avoid short circuit between the data lead lines. The plurality of data lines can be located in the same layer, so that when the data lead line is connected with the data line through the connecting line, the plurality of data lead lines can be connected to the same layer through the via at the position connected with the connecting line, thereby enabling the plurality of data lines to be arranged in the same layer.

[0123] Please continue to refer to FIGS. 2, 3, 5 and 6, no matter whether the data line group includes one data line or a plurality of data lines, a plurality of data lines are arranged on the array substrate as a whole. As shown in FIG. 2, there is a pixel gap f between every two adjacent sub-pixels in the row direction, specifically, two or more data lines can be arranged in one pixel gap, or one data line can be arranged in one pixel gap. Specifically, in some embodiments, the plurality of data lines can be arranged in different pixel gaps.

[0124] Specifically, in an embodiment, the plurality of sub-pixels in a pixel unit can be adjacent in the row direction, the plurality of sub-pixels in the same column correspond to the same light-emitting color, and the adjacent two sub-pixels have a pixel gap therebetween. The orthogonal projection of the plurality of data lines on the substrate substrate can be located in the orthogonal projection of different pixel gaps on the substrate substrate.

[0125] As shown in FIG. 2, each data line group includes one data line, and each data line can be located between adjacent two pixel units, such as each data line being located in the pixel gap between the sub-pixel B and the sub-pixel R of adjacent pixel units. Overall, the plurality of data lines are distributed in different pixel gaps.

[0126] As shown in FIG. 3, each data line group includes a plurality of data lines, and the plurality of data lines in the same data line group can be located in different pixel gaps. Specifically, the plurality of data lines in the same data line group can be located in different pixel gaps in the pixel unit, or the plurality of data lines in the same data line group can include data lines located in the pixel gap inside the pixel unit and data lines located between adjacent two pixel units. As shown in FIG. 3, one data line in the data line group S1 is located between adjacent two pixel units, i.e., in the pixel gap between the sub-pixel R and the sub-pixel B, and another data line in the data line group S1 is located in the pixel gap inside the pixel unit, such as in the pixel gap between the sub-pixel G and the sub-pixel B.

[0127] In a further example of the embodiment, each data line group can include a plurality of data lines, and for each data line group, the adjacent two data lines in the data line group can be spaced apart by one column of sub-pixels or two columns of sub-pixels.

[0128] In the embodiment, when each data line group includes a plurality of data lines, each data line group can include two or three data lines. When each data line group includes two data lines, the two data lines can be spaced apart by one column of sub-pixels or two columns of sub-pixels adjacent in the row direction. Please refer to FIG. 3 and FIG. 6, each data line group includes two data lines, and the two data lines are spaced apart by two columns of sub-pixels, which can be the column of sub-pixels R and the column of sub-pixels G.

[0129] Further exemplarily, as shown in FIG. 9, another layout diagram of an array substrate is shown. As shown in FIG. 9, each data line group includes two data lines, and the two data lines are also spaced apart by two columns of sub-pixels, which are the sub-pixel G and the sub-pixel B. In the array substrates shown in FIG. 3, FIG. 6 and FIG. 9, at least one data line in the plurality of data lines in each data line group is located between adjacent two pixel units.

[0130] For another example, referring to FIG. 10, the data line group includes two data lines, and one column of pixels is arranged between the two data lines. The two data lines can be arranged in the pixel gap inside the pixel unit, or one of the two data lines is arranged in the pixel gap inside the pixel unit, such as the pixel gap between the sub-pixel R and the sub-pixel G, or the pixel gap between the sub-pixel G and the sub-pixel B, and the other data line is arranged in the gap between the pixel units. Of course, in order to reduce the connection difficulty, the two data lines can be arranged in the pixel gap inside the pixel unit.

[0131] In a further example in this embodiment, the data line group can include three data lines, and each two adjacent data lines among the three data lines can be spaced apart by one column of sub-pixels. Referring to FIG. 11, a wiring schematic diagram of another array substrate is shown. As shown in FIG. 11, each data line group includes three data lines, and the three data lines are arranged in different pixel gaps, and each two adjacent data lines are spaced apart by one column of sub-pixels. Specifically, the three data lines can include a data line arranged between the pixel units, and a data line arranged in the pixel gap inside the pixel unit.

[0132] In the case of including three data lines, on the one hand, the connection relationship between the data line and the sub-pixel can be simplified, and the wiring difficulty can be reduced, such as reducing the wiring length from the data line to the sub-pixel, thereby improving the process level. On the other hand, by parallel connection of the three data lines, the resistance of the data line group can be effectively adjusted, so as to control the driving power consumption.

[0133] In a further example of this embodiment, in the case that the data line group includes a plurality of parallel data lines, one or two columns of sub-pixels can be arranged between adjacent data line groups. In the case of spacing one column of sub-pixels, data lines are arranged on opposite sides of the same sub-pixel, and in the case of spacing two columns of sub-pixels, the adjacent data line groups have a large spacing distance, which can further reduce the risk of short circuit between the data line groups.

[0134] In the above embodiment, in the case that the data line group includes a plurality of data lines, there can be one data line, and the orthogonal projection of the data line on the substrate is located in the orthogonal projection of the inter-unit gap on the substrate. Referring to FIGS. 3, 6 and 9, this connection mode can minimize the wiring occupation of the space inside the pixel unit.

[0135] In some examples, from the whole, no matter whether the data line group includes one data line or multiple parallel data lines, the multiple data lines included on the whole array substrate can be located at least in two different film layers, for example, the multiple data lines can occupy two film layers, so that the multiple data lines can be distributed in the two film layers, thereby the short circuit problem between the data lines of different data line groups can be reduced.

[0136] Generally, the size of the sub-pixel is small, and the line width of the data line is micron or nanometer, in this case, in order to avoid the short circuit problem between the adjacent data lines, the multiple data lines can be distributed in different film layers. For example, at least two film layers are included, and in the case that the data line group includes one data line, for the adjacent two data lines, the two data lines are located in different film layers of the two film layers. More specifically, in some examples, the data line group includes multiple data lines, in this case, the multiple data lines in the same data line group can be located in the same film layer. On this basis, the multiple data lines in the adjacent two data line groups can be located in different film layers, and the two data lines in the data line group can be connected end to end, thereby in the case that the multiple data lines in the same data line group are located in the same film layer, the mutual connection between the data lines is facilitated, and the connection wires between the data lines and the multiple sub-pixels can be designed in the same layer, thereby compared with the case that the data lines in the same data line group are located in different film layers, in the case that the data lines in the same data line group are located in the same film layer, the data lines in the data line group can avoid the opening in different film layers, and even if the data lines in the data line group are short-circuited, the transmission of the data signal will not be affected. While the data lines in the adjacent two data line groups are located in different film layers, for example, as shown in FIG. 3 and FIG. 6, the adjacent data line groups S1 and S2, wherein the two data lines in the data line group S1 are arranged in the same film layer, and the two data lines in the data line group S2 are arranged in the same film layer, but the data line group S1 and the data line group S2 are located in different film layers, thereby the short circuit of the data lines between the data line groups can be avoided.

[0137] Among them, the at least two film layers where the data lines are located can be two film layers directly stacked together, the thickness of the two film layers can be consistent, and the two film layers are formed by using insulating transparent material. Specifically, the multiple data lines can be distributed in two film layers, or can be distributed in three, four or even more film layers.

[0138] In some embodiments, the connection between the gate line and the sub-pixel is introduced as follows.

[0139] Among them, in the array substrate with longitudinal pixel arrangement, one gate line group can include multiple gate lines, and the number of the included gate lines is the same as the number of the sub-pixels included in the pixel unit. Among them, the same gate line can be connected with the sub-pixels of different light emitting colors in the same pixel unit.

[0140] In yet some implementations, the gate lines in a gate line group corresponding to the same row of pixel units can be located in different row pixel gaps, which can be understood as that the multiple gate lines in the gate line group are not spaced by a sub-pixel row, or the multiple gate lines in the gate line group are spaced by a sub-pixel row. For example, as shown in FIG. 10, among the three gate lines G1, G2 and G3 connected to the same row of pixel units, the gate line G1 and the gate line G2 are located in one row pixel gap, and the gate line G3 is located in another row pixel gap. Specifically, in an example of this embodiment, the number of gate lines arranged in the first row pixel gap or the last row pixel gap of the array substrate can be less than the number of gate lines included in the remaining row pixel gaps. For example, as shown in FIG. 10, the first row pixel gap includes two gate lines, and the row pixel gaps other than the first row pixel gap include three gate lines. Alternatively, the last row pixel gap includes two gate lines, and the row pixel gaps other than the last row gate line group include three gate lines. By using this design manner of the embodiment, the requirement of narrow frame can be met, for example, by reducing the number of gate lines running in a certain side frame, the width of the display in this side frame can be reduced, and the narrow frame design of this side frame can be realized.

[0141] In some embodiments, the arrangement order of the multiple gate lines in a gate line group can indicate the scanning order of the multiple gate lines. The scanning order can be understood as the lighting order of the multiple sub-pixels in a pixel unit, and the lighting order can be the order of scanning from the first row of sub-pixels to the last row of sub-pixels, or the order of scanning from the last row of sub-pixels to the first row of sub-pixels. Specifically, the multiple gate lines are arranged according to their display order. As shown in FIG. 10, the multiple gate lines are arranged in the order of scanning rows, and each gate line can have a row arrangement number, such as G1, G2, G3, etc.

[0142] The multiple sub-pixels in one pixel unit can also have a starting order, which represents the charging order of the multiple sub-pixels being charged by the data line after being scanned by the gate line, i.e., the order in which the multiple sub-pixels in a pixel unit receive the data voltage input by the data line. Thus, which sub-pixel is connected to a gate line having a scanning order can determine the charging order of the sub-pixel. For example, as shown in FIG. 2, if the gate line G1 is connected to the sub-pixel R, the sub-pixel R is preferentially charged, and if the gate line G1 is connected to the sub-pixel B, the sub-pixel B is preferentially charged. Assuming that each sub-pixel in a pixel unit has a corresponding charging order number, and each gate line connected to the same pixel unit also has a corresponding display order number. In an example, for the same gate line group, the gate line having the i-th display order in the gate line group can be connected to the sub-pixel having the i-th charging order in the pixel unit, that is, the display order number of a gate line is consistent with the charging order number of the sub-pixel connected to the gate line.

[0143] Specifically, from the more visual connection relationship between the plurality of sub-pixels and the gate lines of the array substrate, the plurality of gate lines connected with the same pixel unit are arranged in display order, such as arranged in multiple rows, each gate line has a row number, such as G1, G2, G3, etc., the row number represents the display order of the gate line. The plurality of sub-pixels in each pixel unit are arranged in multiple columns or multiple rows, when arranged in multiple columns, each sub-pixel can have a column number, such as the column number of the sub-pixel R in the pixel unit is 1, the column number of the sub-pixel G is 2, and the column number of the sub-pixel B is 3, the column number represents the column arrangement order of the sub-pixel, which is independent of the sequence number of the charging order. Wherein, when the display order number of a gate line is consistent with the charging order number of the sub-pixel connected with the gate line, the row number of the gate line can be the same as or different from the column number of the sub-pixel connected with the gate line.

[0144] Wherein, when the row number of a gate line is the same as the column number of the sub-pixel connected with the gate line, the charging order of the plurality of sub-pixels is consistent with the column number of the plurality of sub-pixels, which can be understood as that the charging order of the plurality of sub-pixels is consistent with the column arrangement order of the plurality of sub-pixels. For example, referring to FIG. 3, the plurality of gate lines connected with the plurality of sub-pixels in the same pixel unit are located in the same gate line group, the three gate lines in the gate line group are numbered as gate line G1, gate line G2 and gate line G3, which can represent the scanning order of the plurality of gate lines to a certain extent. The column numbers of the plurality of sub-pixels in the pixel unit from left to right are 1, 2 and 3 in turn, wherein the gate line G1 is connected with the sub-pixel R numbered 1, the gate line G2 is connected with the sub-pixel G numbered 2, and the gate line G3 is connected with the sub-pixel B numbered 3, and the charging order of the plurality of sub-pixels is red sub-pixel, green sub-pixel and blue sub-pixel in turn. Thus, the charging order of the sub-pixels is consistent with the column arrangement order of the plurality of sub-pixels.

[0145] In another example, the row number of a gate line can be different from the column number of the sub-pixel connected with the gate line, and the charging order of the plurality of sub-pixels can be inconsistent with the column number of the plurality of sub-pixels, which can be understood as that the charging order of the plurality of sub-pixels is inconsistent with the column arrangement order of the plurality of sub-pixels. For example, referring to FIG. 12, the three gate lines in the gate line group are numbered as gate line G1, gate line G2 and gate line G3, which can represent the scanning order of the plurality of gate lines to a certain extent, i.e. the order of inputting gate voltage to the plurality of gate lines. The column numbers of the plurality of sub-pixels in the pixel unit from left to right are 1, 2 and 3 in turn, wherein the gate line G1 is connected with the sub-pixel G numbered 2, the gate line G2 is connected with the sub-pixel R numbered 1, and the gate line G3 is connected with the sub-pixel B numbered 3, and the charging order of the plurality of sub-pixels is green sub-pixel, red sub-pixel and blue sub-pixel in turn. Thus, the charging order of the sub-pixels is inconsistent with the column arrangement order of the sub-pixels.

[0146] In some embodiments, the plurality of gate lines are arranged into a plurality of rows in a display order, wherein among the plurality of gate lines connected to the plurality of sub-pixels in a pixel unit, a gate line at a frontmost position in the display order can be connected to a sub-pixel emitting a target color light in the pixel unit, wherein the target color light can be a color light other than red light.

[0147] In this embodiment, the gate line at the frontmost position in the display order is a gate line that is preferentially driven among the plurality of gate lines. For example, referring to FIG. 12, the display order is from driving the first row of sub-pixels to the last row of sub-pixels, and the plurality of gate lines are arranged into a plurality of rows from top to bottom, the plurality of gate lines connected to the same pixel unit are G1, G2 and G3, and the gate line G1 can be the gate line at the frontmost position in the display order. The gate line at the frontmost position in the display order is the gate line at the frontmost position in the row arrangement order, and this gate line can be connected to a sub-pixel other than a sub-pixel emitting red light, such as a sub-pixel emitting blue light or a sub-pixel emitting green light. For example, referring to FIG. 12, the gate line G1 at the frontmost position in the display order is connected to the green sub-pixel G, so that the green sub-pixel G is preferentially charged, and the charging order of the green sub-pixel G is the first, which is inconsistent with the column arrangement order.

[0148] In a further example of this embodiment, the gate line at the frontmost position in the display order is connected to a sub-pixel emitting blue light in the pixel unit. Thus, in a row of sub-pixels, the blue sub-pixel is preferentially charged. With this connection mode, the array substrate can be applied to a liquid crystal display, and when driving the liquid crystal display to display, the blue sub-pixel is preferentially driven, which can bring the following advantages:

[0149] Because one data line drives three sub-pixels, the first charged sub-pixel, i.e., the sub-pixel at the top of the charging sequence (hereinafter referred to as the target sub-pixel), can face the problem of insufficient charging. In this case, if the display surface includes a black display area and a white display area, the data voltages of the two target sub-pixels in the same column at the black and white boundary area can differ greatly. For example, referring to FIG. 13, a schematic diagram of a display screen with a black and white boundary is shown. In FIG. 13, the sub-pixel R is preferentially charged, i.e., the target sub-pixel. Among the two adjacent sub-pixels R in the column, one sub-pixel R needs to display black, and the other sub-pixel R needs to display white. Note that the black and white here can be understood as different gray scales. Due to insufficient charging of one of the sub-pixels R, the gray scale of the sub-pixel R will not be at the required gray scale, and thus, the display colors of the two adjacent sub-pixels R differ, which results in a low contrast of the display screen. It should be noted that the remaining sub-pixels, such as the sub-pixel B and the sub-pixel G, do not face the problem of insufficient charging because of their later charging sequence, and thus, the gray scale difference of the sub-pixel B at the black and white boundary is small.

[0150] In the embodiment, in the case where the gate line at the top of the display sequence is connected to the sub-pixel that emits blue light in the pixel unit, the first charged sub-pixel in a row of sub-pixels is the blue sub-pixel. Even if the blue sub-pixel faces the problem of insufficient charging, the two blue sub-pixels at the black and white boundary will have a gray scale difference. However, because of the color efficiency problem of the blue sub-pixel itself, even if there is a gray scale difference, it will not be observed by the human eye, and thus, the contrast of the display screen is improved.

[0151] In the embodiment, the array substrate can further include a common electrode and a touch signal line. Such an array substrate can be applied to a liquid crystal display.

[0152] The touch signal line can realize the touch function of the display. The touch signal line can be electrically connected to a touch module, such as a touch chip, of the array substrate. Generally, the touch signal line can include a touch signal line Tx that transmits signals and a touch signal line Rx that receives signals. The signal line Tx and the signal line Rx are arranged alternately on the array substrate, such as the signal line Tx arranged in multiple rows and the signal line Rx arranged in multiple columns. The signal line Tx and the signal line Rx are both connected to the touch signal line.

[0153] In the case where the common electrode is located on the array substrate, the common electrode and the pixel electrode of the liquid crystal display are located on the same side of the liquid crystal, and a planar electric field that drives the liquid crystal to deflect can be formed between the common electrode and the pixel electrode. Specifically, the common electrode can cover the entire array substrate or cover the area where the sub-pixels are located, so that the array substrate includes multiple common electrodes.

[0154] In one example of this embodiment, the signal supply of the touch lines or the signal supply of the common electrodes or both can be increased by the signal lines staggered with the data lines.

[0155] Referring to FIG. 14, FIG. 15a, FIG. 15b and FIG. 16, four more wiring structure diagrams of the array substrate are shown. As shown in FIG. 14, the array substrate can further include a plurality of signal lines 30 staggered with the plurality of data line groups on the array substrate, wherein the orthogonal projection of the signal lines on the substrate is between the orthogonal projections of the adjacent two sub-pixels on the substrate.

[0156] The plurality of signal lines can include the signal lines connected with the common electrodes of the array substrate and / or the signal lines connected with the touch signal lines of the array substrate.

[0157] In this embodiment, the material forming the signal lines can be the same as the material forming the gate lines and the data lines, which can be metal or metal oxide. The plurality of signal lines can be staggered with the plurality of data line groups, which can mean that at least one signal line is arranged between the adjacent two data line groups. The signal line can be located in a different pixel gap from the data line, or can be located in the same pixel gap as the data line. As shown in FIG. 14, FIG. 15a and FIG. 15b, one signal line is arranged between the adjacent two data line groups, and three columns of sub-pixels can be arranged between the adjacent two signal lines. As shown in FIG. 16, two signal lines can be arranged between the adjacent two data line groups, and one column of sub-pixels can be arranged between the adjacent two signal lines in some display areas, and two columns of sub-pixels can be arranged between the adjacent two signal lines in other display areas.

[0158] The plurality of signal lines can extend along the direction of the data lines, i.e. the signal lines are arranged in multiple columns, and different signal lines are located in different pixel gaps. In this way, the signal lines for increasing the supply of common signals and touch signals can be arranged in the pixel gaps between the sub-pixels, so as to make full use of the pixel gaps between the sub-pixels, i.e. the space of the pixel gaps between the sub-pixels where no data lines are arranged can be used to arrange the signal lines to increase the supply of common signals and touch signals.

[0159] The plurality of signal lines can all be signal lines for increasing the supply of common electrodes, or the plurality of signal lines can all be signal lines for increasing the supply of touch signals. In some examples, the plurality of signal lines can include the signal lines connected with the common electrodes and the signal lines connected with the touch signal lines. Specifically, the signal lines connected with the touch signal lines can be the signal lines connected with the touch signal lines, so as to increase the supply of touch signals.

[0160] In some examples, in the case that the data line group includes one data line, and the adjacent data line groups are spaced apart by three columns of sub-pixels, the plurality of signal lines can include signal lines 30a connected to the touch signal lines, and signal lines 30b overlapped with the common electrodes, and the signal lines 30a and the signal lines 30b are arranged alternately, such as in different pixel gaps, so as to increase the supply of the touch signal and the common electrodes. For example, as shown in FIG. 16, the plurality of signal lines can include signal lines 30a connected to the touch signal lines, and signal lines 30b overlapped with the common electrodes, and between every two adjacent data line groups, the signal lines 30a and the signal lines 30b can be arranged, such as between the data line S1 and the data line S2, the signal lines 30a and the signal lines 30b can be arranged. In this case, the signal lines 30a connected to the touch signal lines and the signal lines 30b overlapped with the common electrodes can be arranged alternately, such as one of the two adjacent signal lines is overlapped with the common electrodes, and the other is connected to the touch signal lines, so as to balance the signal supply to the common electrodes and the signal supply to the touch signal lines.

[0161] In yet some examples, as shown in FIG. 15b, in the case that the data line group includes two data lines, and the adjacent data line groups are spaced apart by two columns of sub-pixels, the plurality of signal lines can include signal lines 30a connected to the touch signal lines, or signal lines 30b overlapped with the common electrodes, and the signal lines can be arranged between the adjacent data line groups, so as to increase the supply of any one of the touch signal lines or the common electrodes.

[0162] In still some examples, in the case that the data line group includes three data lines, and each two adjacent data lines are spaced apart by one column of sub-pixels, in this case, the data lines are arranged between each two adjacent columns of sub-pixels, the signal lines can be arranged between the adjacent pixel units, and are arranged in different layers from the data lines, so as to increase the supply of the touch signal lines or the common electrodes.

[0163] In an example of this embodiment, the plurality of signal lines can be arranged in at least two film layers, and / or the signal lines are arranged in different layers from the data lines.

[0164] In one example, the plurality of signal lines can be located in at least two film layers. Specifically, two adjacent signal lines can be located in different film layers, such as in the case of signal lines 30a and signal lines 30b, all of the signal lines 30a can be located in the same film layer, and all of the signal lines 30b can be located in another film layer. For example, in the case of signal lines being all signal lines 30a or all signal lines 30b, two adjacent signal lines can be located in different film layers, so as to avoid the risk of short circuit between adjacent signal lines, such as the risk of short circuit between signal lines 30a, and to avoid the problem of inaccurate touch.

[0165] In another example, the signal lines and the data lines are in different layers. In this case, the signal lines can be located in one film layer, and the data lines can be located in another film layer. Specifically, the plurality of signal lines can be arranged in the same layer, and the plurality of data lines can also be arranged in the same layer, but the signal lines and the data lines are arranged in different layers. In this way, the risk of short circuit between the data lines and the signal lines can be avoided, especially in the case where the signal lines and the data lines are located in the same pixel gap.

[0166] In yet another example, the plurality of signal lines can be located in at least two film layers, and the signal lines and the data lines are in different layers. In this case, the film layer in which the signal lines are located is not only different from the film layer in which the data lines are located, but also the two adjacent signal lines in the plurality of signal lines are located in different film layers. Referring to FIG. 17, a partial structure diagram of the array substrate in the cross-sectional direction shown in FIG. 16 is shown. As shown in FIG. 17, the data line group includes one data line, the plurality of signal lines are distributed in two film layers, the plurality of data lines are arranged in the same layer, and the signal lines and the data lines are located in different film layers. Among them, the plurality of signal lines includes signal lines 30a and signal lines 30b, the signal lines 30a and the signal lines 30b are located in different film layers, such as the signal lines 30a being located in the same film layer L2, the plurality of signal lines 30a being arranged in the same layer; the plurality of signal lines 30b are located in the same film layer L1, and the plurality of signal lines 30b are arranged in the same layer.

[0167] Of course, in yet other examples, in combination with the above embodiments, in the case where the data line group includes a plurality of parallel data lines, the adjacent data line groups are located in different film layers, and the plurality of data lines in the same data line group are located in the same film layer, for the adjacent data line groups and the signal lines, the adjacent data line groups and the signal lines can also be distributed in different film layers.

[0168] In another example of the embodiment, for one signal line, the signal line is generally connected to the common electrode or the touch signal line through the via hole 301. For example, the signal line 30b is connected to the common electrode through the via hole, and the signal line 30a is connected to the touch signal line through the via hole. In order to avoid opening in the area where the pixel electrode is located, the via hole can be located in the area where the gate line group is located. For example, the orthographic projection of the via hole on the substrate substrate is located in the orthographic projection of the gate line group on the substrate substrate, and does not overlap with the orthographic projection of the gate line on the substrate substrate.

[0169] Referring to FIG. 18, a wiring layout of an array substrate is shown. As shown in FIG. 18, each data line group includes two parallel data lines, and a signal line 30 between adjacent data line groups, which can be the signal line 30b or the signal line 30a, can be connected to the common electrode through the via hole 301 in the area where the gate line group is located, and the orthographic projection of the via hole on the substrate substrate does not overlap with the gate line. That is, the gate line in the gate line group can be routed around the via hole.

[0170] As shown in FIG. 18, a signal line can be connected to the touch signal line or the common electrode through a plurality of via holes, and the plurality of via holes are all located in the area where the gate line group is located and do not overlap with the gate line. The plurality of via holes correspond to a plurality of sub-pixels, that is, a via hole is opened in the area corresponding to each sub-pixel to connect the signal line. Thus, the signal of the common electrode (touch signal) can be more uniform in the plurality of sub-pixels.

[0171] In some embodiments, the signal line can be applied to an array substrate with vertically arranged pixels or an array substrate with horizontally arranged pixels. Specifically, the signal line and the data line can be located in the same pixel gap, or the signal line and the data line can be located in different pixel gaps.

[0172] In the embodiment, in the array substrate with vertically arranged pixels, that is, the plurality of sub-pixels in the pixel unit are adjacent in the row direction, in the case where the number of data lines in the data line group is less than the number of sub-pixels in the pixel unit, the signal line and the data line can be located in different pixel gaps. In this case, the signal line can be disposed in the same layer as the data line or in different layers. In the case where the number of data lines in the data line group is equal to the number of sub-pixels in the pixel unit, the signal line and the data line can be located in the same pixel gap. In this case, the signal line can be disposed in different layers from the data line.

[0173] Exemplarily, as shown in FIG. 18, an array substrate of a longitudinal pixel arrangement is shown, in which the data lines and the signal lines are staggered and located in different pixel gaps. The data lines and the signal lines are staggered, and in the case that the data lines and the signal lines are located in the same pixel gap, there is no overlap between the data lines and the signal lines.

[0174] In yet another example, in an array substrate of a transverse pixel arrangement, i.e., a plurality of sub-pixels in a pixel unit are adjacent in the column direction, the signal lines can be located in the same pixel gap as the data lines, in which case, the signal lines can be arranged in different layers from the data lines.

[0175] Specifically, in the case that the data lines and the signal lines are located in the same pixel gap, the data lines and the signal lines can be arranged in different layers (not shown in the case that the data lines and the signal lines are located in the same pixel gap). Similarly, the signal lines can be connected to the common electrode or the touch signal line through the via hole, and the via hole has no overlap with the orthogonal projection of the gate line on the substrate.

[0176] In some examples, the sub-pixel is a collective term of a thin film transistor and a pixel electrode, the thin film transistor can include a source, a drain and a gate, and the thin film transistor can be a bottom-gate structure or a top-gate structure. Specifically, the thin film transistor can be located at the intersection of the gate line and the data line, for example, the orthogonal projection of the thin film transistor on the substrate can be located at the intersection of the orthogonal projection of the gate line and the orthogonal projection of the data line on the substrate. The gate line is connected to the gate of the thin film transistor, the data line is connected to the source of the thin film transistor, and the pixel electrode is connected to the drain of the thin film transistor.

[0177] In this embodiment, the array substrate can be applied to a liquid crystal display, and the array substrate can further include:

[0178] a common electrode layer, in which the orthogonal projection of the common electrode layer on the substrate can cover the orthogonal projection of the sub-pixel on the substrate;

[0179] a pixel electrode, located on the side of the common electrode layer away from the substrate and connected to the drain of the thin film transistor;

[0180] In which case, the orthogonal projection of the pixel electrode on the substrate can overlap with the orthogonal projection of the source of the second thin film transistor on the substrate, and / or overlap with the orthogonal projection of the gate of the second thin film transistor on the substrate.

[0181] In this embodiment, the common electrode layer can be located between the pixel electrode and the thin film transistor, and the common electrode layer can cover at least the area where the sub-pixel is located, such as covering the orthogonal projection of the pixel electrode in the sub-pixel on the substrate and the orthogonal projection of the thin film transistor on the substrate, or the common electrode can also cover the entire array substrate.

[0182] Referring to FIGS. 19-22, FIG. 19 shows a wiring diagram of an array substrate, FIG. 20 shows a layout design diagram of the array substrate of FIG. 19, FIG. 21 shows a cross-sectional structure diagram of the array substrate of FIG. 20 in the A-A direction, and FIG. 22 shows a cross-sectional structure diagram of the array substrate of FIG. 20 in the B-B direction. As shown in FIGS. 19-22, the pixel electrode is located on the side of the common electrode layer facing away from the substrate, and the common electrode layer covers the substrate.

[0183] In this embodiment, the thin film transistor includes a gate 101, and the pixel electrode 50 can be connected to the drain 102 of the thin film transistor through an opening in the common electrode layer 40. The opposite sides of the drain can be the source 103. Thus, the capacitance formed between the source and the pixel electrode can be shielded by the common electrode layer, and the capacitance formed between the gate and the pixel electrode can also be shielded by the common electrode layer. In this way, as shown in FIG. 22 and FIG. 20, the pixel electrode can overlap the orthographic projection of the source on the substrate and overlap the orthographic projection of the gate on the substrate. Specifically, since the gate is connected to the gate line, the pixel electrode 50 can also overlap the orthographic projection of the gate line on the substrate, as shown in FIG. 20. For example, as shown in FIG. 20, the pixel electrode 50 can also overlap the orthographic projection of the gate line G3 on the substrate.

[0184] In this embodiment, even if the orthographic projection of the pixel electrode on the substrate overlaps the orthographic projection of the gate on the substrate and overlaps the orthographic projection of the source on the substrate, the electric field formed between the pixel electrode and the common electrode layer will not be affected due to the presence of the common electrode layer. Therefore, the pixel electrode can cover the source and / or the gate, thereby increasing the area of the pixel electrode, increasing the aperture ratio, and improving the transmittance.

[0185] In some other embodiments, the thin film transistor can include an active layer and a gate layer. The active layer can include a channel region, and source and drain regions located on opposite sides of the channel region. The orthographic projection of the gate layer on the substrate covers the orthographic projection of the channel region on the substrate. Specifically, for the channel region, the edge of the channel region on the side close to the data line has an orthographic projection on the substrate, which is parallel to the orthographic projection of the data line on the substrate and the edge of the substrate.

[0186] Referring to FIG. 23, an enlarged schematic view of the dashed box area of the array substrate in FIG. 20 is shown. As shown in FIG. 23, the active layer of the thin film transistor can include a channel region 104, and a source region 103 and a drain region 102 located on opposite sides of the channel region. The data line is overlapped with the source region 103, and the pixel electrode 50 is overlapped with the drain region 102, such as the pixel electrode is overlapped with the drain region 102 through the metal layer 51. The channel region is located between the source region and the drain region, and the edge of the channel region close to the data line is parallel to the edge of the substrate. It can be understood that the edge of the channel region close to the data line is flush with the edge of the substrate, or that the edge of the channel region close to the data line does not have an arc-shaped protrusion, or that the distance from the edge of the channel region close to the data line to the edge of the substrate is uniform.

[0187] In the present embodiment, flush can be understood as the distance between the normal projection of the edge 1041 (hereinafter referred to as the first edge) of the channel region close to the data line on the substrate and the edge of the substrate is uniform, for example, the planar distance between each position of the edge of the channel region to the edge of the substrate is the same, for example, as shown in FIG. 23, the planar distance between each position of the edge of the channel region 104 close to the data line to the edge of the substrate is the same; or the planar distance between each position of the edge of the channel region to the edge of the substrate is within a small distance range, for example, the difference between the planar distance between each position of the edge and the edge of the substrate is less than about 0.1 μm. The edge of the substrate can be as shown by the right dashed line in FIG. 23.

[0188] Specifically, by using such a channel region, it can be adapted to the case that one data line is to be connected to one sub-pixel on each side, as shown in FIG. 19, one data line is to be connected to the pixel R and the sub-pixel G on the left and right sides, which means that the thin film transistors of two adjacent sub-pixels need to be connected on opposite sides of one data line. Therefore, the distance between the thin film transistors of the two sub-pixels is very small, and when the channel region of the active layer is formed, if the edge of the channel region close to the data line is not flush, the process fluctuation of the metal layer formed on the source and drain regions on both sides of the channel region will cause the channel regions of the two thin film transistors to be short-circuited on one hand, and the wiring space of the data line is small on the other hand. In the present embodiment, the edge of the channel region is flush, so that the process fluctuation of the metal layer formed on the source and drain regions on both sides of the channel region will only affect the thin film transistor in the y direction shown in FIG. 23, but not in the x direction, and at the same time, it also provides sufficient space for the wiring of the data line.

[0189] In a further example, the orthogonal projection of the channel region on the substrate can be a one-word type, as shown in FIG. 23. In this embodiment, the distance between the opposite edges of the channel region on the left and right sides is uniform. For example, the edge of the channel region close to the data line can be a first edge 1041, and the edge opposite to the first edge 1041 can be a second edge 1042. The orthogonal projection of the channel region on the substrate can be a one-word type, which means that the distance d between the first edge and the second edge of the channel region is uniform, i.e., the distance d is a constant value. In this embodiment, the channel region 104 is in a rectangular shape, such as a long strip shape, when the shape of the channel region is a one-word type.

[0190] As shown in FIG. 23, in some embodiments, the channel region can include two unconnected regions. The pixel electrode is connected to the drain of the thin film transistor through a metal electrode. The data line can be arranged on the opposite sides of the drain. The channel region is arranged between the data line and the drain on the two sides. That is, the thin film transistor includes two source regions and a drain region between the two source regions. The channel region is between the drain region and the source region. The two channel regions can be unconnected. Such a design can facilitate the wiring design of the data line.

[0191] It should be noted that in this embodiment, the shape of the gate can be adapted to the shape of the channel region. For example, referring to FIG. 20, the orthogonal projection of the gate 101 on the substrate can be a continuously bent S shape, thereby forming two unconnected channel regions. The orthogonal projection of the channel region on the substrate can be covered by the orthogonal projection of the gate on the substrate.

[0192] In this embodiment, since the data line group includes one data line or multiple parallel data lines, the number of data lines in the data line group is less than the number of sub-pixels in the pixel unit. In this case, one data line can be connected to one sub-pixel or multiple sub-pixels in the pixel unit. In this way, the data line can be connected to multiple sub-pixels through an extended data line branch. As shown in FIG. 18, when the data line group includes two parallel data lines, one data line needs to be connected to two sub-pixels. The two sub-pixels can be adjacent sub-pixels. Specifically, the two sub-pixels can be located on the left and right sides of the data line. Thus, one data line in the data line group can include a branch connected to one sub-pixel and a branch connected to another sub-pixel. The two branches can be perpendicular to the data line and located on the left and right sides of the data line, respectively.

[0193] In the embodiment, the data line group includes one data line, and the one data line needs to be connected with three sub-pixels in the pixel unit. Referring to FIG. 24 and FIG. 25, FIG. 24 shows a wiring layout of an array substrate according to the embodiment of the present disclosure, and FIG. 25 shows an enlarged schematic diagram of a connection structure between a data line and a pixel unit in FIG. 24. As shown in FIG. 25 and FIG. 24, the sub-pixel includes a thin film transistor, the data line group includes one data line, the data line includes a first branch 1031 connected with the thin film transistor of the first sub-pixel R1, and a second branch 1032 connected with the thin film transistor of the first branch 1031 and the second sub-pixel G1 / B1 respectively; wherein the second branch includes multiple bends.

[0194] As shown in FIG. 25, the data line extends in the column direction, and at the position where the data line needs to be connected with the sub-pixel, the data line can include a first branch, which can be perpendicular to the extension direction of the data line, for example, the first branch can extend in the row direction, and the first branch can be overlapped with the source electrode of the thin film transistor of the first sub-pixel R1 closest to the data line. Then, the data line is overlapped with the source electrode of the thin film transistor of the next second sub-pixel G1 through the second branch connected with the first branch, and the second branch can extend in the direction of the next second sub-pixel B1 to be connected after being connected with the first branch.

[0195] Since the second branch needs to extend in the direction of the second sub-pixel and be connected with the first branch, the second branch can have different extension directions at different positions, that is, the second branch can include multiple bends, for example, the second branch can include two bends or three bends, etc.

[0196] For example, as shown in FIG. 25, the first sub-pixel R1 can be the sub-pixel close to the data line, and the second sub-pixel G1 can be the sub-pixel away from the data line, and the first branch connected on the data line is perpendicular to the data line and is overlapped with the source electrode of the first sub-pixel R1. The second branch is connected with the first branch and has three bends to extend to the second sub-pixel G1 through multiple bends, for example, the section of the second branch connected with the first branch is perpendicular to the first branch, then the branch section perpendicular to the first branch is bent by about 90 degrees and extends in the row direction, and when extending to the gap region between the two thin film transistors, the branch section is bent again and then connected with the source electrode of the thin film transistor of the second sub-pixel G1. As shown in FIG. 25, the bend close to the thin film transistor of the second sub-pixel G1 in the second branch can be an obtuse angle bend to reduce the difficulty of wiring.

[0197] It should be noted that in the case that the data line group includes one data line and the one data line is connected with three sub-pixels, the branch connected with each sub-pixel on the data line can include a first branch and a second branch.

[0198] In some examples, the second branch can have no overlap with the gate lines on the substrate, for example, the second branch can run between adjacent gate lines, thereby ensuring that there is no overlapping capacitance between the second branch and the gate lines, to ensure the quality of the transmitted data signal.

[0199] In further examples of this embodiment, the first branch and the second branch have a substantially U-shaped projection on the substrate, and the first branch and the second branch both overlap the active layer of the thin film transistor.

[0200] In this embodiment, the thin film transistor includes an active layer, and the active layer includes a channel region, a source region and a drain region, wherein, as shown in FIG. 23, the channel region is located between the source region and the drain region, and includes two non-connected channel regions. In this embodiment, the first branch and the second branch have a substantially U-shaped projection on the substrate, which can facilitate the design of a data line connecting multiple sub-pixels in the same row. The first branch and the second branch both overlap the active layer of the thin film transistor, so that the thin film transistor can be provided with two channel regions, as shown in FIG. 25, the drain 102 is located between the two channel regions, and the first branch and the second branch can be located on opposite sides of the drain, so that the first branch and the second branch can both provide a data signal for the thin film transistor, thereby ensuring the performance of the thin film transistor.

[0201] In the following, several specific examples of the array substrate are described.

[0202] Array substrate A:

[0203] Referring to FIG. 24, a layout of the array substrate shown in FIG. 2 is shown. As shown in FIG. 24, the array substrate includes: a plurality of sub-pixels, the sub-pixels in the same column correspond to the same light-emitting color, every adjacent two sub-pixels in the same row correspond to different light-emitting colors, and the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit includes three sub-pixels with different light-emitting colors and adjacent positions;

[0204] a gate line group located between adjacent two rows of sub-pixels, including a plurality of gate lines extending in the row direction, and one gate line in the gate line group is connected with the sub-pixels in the same row emitting the same color light; and

[0205] a data line group including data lines extending in the column direction, the data line group including one data line, the projection of the data line on the substrate is located between the projections of adjacent two pixel units on the substrate, and one data line is connected with the three sub-pixels in the pixel unit.

[0206] Specifically, as shown in FIG. 24, the plurality of sub-pixels in the same column are all connected with the same data line, thereby realizing the driving of column inversion.

[0207] Two signal lines are arranged between two adjacent data line groups, and the two signal lines are respectively located in different pixel gaps. The two signal lines are spaced apart from each other by one sub-pixel. The signal line can be connected to the common electrode of the array substrate through a via hole. The orthogonal projection of the via hole on the substrate can be located in the orthogonal projection of the gate line group on the substrate.

[0208] Each data line is connected to three sub-pixels. The data line can be connected to the source electrode of the sub-pixel R through a first branch, connected to the source electrode of the sub-pixel G through a second branch connected to the first branch, and the first branch of the sub-pixel G also includes the first branch and the second branch. The first branch can be regarded as a second branch extending from the side of the sub-pixel R. The source electrode of the sub-pixel B is connected to the corresponding second branch of the sub-pixel G. The orthogonal projection of the first branch and the second branch on the substrate at the position of each sub-pixel is approximately U-shaped, and the first branch and the second branch overlap the active layer of the thin film transistor. Thus, the connection between one data line and multiple sub-pixels is realized.

[0209] In the array substrate A, the gate lines arranged in the front row are connected to the sub-pixels arranged in the rear column, such as G1 connected to the sub-pixel B, G2 connected to the sub-pixel G, and G3 connected to the sub-pixel R. Thus, the sub-pixel B can be preferentially driven when driving the display.

[0210] The array substrate can greatly reduce the number of data lines, thereby reducing the demand for data driving chips and reducing costs. The signal lines are arranged between the data lines, thereby increasing the supply of the common electrode and improving the uniformity of the common voltage in each region of the array substrate.

[0211] Array substrate B:

[0212] Referring to FIG. 26, the layout of the array substrate shown in FIG. 5 is shown. As shown in FIG. 26, the multiple sub-pixels in the pixel unit are adjacent in the row direction. Unlike the array substrate A, the two adjacent sub-pixels in the same column are connected to the two adjacent data lines, respectively. Thus, the two adjacent pixel units in the same column are connected to the two adjacent data line groups, respectively. Thus, the driving of the dot inversion can be realized.

[0213] Array substrate C:

[0214] Referring to FIG. 15b and FIG. 27, the layout design of FIG. 15b is shown. Unlike the array substrate A, the data line group includes two parallel data lines, and the two data lines are spaced apart by one column of sub-pixels and located in two pixel gaps inside the pixel unit.

[0215] One data line is connected with the sub-pixel B and the sub-pixel G simultaneously, and the other data line is connected with the sub-pixel R. One signal line is arranged between two adjacent data line groups, and the signal line is electrically connected with the touch signal line through a via hole. The via hole is located in the area where the gate line group is located, and the orthographic projection of the via hole on the substrate substrate does not overlap with the gate line. The pixel units located in the same column are connected with the same data line group. For example, the data line group includes two parallel data lines, and the multiple sub-pixels located in the same column are connected with the same data line.

[0216] In the array substrate, one data line is connected with one sub-pixel, and the other data line is connected with the sub-pixels located on both sides of the data line. Therefore, the data line can be directly connected with the source electrode of the thin film transistor of the sub-pixel through the branch perpendicular to the data line, and the second branch for extending the wiring between the sub-pixels is no longer needed, so that the wiring difficulty of the connection between the data line and the sub-pixel can be reduced.

[0217] Array substrate D:

[0218] Referring to FIG. 4, different from the array substrate A, the multiple sub-pixels in the pixel unit are adjacent in the column direction, that is, the sub-pixels in the same row have the same light-emitting color, the adjacent two sub-pixels in the same column correspond to different light-emitting colors, the data line group includes one data line, the interval between the adjacent two data lines is one column of sub-pixels, the gate line group includes three gate lines, and each gate line is connected with the sub-pixels located in the same row. The two pixel units adjacent in the column direction are connected with the adjacent two data lines, respectively, to realize point inversion. The data line and the signal line are located in the same pixel gap and are arranged in different layers.

[0219] Array substrate F:

[0220] Referring to FIG. 9, different from the above-mentioned array substrate C, the data line group includes three parallel data lines, and the interval between the adjacent two data lines is one column of sub-pixels. The signal line can be arranged between the adjacent two data line groups. The signal line can be located in the same pixel gap as the data line in any one data line group, and the data line and the signal line are arranged in different layers.

[0221] By using the above-mentioned array substrate provided in the present disclosure, the number of data line groups can be reduced, the requirements for the data driving chip can be reduced, and the manufacturing cost of the display can be reduced. By parallel driving the pixel unit through two or more data lines, the resistance of the data line group can be reduced, and the driving power consumption can be reduced. By increasing the gate lines, the display area does not need a multiplexing circuit, and the manufacturing cost of the display is further reduced.

[0222] And, the connection sequence of the plurality of gate lines and the plurality of sub-pixels in the pixel unit can be preferred to drive the blue sub-pixel during display driving, thereby enhancing the contrast of the black and white picture displayed by the display at the junction of the black and white picture, and ensuring the display quality of the displayed picture.

[0223] Furthermore, the same data line group can be connected with the sub-pixels of the adjacent two columns, thereby helping the dot inversion driving from the connection relationship, simplifying the logic of the dot inversion driving, and further reducing the driving cost of the liquid crystal display.

[0224] Based on the same inventive concept, the disclosure also provides a driving method of a liquid crystal display. Referring to FIG. 28, a step flowchart of the driving method of the liquid crystal display is shown. As shown in FIG. 27, the liquid crystal display includes the array substrate in any of the example embodiments described above. The driving method includes the following steps:

[0225] Step S11: In a lighting period of lighting the sub-pixels located in the same row, a driving scan signal is sequentially output to the plurality of gate lines in the same gate line group according to a driving timing sequence.

[0226] Step S12: When the driving scan signal is output to the gate line, a corresponding data voltage is output to the data line in each data line group, and in each lighting period, the data voltage with opposite polarity is input to the adjacent two data line groups, so that the data voltage input by the same data line group in the adjacent two lighting periods has the same polarity.

[0227] In the embodiment, in each of the lighting periods, the data voltage with opposite polarity is input to the adjacent two data line groups, so that in the case that the data voltage input by the same data line group in the adjacent two lighting periods has the same polarity, the data voltage driving the plurality of sub-pixels in the same frame picture can be made to have different polarities.

[0228] In the embodiment, the liquid crystal display drives each row of sub-pixels by row, and the plurality of sub-pixels in the pixel unit in the array substrate can be adjacent in the row direction or adjacent in the column direction. The driving timing sequence can be understood as the charging timing sequence of the plurality of sub-pixels in the pixel unit. For example, the pixel unit includes a sub-pixel R, a sub-pixel G, and a sub-pixel B, and the driving timing sequence can be to drive the sub-pixel R first, then drive the sub-pixel G, and finally drive the sub-pixel B. In practice, the driving timing sequence is related to the sequence of outputting the driving scan signal to the plurality of gate lines in the gate line group. For example, referring to FIG. 2, if the driving timing sequence is sub-pixel R, sub-pixel G, and sub-pixel B in sequence, the sequence of outputting the driving scan signal to the plurality of gate lines in the gate line group can be G1, G2, and G3.

[0229] When outputting the driving scanning signal to each gate line, the corresponding data voltage can be outputted to the data lines in each data line group, and the polarity of the data voltage outputted to the data line group can be controlled, wherein the polarity of the data voltage in the data line group can be such that the polarity of the data voltage driving the plurality of sub-pixels in the same frame of picture is not completely the same.

[0230] The polarity of the data voltage driving the plurality of sub-pixels in the same frame of picture can be understood as that the polarity of the pixel units in the adjacent two columns is not the same, or the polarity of the sub-pixels in the adjacent two rows is not the same.

[0231] Exemplarily, the polarity of the data voltage outputted to the adjacent two data line groups can be opposite, thereby the column inversion or the dot inversion can be realized. Taking FIG. 2 as an example, assuming that the polarity of the data voltage outputted to the data line S1 is positive, the data voltage of the three sub-pixels connected to the data line S1 is positive, and the polarity of the data voltage outputted to the data line S2 is negative, thereby the data voltage of the three sub-pixels connected to the data line S2 is negative, so that the polarity of the adjacent pixel units can be opposite, thereby the column inversion driving of 3Dot can be realized.

[0232] Since one data line group on the array substrate corresponds to one output channel of the data signal, and the data line group can connect the plurality of sub-pixels in the pixel unit, thereby the number of the output pins of the data driving chip can be greatly reduced, so that the number of the data driving chip can be reduced, and thus the cost can be reduced, and thereby the driving logic can be simplified based on the driving of the array substrate.

[0233] In further examples of the embodiment, the driving timing can be related to the connection relationship between the gate and the plurality of sub-pixels in the pixel unit in the array substrate, and the plurality of gate lines connected to the same pixel unit are arranged in the display order, such as being arranged in multiple rows, each gate line has a row number, and the row number represents the display order of the gate line; wherein the plurality of sub-pixels in one pixel unit can also have a starting order, which represents the charging order of the plurality of sub-pixels charged by the data line, that is, the order in which the plurality of sub-pixels in the pixel unit respectively receive the data voltage inputted by the data line, and the charging order can be understood as the driving timing.

[0234] The driving timing can be consistent with the column arrangement order of the plurality of sub-pixels, or inconsistent with the column arrangement order of the plurality of sub-pixels. In the embodiment, the driving timing can be the timing of non-prior lighting the red sub-pixel in the pixel unit, such as the timing of prior lighting the green sub-pixel. Specifically, the driving timing is inconsistent with the column order of the plurality of sub-pixels, in which case the gate line with the earlier display order in the array substrate can be connected to the non-red sub-pixel, such as the green sub-pixel, so that the driving timing is adapted to the connection order between the gate line and the sub-pixel in the array substrate.

[0235] Specifically, the driving timing can be the timing of preferentially lighting the blue sub-pixel in the pixel unit. In this embodiment, the gate line in the array substrate which displays in the front order can be connected with the sub-pixel which emits blue light, so that the blue sub-pixel is preferentially driven. As described in the above embodiment of the array substrate, because of the color efficiency problem of the sub-pixel which emits blue light, when one data line group is preferentially charged, even if there is a charging shortage, that is, there is a gray scale difference, it will not be observed by the human eye, and then the contrast of the display picture is improved.

[0236] In some embodiments, for the array substrate with vertical pixel arrangement, the multiple sub-pixels in the same column can be connected with the same data line, or the two adjacent pixel units in the same column can be connected with two adjacent data line groups respectively. In the case that the two adjacent pixel units in the same column are connected with two adjacent data line groups respectively, the simplification of the point inversion driving logic can be realized. When the polarity of the data voltage output to the data line group is controlled, the data voltage with opposite polarity can be input to the adjacent two data line groups in each lighting period, and the polarity of the data voltage input by the same data line group in the adjacent two lighting periods is the same.

[0237] In this embodiment, one lighting period is the period of driving a row of sub-pixels, which generally includes three driving periods, and each driving period drives the sub-pixels which emit the same color light in the row of sub-pixels to light. Since the connection between the data line group and the sub-pixel has been prepared for point inversion, thus, only the polarity of the data voltage of the data line in one frame of picture needs to be controlled to remain the same, so as to achieve the purpose of opposite polarity between the adjacent two pixel units in one frame of picture, therefore, in the actual driving process, the data voltage with opposite polarity can be input to the adjacent two data line groups in the same lighting period, and the polarity of the data voltage input by each data line group remains unchanged until the next frame of display picture arrives.

[0238] In which, for the same data line group, the polarity of the data voltage input by the same data line group in the driving of the adjacent two frames of display picture can be opposite, for example, in the same lighting period, the data voltage of the data line S1 and the data line S2 is opposite, and the polarity of the data voltage of the data line S1 and the data line S2 in the same frame of display picture is the same; while in the i-th frame of display picture and the i+1-th frame of display picture, the polarity of the data voltage on the data line S1 is opposite.

[0239] By using this driving method, combined with the array substrate, the complexity of the control of the polarity of the data voltage on the data line can be reduced, and the point inversion driving can be realized without frequently switching the polarity of the data voltage on the data line, thereby reducing the complexity of the driving logic.

[0240] Next, the driving method is exemplarily introduced in combination with the array substrate provided in the above examples.

[0241] For the array substrate A as shown in Fig. 2, the driving process is as follows:

[0242] When G1-3 in the gate signal line are sequentially high, S1 opens the sub-pixels in the first row, the third column, the second column and the first column in sequence, and S2 opens the sub-pixels in the first row, the sixth column, the fifth column and the fourth column in sequence.

[0243] When G4-6 in the gate signal line are sequentially high, S1 opens the sub-pixels in the second row, the third column, the second column and the first column in sequence, and S2 opens the sub-pixels in the second row, the sixth column, the fifth column and the fourth column in sequence.

[0244] The above-mentioned row-by-row scanning is performed to complete the scanning of the ith frame, wherein the polarities of the data voltages on the adjacent two data lines in the ith frame display picture are opposite, thereby realizing column inversion driving.

[0245] When the (i+1)th frame is entered, in the (i+1)th frame, G1 in the gate signal line is high again, the data voltage on the same data line is inverted in polarity, and the sub-pixels are charged, and the above-mentioned process is repeated to realize display.

[0246] Referring to Fig. 29, the waveforms of S1 & S2 and G1 G2 G3 when the array substrate A displays a blue picture (B255) are shown.

[0247] For the array substrate B as shown in Fig. 2, the driving process is as follows:

[0248] When G1-3 in the gate signal line are sequentially high, S1 opens the sub-pixels in the first row, the third column, the second column and the first column in sequence, and S2 opens the sub-pixels in the first row, the sixth column, the fifth column and the fourth column in sequence.

[0249] When G4-6 in the gate signal line are sequentially high, S2 opens the sub-pixels in the second row, the third column, the second column and the first column in sequence, and S3 opens the sub-pixels in the second row, the sixth column, the fifth column and the fourth column in sequence.

[0250] The above-mentioned row-by-row scanning is performed to complete the scanning of the ith frame, wherein the polarities of the data voltages on the adjacent two data lines in the ith frame display picture are opposite, thereby realizing column inversion driving.

[0251] When the (i+1)th frame is entered, in the (i+1)th frame, G1 in the gate signal line is high again, the data voltage on the same data line is inverted in polarity, and the sub-pixels are charged, and the above-mentioned process is repeated to realize point inversion driving display.

[0252] The driving process of the array substrate C shown in Fig. 13b is as follows:

[0253] Referring to Fig. 13b, when G1-3 in the gate signal line are sequentially high, S1 sequentially opens the sub-pixels in the first row, the second column, the third column and the first column, and S2 sequentially opens the sub-pixels in the first row, the fifth column, the sixth column and the fourth column;

[0254] When G4-6 in the gate signal line are sequentially high, S2 sequentially opens the sub-pixels in the second row, the third column, the second column and the first column, and S3 sequentially opens the sub-pixels in the second row, the sixth column, the fifth column and the fourth column; in this way, in the lighting period of each row, the green sub-pixels are preferentially driven.

[0255] The row-by-row scanning is performed in the above manner to complete the scanning of the ith frame, wherein the polarities of the data voltages on the adjacent two data lines in the ith frame are opposite, thereby realizing the column inversion driving.

[0256] In the i+1th frame, G1 in the gate signal line is high again, the data voltage on the same data line is inverted in polarity, and the sub-pixels are charged; and the process is repeated to realize the column inversion driving display.

[0257] The driving process of the array substrate D shown in Fig. 4 is as follows:

[0258] The driving manner is as follows: when G1-3 in the gate signal line are sequentially high, S1 sequentially opens the sub-pixels in the first column, the first row to the third row, and S2 sequentially opens the sub-pixels in the second column, the first row to the third row; when G4-6 in the gate signal line are sequentially high, S2 sequentially opens the sub-pixels in the first column, the fourth row to the sixth row, and S3 sequentially opens the sub-pixels in the second column, the fourth row to the sixth row; when G7-9 in the gate signal line are sequentially high, S1 sequentially opens the sub-pixels in the first column, the seventh row to the ninth row, and S2 sequentially opens the sub-pixels in the second column, the seventh row to the ninth row; the row-by-row scanning is performed in this way to complete the driving of the pixel units in the ith frame.

[0259] In the i+1th frame, G1 in the gate signal line is high again; wherein in the ith frame, the polarities of the data voltages on the adjacent two data lines are opposite; in the i+1th frame, the data lines are inverted in polarity, so that the polarities of the data voltages on the same data line in two adjacent frames are opposite; and the process is repeated to realize the display.

[0260] In the driving of the pixel units of the array substrate D, the blue sub-pixels are preferentially driven.

[0261] Based on the same inventive concept, the present disclosure also provides a display device comprising the array substrate described in any of the above example embodiments, wherein the display device can be a liquid crystal display device, and the display device can comprise the array substrate and a counter substrate opposite to the array substrate, liquid crystal is arranged between the counter substrate and the array substrate, and a color filter layer can be arranged on the counter substrate, and a normal projection of the color filter layer on the array substrate overlaps with the sub-pixel on the array substrate. Since one data line group of the array substrate can be shared by sub-pixels of different light emitting colors, the cost of the array substrate is reduced, and the manufacturing cost of the entire display device is further reduced.

[0262] Each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0263] Finally, it should be noted that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0264] The array substrate, the driving method of the liquid crystal display and the display device provided by the present disclosure are described in detail above, and the principles and implementation manners of the present disclosure are described by applying specific examples in this document, and the above embodiment description is only used to help understand the method of the present disclosure and its core idea; at the same time, for those skilled in the art, according to the idea of the present disclosure, the specific implementation manner and application range will be changed, and the above description should not be understood as a limitation of the present disclosure.

[0265] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the specification and practice of the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following the general principles thereof and including the known equivalents and modifications thereof. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0266] It is to be understood that the present disclosure is not limited to the precise construction that has been described and shown in the accompanying drawings, and that various modifications and changes can be effected therein by those skilled in the art without departing from the scope of the disclosure. The scope of the disclosure is limited only by the claims that follow.

[0267] Reference herein to "one embodiment", "an embodiment" or "one or more embodiments" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0268] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0269] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The disclosure can be implemented by means of both hardware and software, and any combination thereof. In a unit claim, several elements can be presented - the use of "each" before the first of these elements does not exclude the presence of a plurality of these elements. The usage of the words "first", "second" and "third" etc. do not limit the number of these elements. These words are only used to distinguish between alternative claims.

[0270] Finally, it should be noted that the above-mentioned embodiments are merely intended for describing and illustrating the technical solutions of the present disclosure, rather than limiting the present disclosure; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified or equivalent replacements can be made to some technical features; and such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An array substrate, wherein, The array substrate comprises: a plurality of pixel units arranged in an array, each of the pixel units comprising at least three sub-pixels of different colors and adjacent positions; a plurality of gate line groups corresponding to a plurality of rows of the pixel units, each of the gate line groups comprising a plurality of gate lines extending in a row direction, the number of the gate lines in each of the gate line groups being the same as the number of the sub-pixels in the pixel units, wherein one of the gate lines in one of the gate line groups is connected to the sub-pixels of the same row and emitting the same color light; and a plurality of data line groups corresponding to a plurality of columns of the pixel units, each of the data line groups comprising one or more parallel data lines extending in a column direction, all the sub-pixels in a single one of the pixel units being connected to the data line in the same one of the data line groups.

2. The array substrate according to claim 1, wherein, The data line group comprises one data line, and the orthogonal projection of the data line on the substrate substrate is located between the orthogonal projections of two adjacent pixel units on the substrate substrate.

3. The array substrate according to claim 1, wherein, A plurality of pixel units in the same column are connected to the data line in the same data line group.

4. The array substrate of claim 1, wherein, Two adjacent pixel units in the same column are connected to two adjacent data line groups, respectively.

5. The array substrate of claim 1, wherein, The data line comprises a first end and a second end, and the data line group comprises a plurality of parallel data lines. The first ends of the plurality of data lines in the data line group are connected to each other, and / or the second ends of the plurality of data lines are connected to each other.

6. The array substrate according to claim 5, wherein, The array substrate comprises a display area and a peripheral area, and the plurality of pixel units are located in the display area. The peripheral area comprises a fan-out area, a transition area and a load area, the load area is arranged close to the display area, the fan-out area is located on the side of the transition area away from the display area, the transition area is located between the fan-out area and the load area, and the fan-out area comprises a plurality of data leads. The plurality of data lines in the data line group are connected to each other at one end close to the fan-out area. The connection points are located on the side of the load area close to the transition area, and the data leads are connected to the connection points of the plurality of data lines in the data line group after running along the transition area.

7. The array substrate of claim 1, wherein, The plurality of sub-pixels in the pixel unit are adjacent in the row direction, the data line group comprises a plurality of parallel data lines, adjacent two data lines in the same data line group are separated by one or two columns of the sub-pixels, and adjacent two data line groups are separated by one or two columns of the sub-pixels.

8. The array substrate of claim 1, wherein, The plurality of data lines on the array substrate are located in at least two different film layers.

9. The array substrate of claim 8, wherein, The data line group comprises a plurality of parallel data lines, and adjacent two data line groups are located in different film layers.

10. The array substrate of claim 1-9, wherein, The plurality of sub-pixels in the pixel unit are adjacent in the row direction, the plurality of gate lines in the gate line group are arranged in a plurality of rows according to a display order, and the display order is used to represent the scanning order of the plurality of rows of sub-pixels. Among the plurality of gate lines connected to the plurality of sub-pixels in one of the pixel units, the gate line at the front of the display order is connected to the sub-pixel emitting the target color light in the pixel unit, and the target color light is a color light other than red light.

11. The array substrate of claim 10, wherein, The most front gate line in the display order is connected with a blue light emitting sub-pixel in the pixel unit.

12. The array substrate of claim 1, wherein, The array substrate further comprises: a plurality of signal lines, which are arranged in the column direction and are staggered with the plurality of data line groups on the array substrate; wherein a projection of the signal line on the substrate substrate is located between the projections of the adjacent two sub-pixels on the substrate substrate. Among the plurality of signal lines, there are signal lines connected with the common electrode of the array substrate and / or signal lines connected with the touch signal lines of the array substrate.

13. The array substrate of claim 12, wherein, The plurality of signal lines are located in at least two different film layers; and / or the signal lines are arranged in different layers from the data lines.

14. The array substrate of claim 12, wherein, The signal line is connected with the common electrode or the touch signal line through a via hole; The projection of the via hole on the substrate substrate is located within the projection of the gate line group on the substrate substrate, and does not overlap with the projection of the gate line on the substrate substrate. The sub-pixel comprises a thin film transistor, and 15. The array substrate of claim 1, wherein, a common electrode layer, the projection of the common electrode layer on the substrate substrate covers the area where the sub-pixel is located; a pixel electrode, located on the side of the common electrode layer away from the substrate substrate, and connected with the drain electrode of the thin film transistor; The projection of the pixel electrode on the substrate substrate overlaps with the projection of the source electrode of the thin film transistor on the substrate substrate, and / or overlaps with the projection of the gate electrode of the thin film transistor on the substrate substrate. The sub-pixel comprises a thin film transistor, the thin film transistor comprises:

16. The array substrate of claim 1, wherein, an active layer, comprising a channel region and a source region and a drain region located on the opposite sides of the channel region; a gate layer, the projection of the gate layer on the substrate substrate covers the projection of the channel region on the substrate substrate; The projection of the edge of the channel region on the substrate substrate, which is close to the side of the data line, is parallel to the edge of the substrate substrate. The projection of the channel region on the substrate substrate is in the shape of a character.

17. The array substrate of claim 16, wherein, The data line group comprises one data line, which is connected with a plurality of sub-pixels in the pixel unit; wherein the data line comprises a first branch connected with a first sub-pixel, and a second branch connected with the first branch and a second sub-pixel respectively; 18. The array substrate of claim 1, wherein, The second branch comprises a plurality of bends, and the second sub-pixel is adjacent to the first sub-pixel. The projection of the first branch and the second branch on the substrate substrate is approximately U-shaped, and the sub-pixel comprises a thin film transistor; 19. The array substrate of claim 18, wherein, The first branch and the second branch overlap with the active layer of the thin film transistor. The liquid crystal display comprises the array substrate of any one of claims 1-19, and the driving method comprises:

20. A method for driving a liquid crystal display device, wherein In the lighting period of lighting the sub-pixels located in the same row, according to the driving timing, the driving scanning signals are sequentially output to the plurality of gate lines in the same gate line group. ​ And, when outputting the driving scanning signal to the gate line, outputting a corresponding data voltage to the data line in each of the data line groups, and inputting data voltages of opposite polarities to adjacent two of the data line groups in each of the lighting periods, so that the data voltage input to the same data line group in adjacent two of the lighting periods has the same polarity.

21. A display device, wherein, The array substrate of any one of claims 1-19.

Images