Scanning circuit, method of operating scanning circuit, and display device

Abstract

A display panel having a display area and a peripheral area is provided. The display panel comprises a plurality of sub-pixels and a plurality of control signal lines, wherein the sub-pixels and the control signal lines are located in the display area. The scanning circuits and the signal lines are located in the peripheral area. The one or more scan circuits include a first scan circuit and at least a second scan circuit. The first scanning circuit includes a plurality of scanning units. Each scanning unit includes a second output terminal configured to output a control signal to a corresponding control signal line of the plurality of control signal lines. The plurality of signal lines located in the peripheral area include a first start signal line configured to provide a start signal to each scanning unit, and at least a second start signal line configured to provide a start signal to the second scanning circuit.

Description

Technical Field

[0001] This invention relates to display technology, and more specifically, to scanning circuits, methods of operating scanning circuits, and display devices. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides a display panel having a display area and a peripheral area, comprising: a plurality of sub-pixels and a plurality of control signal lines located in the display area; and one or more scanning circuits and a plurality of signal lines located in the peripheral area; wherein the one or more scanning circuits are configured to provide control signals to the plurality of sub-pixels; the one or more scanning circuits include a first scanning circuit and at least a second scanning circuit; the first scanning circuit includes a plurality of scanning units cascaded in series; each of the plurality of scanning units includes a second output terminal configured to output a control signal to a corresponding control signal line among the plurality of control signal lines; and the plurality of signal lines located in the peripheral area include a first start signal line configured to provide a start signal to each scanning unit, and at least a second start signal line configured to provide a start signal to the second scanning circuit.

[0004] Optionally, the plurality of signal lines located in the peripheral region are grouped into a plurality of sequentially arranged groups; wherein, the plurality of groups includes a first group; the first group includes a second start signal line configured to provide a start signal to the second scanning circuit, a first corresponding first power line among the one or more first power lines, a first clock signal line and a second clock signal line; and the orthographic projections of the second start signal line, the first corresponding first power line, the first clock signal line and the second clock signal line on the substrate are arranged sequentially; the orthographic projections of the second start signal line, the first corresponding first power line, the first clock signal line and the second clock signal line on the substrate are substantially parallel to each other.

[0005] Optionally, the first group is located on the side of the plurality of groups that is away from the display area.

[0006] Optionally, the first scanning circuit is a gate scan signal generating circuit configured to generate gate scan signals for sub-pixels located in the display area; and the second scanning circuit is a light emission control signal generating circuit configured to generate light emission control signals for sub-pixels located in the display area.

[0007] Optionally, the plurality of groups further includes a second group; the second group includes a third start signal line, a fourth start signal line, a fifth start signal line, a first corresponding second power line, a first start signal line, and a second corresponding first power line among the one or more second power lines; the orthographic projections of the third start signal line, the fourth start signal line, the fifth start signal line, the first corresponding second power line, the first start signal line, and the second corresponding first power line among the one or more first power lines on the substrate are arranged sequentially; and the orthographic projections of the third start signal line, the fourth start signal line, the fifth start signal line, the first corresponding second power line, the first start signal line, and the second corresponding first power line among the one or more first power lines on the substrate are substantially parallel to each other.

[0008] Optionally, the second group is located on the side of the first group that is closer to the display area.

[0009] Optionally, the display panel further includes a third scanning circuit, a fourth scanning circuit, and a fifth scanning circuit; the third start signal line is configured to provide a start signal to the third scanning circuit; the fourth start signal line is configured to provide a start signal to the fourth scanning circuit; and the fifth start signal line is configured to provide a start signal to the fifth scanning circuit; and the first start signal line is configured to provide a start signal to the first scanning circuit.

[0010] Optionally, the plurality of groups further includes a third group; the third group includes a first selection signal line among the one or more selection signal lines, a second selection signal line among the one or more selection signal lines, and a second corresponding second power line among the one or more second power lines; the orthographic projections of the first selection signal line among the one or more selection signal lines, the second selection signal line among the one or more selection signal lines, and the second corresponding second power line among the one or more second power lines on the substrate are arranged sequentially; and the orthographic projections of the first selection signal line among the one or more selection signal lines, the second selection signal line among the one or more selection signal lines, and the second corresponding second power line among the one or more second power lines on the substrate are substantially parallel to each other.

[0011] Optionally, the third group is located on the side of the second group that is away from the first group.

[0012] Optionally, the first scanning circuit includes multiple parts; the multiple parts include a first part; the first part includes a first transistor, a second transistor, a third transistor, a sixth transistor, a seventh transistor, and an eighth transistor; and the orthogonal projections of the second transistor and the third transistor on the substrate and the orthogonal projections of the sixth transistor and the seventh transistor on the substrate are separated by the orthogonal projections of the first transistor and the eighth transistor on the substrate.

[0013] Optionally, the plurality of portions further includes a second portion; the second portion includes a fourth transistor, a fifth transistor, a third selection transistor, a first capacitor, a second capacitor, and a selection capacitor; and the orthographic projections of the fourth transistor and the fifth transistor on the substrate and the orthographic projections of the selection capacitor and the third selection transistor on the substrate are separated by the orthographic projections of the first capacitor and the second capacitor on the substrate.

[0014] Optionally, the second capacitor electrode of the first capacitor, the second capacitor electrode of the second capacitor, and the second capacitor electrode of the selection capacitor have shapes that are substantially complementary to and spaced apart from the boundaries of adjacent second capacitor electrodes; and the first capacitor electrode of the first capacitor, the first capacitor electrode of the second capacitor, and the first capacitor electrode of the selection capacitor have shapes that are substantially complementary to and spaced apart from the boundaries of adjacent first capacitor electrodes.

[0015] Optionally, the plurality of portions further includes a third portion; and wherein the third portion includes a first selection transistor and a second selection transistor.

[0016] Optionally, the plurality of signal lines located in the peripheral region include one or more selection signal lines; and the orthogonal projection of the one or more selection signal lines on the substrate at least partially overlaps with the orthogonal projection of the first selection transistor on the substrate, and at least partially overlaps with the orthogonal projection of the second selection transistor on the substrate; wherein the one or more selection signal lines include a first selection signal line and a second selection signal line; the first scanning circuit includes a multi-level cascaded scanning unit configured to provide a plurality of control signals to multiple rows of sub-pixels; the multi-level cascaded scanning unit includes an M-level scanning unit, the M-level scanning unit including a (2m-1)-th level scanning unit and a (2m)-th level scanning unit, where M and m are positive integers, 1≤m≤(M / 2); the first selection signal line is configured to provide a selection signal to the (2m-1)-th level scanning unit; and the second selection signal line is configured to provide a selection signal to the (2m)-th level scanning unit.

[0017] Optionally, the channel width to channel length ratio of the active layer of the first selection transistor is in the range of 50:3.5 to 70:3.5; and the channel width to channel length ratio of the active layer of the second selection transistor is in the range of 150:3.5 to 210:3.5.

[0018] In another aspect, this disclosure provides a display device including the display panel and one or more integrated circuits connected to the display panel.

[0019] In another aspect, this disclosure provides a scanning circuit including a plurality of scanning units; wherein each of the plurality of scanning units includes a first output sub-circuit and a second output sub-circuit, the first output sub-circuit being configured to output a carry signal as an input to a scanning unit in a different stage, and the second output sub-circuit being configured to output a control signal configured to drive a pixel driving circuit; wherein the first output sub-circuit includes a first output transistor and a second output transistor, the second electrodes of the first output transistor and the second output transistor being connected to a first output terminal configured to output the carry signal; the second output sub-circuit includes a first selection transistor and a second selection transistor, the second electrodes of the first selection transistor and the second selection transistor being connected to a second output terminal configured to output the control signal; the gates of the first output transistor and the first selection transistor are electrically connected to each other; and the first electrodes of the first output transistor and the first selection transistor are configured to be provided with different signals.

[0020] Optionally, the first electrode of the first selection transistor is configured to be provided with a selection signal; and the selection signal includes at least a portion of an AC signal.

[0021] Optionally, the first electrode of the first output transistor is configured to be supplied with a constant signal.

[0022] Optionally, the gate of the second output transistor and the gate of the second selection transistor are electrically isolated by a stabilizing transistor; the first electrode of the stabilizing transistor is electrically connected to the gate of the second selection transistor; and the second electrode of the stabilizing transistor is electrically connected to the gate of the second output transistor.

[0023] In another aspect, this disclosure provides a method for operating a scanning circuit having multiple scanning units, comprising: electrically connecting the second electrodes of a first output transistor and a second output transistor of a first output sub-circuit of each of the multiple scanning units to a first output terminal configured to output a carry signal, the carry signal being configured as an input to a scanning unit in a different stage; electrically connecting the second electrodes of a first selection transistor and a second selection transistor of a second output sub-circuit of each of the scanning units to a second output terminal configured to output a control signal, the control signal being configured to drive a pixel driving circuit; electrically connecting the gates of the first output transistor and the first selection transistor to each other; providing different signals to the first electrodes of the first output transistor and the first selection transistor respectively; outputting the carry signal from the first output sub-circuit; and outputting the control signal from the second output sub-circuit. Attached Figure Description

[0024] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0025] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0026] FIG. 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] FIG. 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0028] FIG. 3 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0029] FIG. 4 This is a circuit diagram of a corresponding scanning unit of a scanning circuit according to some embodiments of the present disclosure.

[0030] FIG. 5 It is shown FIG. 4 The timing diagram shown illustrates the operation of the corresponding scanning unit in the first mode.

[0031] FIG. 6 It is shown FIG. 4 The timing diagram shown illustrates the operation of the corresponding scanning unit in the second mode.

[0032] FIG. 7 The outputs of different stages of a scanning circuit that operate alternately in a first mode and a second mode according to some embodiments of the present disclosure are depicted.

[0033] FIG. 8A This is a diagram illustrating the structure of a corresponding scanning unit of a scanning circuit according to some embodiments of the present disclosure.

[0034] FIG. 8B It is shown FIG. 8A A diagram showing the structure of the semiconductor material layer in the corresponding scanning unit.

[0035] FIG. 8C It is shown FIG. 8A A diagram showing the structure of the first conductive layer in the corresponding scanning unit.

[0036] FIG. 8D It is shown FIG. 8A A diagram showing the structure of the second conductive layer in the corresponding scanning unit.

[0037] FIG. 8E It is shown FIG. 8AA diagram showing the structure of the third conductive layer in the corresponding scanning unit.

[0038] FIG. 8F It is shown FIG. 8A The diagram shows a via extending through the third gate insulating layer in the corresponding scan cell.

[0039] FIG. 8G It is shown FIG. 8A The diagram shows the structure of the first signal line layer in the corresponding scanning unit.

[0040] FIG. 8H It is shown FIG. 8A The diagram shows the vias extending through the passivation layer in the corresponding scanning unit.

[0041] FIG. 8I It is shown FIG. 8A The diagram shows the structure of the second signal line layer in the corresponding scanning unit.

[0042] FIG. 9 It is along FIG. 8A A cross-sectional view of line A-A' in the diagram.

[0043] FIG. 10 This is a circuit diagram of a corresponding scanning unit of a scanning circuit according to some embodiments of the present disclosure.

[0044] FIG. 11 It is shown FIG. 10 The timing diagram shown illustrates the operation of the corresponding scanning unit in the first mode.

[0045] FIG. 12 It is shown FIG. 10 The timing diagram shown illustrates the operation of the corresponding scanning unit in the second mode.

[0046] FIG. 13 This is a circuit diagram of a corresponding scanning unit of a scanning circuit according to some embodiments of the present disclosure.

[0047] FIG. 14 It is shown FIG. 13 The timing diagram shown illustrates the operation of the corresponding scanning unit in the first mode.

[0048] FIG. 15 It is shown FIG. 13 The timing diagram shown illustrates the operation of the corresponding scanning unit in the second mode. Detailed Implementation

[0049] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0050] This disclosure provides, in particular, a display panel, a display device, a scanning circuit, and a method for operating the scanning circuit, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a display panel. In some embodiments, the display panel includes a display area and a peripheral area. In some embodiments, the display panel includes a plurality of sub-pixels and a plurality of control signal lines located in the display area; and one or more scanning circuits and a plurality of signal lines located in the peripheral area. Optionally, the one or more scanning circuits are configured to provide control signals to the plurality of sub-pixels. Optionally, the one or more scanning circuits include a first scanning circuit and at least a second scanning circuit. Optionally, the first scanning circuit includes a plurality of scanning units cascaded in series. Optionally, each of the plurality of scanning units includes a second output terminal configured to output a control signal to a corresponding control signal line among the plurality of control signal lines. Optionally, the plurality of signal lines located in the peripheral area include a first start signal line configured to provide a start signal to each scanning unit, and at least a second start signal line configured to provide a start signal to the second scanning circuit.

[0051] In some embodiments, the display panel includes an array substrate. In some embodiments, the array substrate includes a plurality of light-emitting elements, a plurality of pixel driving circuits configured to drive the plurality of light-emitting elements to emit light, and one or more gate-on-array circuits configured to provide one or more control signals to the plurality of pixel driving circuits.

[0052] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0053] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) FIG. 1The array substrate includes an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of voltage supply lines Vdd, and a corresponding second voltage supply line (e.g., a low voltage supply line Vss). The emission of light from each subpixel Sp is driven by the corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding high voltage supply line among the plurality of voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0054] FIG. 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) FIG. 2AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL1 among a plurality of second gate lines. The transistor consists of: a gate of transistor T2; a first electrode connected to the gate of the storage capacitor Cst and the first electrode of the driving transistor Td; a second electrode connected to the second electrode of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines; a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines; and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines; a first electrode connected to the second electrode of the driving transistor Td and the second electrode of the second transistor T2; and a second electrode connected to the anode of the light-emitting element LE; and a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines; a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines; and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE. A second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0055] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0056] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0057] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, a corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0058] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td.

[0059] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) FIG. 2A The second transistor T2 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0060] FIG. 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) FIG. 2A and FIG. 2B During one frame of an image, the operation of the pixel driving circuit includes an initial sub-stage t0, a first reset sub-stage t1, a data writing sub-stage t2, a second reset sub-stage t3, and a light emission sub-stage t4. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn off. A cutoff reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 and the third reset transistor Tr3 to turn off. In the initial sub-stage t0, cutoff signals are provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, therefore the first transistor T1 and the second transistor T2 are turned off.

[0061] In the first reset stage t1, a reset control signal is provided to the gate of the second reset transistor Tr2 via the second reset control signal line rst2 to turn on the second reset transistor Tr2; this allows the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and further to the second electrode of the second transistor T2 and the second electrode of the driving transistor Td. Node N3 is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in the first reset stage t1. In the first reset stage t1, each of the first gate lines GL1 is provided with a cutoff signal, therefore the first transistor T1 is turned off. In the first reset stage t1, each of the second gate lines GL2 is provided with a conduction signal, therefore the second transistor T2 is turned on. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0062] During the data write sub-stage t2, the cutoff reset control signal is again provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn off. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with conduction signals, thus turning on the first transistor T1 and the second transistor T2. The second electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Because the second transistor T2 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. Node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Because only the PN junction between the gate of the driving transistor Td and the first electrode is active, the voltage level of node N1 gradually increases to (Vdata + Vth) during the data writing sub-stage t2, where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0063] In the second reset stage t3, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1 to turn on the first reset transistor Tr1; this allows the initialization voltage signal from the corresponding first reset signal line Vint1 to pass from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and sequentially to node N4. The anode of the light-emitting element LE is initialized. A turn-on reset control signal is provided to the gate of the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn on the third reset transistor Tr3; this allows the initialization voltage signal from the corresponding third reset signal line Vint3 to pass from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and sequentially to node N2. Node N2 is initialized.

[0064] In the second reset stage t3, a cutoff reset control signal is again provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. Each first gate line GL1 and each second gate line GL2 is provided with a cutoff signal, and the first transistor T1 and the second transistor T2 are turned off.

[0065] During the light-emitting phase t4, a low voltage signal is provided to the corresponding light-emitting control signal line em to turn on the third transistor T3 and the fourth transistor T4. During t4, the voltage level at node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level and operates in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0066] Typically, display panels, such as those in mobile phones, have only one refresh rate per frame. For example, within a frame, during the high refresh rate period, there is only one high refresh rate from the top to the bottom of the display panel, and during the low refresh rate period, there is only one low refresh rate. However, a high refresh rate means higher power consumption, which poses a significant challenge to battery capacity and durability.

[0067] In some embodiments, the array substrate and display device according to this disclosure employ partial refresh technology. Partial refresh technology is a novel driving method that can achieve both high and low refresh rates within a single frame, thereby reducing power consumption. FIG. 3 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. ReferenceFIG. 3 The array substrate includes a first region Z1 and a second region Z2. During image display, the first region Z1 and the second region Z2 can have different refresh rates.

[0068] Scanning circuits used to implement partial refresh technology (e.g., 16T3C, 13T3C, 12T3C, 10T3C, 8T2C scanning circuits) may include selector circuits. The inventors of this disclosure have discovered a novel scanning circuit in which the output transistor of the selector circuit does not share its gate with other output transistors in the scanning circuit. The inventors of this disclosure have discovered that the novel scanning circuit has reduced load on the gate of the output transistor and a relatively uniform output voltage. The inventors of this disclosure have discovered, surprisingly and unexpectedly, that the novel scanning circuit can improve performance in different regions (e.g., FIG. 3 The stability of the output voltage in the first zone Z1 and the second zone Z2.

[0069] FIG. 4 This is a circuit diagram of a corresponding scanning unit of a scanning circuit according to some embodiments of this disclosure. (See reference...) FIG. 4 In some embodiments, each scanning unit includes an input sub-circuit ISC, a first output sub-circuit OSC1, a second output sub-circuit OSC2, and one or more additional sub-circuits. In some embodiments, the one or more additional sub-circuits include a first sub-circuit SC1, a second sub-circuit SC2, a third sub-circuit SC3, and a fourth sub-circuit SC4.

[0070] In some embodiments, the input sub-circuit ISC is connected to one or more additional sub-circuits; the first output sub-circuit OSC1 is connected to one or more additional sub-circuits and is also connected to the second output sub-circuit OSC2.

[0071] In some embodiments, the input subcircuit ISC is connected to the first subcircuit SC1. The first subcircuit SC1 is connected to the input subcircuit ISC, the second subcircuit SC2, and the fourth subcircuit SC4. The second subcircuit SC2 is connected to the first subcircuit SC1 and to the first output subcircuit OSC1. The third subcircuit SC3 is connected to the fourth subcircuit SC4 and to the first output subcircuit OSC1. The fourth subcircuit SC4 is connected to the first subcircuit SC1 and to the third subcircuit SC3. The first output subcircuit OSC1 is connected to the second subcircuit SC2, the third subcircuit SC3, and the second output subcircuit OSC2. The second output subcircuit OSC2 is connected to the first output subcircuit OSC1.

[0072] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals provided to the input terminal IN and the first clock signal terminal CK1, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0073] The first transistor T1 is coupled between the input terminal IN and the first node N1. The gate of the first transistor T1 is coupled to the first clock signal terminal CK1. When the effective voltage of the first clock signal is provided to the first clock signal terminal CK1, the first transistor T1 is turned on to electrically couple the input terminal IN to the first node N1.

[0074] In some embodiments, the gate of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0075] In some embodiments, the first sub-circuit SC1 is configured to control the voltage of the first node N1 and / or the voltage of the second node N2. Optionally, the first sub-circuit SC1 includes a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7.

[0076] In some embodiments, the gate of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2.

[0077] In some embodiments, the gate of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is configured to be provided with a first power supply signal VGL, and the second electrode of the third transistor T3 is electrically connected to the second node N2.

[0078] In some embodiments, the gate of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is configured to be provided with a second power supply signal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7.

[0079] In some embodiments, the gate of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh transistor T7 is electrically connected to the second electrode of the sixth transistor T6, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0080] In some embodiments, the second sub-circuit SC2 includes a first capacitor C1. In some embodiments, the first plate C11 of the first capacitor C1 is electrically connected to the second node N2, and the second plate C12 of the first capacitor C1 is configured to be supplied with a second power signal VGH.

[0081] In some embodiments, the third sub-circuit SC3 includes a second capacitor C2. In some embodiments, the first plate C21 of the second capacitor C2 is electrically connected to the third node N3, and the second plate C22 of the second capacitor C2 is electrically connected to the first output terminal OUT1.

[0082] In some embodiments, a fourth sub-circuit SC4 is coupled between a first node N1 and a third node N3. Optionally, the fourth sub-circuit SC4 is configured to limit the voltage drop width of the first node N1. Optionally, the fourth sub-circuit SC4 includes an eighth transistor T8.

[0083] In some embodiments, the gate of the eighth transistor T8 is configured to be supplied with a first power supply signal VGL, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3.

[0084] In some embodiments, the first output sub-circuit OSC1 is configured to provide the voltage of the second power supply signal VGH to the first output terminal OUT1 in response to the voltage of the second node N2. Optionally, the first output sub-circuit OSC1 includes a fourth transistor T4 and a fifth transistor T5.

[0085] In some embodiments, the gate of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is configured to be supplied with a second power supply signal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the first output terminal OUT1.

[0086] In some embodiments, the gate of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first output terminal OUT1.

[0087] In some embodiments, the second output sub-circuit OSC2 is configured to provide the voltage of the selection signal MS to the second output terminal OUT2 in response to the voltage of the first node N1. Optionally, the second output sub-circuit OSC2 includes a first selection transistor ST1, a second selection transistor ST2, a third selection transistor ST3, and a selection capacitor SC. In some embodiments, the selection signal MS includes an AC signal. Optionally, the amplitude of the high-voltage portion of the AC signal is higher than the amplitude of the high-voltage portion of the second power supply signal VGH.

[0088] In some embodiments, the gate of the first selection transistor ST1 is electrically connected to the second node N2, the first electrode of the first selection transistor ST1 is configured to be provided with a second power supply signal VGH, and the second electrode of the first selection transistor ST1 is electrically connected to the second output terminal OUT2.

[0089] In some embodiments, the gate of the second selection transistor ST2 is electrically connected to the second electrode of the third selection transistor ST3, the first electrode of the second selection transistor ST2 is configured to be provided with a selection signal MS, and the second electrode of the second selection transistor ST2 is electrically connected to the second output terminal OUT2.

[0090] In some embodiments, the gate of the third selection transistor ST3 is configured to be provided with a first power supply signal VGL, the first electrode of the third selection transistor ST3 is electrically connected to the first node N1, and the second electrode of the third selection transistor ST3 is electrically connected to the gate of the second selection transistor ST2.

[0091] In some embodiments, the first plate CE1 of the selection capacitor SC is electrically connected to the gate of the second selection transistor ST2, and the second plate CE2 of the selection capacitor SC is electrically connected to the second output terminal OUT2.

[0092] This disclosure can be implemented in scanning circuits having various types of transistors, including scanning circuits with p-type transistors, scanning circuits with n-type transistors, or scanning circuits with one or more p-type transistors and one or more n-type transistors. For p-type transistors, the active control signal (e.g., a turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., a turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a low-voltage signal. In one example, the first transistors T1 to T8 and the first selection transistors ST1 to ST3 can be p-type transistors, such as polysilicon transistors. In one example, the first transistors T1 to T8 and the first selection transistors ST1 to ST3 can be n-type transistors, such as metal-oxide-semiconductor transistors.

[0093] In one example, the second power signal VGH provides a continuous high-level signal, while the first power signal VGL provides a continuous low-level signal.

[0094] In this scanning circuit, the gates of the second selection transistor ST2 and the fifth transistor T5 are provided with different voltages. For example, the gate of the second selection transistor ST2 may be provided with the potential of the first node N1, while the gate of the fifth transistor T5 may be provided with the potential of the third node N3. The gates of the second selection transistor ST2 and the fifth transistor T5 are spaced apart by at least the eighth transistor T8.

[0095] FIG. 5 It is shown FIG. 4The timing diagram shown illustrates the operation of the corresponding scanning unit in the first mode. (Refer to...) FIG. 4 and FIG. 5 In some embodiments, the operation of each scanning unit includes a first time period p1, a second time period p2, a third time period p3, and a fourth time period p4.

[0096] During the first time period p1, the input terminal IN is low, CK1 is low, and CK2 is high. The first sub-circuit SC1 controls the potential of the second node N2 to be low. The input sub-circuit ISC, under the control of CK1, controls the connection between the first node N1 and the input terminal IN, thereby controlling the potential of the first node N1 to be low. The fourth sub-circuit SC4 controls the connection between the first node N1 and the third node N3, causing the potential of the third node N3 to be low. The first output sub-circuit OSC1, under the control of the potential of the third node N3, outputs CK2 to the first output terminal OUT1, and under the control of the potential of the second node N2, outputs VGH to the first output terminal OUT1, thereby outputting a high level through the first output terminal OUT1. The signal output from the first output terminal OUT1 is used as a carry signal and can be output to the scan units in different stages of the scan circuit. As used herein, the term carry signal refers to the signal that propagates from one stage of the circuit to another. The carry signal is a sequential signal that controls the shift registers of the entire scan circuit to be sequentially timed and activated. It ensures that the shift registers are activated in the correct order. The carry signal is output from the output of the first stage and input to the input of another stage (e.g., the next stage).

[0097] During the first time period p1, the second output sub-circuit OSC2, under the control of the potential of the first node N1, outputs the selection signal MS to the second output terminal OUT2, and under the control of the potential of the second node N2, outputs VGH to the second output terminal OUT2, thereby outputting a high level through the second output terminal OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal, and is transmitted to... FIG. 2A The gate of the first transistor T1 in the corresponding pixel driving circuit shown. The high level output from the second output terminal OUT2 is cut off. FIG. 2A The first transistor T1 in the corresponding pixel driving circuit shown.

[0098] During the second time period p2, the input terminal IN is at a high level, CK1 is at a high level, and CK2 is at a low level. Under the control of CK1, the input sub-circuit ISC disconnects the first node N1 from the input terminal IN, thus maintaining the potential of the first node N1 at a low level. Under the control of the potential of the first node N1, the first sub-circuit SC1 controls the second node N2 to receive CK1, thus controlling the potential of the second node N2 to a high level. Under the control of the potential of the second node N2, the first sub-circuit SC1 also disconnects the first node N1 from VGH. With the second node N2 at a high level, the fourth transistor T4 is turned off.

[0099] During the second time period p2, the third node N3 is at a low level, thus turning on the fifth transistor T5. CK2 is also at a low level. The first output sub-circuit OSC1, under the control of the potential of the third node N3, outputs CK2 to the first output terminal OUT1, thereby outputting a low level through the first output terminal OUT1. Because the first output terminal OUT1 outputs a low level, and the first capacitor electrode of the second capacitor C2 is connected to the first output terminal OUT1, the second capacitor C2 further pulls down the potential of the third node N3 based on the voltage level at the first output terminal OUT1. The signal output from the first output terminal OUT1 is used as a carry signal and can be output to the scan units in different stages of the scan circuit.

[0100] During the second time period p2, the second node N2 is at a high level, thus turning off the first selection transistor ST1. The potential of the first node N1 remains at a low level, thus turning on the second selection transistor ST2. Under the control of the potential of the first node N1, the second output sub-circuit OSC2 outputs the selection signal MS to the second output terminal OUT2, thereby outputting a low level through the second output terminal OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the first transistor T1 in the corresponding pixel driving circuit shown is activated by a low level output from the second output terminal OUT2 (e.g., the low-level portion of the AC signal of the selection signal MS). FIG. 2A The first transistor T1 in the corresponding pixel driving circuit shown.

[0101] During the third time period p3, the input terminal IN is high, CK1 is low, and CK2 is high. The first sub-circuit SC1, under the control of CK1, controls the second node N2 to receive VGL. The first output sub-circuit OSC1, under the control of the potential of the second node N2, outputs VGH to the first output terminal OUT1. The input sub-circuit ISC, under the control of CK1, controls the connection between the first node N1 and the input terminal IN, thereby controlling the potential of the first node N1 to be high. The fourth sub-circuit SC4 controls the connection between the first node N1 and the third node N3, thereby controlling the potential of the third node N3 to be high.

[0102] During the third time period p3, the first node N1 is at a high level, thus turning off the second selection transistor ST2. The second node N2 is at a low level, thus turning on the first selection transistor ST1. The second output sub-circuit OSC2, under the control of the potential of the second node N2, outputs VGH to the second output terminal OUT2, thereby outputting a high level through the second output terminal OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the first transistor T1 in the corresponding pixel driving circuit shown. The high level output from the second output terminal OUT2 is cut off. FIG. 2A The first transistor T1 in the corresponding pixel driving circuit shown.

[0103] During the fourth time period p4, the input terminal is high, CK1 is high, and CK2 is low. The first sub-circuit SC1 maintains the potential of the second node N2 at a low level. The input sub-circuit ISC controls and maintains the potential of the first node N1 at a high level. The fourth sub-circuit SC4 controls the connection between the first node N1 and the third node N3, thereby controlling the potential of the third node N3 to be high. The first output sub-circuit OSC1, under the control of the potential of the second node N2, outputs VGH to the first output terminal OUT1.

[0104] During the fourth time period p4, the first node N1 is at a high level, thus turning off the second selection transistor ST2. The second node N2 is at a low level, thus turning on the first selection transistor ST1. The second output sub-circuit OSC2, under the control of the potential of the second node N2, outputs VGH to the second output terminal OUT2, thereby outputting a high level through the second output terminal OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2AThe gate of the first transistor T1 in the corresponding pixel driving circuit shown. The high level output from the second output terminal OUT2 is cut off. FIG. 2A The first transistor T1 in the corresponding pixel driving circuit shown.

[0105] FIG. 6 It is shown FIG. 4 The timing diagram shows the operation of the corresponding scanning unit in the second mode. (Refer to...) FIG. 4 and FIG. 6 In some embodiments, the operation of each scanning unit includes a first time period p1, a second time period p2, a third time period p3, and a fourth time period p4.

[0106] During the first time period p1, the input terminal IN is at a low level, CK1 is at a low level, and CK2 is at a high level. The first sub-circuit SC1 controls the potential of the second node N2 to be low. The input sub-circuit ISC, under the control of CK1, controls the connection between the first node N1 and the input terminal IN, thereby controlling the potential of the first node N1 to be low. The fourth sub-circuit SC4 controls the connection between the first node N1 and the third node N3, causing the potential of the third node N3 to be low. The first output sub-circuit OSC1, under the control of the potential of the third node N3, outputs CK2 to the first output terminal OUT1, and under the control of the potential of the second node N2, outputs VGH to the first output terminal OUT1, thereby outputting a high level through the first output terminal OUT1. The signal output from the first output terminal OUT1 is used as a carry signal and can be output to the scanning units in different stages of the scanning circuit.

[0107] During the first time period p1, the second output sub-circuit OSC2, under the control of the potential of the first node N1, outputs the selection signal MS to the second output terminal OUT2, and under the control of the potential of the second node N2, outputs VGH to the second output terminal OUT2, thereby outputting a high level through the second output terminal OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal, and is transmitted to... FIG. 2A The gate of the first transistor T1 in the corresponding pixel driving circuit shown. The high level output from the second output terminal OUT2 is cut off. FIG. 2A The first transistor T1 in the corresponding pixel driving circuit shown.

[0108] During the second time period p2, the input terminal IN is at a high level, CK1 is at a high level, and CK2 is at a low level. The input sub-circuit ISC, under the control of CK1, controls the disconnection between the first node N1 and the input terminal IN, thus maintaining the potential of the first node N1 at a low level. The first sub-circuit SC1, under the control of the potential of the first node N1, controls the second node N2 to receive CK1, thus controlling the potential of the second node N2 to a high level. The first sub-circuit SC1, under the control of the potential of the second node N2, controls the disconnection between the first node N1 and VGH. The second node N2 is at a high level, thus turning off the fourth transistor T4. The third sub-circuit SC3 further pulls down the potential of the third node N3 based on the voltage level at the first output terminal OUT1. The third node N3 is at a low level, thus turning on the fifth transistor T5. CK2 is at a low level. The first output sub-circuit OSC1, under the control of the potential of the third node N3, outputs CK2 to the first output terminal OUT1, thus outputting a low level through the first output terminal OUT1. The signal output from the first output terminal OUT1 is used as a carry signal and can be output to the scanning unit in different stages of the scanning circuit.

[0109] During the second time period p2, the second node N2 is at a high level, thus turning off the first selection transistor ST1. The potential of the first node N1 remains at a low level, thus turning on the second selection transistor ST2. The second output sub-circuit OSC2, under the control of the potential of the first node N1, outputs the selection signal MS to the second output terminal OUT2. In the second mode, the selection signal MS is at a high level during the second time period p2. Therefore, the second output sub-circuit OSC2 outputs a high level through the second output terminal OUT2 during the second time period p2. This differs from the first mode. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the high-level signal output from the second output terminal OUT2 is transmitted to... FIG. 2A The gate of the first transistor T1 in the corresponding pixel driving circuit depicted in the diagram. The high level output from the second output terminal OUT2 is cut off. FIG. 2A The first transistor T1 in the corresponding pixel driving circuit is shown. Each pixel driving circuit retains the data signal previously input to the corresponding pixel driving circuit.

[0110] During the third time period p3, the input terminal IN is high, CK1 is low, and CK2 is high. The first sub-circuit SC1, under the control of CK1, controls the second node N2 to receive VGL. The first output sub-circuit OSC1, under the control of the potential of the second node N2, outputs VGH to the first output terminal OUT1. The input sub-circuit ISC, under the control of CK1, controls the connection between the first node N1 and the input terminal IN, thereby controlling the potential of the first node N1 to be high. The fourth sub-circuit SC4 controls the connection between the first node N1 and the third node N3, thereby controlling the potential of the third node N3 to be high.

[0111] During the third time period p3, the first node N1 is at a high level, thus turning off the second selection transistor ST2. The second node N2 is at a low level, thus turning on the first selection transistor ST1. The second output sub-circuit OSC2, under the control of the potential of the second node N2, outputs VGH to the second output terminal OUT2, thereby outputting a high level through the second output terminal OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the first transistor T1 in the corresponding pixel driving circuit shown. The high level output from the second output terminal OUT2 is cut off. FIG. 2A The first transistor T1 in the corresponding pixel driving circuit shown.

[0112] During the fourth time period p4, the input terminal is high, CK1 is high, and CK2 is low. The first sub-circuit SC1 maintains the potential of the second node N2 at a low level. The input sub-circuit ISC controls and maintains the potential of the first node N1 at a high level. The fourth sub-circuit SC4 controls the connection between the first node N1 and the third node N3, thereby controlling the potential of the third node N3 to be high. The first output sub-circuit OSC1, under the control of the potential of the second node N2, outputs VGH to the first output terminal OUT1.

[0113] During the fourth time period p4, the first node N1 is at a high level, thus turning off the second selection transistor ST2. The second node N2 is at a low level, thus turning on the first selection transistor ST1. The second output sub-circuit OSC2, under the control of the potential of the second node N2, outputs VGH to the second output terminal OUT2, thereby outputting a high level through the second output terminal OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2AThe gate of the first transistor T1 in the corresponding pixel driving circuit shown. The high level output from the second output terminal OUT2 is cut off. FIG. 2A The first transistor T1 in the corresponding pixel driving circuit shown.

[0114] FIG. 7 The outputs of different stages of a scanning circuit, operating alternately in a first mode and a second mode, are depicted according to some embodiments of this disclosure. (Refer to...) FIG. 7 The scanning circuit operates alternately in a first mode and a second mode. In the first mode, the selection signal MS is low. In the second mode, the selection signal MS is high for at least one frame of the image. FIG. 7 The output of the scanning circuit in four frames (including frame 1, frame 2, frame 3 and frame 4) of the image is described.

[0115] like FIG. 7 As shown, in the first zone Z1, the scanning circuit outputs a valid control signal for the pixel driving circuit only in the first mode, and an invalid control signal for the pixel driving circuit in the second mode. The display panel displays the image in a low-frequency mode in the first zone Z1. In the second zone Z2, the scanning circuit outputs a valid control signal for the pixel driving circuit in both the first and second modes. The display panel displays the image in a high-frequency mode in the second zone Z2.

[0116] FIG. 8A This is a diagram illustrating the structure of a corresponding scanning unit of a scanning circuit according to some embodiments of the present disclosure. FIG. 8B It is shown FIG. 8A A diagram showing the structure of the semiconductor material layer in the corresponding scanning unit. FIG. 8C It is shown FIG. 8A A diagram showing the structure of the first conductive layer in the corresponding scanning unit. FIG. 8D It is shown FIG. 8A A diagram showing the structure of the second conductive layer in the corresponding scanning unit. FIG. 8E It is shown FIG. 8A A diagram showing the structure of the third conductive layer in the corresponding scanning unit. FIG. 8F It is shown FIG. 8A The diagram shows a via extending through the third gate insulating layer in the corresponding scan cell. FIG. 8G It is shown FIG. 8A The diagram shows the structure of the first signal line layer in the corresponding scanning unit. FIG. 8H It is shown FIG. 8A The diagram shows the vias extending through the passivation layer in the corresponding scanning unit. FIG. 8I It is shown FIG. 8A The diagram shows the structure of the second signal line layer in the corresponding scanning unit. FIG. 9 It is alongFIG. 8A A cross-sectional view of line A-A' in the diagram.

[0117] refer to FIG. 8A to FIG. 8I and FIG. 9 In some embodiments, each scanning unit includes a substrate BS; a semiconductor material layer SML located on the substrate BS; an insulating layer IN located on the side of the semiconductor material layer SML away from the substrate BS; a first conductive layer CT1 located on the side of the insulating layer IN away from the substrate BS; a first gate insulating layer GI1 located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2 located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2 located on the side of the second conductive layer CT2 away from the substrate BS; a third conductive layer CT3 located on the side of the second gate insulating layer GI2 away from the substrate BS; a third gate insulating layer GI3 located on the side of the third conductive layer CT3 away from the substrate BS; a first signal line layer SD1 located on the side of the third gate insulating layer GI3 away from the substrate BS; a passivation layer PVX located on the side of the first signal line layer SD1 away from the substrate BS; and a second signal line layer SD2 located on the side of the passivation layer PVX away from the substrate BS.

[0118] Reference FIG. 8A and FIG. 8B In some embodiments, the semiconductor material layer SML includes the active layer of the transistors in each scan unit. FIG. 8B The active layers of the transistors in each scanning unit are marked, for example, the active layer ACT1 of the first transistor T1, the active layer ACT2 of the second transistor T2, the active layer ACT3 of the third transistor T3, the active layer ACT4 of the fourth transistor T4, the active layer ACT5 of the fifth transistor T5, the active layer ACT6 of the sixth transistor T6, the active layer ACT7 of the seventh transistor T7, the active layer ACT8 of the eighth transistor T8, the active layer ACTs1 of the first selection transistor Ts1, the active layer ACTs2 of the second selection transistor Ts2, and the active layer ACTs3 of the third selection transistor Ts3. Optionally, the semiconductor material layer SML also includes a portion connecting the active layer ACT6 of the sixth transistor T6 to the active layer ACT7 of the seventh transistor T7, which serves as the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer SML. Examples of semiconductor materials used to fabricate semiconductor material layers (SMLs) include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxynitride).

[0119] Reference FIG. 8A andFIG. 8C In some embodiments, the first conductive layer CT1 includes a first capacitor electrode C11 of a first capacitor C1, a first capacitor electrode C21 of a second capacitor C2, a first capacitor electrode CE1 of a selection capacitor SC, a gate G1 of a first transistor T1, a gate G2 of a second transistor T2, a gate G3 of a third transistor T3, a gate G4 of a fourth transistor T4, a gate G5 of a fifth transistor T5, a gate G6 of a sixth transistor T6, a gate G7 of a seventh transistor T7, a gate G8 of an eighth transistor T8, a gate Gs1 of a first selection transistor Ts1, a gate Gs2 of a second selection transistor Ts2, and a gate Gs3 of a third selection transistor Ts3. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer CT1. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer CT1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0120] See FIG. 8A and FIG. 8D In some embodiments, the second conductive layer CT2 includes a second capacitor electrode C12 of the first capacitor C1, a second capacitor electrode C22 of the second capacitor C2, and a second capacitor electrode CE2 of the selection capacitor SC. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second conductive layer CT2. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer CT2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0121] In some embodiments, the second capacitor electrode C12 of the first capacitor C1, the second capacitor electrode C22 of the second capacitor C2, and the second capacitor electrode CE2 of the select capacitor SC have shapes that are substantially complementary to and spaced apart from the boundaries of adjacent second capacitor electrodes (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the second capacitor electrode C12 of the first capacitor C1 has a shape that is substantially complementary to and spaced apart from the boundaries of the second capacitor electrode C22 of the second capacitor C2 and the second capacitor electrode CE2 of the select capacitor SC (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the second capacitor electrode C22 of the second capacitor C2 has a shape that is substantially complementary to and spaced apart from the boundaries of the second capacitor electrode C12 of the first capacitor C1 and the second capacitor electrode CE2 of the select capacitor SC (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the second capacitor electrode CE2 of the selected capacitor SC has a shape that is substantially complementary to and spaced apart from the boundaries of the second capacitor electrode C12 of the first capacitor C1 and the second capacitor electrode C22 of the second capacitor C2. The inventors of this disclosure have found that this structure can effectively save space in the layout.

[0122] In some embodiments, the first capacitor electrode C11 of the first capacitor C1, the first capacitor electrode C21 of the second capacitor C2, and the first capacitor electrode CE1 of the select capacitor SC have shapes that are substantially complementary to and spaced apart from the boundaries of adjacent first capacitor electrodes (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the first capacitor electrode C11 of the first capacitor C1 has a shape that is substantially complementary to and spaced apart from the boundaries of the first capacitor electrode C21 of the second capacitor C2 and the first capacitor electrode CE1 of the select capacitor SC (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the first capacitor electrode C21 of the second capacitor C2 has a shape that is substantially complementary to and spaced apart from the boundaries of the first capacitor electrode C11 of the first capacitor C1 and the first capacitor electrode CE1 of the select capacitor SC (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the first capacitor electrode CE1 of the selected capacitor SC has a shape that is substantially complementary to and spaced apart from the boundaries of the first capacitor electrode C11 of the first capacitor C1 and the first capacitor electrode C21 of the second capacitor C2 (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). The inventors of this disclosure have found that this structure can effectively save space in the layout.

[0123] refer to FIG. 8A and FIG. 8E In some embodiments, the third conductive layer CT3 includes a second node connection line Cln2. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the third conductive layer CT3. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third conductive layer CT3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0124] Reference FIG. 8A and FIG. 8GIn some embodiments, the first signal line layer SD1 includes a first electrode S1 of a first transistor T1, a first electrode S2 of a second transistor T2, a first electrode S3 of a third transistor T3, a first electrode S4 of a fourth transistor T4, a first electrode S5 of a fifth transistor T5, a first electrode S6 of a sixth transistor T6, a first electrode S8 of an eighth transistor T8, a first electrode Ss1 of a first selection transistor Ts1, a first electrode Ss2 of a second selection transistor Ts2, and a first electrode Ss3 of a third selection transistor Ts3. Optionally, the first signal line layer SD1 also includes a second electrode D1 of a first transistor T1, a second electrode D2 of a second transistor T2, a second electrode D3 of a third transistor T3, a second electrode D4 of a fourth transistor T4, a second electrode D5 of a fifth transistor T5, a second electrode D7 of a seventh transistor T7, a second electrode D8 of an eighth transistor T8, a second electrode Ds1 of a first selection transistor Ts1, a second electrode Ds2 of a second selection transistor Ts2, and a second electrode Ds3 of a third selection transistor Ts3. Optionally, the first signal line layer SD1 further includes a first node connection line Cln1, a third node connection line Cln3, an input signal line ISL, a first output signal line OSL1, a voltage connection line Clv, a first connection line Cl1, a second connection line Cl2, and a third connection line Cl3.

[0125] refer to FIG. 8A and FIG. 8I In some embodiments, the second signal line layer SD2 includes one or more start signal lines (GSTV, ESTV, RPSTV, RHSTV, and GNSTV), one or more second power lines VGHL, one or more first power lines VGLL, a first clock signal line CK1L, a second clock signal line CK2L, and one or more select signal lines MSL. The one or more start signal lines are configured to transmit a start signal. The one or more second power lines VGHL are configured to provide a second power signal. The one or more first power lines VGLL are configured to provide a first power signal. The first clock signal line CK1L is configured to provide a first clock signal. The second clock signal line CK2L is configured to provide a second clock signal. The one or more select signal lines MSL are configured to provide a select signal.

[0126] In some embodiments, one or more select signal lines MSL include a first select signal line and a second select signal line. In some embodiments, the scanning circuit includes a multi-level cascaded scanning unit. Optionally, the multi-level cascaded scanning unit is configured to provide multiple control signals (e.g., gate scan signals, reset control signals, or emission control signals) to multiple rows of sub-pixels. In some embodiments, the multi-level cascaded scanning unit is arranged in multiple rows. In some embodiments, the multi-level cascaded scanning unit includes M-level scanning units, including a (2m-1)th level scanning unit and a (2m)th level scanning unit, where M and m are positive integers, 1 ≤ m ≤ M / 2. As used herein, the terms "(2m-1)th level" and "(2m)th level" are used in the case of M levels. The scanning circuit may or may not include additional levels(s) preceding the first level in the M levels and / or additional levels following the last level in the M levels. In the case of the scanning circuit, the term "(2m-1)th level" does not necessarily refer to an odd-numbered level, and the term "(2m)th level" does not necessarily refer to an even-numbered level. In one example, the (2m-1)th stage is an odd number of stages in the case of M stages, but can be an even number of stages in the case of a scanning circuit. In another example, the (2m-1)th stage is an odd number of stages in the case of M stages, and is also an odd number of stages in the case of a scanning circuit. In one example, the (2m)th stage is an even number of stages in the case of M stages, but can be an odd number of stages in the case of a scanning circuit. In another example, the (2m)th stage is an even number of stages in the case of M stages, and is also an even number of stages in the case of a scanning circuit.

[0127] In some embodiments, a first selection signal line is configured to provide a selection signal to a (2m-1)th level scan unit, and a second selection signal line is configured to provide a selection signal to a (2m-1)th level scan unit. The inventors of this disclosure have found that by having this structure, the load on the scan circuit can be reduced. Optionally, the first selection signal line is configured not to provide a selection signal to the (2m-1)th level scan unit; and the second selection signal line is configured not to provide a selection signal to the (2m-1)th level scan unit.

[0128] In some embodiments, the first node connection line Cln1 located in the first signal line layer SD1, the second node connection line Cln2 located in the third conductive layer CT3, and the third node connection line Cln3 located in the first signal line layer SD1 connect the first electrode Ss3 of the third selection transistor Ts3 to the second electrode D7 of the seventh transistor T7, the first electrode S8 of the eighth transistor T8, the second electrode D1 of the first transistor T1, and the gate G2 of the second transistor T2. The first node connection line Cln1 located in the first signal line layer SD1 connects the first electrode Ss3 of the third selection transistor Ts3 to the second node connection line Cln2 located in the third conductive layer CT3. The second node connection line Cln2 located in the third conductive layer CT3 connects to the third node connection line Cln3 located in the first signal line layer SD1. The third node connection line Cln3 located in the first signal line layer SD1 connects to the second electrode D7 of the seventh transistor T7, the first electrode S8 of the eighth transistor T8, the second electrode D1 of the first transistor T1, and the gate G2 of the second transistor T2.

[0129] In some embodiments, the input signal line ISL is connected to the first electrode S1 of the first transistor T1 and is configured to provide input to the first electrode S1 of the first transistor T1. In one example, the input may be a start signal provided by one or more start signal lines. In another example, the input may be a carry signal provided by the second output of the previous or next stage scan circuit.

[0130] In some embodiments, the first output signal line OSL1 is connected to the second electrode D4 of the fourth transistor T4 and to the second electrode D5 of the fifth transistor T5. The first output signal line OSL1 is configured to transmit a carry signal output from the second electrode D4 of the fourth transistor T4 and / or the second electrode D5 of the fifth transistor T5.

[0131] In some embodiments, the voltage connection line Clv is connected to one of one or more second power lines VGHL, the first electrode S4 of the fourth transistor T4, and the first electrode S6 of the sixth transistor T6. The voltage connection line Clv is configured to provide a second power signal from one of the one or more second power lines VGHL to the first electrode S4 of the fourth transistor T4 and the first electrode S6 of the sixth transistor T6.

[0132] In some embodiments, the first connection line Cl1 connects the first electrode S2 of the second transistor T2 to the first clock signal line CLK1L.

[0133] In some embodiments, the second connection line Cl2 is connected to the third connection line Cl3, connected to the gate G7 of the seventh transistor T7, and connected to the first electrode S5 of the fifth transistor T5.

[0134] In some embodiments, the third connection line Cl3 is connected to the second connection line Cl2 and to the second clock signal line CLK2L.

[0135] In some embodiments, one or more start signal lines include a first start signal line GSTV, a second start signal line ESTV, a third start signal line RPSTV, a fourth start signal line RHSTV, and a fifth start signal line GNSTV. In some embodiments, the display panel includes multiple scanning circuits, such as a first scanning circuit, a second scanning circuit, a third scanning circuit, a fourth scanning circuit, and a fifth scanning circuit. Examples of scanning circuits include a light emission control signal generation circuit configured to generate light emission control signals for sub-pixels in the array substrate, a reset control signal generation circuit configured to generate reset control signals for sub-pixels in the array substrate, and a gate scan signal generation circuit configured to generate gate scan signals for sub-pixels in the array substrate. In some embodiments, each of the multiple scanning circuits includes a multi-stage cascaded scanning unit. Optionally, the multi-stage cascaded scanning unit is configured to provide multiple control signals (e.g., gate scan signals, reset control signals, or light emission control signals) to multiple rows of sub-pixels.

[0136] In some embodiments, the first start signal line GSTV is configured to provide a start signal to the first scan circuit; the second start signal line ESTV is configured to provide a start signal to the second scan circuit; the third start signal line RPSTV is configured to provide a start signal to the third scan circuit; the fourth start signal line RHSTV is configured to provide a start signal to the fourth scan circuit; and the fifth start signal line GNSTV is configured to provide a start signal to the fifth scan circuit.

[0137] In some embodiments, the first start signal line GSTV, the second start signal line ESTV, the third start signal line RPSTV, the fourth start signal line RHSTV, and the fifth start signal line GNSTV are located on the same layer, for example, on the second signal line layer.

[0138] In some embodiments, the orthographic projection of the first start signal line GSTV on the substrate at least partially overlaps with the orthographic projection of at least one layer of the first scanning circuit (e.g., a semiconductor material layer, a first conductive layer, a second conductive layer, a third conductive layer, or a first signal line layer) on the substrate; the orthographic projection of the second start signal line ESTV on the substrate at least partially overlaps with the orthographic projection of at least one layer of the first scanning circuit (e.g., a semiconductor material layer, a first conductive layer, a second conductive layer, a third conductive layer, or a first signal line layer) on the substrate; the orthographic projection of the third start signal line RPSTV on the substrate overlaps with the orthographic projection of at least one layer of the first scanning circuit (e.g., a semiconductor material layer, a first conductive layer, a second conductive layer, a third conductive layer, or a first signal line layer) on the substrate. The orthographic projections of the material layer, the first conductive layer, the second conductive layer, the third conductive layer, or the first signal line layer on the substrate at least partially overlap; the orthographic projection of the fourth start signal line RHSTV on the substrate at least partially overlaps with the orthographic projection of at least one layer of the first scan circuit (e.g., a semiconductor material layer, the first conductive layer, the second conductive layer, the third conductive layer, or the first signal line layer) on the substrate at least partially overlap; and the orthographic projection of the fifth start signal line GNSTV on the substrate at least partially overlaps with the orthographic projection of at least one layer of the first scan circuit (e.g., a semiconductor material layer, the first conductive layer, the second conductive layer, the third conductive layer, or the first signal line layer) on the substrate at least partially overlap. The inventors of this disclosure have found that by having this structure, the display panel can have a further reduced bezel area. In some embodiments, the second start signal line ESTV, the third start signal line RPSTV, the fourth start signal line RHSTV, and the fifth start signal line GNSTV are connected to corresponding scan circuits on top of the array substrate.

[0139] Various alternative scanning circuits can be used in this disclosure. FIG. 10 This is a circuit diagram of a corresponding scanning unit of a scanning circuit according to some embodiments of this disclosure. (See reference...) FIG. 10 In some embodiments, each scanning unit includes an input sub-circuit ISC, a first output sub-circuit OSC1, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, a third processing sub-circuit PSC3, a first stabilizing sub-circuit SSC1, a second stabilizing sub-circuit SSC2, and a second output sub-circuit OSC2. Each scanning unit can be configured to send control signals to one or more rows of sub-pixels. In one example, each scanning unit is configured to send control signals to a single row of sub-pixels. In another example, each scanning unit is configured to send control signals to two or more rows of sub-pixels.

[0140] In some embodiments, the first output sub-circuit OSC1 is configured to provide a second power supply signal VGH or a first power supply signal VGL to the first output terminal OUT1 in response to the voltage of the fourth node N4 and / or the seventh node N7. Optionally, the first output sub-circuit OSC1 includes a ninth transistor T9 and a tenth transistor T10.

[0141] The ninth transistor T9 is coupled between the second power supply signal VGH and the first output terminal OUT1. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the first output terminal OUT1, and this voltage ( FIG. 10 The signal marked as Outc can be transmitted to the nth gate line and used as a gate drive signal with a gate on level.

[0142] The tenth transistor T10 is coupled between the first output terminal OUT1 and the first power supply signal VGL. The gate of the tenth transistor T10 is coupled to the seventh node N7. Because the twelfth transistor T12 is always on, the seventh node N7 is coupled to the first node N1, therefore the gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off depending on the voltage of the first node N1. Optionally, when the tenth transistor T10 is on, the voltage of the first power supply signal VGL is provided to the first output terminal OUT1, which (in FIG. 10 The signal marked Outc can be provided to the nth gate line and used as a gate drive signal with a gate cutoff level. In one example, when the gate drive signal has a gate cutoff level, it can be understood that no gate drive signal is provided.

[0143] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1 and a fourteenth transistor T14.

[0144] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK1 is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 and the first node N1.

[0145] The fourteenth transistor T14 is coupled between the first input terminal TM1 and the eighth node N8. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the effective voltage of the first clock signal CK1 is provided to the second input terminal TM2, the fourteenth transistor T14 is turned on to electrically couple the first input terminal TM1 and the eighth node N8.

[0146] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0147] The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 can be turned on or off according to the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH can be provided to the fourth node N4.

[0148] The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0149] In some embodiments, the second processing sub-circuit PSC2 is coupled to the fifth node N5 and configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0150] The first terminal of the first capacitor C1 is coupled to the fifth node N5, and the second terminal of the first capacitor C1 is coupled to the third node N3, which is the common node between the sixth transistor T6 and the seventh transistor T7.

[0151] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5, so that the voltage corresponding to the second clock signal CK2 provided to the third input terminal TM3 can be applied to the third node N3.

[0152] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the effective voltage of the second clock signal CK2 provided to the third input terminal TM3. When the seventh transistor T7 and the eighth transistor T8 are turned on, the voltage of the second power supply signal VGH is transmitted to the third node N3 through the eighth transistor T8 and the seventh transistor T7.

[0153] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0154] The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. The gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0155] The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. The first electrode of the fourth transistor T4 is configured to be supplied with a second clock signal CK2 to the third input terminal TM3. The gate of the fourth transistor T4 is coupled to the gate of the sixteenth transistor T16. The second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.

[0156] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the first node N1.

[0157] The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the effective voltage of the first clock signal CK1 is provided to the second input terminal TM2, the third transistor T3 can be turned on, so that the voltage of the first power supply signal VGL can be provided to the second node N2.

[0158] The third capacitor C3 is coupled between the sixteenth transistor T16 and the fourth transistor T4. The first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the first electrode of the fourth transistor T4. The second capacitor electrode of the third capacitor C3 is coupled to the gate of the fourth transistor T4 and the gate of the sixteenth transistor T16.

[0159] In some embodiments, a first stabilizing subcircuit SSC1 is coupled between a second processing subcircuit PSC2 and a third processing subcircuit PSC3. Optionally, the first stabilizing subcircuit SSC1 is configured to limit the voltage drop width of the second node N2. Optionally, the first stabilizing subcircuit SSC1 includes an eleventh transistor T11.

[0160] Eleventh transistor T11 is coupled between second node N2 and fifth node N5. The gate of eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate on-level voltage, eleventh transistor T11 can always remain on. Therefore, second node N2 and fifth node N5 can maintain the same voltage and operate as substantially the same node.

[0161] In some embodiments, the second stabilizing sub-circuit SSC2 is coupled between the first node N1 and the first output sub-circuit OSC1. Optionally, the second stabilizing sub-circuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second stabilizing sub-circuit SSC2 includes a twelfth transistor T12, a fifteenth transistor T15, and a sixteenth transistor T16.

[0162] The twelfth transistor T12 is coupled between the first node N1 and the gate (seventh node N7) of the tenth transistor T10. The gate of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate on-level voltage, the twelfth transistor T12 can always remain on. Therefore, the gates of the first node N1 and the tenth transistor T10 can be maintained at the same voltage.

[0163] The fifteenth transistor T15 is coupled between the eighth node N8 and the second output sub-circuit OSC2. The gate of the fifteenth transistor T15 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate on-level voltage, the fifteenth transistor T15 can always remain on. Therefore, the eighth node N8 is electrically connected to the second output sub-circuit OSC2.

[0164] The sixteenth transistor T16 is coupled between the gate (seventh node N7) of the tenth transistor T10 and the second output sub-circuit OSC2. The gate of the sixteenth transistor T16 is coupled to the ninth node N9, which is coupled to the second capacitor electrode of the third capacitor C3.

[0165] In some embodiments, the second output sub-circuit OSC2 is coupled between the first node N1 and the fourth node N4. Optionally, the second output sub-circuit OSC2 is configured to provide a first power supply signal VGL or a selection signal MS to the second output terminal OUT2 in response to the voltage of the fourth node N4 and / or the first node N1. Optionally, the second output sub-circuit OSC2 includes a first selection transistor ST1, a second selection transistor ST2, a third selection transistor ST3, and a selection capacitor SC.

[0166] The first selection transistor ST1 is coupled between the second output terminal OUT2 and the fourth node N4. The gate of the first selection transistor ST1 is coupled to the fourth node N4. The first electrode of the first selection transistor ST1 is coupled to the selection signal MS. The second electrode of the first selection transistor ST1 is coupled to the second output terminal OUT2.

[0167] The second selection transistor ST2 is coupled between the second output terminal OUT2 and the first node N1. The gate of the second selection transistor ST2 is coupled to the first node N1. The first electrode of the second selection transistor ST2 is coupled to the first power supply signal VGL. The second electrode of the second selection transistor ST2 is coupled to the second output terminal OUT2.

[0168] The third selection transistor ST3 is coupled between the first node N1 and the second stable sub-circuit SSC2. The gate and first electrode of the third selection transistor ST3 are coupled to the gate and second electrode of the sixteenth transistor T16, and to the second electrode of the fourteenth transistor T14. The second electrode of the third selection transistor ST3 is coupled to the gate of the second selection transistor ST2 and the first node N1.

[0169] The first capacitor electrode of the selection capacitor SC is coupled to the gate of the first selection transistor ST1 and the fourth node N4. The second capacitor electrode of the selection capacitor SC is coupled to the first electrode of the first selection transistor ST1 and the selection signal MS.

[0170] In some embodiments, reference FIG. 10 Each of the first transistor T1 to the sixteenth transistor T16, the first selection transistor ST1, the second selection transistor ST2, and the third selection transistor ST3 can be formed by an n-type transistor. In some embodiments, the gate on-state voltage of the first transistor T1 to the sixteenth transistor T16, the first selection transistor ST1, the second selection transistor ST2, and the third selection transistor ST3 can be set to a high level, and their gate off-state voltage can be set to a low level.

[0171] In an alternative embodiment, each of the first transistor T1 to the sixteenth transistor T16, the first selection transistor ST1, the second selection transistor ST2, and the third selection transistor ST3 may be formed of a p-type transistor. In some embodiments, the gate on-state voltage of the first transistor T1 to the sixteenth transistor T16, the first selection transistor ST1, the second selection transistor ST2, and the third selection transistor ST3 may be set to a low level, and their gate off-state voltage may be set to a high level.

[0172] FIG. 11 It is shown FIG. 10 The timing diagram shown illustrates the operation of the corresponding scanning unit in the first mode. (Refer to...) FIG. 10 and FIG. 11 In some embodiments, the operation of each scanning unit includes a first time period p1, a second time period p2, a third time period p3, a fourth time period p4, and a fifth time period p5.

[0173] In some embodiments, during the first time period p1, the first clock signal CK1 is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on. Furthermore, during the first time period p1, the second clock signal CK2 is not provided to the third input terminal TM3, and the seventh transistor T7 is turned off.

[0174] In some embodiments, during the first time period p1, the start signal STV to be provided to the first input terminal TM1 or the output signal Outp from the output terminal of the previous scan unit is at a low level, and a low voltage (e.g., the voltage of the first power supply signal VGL) can be applied to the first node N1. When the first node N1 is set to a low voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned on.

[0175] In some embodiments, when the second transistor T2 is turned on, the voltage of the first clock signal CK1 is provided to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0176] In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is supplied to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0177] In some embodiments, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH is provided to the fourth node N4. The ninth transistor T9 is turned off.

[0178] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to the scan unit in different stages of the scan circuit. In some embodiments, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is provided to the first output terminal OUT1.

[0179] During the first time period p1, the first selection transistor ST1 is off, and the second selection transistor ST2 is on. The second output sub-circuit OSC2, under the control of the potential of the first node N1, outputs VGL to the second output terminal OUT2, thus outputting a low level through OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal, and it is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0180] In some embodiments, during the second time period p2, the first clock signal CK1 is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are off. The first node N1 maintains the voltage of the previous time period. Since the first node N1 remains in a low voltage state, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 remain on. When the eighth transistor T8 remains on, the voltage of the second power supply signal VGH is provided to the fourth node N4. Since the fourth node N4 remains in a high voltage state, the ninth transistor T9 remains off.

[0181] In some embodiments, during the second time period p2, the second clock signal CK2 is not provided to the third input terminal TM3. The seventh transistor T7 is turned on. When the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. The third node N3 is set to a high voltage.

[0182] During the second time period p2, the first selection transistor ST1 is off, and the second selection transistor ST2 is on. The second output sub-circuit OSC2, under the control of the potential of the first node N1, outputs VGL to the second output terminal OUT2, thus outputting a low level through OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal, and it is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0183] In some embodiments, during the third time period p3, the second clock signal CK2 is provided to the third input terminal TM3. When the second clock signal CK2 is provided to the third input terminal TM3, the seventh transistor T7 is turned off.

[0184] In some embodiments, during the third time period p3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is provided to the first input terminal TM1, and the first clock signal CK1 is not provided to the second input terminal TM2. When the first clock signal CK1 is not provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on.

[0185] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 is electrically coupled to the first node N1. The first node N1 is set to a high voltage by a start signal STV provided to the first input terminal TM1 or an output signal Outp from the output terminal of the previous scan unit. When the first node N1 is set to a high voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0186] In some embodiments, when the sixth transistor T6 is turned on, the third input terminal TM3 is electrically coupled to the third node N3. Since the second clock signal CK2 is provided to the third input terminal TM3 during the third time period p3, the third node N3 remains at a high voltage. Since the seventh transistor T7 remains off, the voltage of the third node N3 does not affect the voltage of the fourth node N4. The first capacitor C1 is configured to store the voltage corresponding to the on-level of the sixth transistor T6.

[0187] During the third time period p3, the first selection transistor ST1 is turned off, and the second selection transistor ST2 is turned off. The second output sub-circuit OSC2 does not output a signal through the second output terminal OUT2. FIG. 2A The second transistor T2 in each pixel driving circuit described herein remains off.

[0188] In some embodiments, during the fourth time period p4, the second clock signal CK2 is not provided to the third input terminal TM3. When the second clock signal CK2 is not provided to the third input terminal TM3, the seventh transistor T7 is turned on.

[0189] In some embodiments, when the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. A low voltage of the second clock signal CK2 at the third input terminal TM3 is provided to the third node N3 and the fourth node N4 via the sixth transistor T6, which remains on. When the low voltage is provided to the fourth node N4, the ninth transistor T9 is turned on.

[0190] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to scan units in different stages of the scan circuit. In some embodiments, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the first output terminal OUT1. The voltage of the second power supply signal VGH provided to the first output terminal OUT1 is used as a carry signal.

[0191] During the fourth time period p4, the first selection transistor ST1 is turned on, and the second selection transistor ST2 is turned off. Under the control of the potential at the fourth node N4, the second output sub-circuit OSC2 outputs the selection signal MS to the second output terminal OUT2, thus outputting a high level through OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal, and it is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A high level output from the second output terminal OUT2 (e.g., the high-level portion of the AC signal of the selection signal MS) is turned on. FIG. 2A The second transistor T2 in each pixel driving circuit shown.

[0192] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to scan units in different stages of the scan circuit. In some embodiments, during the fifth time period p5, the second clock signal CK2 is provided to the third input terminal TM3. When the second clock signal CK2 is provided to the third input terminal TM3, the seventh transistor T7 is turned off. The fourth node N4 is stably maintained at a low voltage through the second capacitor C2.

[0193] The ninth transistor T9 remains on, and the voltage of the second power supply signal VGH is provided as a carry signal.

[0194] During the fifth period p5, a second clock signal CK2 is provided, which keeps the seventh transistor T7 off, and therefore the voltage of the second clock signal CK2 does not affect the voltage of the fourth node N4.

[0195] During the fifth time period p5, the fourth node N4 maintains the low voltage level of the previous time period, the ninth transistor T9 and the first selection transistor ST1 are turned on, and the second selection transistor ST2 is turned off. Under the control of the potential of the fourth node N4, the second output sub-circuit OSC2 outputs the selection signal MS to the second output terminal OUT2, thereby outputting a high level through the second output terminal OUT2.

[0196] During the fifth time period p5, the first clock signal CK1 is not provided to the second input terminal TM2, and the first transistor T1 and the fourteenth transistor T14 are turned on. The high voltage signal from the first terminal TM1 is transmitted to the first node N1 and the eighth node N8 through the first transistor T1 and the fourteenth transistor T14, respectively. The high voltage signal is transmitted to the seventh node N7 and the ninth node N9 through the twelfth transistor T12 and the fifteenth transistor T15, respectively. The tenth transistor T10, the sixteenth transistor T16, the third selection transistor ST3, and the second selection transistor ST2 are turned off.

[0197] FIG. 12 It is shown FIG. 10 The timing diagram shows the operation of the corresponding scanning unit in the second mode. (Refer to...) FIG. 10 and FIG. 12 In some embodiments, the operation of each scanning unit includes a first time period p1, a second time period p2, a third time period p3, a fourth time period p4, and a fifth time period p5.

[0198] In some embodiments, during the first time period p1, the first clock signal CK1 is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on. Furthermore, during the first time period p1, the second clock signal CK2 is not provided to the third input terminal TM3, and the seventh transistor T7 is turned off.

[0199] In some embodiments, during the first time period p1, the start signal STV to be provided to the first input terminal TM1 or the output signal Outp from the output terminal of the previous scan unit is at a low level, and a low voltage (e.g., the voltage of the first power supply signal VGL) can be applied to the first node N1. When the first node N1 is set to a low voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned on.

[0200] In some embodiments, when the second transistor T2 is turned on, the voltage of the first clock signal CK1 is provided to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0201] In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is supplied to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0202] In some embodiments, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH is provided to the fourth node N4. The ninth transistor T9 is turned off.

[0203] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to the scan unit in different stages of the scan circuit. In some embodiments, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is provided to the first output terminal OUT1.

[0204] During the first time period p1, the first selection transistor ST1 is off, and the second selection transistor ST2 is on. The second output sub-circuit OSC2, under the control of the potential of the first node N1, outputs VGL to the second output terminal OUT2, thus outputting a low level through OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal, and it is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0205] In some embodiments, during the second time period p2, the first clock signal CK1 is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are off. The first node N1 maintains the voltage of the previous time period. Since the first node N1 remains in a low voltage state, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 remain on. When the eighth transistor T8 remains on, the voltage of the second power supply signal VGH is provided to the fourth node N4. Since the fourth node N4 remains in a high voltage state, the ninth transistor T9 remains off.

[0206] In some embodiments, during the second time period p2, the second clock signal CK2 is not provided to the third input terminal TM3. The seventh transistor T7 is turned on. When the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. The third node N3 is set to a high voltage.

[0207] During the second time period p2, both the first selection transistor ST1 and the second selection transistor ST2 are turned off. The second output sub-circuit OSC2, controlled by the potential of the first node N1, outputs VGL to the second output terminal OUT2, thus outputting a low level through OUT2. The signal output from OUT2 serves as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0208] In some embodiments, during the third time period p3, the second clock signal CK2 is provided to the third input terminal TM3. When the second clock signal CK2 is provided to the third input terminal TM3, the seventh transistor T7 is turned off.

[0209] In some embodiments, during the third time period p3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is provided to the first input terminal TM1, and the first clock signal CK1 is not provided to the second input terminal TM2. When the first clock signal CK1 is not provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on.

[0210] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 is electrically coupled to the first node N1. The first node N1 is set to a high voltage by a start signal STV provided to the first input terminal TM1 or an output signal Outp from the output terminal of the previous scan unit. When the first node N1 is set to a high voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0211] In some embodiments, when the sixth transistor T6 is turned on, the third input terminal TM3 is electrically coupled to the third node N3. Since the second clock signal CK2 is provided to the third input terminal TM3 during the third time period p3, the third node N3 remains at a high voltage. Since the seventh transistor T7 remains off, the voltage of the third node N3 does not affect the voltage of the fourth node N4. The first capacitor C1 is configured to store the voltage corresponding to the on-level of the sixth transistor T6.

[0212] During the third time period p3, the first selection transistor ST1 is turned off, and the second selection transistor ST2 is turned off. The second output sub-circuit OSC2 does not output a signal through the second output terminal OUT2. FIG. 2A The second transistor T2 in each pixel driving circuit described herein remains off.

[0213] In some embodiments, during the fourth time period p4, the second clock signal CK2 is not provided to the third input terminal TM3. When the second clock signal CK2 is not provided to the third input terminal TM3, the seventh transistor T7 is turned on.

[0214] In some embodiments, when the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. A low voltage of the second clock signal CK2 at the third input terminal TM3 is provided to the third node N3 and the fourth node N4 via the sixth transistor T6, which remains on. When the low voltage is provided to the fourth node N4, the ninth transistor T9 is turned on.

[0215] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to scan units in different stages of the scan circuit. In some embodiments, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the first output terminal OUT1. The voltage of the second power supply signal VGH provided to the first output terminal OUT1 is used as a carry signal.

[0216] During the fourth time period p4, the first selection transistor ST1 is turned on, and the second selection transistor ST2 is turned off. The second output sub-circuit OSC2, under the control of the potential at the fourth node N4, outputs the selection signal MS to the second output terminal OUT2. In the second mode, the selection signal MS is low during the fourth time period p4. Therefore, the second output sub-circuit OSC2 outputs a low level through the second output terminal OUT2 during the fourth time period p4. This differs from the first mode. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in each pixel driving circuit shown.

[0217] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to scan units in different stages of the scan circuit. In some embodiments, during the fifth time period p5, the second clock signal CK2 is provided to the third input terminal TM3. When the second clock signal CK2 is provided to the third input terminal TM3, the seventh transistor T7 is turned off. The fourth node N4 is stably maintained at a low voltage through the second capacitor C2.

[0218] The ninth transistor T9 remains on, and the voltage of the second power supply signal VGH is provided as a carry signal.

[0219] During the fifth period p5, a second clock signal CK2 is provided, which keeps the fourth transistor T4 off, and therefore the voltage of the second clock signal CK2 does not affect the voltage of the first node N1.

[0220] During the fifth time period p5, the first selection transistor ST1 is turned on, and the second selection transistor ST2 is turned off. The second output sub-circuit OSC2, under the control of the potential of the fourth node N4, outputs the selection signal MS to the second output terminal OUT2. In the second mode, the selection signal MS is low during the fifth time period p5. Therefore, the second output sub-circuit OSC2 outputs a low level through the second output terminal OUT2 during the fifth time period p5. This differs from the first mode. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0221] In some embodiments, the scanning circuit operates alternately in a first mode and a second mode. In the first mode, the selection signal MS is high. In the second mode, the selection signal MS is low for at least one frame of image time. In some embodiments, in the first area, the scanning circuit outputs a valid control signal for the pixel driving circuit only in the first mode and an invalid control signal for the pixel driving circuit in the second mode. The display panel displays the image in a low-frequency mode in the first area. In the second area, the scanning circuit outputs a valid control signal for the pixel driving circuit in both the first and second modes. The display panel displays the image in a high-frequency mode in the second area.

[0222] Various alternative scanning circuits can be used in this disclosure. FIG. 13 This is a circuit diagram of a corresponding scanning unit of a scanning circuit according to some embodiments of this disclosure. (See reference...) FIG. 13 In some embodiments, each scanning unit includes an input sub-circuit ISC, a first output sub-circuit OSC1, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, a third processing sub-circuit PSC3, a first stabilizing sub-circuit SSC1, a second stabilizing sub-circuit SSC2, and a second output sub-circuit OSC2. Each scanning unit can be configured to send control signals to one or more rows of sub-pixels. In one example, each scanning unit is configured to send control signals to a single row of sub-pixels. In another example, each scanning unit is configured to send control signals to two or more rows of sub-pixels.

[0223] In some embodiments, the first output sub-circuit OSC1 is configured to provide a second power supply signal VGH or a first power supply signal VGL to the first output terminal OUT1 in response to the voltage of the fourth node N4 and / or the seventh node N7. Optionally, the first output sub-circuit OSC1 includes a ninth transistor T9 and a tenth transistor T10.

[0224] The ninth transistor T9 is coupled between the second power supply signal VGH and the first output terminal OUT1. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the first output terminal OUT1, and this voltage ( FIG. 13 The signal marked as Outc can be transmitted to the nth gate line and used as a gate drive signal with a gate on level.

[0225] The tenth transistor T10 is coupled between the first output terminal OUT1 and the first power supply signal VGL. The gate of the tenth transistor T10 is coupled to the seventh node N7. Because the twelfth transistor T12 is always on, the seventh node N7 is coupled to the first node N1, therefore the gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off depending on the voltage of the first node N1. Optionally, when the tenth transistor T10 is on, the voltage of the first power supply signal VGL is provided to the first output terminal OUT1, which (in FIG. 13 The signal marked Outc can be provided to the nth gate line and used as a gate drive signal with a gate cutoff level. In one example, when the gate drive signal has a gate cutoff level, it can be understood that no gate drive signal is provided.

[0226] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1 and a fourteenth transistor T14.

[0227] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK1 is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 and the first node N1.

[0228] The fourteenth transistor T14 is coupled between the first input terminal TM1 and the eighth node N8. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the effective voltage of the first clock signal CK1 is provided to the second input terminal TM2, the fourteenth transistor T14 is turned on to electrically couple the first input terminal TM1 and the eighth node N8.

[0229] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0230] The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 can be turned on or off according to the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH can be provided to the fourth node N4.

[0231] The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0232] In some embodiments, the second processing sub-circuit PSC2 is coupled to the fifth node N5 and configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0233] The first terminal of the first capacitor C1 is coupled to the fifth node N5, and the second terminal of the first capacitor C1 is coupled to the third node N3, which is the common node between the sixth transistor T6 and the seventh transistor T7.

[0234] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5, so that the voltage corresponding to the second clock signal CK2 provided to the third input terminal TM3 can be applied to the third node N3.

[0235] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the effective voltage of the second clock signal CK2 provided to the third input terminal TM3. When the seventh transistor T7 and the eighth transistor T8 are turned on, the voltage of the second power supply signal VGH is transmitted to the third node N3 through the eighth transistor T8 and the seventh transistor T7.

[0236] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0237] The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. The gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0238] The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. The first electrode of the fourth transistor T4 is configured to be supplied with a second clock signal CK2 to the third input terminal TM3. The gate of the fourth transistor T4 is coupled to the gate of the sixteenth transistor T16. The second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.

[0239] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the first node N1.

[0240] The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the effective voltage of the first clock signal CK1 is provided to the second input terminal TM2, the third transistor T3 can be turned on, so that the voltage of the first power supply signal VGL can be provided to the second node N2.

[0241] The third capacitor C3 is coupled between the sixteenth transistor T16 and the fourth transistor T4. The first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the first electrode of the fourth transistor T4. The second capacitor electrode of the third capacitor C3 is coupled to the gate of the fourth transistor T4 and the gate of the sixteenth transistor T16.

[0242] In some embodiments, a first stabilizing subcircuit SSC1 is coupled between a second processing subcircuit PSC2 and a third processing subcircuit PSC3. Optionally, the first stabilizing subcircuit SSC1 is configured to limit the voltage drop width of the second node N2. Optionally, the first stabilizing subcircuit SSC1 includes an eleventh transistor T11.

[0243] Eleventh transistor T11 is coupled between second node N2 and fifth node N5. The gate of eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate on-level voltage, eleventh transistor T11 can always remain on. Therefore, second node N2 and fifth node N5 can maintain the same voltage and operate as substantially the same node.

[0244] In some embodiments, the second stabilizing sub-circuit SSC2 is coupled between the first node N1 and the first output sub-circuit OSC1. Optionally, the second stabilizing sub-circuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second stabilizing sub-circuit SSC2 includes a twelfth transistor T12, a fifteenth transistor T15, and a sixteenth transistor T16.

[0245] The twelfth transistor T12 is coupled between the first node N1 and the gate (seventh node N7) of the tenth transistor T10. The gate of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate on-level voltage, the twelfth transistor T12 can always remain on. Therefore, the gates of the first node N1 and the tenth transistor T10 can be maintained at the same voltage.

[0246] The fifteenth transistor T15 is coupled between the eighth node N8 and the second output sub-circuit OSC2. The gate of the fifteenth transistor T15 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate on-level voltage, the fifteenth transistor T15 can always remain on. Therefore, the eighth node N8 is electrically connected to the second output sub-circuit OSC2.

[0247] The sixteenth transistor T16 is coupled between the gate (seventh node N7) of the tenth transistor T10 and the second output sub-circuit OSC2. The gate of the sixteenth transistor T16 is coupled to the ninth node N9, which is coupled to the second capacitor electrode of the third capacitor C3.

[0248] In some embodiments, the second output sub-circuit OSC2 is coupled between the eighth node N8 and the fourth node N4. Optionally, the second output sub-circuit OSC2 is configured to provide a first power supply signal VGL or a selection signal MS voltage to the second output terminal OUT2 in response to the voltage of the fourth node N4 and / or the eighth node N8. Optionally, the second output sub-circuit OSC2 includes a first selection transistor ST1, a second selection transistor ST2, a third selection transistor ST3, and a selection capacitor SC.

[0249] The first selection transistor ST1 is coupled between the second output terminal OUT2 and the fourth node N4. The gate of the first selection transistor ST1 is coupled to the fourth node N4. The first electrode of the first selection transistor ST1 is coupled to the selection signal MS. The second electrode of the first selection transistor ST1 is coupled to the second output terminal OUT2.

[0250] The second selection transistor ST2 is coupled between the second output terminal OUT2 and the eighth node N8. The gate of the second selection transistor ST2 is coupled to the eighth node N8. The first electrode of the second selection transistor ST2 is coupled to the first power supply signal VGL. The second electrode of the second selection transistor ST2 is coupled to the second output terminal OUT2.

[0251] The third selection transistor ST3 is coupled between the eighth node N8 and the second stable sub-circuit SSC2. The gate and first electrode of the third selection transistor ST3 are coupled to the gate and second electrode of the sixteenth transistor T16, and to the second electrode of the fourteenth transistor T14. The second electrode of the third selection transistor ST3 is coupled to the gate of the second selection transistor ST2 and the eighth node N8.

[0252] The first capacitor electrode of the selection capacitor SC is coupled to the gate of the first selection transistor ST1 and the fourth node N4. The second capacitor electrode of the selection capacitor SC is coupled to the first electrode of the first selection transistor ST1 and the selection signal MS.

[0253] In some embodiments, reference FIG. 13 Each of the first transistor T1 to the sixteenth transistor T16, the first selection transistor ST1, the second selection transistor ST2, and the third selection transistor ST3 can be formed by an n-type transistor. In some embodiments, the gate on-state voltage of the first transistor T1 to the sixteenth transistor T16, the first selection transistor ST1, the second selection transistor ST2, and the third selection transistor ST3 can be set to a high level, and their gate off-state voltage can be set to a low level.

[0254] In an alternative embodiment, each of the first transistor T1 to the sixteenth transistor T16, the first selection transistor ST1, the second selection transistor ST2, and the third selection transistor ST3 may be formed of a p-type transistor. In some embodiments, the gate on-state voltage of the first transistor T1 to the sixteenth transistor T16, the first selection transistor ST1, the second selection transistor ST2, and the third selection transistor ST3 may be set to a low level, and their gate off-state voltage may be set to a high level.

[0255] FIG. 14 It is shown FIG. 13 The timing diagram shown illustrates the operation of the corresponding scanning unit in the first mode. (Refer to...) FIG. 13 and FIG. 14 In some embodiments, the operation of each scanning unit includes a first time period p1, a second time period p2, a third time period p3, a fourth time period p4, and a fifth time period p5.

[0256] In some embodiments, during the first time period p1, the first clock signal CK1 is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on. Furthermore, during the first time period p1, the second clock signal CK2 is not provided to the third input terminal TM3, and the fourth transistor T4 and the seventh transistor T7 are turned off.

[0257] In some embodiments, during the first time period p1, the start signal STV to be provided to the first input terminal TM1 or the output signal Outp from the output terminal of the previous scan unit is at a low level, and a low voltage (e.g., the voltage of the first power supply signal VGL) can be applied to the first node N1. When the first node N1 is set to a low voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned on.

[0258] In some embodiments, when the second transistor T2 is turned on, the voltage of the first clock signal CK1 is provided to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0259] In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is supplied to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0260] In some embodiments, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH is provided to the fourth node N4. The ninth transistor T9 is turned off.

[0261] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to the scan unit in different stages of the scan circuit. In some embodiments, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is provided to the first output terminal OUT1.

[0262] During the first time period p1, the first selection transistor ST1 is off, and the second selection transistor ST2 is on. The second output sub-circuit OSC2, under the control of the potential at the eighth node N8, outputs VGL to the second output terminal OUT2, thus outputting a low level through OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal, and it is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0263] In some embodiments, during the second time period p2, the first clock signal CK1 is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are off. The first node N1 maintains the voltage of the previous time period. Since the first node N1 remains in a low voltage state, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 remain on. When the eighth transistor T8 remains on, the voltage of the second power supply signal VGH is provided to the fourth node N4. Since the fourth node N4 remains in a high voltage state, the ninth transistor T9 remains off.

[0264] In some embodiments, during the second time period p2, the second clock signal CK2 is not provided to the third input terminal TM3. The seventh transistor T7 is turned on. When the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. The third node N3 is set to a high voltage.

[0265] During the second time period p2, the first selection transistor ST1 is turned on, and the second selection transistor ST2 is turned off. The second output sub-circuit OSC2, under the control of the potential at the eighth node N8, outputs VGL to the second output terminal OUT2, thus outputting a low level through OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0266] In some embodiments, during the third time period p3, the second clock signal CK2 is provided to the third input terminal TM3. When the second clock signal CK2 is provided to the third input terminal TM3, the seventh transistor T7 is turned off.

[0267] In some embodiments, during the third time period p3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is provided to the first input terminal TM1, and the first clock signal CK1 is not provided to the second input terminal TM2. When the first clock signal CK1 is not provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on.

[0268] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 is electrically coupled to the first node N1. The first node N1 is set to a high voltage by a start signal STV provided to the first input terminal TM1 or an output signal Outp from the output terminal of the previous scan unit. When the first node N1 is set to a high voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0269] In some embodiments, when the sixth transistor T6 is turned on, the third input terminal TM3 is electrically coupled to the third node N3. Since the second clock signal CK2 is provided to the third input terminal TM3 during the third time period p3, the third node N3 remains at a high voltage. Since the seventh transistor T7 remains off, the voltage of the third node N3 does not affect the voltage of the fourth node N4. The first capacitor C1 is configured to store the voltage corresponding to the on-level of the sixth transistor T6.

[0270] During the third time period p3, the first selection transistor ST1 is turned off, and the second selection transistor ST2 is turned off. The second output sub-circuit OSC2 does not output a signal through the second output terminal OUT2. FIG. 2A The second transistor T2 in each pixel driving circuit described herein remains off.

[0271] In some embodiments, during the fourth time period p4, the second clock signal CK2 is not provided to the third input terminal TM3. When the second clock signal CK2 is not provided to the third input terminal TM3, the seventh transistor T7 is turned on.

[0272] In some embodiments, when the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. A low voltage of the second clock signal CK2 at the third input terminal TM3 is provided to the third node N3 and the fourth node N4 via the sixth transistor T6, which remains on. When the low voltage is provided to the fourth node N4, the ninth transistor T9 is turned on.

[0273] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to scan units in different stages of the scan circuit. In some embodiments, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the first output terminal OUT1. The voltage of the second power supply signal VGH provided to the first output terminal OUT1 is used as a carry signal.

[0274] During the fourth time period p4, the first selection transistor ST1 is turned on, and the second selection transistor ST2 is turned off. Under the control of the potential at the fourth node N4, the second output sub-circuit OSC2 outputs the selection signal MS to the second output terminal OUT2, thus outputting a high level through OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal, and it is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A high level output from the second output terminal OUT2 (e.g., the high-level portion of the AC signal of the selection signal MS) is turned on. FIG. 2A The second transistor T2 in each pixel driving circuit shown.

[0275] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to scan units in different stages of the scan circuit. In some embodiments, during the fifth time period p5, the second clock signal CK2 is provided to the third input terminal TM3. When the second clock signal CK2 is provided to the third input terminal TM3, the seventh transistor T7 is turned off. The fourth node N4 is stably maintained at a low voltage through the second capacitor C2.

[0276] The ninth transistor T9 remains on, and the voltage of the second power supply signal VGH is provided as a carry signal.

[0277] During the fifth period p5, a second clock signal CK2 is provided, which keeps the seventh transistor T7 off, and therefore the voltage of the second clock signal CK2 does not affect the voltage of the fourth node N4.

[0278] During the fifth time period p5, the fourth node N4 maintains the low voltage level of the previous time period, the ninth transistor T9 and the first selection transistor ST1 are turned on, and the second selection transistor ST2 is turned off. Under the control of the potential of the fourth node N4, the second output sub-circuit OSC2 outputs the selection signal MS to the second output terminal OUT2, thereby outputting a high level through the second output terminal OUT2.

[0279] During the fifth time period p5, the first clock signal CK1 is not provided to the second input terminal TM2, and the first transistor T1 and the fourteenth transistor T14 are turned on. The high voltage signal from the first terminal TM1 is transmitted to the first node N1 and the eighth node N8 through the first transistor T1 and the fourteenth transistor T14, respectively. The high voltage signal is transmitted to the seventh node N7 and the ninth node N9 through the twelfth transistor T12 and the fifteenth transistor T15, respectively. The tenth transistor T10, the sixteenth transistor T16, the third selection transistor ST3, and the second selection transistor ST2 are turned off.

[0280] FIG. 15 It is shown FIG. 13 The timing diagram shows the operation of the corresponding scanning unit in the second mode. (Refer to...) FIG. 13 and FIG. 15 In some embodiments, the operation of each scanning unit includes a first time period p1, a second time period p2, a third time period p3, a fourth time period p4, and a fifth time period p5.

[0281] In some embodiments, during the first time period p1, the first clock signal CK1 is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on. Furthermore, during the first time period p1, the second clock signal CK2 is not provided to the third input terminal TM3, and the fourth transistor T4 and the seventh transistor T7 are turned off.

[0282] In some embodiments, during the first time period p1, the start signal STV to be provided to the first input terminal TM1 or the output signal Outp from the output terminal of the previous scan unit is at a low level, and a low voltage (e.g., the voltage of the first power supply signal VGL) can be applied to the first node N1. When the first node N1 is set to a low voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned on.

[0283] In some embodiments, when the second transistor T2 is turned on, the voltage of the first clock signal CK1 is provided to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0284] In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is supplied to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0285] In some embodiments, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH is provided to the fourth node N4. The ninth transistor T9 is turned off.

[0286] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to the scan unit in different stages of the scan circuit. In some embodiments, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is provided to the first output terminal OUT1.

[0287] During the first time period p1, the first selection transistor ST1 is off, and the second selection transistor ST2 is on. The second output sub-circuit OSC2, under the control of the potential at the eighth node N8, outputs VGL to the second output terminal OUT2, thus outputting a low level through OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal, and it is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0288] In some embodiments, during the second time period p2, the first clock signal CK1 is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are off. The first node N1 maintains the voltage of the previous time period. Since the first node N1 remains in a low voltage state, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 remain on. When the eighth transistor T8 remains on, the voltage of the second power supply signal VGH is provided to the fourth node N4. Since the fourth node N4 remains in a high voltage state, the ninth transistor T9 remains off.

[0289] In some embodiments, during the second time period p2, the second clock signal CK2 is not provided to the third input terminal TM3. The seventh transistor T7 is turned on. When the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. The third node N3 is set to a high voltage.

[0290] During the second time period p2, the first selection transistor ST1 is off, and the second selection transistor ST2 is off. The second output sub-circuit OSC2, under the control of the potential at the eighth node N8, outputs VGL to the second output terminal OUT2, thus outputting a low level through OUT2. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0291] In some embodiments, during the third time period p3, the second clock signal CK2 is provided to the third input terminal TM3. When the second clock signal CK2 is provided to the third input terminal TM3, the seventh transistor T7 is turned off.

[0292] In some embodiments, during the third time period p3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is provided to the first input terminal TM1, and the first clock signal CK1 is not provided to the second input terminal TM2. When the first clock signal CK1 is not provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on.

[0293] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 is electrically coupled to the first node N1. The first node N1 is set to a high voltage by a start signal STV provided to the first input terminal TM1 or an output signal Outp from the output terminal of the previous scan unit. When the first node N1 is set to a high voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0294] In some embodiments, when the sixth transistor T6 is turned on, the third input terminal TM3 is electrically coupled to the third node N3. Since the second clock signal CK2 is provided to the third input terminal TM3 during the third time period p3, the third node N3 remains at a high voltage. Since the seventh transistor T7 remains off, the voltage of the third node N3 does not affect the voltage of the fourth node N4. The first capacitor C1 is configured to store the voltage corresponding to the on-level of the sixth transistor T6.

[0295] During the third time period p3, the first selection transistor ST1 is turned off, and the second selection transistor ST2 is turned off. The second output sub-circuit OSC2 does not output a signal through the second output terminal OUT2. FIG. 2A The second transistor T2 in each pixel driving circuit described herein remains off.

[0296] In some embodiments, during the fourth time period p4, the second clock signal CK2 is not provided to the third input terminal TM3. When the second clock signal CK2 is not provided to the third input terminal TM3, the seventh transistor T7 is turned on.

[0297] In some embodiments, when the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. A low voltage of the second clock signal CK2 at the third input terminal TM3 is provided to the third node N3 and the fourth node N4 via the sixth transistor T6, which remains on. When the low voltage is provided to the fourth node N4, the ninth transistor T9 is turned on.

[0298] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to scan units in different stages of the scan circuit. In some embodiments, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the first output terminal OUT1. The voltage of the second power supply signal VGH provided to the first output terminal OUT1 is used as a carry signal.

[0299] During the fourth time period p4, the first selection transistor ST1 is turned on, and the second selection transistor ST2 is turned off. The second output sub-circuit OSC2, under the control of the potential at the fourth node N4, outputs the selection signal MS to the second output terminal OUT2. In the second mode, the selection signal MS is low during the fourth time period p4. Therefore, the second output sub-circuit OSC2 outputs a low level through the second output terminal OUT2 during the fourth time period p4. This differs from the first mode. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in each pixel driving circuit shown.

[0300] The signal output from the first output terminal OUT1 is used as a carry signal and can be output to scan units in different stages of the scan circuit. In some embodiments, during the fifth time period p5, the second clock signal CK2 is provided to the third input terminal TM3. When the second clock signal CK2 is provided to the third input terminal TM3, the seventh transistor T7 is turned off. The fourth node N4 is stably maintained at a low voltage through the second capacitor C2.

[0301] The ninth transistor T9 remains on, and the voltage of the second power supply signal VGH is provided as a carry signal.

[0302] During the fifth period p5, a second clock signal CK2 is provided, which keeps the fourth transistor T4 off, and therefore the voltage of the second clock signal CK2 does not affect the voltage of the first node N1.

[0303] During the fifth time period p5, the first selection transistor ST1 is turned on, and the second selection transistor ST2 is turned off. The second output sub-circuit OSC2, under the control of the potential of the fourth node N4, outputs the selection signal MS to the second output terminal OUT2. In the second mode, the selection signal MS is low during the fifth time period p5. Therefore, the second output sub-circuit OSC2 outputs a low level through the second output terminal OUT2 during the fifth time period p5. This differs from the first mode. The signal output from the second output terminal OUT2 is used as a control signal and can be output to one or more pixel driving circuits in the array substrate. In one example, the control signal output from the second output terminal OUT2 is a gate scan signal and is transmitted to... FIG. 2A The gate of the second transistor T2 in the corresponding pixel driving circuit shown. A low level output from the second output terminal OUT2 cuts off. FIG. 2A The second transistor T2 in the corresponding pixel driving circuit shown.

[0304] In some embodiments, the scanning circuit operates alternately in a first mode and a second mode. In the first mode, the selection signal MS is high. In the second mode, the selection signal MS is low for at least one frame of image time. In some embodiments, in the first area, the scanning circuit outputs a valid control signal for the pixel driving circuit only in the first mode and an invalid control signal for the pixel driving circuit in the second mode. The display panel displays the image in a low-frequency mode in the first area. In the second area, the scanning circuit outputs a valid control signal for the pixel driving circuit in both the first and second modes. The display panel displays the image in a high-frequency mode in the second area.

[0305] Reference FIG. 4 to FIG. 7 as well as FIG. 10 to FIG. 15 This disclosure provides a scanning circuit including a plurality of scanning units. In some embodiments, each of the plurality of scanning units includes a first output sub-circuit OSC1 configured to output a carry signal as input to a scanning unit in a different stage; and a second output sub-circuit OSC2 configured to output a control signal configured to drive a pixel driving circuit. In some embodiments, the first output sub-circuit OSC1 includes a first output transistor (e.g., FIG. 4 T4 in FIG. 10 or FIG. 13 T9 in the middle) and the second output transistor (e.g., FIG. 4 T5 in FIG. 10 or FIG. 13In the T10 configuration, the second electrodes of the first output transistor and the second output transistor are connected to the first output terminal OUT1, which is configured to output a carry signal. Optionally, the second output sub-circuit includes a first selection transistor ST1 and a second selection transistor ST2, the second electrodes of which are connected to the second output terminal OUT2, which is configured to output a control signal. Optionally, the gates of the first output transistor and the first selection transistor ST1 are electrically connected to each other. Optionally, the first electrodes of the first output transistor and the first selection transistor ST1 are configured to provide different signals (e.g., ...). FIG. 4 , FIG. 10 or FIG. 13 (VGH and MS in the text).

[0306] In some embodiments, the first electrode of the first selection transistor ST1 is configured to provide a selection signal; and the selection signal includes at least a portion of an AC signal.

[0307] In some embodiments, the first output transistor (e.g., FIG. 4 T4 in FIG. 10 or FIG. 13 The first electrode of T9 is configured to be supplied with a constant signal.

[0308] In some embodiments, the second output transistor (e.g., FIG. 4 T5 in FIG. 10 or FIG. 13 The gate of T10 and the gate of the second selection transistor ST2 are stabilized by a stabilizing transistor (e.g., FIG. 10 T8 in FIG. 13 or FIG. 4 The stabilizing transistor is electrically isolated from the T12. Optionally, the first electrode of the stabilizing transistor is electrically connected to the gate of the second selection transistor ST2. Optionally, the second electrode of the stabilizing transistor is electrically connected to the gate of the second output transistor.

[0309] In some embodiments, the first electrodes of the second output transistor and the second selection transistor are configured to be provided with the same signal (e.g., FIG. 4 or FIG. 10 VGL in (the context of VGL).

[0310] In an alternative embodiment, the first electrode of the second output transistor is configured to be provided with a clock signal (e.g., FIG. 13 In CK2), and the first electrode of the second selection transistor is configured to be provided with a constant signal (e.g., FIG. 4 VGL in (the context of VGL).

[0311] In some embodiments, the second output transistor and the second selection transistor are controlled by the same signal.

[0312] In some embodiments, the second output transistor and the second selection transistor are controlled by the same signal input to the input terminal of the respective scan unit.

[0313] In some embodiments, the second output sub-circuit further includes a selection capacitor. Optionally, the first capacitor electrode of the selection capacitor is connected to the first selection transistor (e.g., FIG. 4 or FIG. 10 The gate or second selection transistor (e.g., ST1) in the middle. FIG. 13 The gate of ST2 in the middle.

[0314] In some embodiments, the second capacitor electrode of the selector capacitor is connected to the second output terminal (see, for example...). FIG. 8A to FIG. 8I ).

[0315] In some embodiments, the second capacitor electrode of the selection capacitor is connected to the first selection transistor (e.g., ...). FIG. 9 or ​ The first electrode of ST1 in the middle.

[0316] In one aspect, this disclosure provides a display panel. In some embodiments, reference is made to... ​ as well as ​ The display panel includes a display area and a peripheral area. As used herein, the term "display area" refers to the area of ​​the display panel where an image is actually displayed. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting diode display panel. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas in two adjacent pixels. As used herein, the term "peripheral area" refers to the area of ​​the display panel where various circuits and wires are provided to transmit signals to the display panel. To increase the transparency of the display device, opaque or non-opaque components of the display device (e.g., batteries, printed circuit boards, metal frames) may be located in the peripheral area instead of the display area. In some embodiments, the display panel includes a plurality of subpixels and a plurality of control signal lines located in the display area; and one or more scan circuits and a plurality of signal lines located in the peripheral area. One or more scanning circuits are configured to provide control signals to multiple sub-pixels.

[0317] In some embodiments, one or more scanning circuits include a first scanning circuit and at least a second scanning circuit. In some embodiments, the first scanning circuit includes a plurality of scanning units cascaded in series. Each of the plurality of scanning units includes a second output terminal configured to output a control signal to a corresponding control signal line among a plurality of control signal lines.

[0318] In some embodiments, the plurality of signal lines located in the peripheral area include a first start signal line configured to provide a start signal to a corresponding scanning unit, and a second start signal line configured to at least provide a start signal to a second scanning circuit.

[0319] In some embodiments, multiple signal lines located in the peripheral region are grouped into multiple groups arranged sequentially. In some embodiments, the multiple groups include a first group GP1. In some embodiments, the first group GP1 includes a second start signal line ESTV configured to provide a start signal to a second scan circuit, a first corresponding first power line in one or more first power lines VGLL, a first clock signal line CK1L, and a second clock signal line CK2L. The orthographic projections of the second start signal line ESTV, the first corresponding first power line, the first clock signal line CK1L, and the second clock signal line CK2L on the substrate are arranged sequentially; the orthographic projections of the second start signal line ESTV, the first corresponding first power line, the first clock signal line CK1L, and the second clock signal line CK2L on the substrate are substantially parallel to each other. As used herein, the term "substantially parallel" means an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, and 0 degrees to about 30 degrees.

[0320] In some embodiments, the orthographic projection of the first corresponding first power line on the substrate is between the orthographic projection of the second start signal line ESTV on the substrate and the orthographic projection of the first clock signal line CK1L on the substrate. In some embodiments, the orthographic projection of the first clock signal line CK1L on the substrate is between the orthographic projection of the first corresponding first power line on the substrate and the orthographic projection of the second clock signal line CK2L on the substrate.

[0321] In some embodiments, the first group GP1 is located on the side of the plurality of groups that is away from the display area.

[0322] In some embodiments, the first scanning circuit is a gate scan signal generating circuit configured to generate a gate scan signal for a sub-pixel located in the display area, and the second scanning circuit is a light emission control signal generating circuit configured to generate a light emission control signal for a sub-pixel located in the display area.

[0323] In some embodiments, the plurality of groups further includes a second group GP2. In some embodiments, the second group GP2 includes a third start signal line RPSTV, a fourth start signal line RHSTV, a fifth start signal line GNSTV, a first corresponding second power line in one or more second power lines VGHL, a first start signal line GSTV, and a second corresponding first power line in one or more first power lines VGLL.

[0324] In some embodiments, the orthographic projections of the third start signal line RPSTV, the fourth start signal line RHSTV, the fifth start signal line GNSTV, the first corresponding second power line in one or more second power lines VGHL, the first start signal line GSTV, and the second corresponding first power line in one or more first power lines VGLL on the substrate are arranged sequentially; and the orthographic projections of the third start signal line RPSTV, the fourth start signal line RHSTV, the fifth start signal line GNSTV, the first corresponding second power line in one or more second power lines VGHL, the first start signal line GSTV, and the second corresponding first power line in one or more first power lines VGLL on the substrate are substantially parallel to each other.

[0325] In some embodiments, the orthographic projection of the fourth start signal line RHSTV on the substrate lies between the orthographic projections of the third start signal line RPSTV and the fifth start signal line GNSTV on the substrate. In some embodiments, the orthographic projection of the fifth start signal line GNSTV on the substrate lies between the orthographic projection of the fourth start signal line RHSTV on the substrate and the orthographic projection of a first corresponding second power line in one or more second power lines VGHL on the substrate. In some embodiments, the orthographic projection of the first corresponding second power line in one or more second power lines VGHL on the substrate lies between the orthographic projection of the fifth start signal line GNSTV on the substrate and the orthographic projection of the first start signal line GSTV on the substrate. In some embodiments, the orthographic projection of the first start signal line GSTV on the substrate lies between the orthographic projection of the first corresponding second power line in one or more second power lines VGHL on the substrate and the orthographic projection of a second corresponding first power line in one or more first power lines VGLL on the substrate.

[0326] In some embodiments, the second group GP2 is located on the side of the first group G1 closer to the display area.

[0327] In some embodiments, the display panel further includes a third scanning circuit, a fourth scanning circuit, and a fifth scanning circuit. In some embodiments, a third start signal line RPSTV is configured to provide a start signal to the third scanning circuit; a fourth start signal line RHSTV is configured to provide a start signal to the fourth scanning circuit; a fifth start signal line GNSTV is configured to provide a start signal to the fifth scanning circuit; and a first start signal line GSTV is configured to provide a start signal to the first scanning circuit.

[0328] In some embodiments, the plurality of groups further includes a third group GP3. In some embodiments, the third group GP3 includes a first select signal line in one or more select signal lines MSL, a second select signal line in one or more select signal lines MSL, and a second corresponding second power line in one or more second power lines VGHL.

[0329] In some embodiments, the orthographic projections of the first select signal line in one or more select signal lines MSL, the second select signal line in one or more select signal lines MSL, and the second corresponding second power line in one or more second power lines VGHL on the substrate are arranged sequentially; and the orthographic projections of the first select signal line in one or more select signal lines MSL, the second select signal line in one or more select signal lines MSL, and the second corresponding second power line in one or more second power lines VGHL on the substrate are substantially parallel to each other.

[0330] In some embodiments, the orthographic projection of a second select signal line in one or more select signal lines MSL onto the substrate lies between the orthographic projection of a first select signal line in one or more select signal lines MSL onto the substrate and the orthographic projection of a second corresponding second power line in one or more second power lines VGHL onto the substrate.

[0331] In some embodiments, the third group GP3 is located on the side of the second group GP2 away from the first group G1.

[0332] In some embodiments, the first scanning circuit includes multiple parts. In some embodiments, the multiple parts include a first part P1. In some embodiments, the first part P1 includes a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0333] In some embodiments, the orthographic projections of the second transistor T2 and the third transistor T3 on the substrate are spaced apart from the orthographic projections of the sixth transistor T6 and the seventh transistor T7 on the substrate by the orthographic projections of the first transistor T1 and the eighth transistor T8 on the substrate. Optionally, the orthographic projection of the first clock signal line CK1L on the substrate at least partially overlaps with the orthographic projection of the first transistor T1 on the substrate. Optionally, the orthographic projection of a first corresponding first power line in one or more first power lines VGLL on the substrate at least partially overlaps with the orthographic projection of the second transistor T2 on the substrate, and at least partially overlaps with the orthographic projection of the third transistor T3 on the substrate. Optionally, the orthographic projection of the second clock signal line CK2L on the substrate at least partially overlaps with the orthographic projection of the sixth transistor T6 on the substrate, and at least partially overlaps with the orthographic projection of the seventh transistor T7 on the substrate.

[0334] In some embodiments, the plurality of portions further includes a second portion. In some embodiments, the second portion includes a fourth transistor T4, a fifth transistor T5, a third selection transistor ST3, a first capacitor C1, a second capacitor C2, and a selection capacitor SC.

[0335] In some embodiments, the orthographic projections of the fourth transistor T4 and the fifth transistor T5 onto the substrate are separated from the orthographic projections of the selection capacitor SC and the third selection transistor ST3 onto the substrate by the orthographic projections of the first capacitor C1 and the second capacitor C2 onto the substrate. Optionally, the orthographic projection of the third start signal line RPSTV onto the substrate at least partially overlaps with the orthographic projection of the fourth transistor T4 onto the substrate, and at least partially overlaps with the orthographic projection of the fifth transistor T5 onto the substrate. Optionally, the orthographic projection of the fourth start signal line RHSTV onto the substrate at least partially overlaps with the orthographic projection of the first capacitor C1 onto the substrate, and at least partially overlaps with the orthographic projection of the second capacitor C2 onto the substrate. Optionally, the orthographic projection of the fifth start signal line GNSTV onto the substrate at least partially overlaps with the orthographic projection of the first capacitor C1 onto the substrate, and at least partially overlaps with the orthographic projection of the second capacitor C2 onto the substrate. Optionally, the orthographic projection of a first corresponding second power line in one or more second power lines VGHL onto the substrate at least partially overlaps with the orthographic projection of a first capacitor C1 onto the substrate, at least partially overlaps with the orthographic projection of a second capacitor C2 onto the substrate, and at least partially overlaps with the orthographic projection of a selection capacitor SC onto the substrate. Optionally, the orthographic projection of a first start signal line GSTV onto the substrate at least partially overlaps with the orthographic projection of a selection capacitor SC onto the substrate, and at least partially overlaps with the orthographic projection of a third selection transistor ST3 onto the substrate. Optionally, the orthographic projection of a second corresponding first power line in one or more first power lines VGLL onto the substrate at least partially overlaps with the orthographic projection of a selection capacitor SC onto the substrate, and at least partially overlaps with the orthographic projection of a third selection transistor ST3 onto the substrate.

[0336] In some embodiments, the plurality of portions further includes a third portion. In some embodiments, the third portion includes a first selection transistor ST1 and a second selection transistor ST2.

[0337] In some embodiments, the orthogonal projection of one or more selection signal lines MSL on the substrate at least partially overlaps with the orthogonal projection of the first selection transistor ST1 on the substrate, and at least partially overlaps with the orthogonal projection of the second selection transistor ST2 on the substrate.

[0338] In some embodiments, the channel width to channel length ratio of the active layer of the fourth transistor T4 is in the range of 6.5:3.5 to 8.5:3.5, for example, 6.5:3.5 to 7.0:3.5, 7.0:3.5 to 7.5:3.5, 7.5:3.5 to 8.0:3.5, or 8.0:3.5 to 8.5:3.5. In one example, the channel width to channel length ratio of the active layer of the fourth transistor T4 is 7.5:3.5. In another example, the channel width of the fourth transistor T4 is in the range of 3.5 μm to 10 μm.

[0339] In some embodiments, the channel width to channel length ratio of the active layer of the fifth transistor T5 is in the range of 6.5:3.5 to 8.5:3.5, for example, 6.5:3.5 to 7.0:3.5, 7.0:3.5 to 7.5:3.5, 7.5:3.5 to 8.0:3.5, or 8.0:3.5 to 8.5:3.5. In one example, the channel width to channel length ratio of the active layer of the fifth transistor T5 is 7.5:3.5. In another example, the channel width of the fifth transistor T5 is in the range of 3.5 μm to 10 μm.

[0340] In some embodiments, the ratio of the channel width to the channel length of the active layer of the first selection transistor ST1 is in the range of 50:3.5 to 70:3.5, for example, 50:3.5 to 55:3.5, 55:3.5 to 60:3.5, 60:3.5 to 65:3.5, or 65:3.5 to 70:3.5. In one example, the ratio of the channel width to the channel length of the active layer of the first selection transistor ST1 is 60:3.5. In another example, the channel width of the first selection transistor ST1 is in the range of 30 μm to 80 μm.

[0341] In some embodiments, the channel width to channel length ratio of the active layer of the second selection transistor ST2 is in the range of 150:3.5 to 210:3.5, for example, 150:3.5 to 160:3.5, 160:3.5 to 170:3.5, 170:3.5 to 180:3.5, 180:3.5 to 190:3.5, 190:3.5 to 200:3.5, or 200:3.5 to 210:3.5. In one example, the channel width to channel length ratio of the active layer of the second selection transistor ST2 is 180:3.5. In another example, the channel width of the second selection transistor ST2 is in the range of 100 μm to 250 μm.

[0342] The inventors of this disclosure have discovered that by giving the first selection transistor ST1 and the second selection transistor ST2 different channel width-to-length ratios, the output capacitor of the second selection transistor ST2 can be further increased, and the layout of the array substrate can be further optimized.

[0343] In another aspect, this disclosure provides a display device having a display panel as described herein and one or more integrated circuits connected to the display panel. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a quantum dot display device.

[0344] In another aspect, this disclosure provides a method of operating a scanning circuit having a plurality of scanning units. In some embodiments, the method includes electrically connecting the second electrodes of a first output transistor and a second output transistor of a first output sub-circuit of each of the plurality of scanning units to a first output terminal configured to output a carry signal, the carry signal being configured as an input to a scanning unit in a different stage; electrically connecting the second electrodes of a first selection transistor and a second selection transistor of a second output sub-circuit of each of the scanning units to a second output terminal configured to output the control signal, the control signal being configured to drive a pixel driving circuit; electrically connecting the gates of the first output transistor and the first selection transistor to each other; providing different signals to the first electrodes of the first output transistor and the first selection transistor, respectively; outputting the carry signal from the first output sub-circuit; and outputting the control signal from the second output sub-circuit.

[0345] In some embodiments, the method further includes providing a selection signal to a first electrode of the first selection transistor. Optionally, the selection signal includes at least a portion of an AC signal.

[0346] In some embodiments, the method further includes providing a constant signal to a first electrode of a first output transistor.

[0347] In some embodiments, the method further includes electrically isolating the gate of the second output transistor and the gate of the second selection transistor by means of a stabilizing transistor. Optionally, a first electrode of the stabilizing transistor is electrically connected to the gate of the second selection transistor; and a second electrode of the stabilizing transistor is electrically connected to the gate of the second output transistor.

[0348] In some embodiments, the method further includes operating the scanning circuit in a first mode. Optionally, in the first mode, the second output sub-circuit is configured to output an AC signal as an effective voltage for driving the pixel driving circuit.

[0349] In some embodiments, in a first mode: during one or more periods when the first output sub-circuit is configured to output an effective voltage signal as a carry signal, the second output sub-circuit is configured to output an AC signal as an effective voltage for driving the pixel driving circuit; and during one or more periods when the first output sub-circuit is configured to output an invalid voltage signal, the second output sub-circuit is configured to output an invalid voltage signal.

[0350] In some embodiments, the method further includes operating the scanning circuit in a second mode. Optionally, in the second mode, the second output sub-circuit is configured to output an invalid voltage signal.

[0351] In some embodiments, the selection signal includes a portion of an AC signal and a portion of an invalid voltage signal.

[0352] In some embodiments, in the second mode: during one or more periods when the first output sub-circuit is configured to output an effective voltage signal as a carry signal, the second output sub-circuit is configured to output an invalid voltage; and during one or more periods when the first output sub-circuit is configured to output an invalid voltage signal, the second output sub-circuit is configured to output an invalid voltage signal.

[0353] In another aspect, the present invention provides a display device including a scanning circuit described herein or manufactured by the methods described herein, and a display panel having a plurality of light-emitting elements. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a quantum dot display device.

[0354] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A display panel having a display area and a peripheral area, comprising: Multiple sub-pixels and multiple control signal lines located in the display area; as well as One or more scanning circuits and multiple signal lines located in the surrounding area; The one or more scanning circuits are configured to provide control signals to the plurality of sub-pixels; The one or more scanning circuits include a first scanning circuit and at least a second scanning circuit; The first scanning circuit includes multiple scanning units connected in series; Each of the plurality of scanning units includes a second output terminal, which is configured to output a control signal to a corresponding control signal line among the plurality of control signal lines. as well as The plurality of signal lines located in the surrounding area include a first start signal line configured to provide a start signal to each scan unit, and at least a second start signal line configured to provide a start signal to the second scan circuit.

2. The display panel according to claim 1, wherein, The plurality of signal lines located in the surrounding area are grouped into a plurality of groups arranged in sequence; The plurality of groups includes the first group; The first group includes a second start signal line configured to provide a start signal to the second scan circuit, a first corresponding first power supply line among the one or more first power supply lines, a first clock signal line, and a second clock signal line; and The orthographic projections of the second start signal line, the first corresponding first power supply line, the first clock signal line, and the second clock signal line on the substrate are arranged sequentially; the orthographic projections of the second start signal line, the first corresponding first power supply line, the first clock signal line, and the second clock signal line on the substrate are substantially parallel to each other.

3. The display panel according to claim 2, wherein, The first group is located on the side of the plurality of groups that is away from the display area.

4. The display panel according to claim 1, wherein, The first scanning circuit is a gate scan signal generation circuit configured to generate gate scan signals for sub-pixels located in the display area; as well as The second scanning circuit is a light emission control signal generation circuit configured to generate light emission control signals for sub-pixels located in the display area.

5. The display panel according to claim 2, wherein, The plurality of groups also includes a second group; The second group includes a third start signal line, a fourth start signal line, a fifth start signal line, a first corresponding second power line among the one or more second power lines, a first start signal line, and a second corresponding first power line among the one or more first power lines; The third start signal line, the fourth start signal line, the fifth start signal line, the first corresponding second power line of the one or more second power lines, the first start signal line, and the second corresponding first power line of the one or more first power lines are arranged sequentially on the substrate by their orthogonal projections; and The orthographic projections of the third start signal line, the fourth start signal line, the fifth start signal line, the first corresponding second power line of the one or more second power lines, the first start signal line, and the second corresponding first power line of the one or more first power lines on the substrate are substantially parallel to each other.

6. The display panel according to claim 5, wherein, The second group is located on the side of the first group that is closer to the display area.

7. The display panel according to claim 5, wherein, The display panel also includes a third scanning circuit, a fourth scanning circuit, and a fifth scanning circuit; The third start signal line is configured to provide a start signal to the third scan circuit; The fourth start signal line is configured to provide a start signal to the fourth scan circuit; as well as The fifth start signal line is configured to provide a start signal to the fifth scan circuit; and the first start signal line is configured to provide a start signal to the first scan circuit.

8. The display panel according to claim 2, wherein, The plurality of groups also includes a third group; The third group includes a first selection signal line among the one or more selection signal lines, a second selection signal line among the one or more selection signal lines, and a second corresponding second power line among the one or more second power lines; The first selection signal line, the second selection signal line, and the corresponding second power line in the one or more selection signal lines are arranged in sequence on the substrate. as well as The orthographic projections of the first selection signal line, the second selection signal line, and the second corresponding second power line in the one or more selection signal lines on the substrate are substantially parallel to each other.

9. The display panel according to claim 8, wherein, The third group is located on the side of the second group that is furthest from the first group.

10. The display panel according to claim 1, wherein, The first scanning circuit includes multiple parts; The plurality of parts includes the first part; The first part includes a first transistor, a second transistor, a third transistor, a sixth transistor, a seventh transistor, and an eighth transistor; as well as The orthographic projections of the second and third transistors on the substrate and the orthographic projections of the sixth and seventh transistors on the substrate are separated by the orthographic projections of the first and eighth transistors on the substrate.

11. The display panel according to claim 10, wherein, The plurality of parts also includes a second part; The second part includes a fourth transistor, a fifth transistor, a third selection transistor, a first capacitor, a second capacitor, and a selection capacitor; as well as The orthographic projections of the fourth and fifth transistors on the substrate and the orthographic projections of the selection capacitor and the third selection transistor on the substrate are separated by the orthographic projections of the first and second capacitors on the substrate.

12. The display panel according to claim 11, wherein, The second capacitor electrode of the first capacitor, the second capacitor electrode of the second capacitor, and the second capacitor electrode of the selected capacitor have shapes that are substantially complementary to and spaced apart from the boundaries of the adjacent second capacitor electrodes; as well as The first capacitor electrode of the first capacitor, the first capacitor electrode of the second capacitor, and the first capacitor electrode of the selected capacitor have shapes that are substantially complementary to and spaced apart from the boundaries of the adjacent first capacitor electrodes.

13. The display panel according to claim 10, wherein, The plurality of parts also includes a third part; and The third part includes a first selection transistor and a second selection transistor.

14. The display panel according to claim 13, wherein, The plurality of signal lines located in the surrounding area include one or more select signal lines; and The orthogonal projection of the one or more selection signal lines on the substrate at least partially overlaps with the orthogonal projection of the first selection transistor on the substrate, and at least partially overlaps with the orthogonal projection of the second selection transistor on the substrate; The one or more selection signal lines include a first selection signal line and a second selection signal line; The first scanning circuit includes a multi-level cascaded scanning unit, which is configured to provide multiple control signals to multiple rows of sub-pixels; The multi-level cascaded scanning unit includes M-level scanning units, which include a (2m-1)th level scanning unit and a (2m)th level scanning unit, where M and m are positive integers, and 1 ≤ m ≤ (M / 2). The first selection signal line is configured to provide a selection signal to the (2m-1)th level scan unit; and The second selection signal line is configured to provide a selection signal to the (2m)th level scan unit.

15. The display panel according to claim 13, wherein, The ratio of the channel width to the channel length of the active layer of the first selection transistor is in the range of 50:3.5 to 70:3.5; and The ratio of the channel width to the channel length of the active layer of the second selection transistor is in the range of 150:3.5 to 210:3.

5.

16. A display device comprising a display panel according to any one of claims 1 to 15, and one or more integrated circuits connected to the display panel.

17. A scanning circuit comprising multiple scanning units; in, Each of the plurality of scanning units includes a first output sub-circuit and a second output sub-circuit. The first output sub-circuit is configured to output a carry signal as an input to the scanning unit in a different stage, and the second output sub-circuit is configured to output a control signal configured to drive a pixel driving circuit. The first output sub-circuit includes a first output transistor and a second output transistor, and the second electrodes of the first output transistor and the second output transistor are connected to a first output terminal configured to output the carry signal. The second output sub-circuit includes a first selection transistor and a second selection transistor, the second electrodes of which are connected to a second output terminal configured to output the control signal; The gates of the first output transistor and the first selection transistor are electrically connected to each other; and The first electrode of the first output transistor and the first selection transistor are configured to be supplied with different signals.

18. The scanning circuit according to claim 17, wherein, The first electrode of the first selection transistor is configured to be provided with a selection signal; and The selection signal includes at least a portion of the AC signal.

19. The scanning circuit according to claim 17, wherein, The first electrode of the first output transistor is configured to be supplied with a constant signal.

20. The scanning circuit according to any one of claims 17 to 19, wherein, The gate of the second output transistor and the gate of the second selection transistor are electrically isolated by a stabilizing transistor; The first electrode of the stabilizing transistor is electrically connected to the gate of the second selecting transistor; and The second electrode of the stabilizing transistor is electrically connected to the gate of the second output transistor.

21. A method of operating a scanning circuit having multiple scanning units, comprising: The first output transistor and the second output transistor of the first output sub-circuit of each of the plurality of scanning units are electrically connected to the second electrode of the second output transistor, which is configured to output a carry signal, the carry signal being configured as the input of the scanning unit in different stages; The first selection transistor and the second electrode of the second selection transistor of the second output sub-circuit of each scanning unit are electrically connected to the second output terminal configured to output the control signal, which is configured to drive the pixel driving circuit. The gates of the first output transistor and the first selection transistor are electrically connected to each other; Different signals are provided to the first electrodes of the first output transistor and the first selection transistor, respectively; The carry signal is output from the first output sub-circuit; as well as The control signal is output from the second output sub-circuit.

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