Optoelectronic devices and methods of making and using same

Abstract

Various semiconductor structures including buried tunnel junctions or hole regions are described. Further disclosed are methods of making and using such semiconductor structures, e.g., useful in optoelectronic devices, such as vertical cavity surface emitting lasers (VCSEL), that are capable of emitting light at long wavelengths.

Description

Cross Reference to Related Applications

[0001] This application claims priority to U.S. Provisional Application No. 63 / 509,683, filed June 22, 2023, which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0002] The present invention relates to the field of optoelectronic devices, such as vertical cavity surface emitting lasers operating in long wavelength continuous wave (CW) mode at room temperature (RT). BACKGROUND

[0003] In the late 1990s and early 2000s, driven by high-bandwidth optical network applications and fueled by the so-called “telecommunications bubble”, the industry invested significant research and development resources and commercialization efforts to develop long wavelength (LW) vertical cavity surface emitting lasers (VCSELs). Unfortunately, these efforts did not yield the expected results. With the collapse of the overheated optical communications market in 2001, progress in this area came to a standstill. The wavelength range from 1,200 nm to 2,400 nm is of paramount importance, as it is traditionally the optical transmission band for silica fibers in long-haul single-mode communications. Long wavelength vertical cavity surface emitting lasers (LW-VCSELs) capable of operating in this wavelength range have regained strong interest due to a variety of application demands: 1) the need for low-power on-chip laser sources for optoelectronic integrated circuits; 2) the growing market for eye-safe optical sensing systems based on VCSELs and VCSEL arrays; 3) the emerging market for low-cost optical links based on single-mode fibers for distances exceeding 1 km; 4) free-space (last kilometer or indoor personal networks) optical communications for 6G mobile networks and optical wireless networks; 5) Internet of Things applications; 6) low-cost light detection and ranging systems; 7) biomedical sensing and diagnostic devices and systems. In short, mass-producible 1,550 nm band VCSELs would provide technological support for numerous sensing and communication applications.

[0004] However, one of the challenges in developing near-infrared to mid-infrared vertical cavity surface emitting lasers is the need to combine a semiconductor active region capable of providing high optical gain in the 1,200-2,400 nm band with a mirror that has high reflectivity, low optical absorption, and high thermal conductivity. An ideal semiconductor active region is, for example, InAlGaAs quantum wells grown on an InP substrate, while the best mirror reported to date is an AlAs-GaAs double- barrier reflector (DBR) grown on a GaAs substrate. However, there is a general incompatibility between InP and GaAs-based structures in terms of epitaxial growth, which makes the realization of such VCSELs almost impossible. Despite various methods for fabricating near-infrared to mid-infrared VCSELs, even achieving small-scale commercialization, to date, no economically efficient mass production stage has been reached.

[0005] Therefore, there is still a great challenge to manufacture VCSELs capable of emitting light in a long wavelength range. As such, there is still a core need in the field of long wavelength emitting VCSELs that remains unsolved.

[0006] Therefore, there is a need to develop various structures that can be used as mirrors, which can be manufactured by simplifying the process and can be used to prepare vertical cavity surface emitting lasers (VCSELs) having a target emission wavelength. SUMMARY

[0007] It is an object of the present application to provide such structures to address and overcome the known problems in the art in manufacturing devices such as VCSELs.

[0008] It is a further object of the present application to provide novel methods of preparing such structures.

[0009] It is a further object of the present application to provide methods of using the structures, such as for VCSELs.

[0010] Described herein are various semiconductor structures comprising a buried tunnel junction (BTJ). Such semiconductor structures can be used to manufacture optoelectronic devices, including vertical cavity surface emitting lasers (VCSELs). The semiconductor structures comprising a BTJ and the optoelectronic devices made therefrom are described in detail herein.

[0011] Further described herein are various light emitting structures comprising a hole region formed by ion implantation. Such light emitting structures can be used to manufacture optoelectronic devices, such as vertical cavity surface emitting lasers (VCSELs). The various light emitting structures comprising a hole region formed by ion implantation and the optoelectronic devices made therefrom are further described in detail herein.

[0012] The various semiconductor structures, light emitting structures, and the optoelectronic devices (e.g., VCSELs) made therefrom described above can be applied in a wide range of fields, including electronics, photonics, and optoelectronics. In particular, the VCSELs can achieve long wavelength emission (i.e., emission in the red, near-red, or infrared wavelength band, covering sub-bands and specific wavelengths within the range of 900 to 3,000 nm). Further, the VCSELs can have significant advantages in optical and electrical performance over more common laser diodes, such as exhibiting superior beam quality, compact form factor, low power operation, cost-effective wafer-level testing, higher yield, and lower manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0013] The non-limiting embodiments are described by reference to the drawings, which are schematic and not drawn to scale. In the drawings, like reference numerals refer to like parts throughout the various figures. For clarity, not every component is labeled in every figure nor is every component of each figure labeled, so that the figures can advocate clear discussion of the related drawings. Merely exemplary embodiments are described herein.

[0014] Figure 1A A non-limiting cross-sectional schematic view is shown, depicting an epitaxial semiconductor structure 100, constructed from the bottom up: (1) a stack 110 of 12 pairs of alternating layers, including n + -type indium phosphide (InP) and n - -type InP; (2) a thick n-type InP layer 120; (3) a light-emitting structure layer 130 of InAlGaAs, forming an active region with a target emission wavelength of 1550 nm; (4) a p-type InP layer 140; (5) a buried tunnel junction, consisting of: a p ++ -type InGaAs layer 150 and n ++ -type InGaAs layer 160; wherein (6) a current spreading layer 170 wraps the buried tunnel junction; optionally (7) a non-planar structure exists on the surface of the current spreading layer, forming a staircase feature (180) and can provide an optical confinement effect.

[0015] Figure 1B A non-limiting cross-sectional schematic view is shown, depicting an epitaxial semiconductor structure 100', constructed from the bottom up: (1) a stack 110' of 12 pairs of alternating layers, including n + -type indium phosphide (InP) and n - -type InP; (2) a thick n-type InP layer 120'; (3) a light-emitting structure layer 130' of InAlGaAs, forming an active region with a target emission wavelength of 1550 nm; (4) a p-type InP layer 140'; (5) a buried tunnel junction, consisting of: a p ++ -type InGaAs layer 150'; (6) a buried tunnel junction, consisting of n ++ -type InGaAs layer 160'; wherein (7) a current spreading layer 170' wraps the buried tunnel junction; optionally (7) a non-planar structure exists on the surface of the current spreading layer, forming a staircase feature (180') and can provide an optical confinement effect.

[0016] Figure 1C A non-limiting cross-sectional schematic view of an epitaxial semiconductor structure 100" is shown, in which the p-type doped second semiconductor layer 150" is partially etched, such that the thickness of the 150" layer underneath the n-type doped second semiconductor layer 160" is greater than the rest of the 150" layer. For simplicity, other layers and structures are not labeled.

[0017] Figure 1DA non-limiting cross-sectional schematic of epitaxial semiconductor structure 100'" is shown, where the p-doped second semiconductor layer 150'" has been partially and fully etched, such that the 150" layer under the n-doped second semiconductor layer 160'" is thicker than the rest of the 150" layer, and portions of the original layer have been fully etched away. Other layers and structures are not labeled for simplicity.

[0018] Figure 1E A non-limiting cross-sectional schematic of epitaxial semiconductor structure 100"" is shown, where the p-doped second semiconductor layer 150"" has a uniform thickness, and portions of the original layer have been fully etched away. Also visible is that the n-doped current spreading layer 170"" can include additional non-planar regions, with portions of the layer being locally etched away. Other layers and structures are not labeled for simplicity.

[0019] Figure If shows a non-limiting cross-sectional schematic of epitaxial semiconductor structure 100""", where the p-doped second semiconductor layer 150"" is etched to have a smaller area than the n-doped second semiconductor layer 160'""" above it. Other layers and structures are not labeled for simplicity.

[0020] Figure 2 A non-limiting process flow for fabricating a structure (such as semiconductor structure 100) with a buried tunnel junction (BTJ) is shown.

[0021] Figure 3 A non-limiting cross-sectional schematic of a light emitting structure 200 including a distributed Bragg reflector (DBR) and a buried tunnel junction (BTJ) is shown, from bottom to top: (1) a bottom structure 210 of a stack of 12 pairs of alternating layers, including n + -type InP and n - -type InP layers, where the n + -type InP layers are electrochemically etched to form a porous structure (as shown by the dark bands); (2) a thick n-type InP layer 220; (3) a tapered structure, from bottom to top, including: an InAlGaAs layer 230, a p-type InAlAs layer 240; a BJT formed by a p ++ -type InAlAs layer 250 and an n ++ -type InP layer; and a top n-type InP current spreading layer 270, with a surface having a stepped feature 280. Additional Al203 layers (295) and Si02 layers (290) are shown due to processing.

[0022] Figure 4 A non-limiting fabrication process for creating a light emitting structure 200 including a distributed Bragg reflector (DBR) and a buried tunnel junction (BTJ) is shown.

[0023] Figure 5 A non-limiting cross-sectional schematic of a vertical cavity surface emitting laser (VCSEL) 300 is shown, which is constructed from a light emitting structure 200, including a bottom DBR mirror, a top dielectric DBR mirror 310 on top of the mesa structure of the light emitting structure 200, and a metal electrode 320.

[0024] Figure 6 A non-limiting process flow for fabricating a vertical cavity surface emitting laser, such as VCSEL 300, is shown.

[0025] Figure 7 I-V curve plot for a DBR device with a 10 pm diameter buried tunnel junction (BTJ) (solid line) and a DBR device without a BTJ (dashed line).

[0026] Figure 8A L-I or L-J plot for an NP-type InP VCSEL with a 6 pm aperture region.

[0027] Figure 8B Single mode lasing spectrum plot for an NP-type InP VCSEL with a 6 pm aperture region.

[0028] Figure 9 A non-limiting cross-sectional schematic of a heteroepitaxial structure 400 formed from bottom to top is shown, including: (1) a bottom structure 410 composed of a stack of 12 pairs of alternating n + type InP layers; (2) a thick n-type InP layer 420; (3) a light emitting structure 430 composed of InAlGaAs, providing an active region with a target emission wavelength of 1550 nm; (4) a p-type InAlAs layer 440; (5) a p ++ type InAlAs layer 450; (6) an n ++ type InP layer 460; and (7) an n-type InP layer 470.

[0029] Figure 10 A non-limiting fabrication process for preparing a light emitting structure 600 including a distributed Bragg reflector (DBR) and an aperture region is shown.

[0030] Figure 11 A plot of a doping-induced defect distribution using SRIM simulation is shown, with layer boundaries marked by black dashed lines.

[0031] Figure 12 A non-limiting cross-sectional schematic of a light emitting structure 600 including a distributed Bragg reflector (DBR) and an aperture region is shown, present from bottom to top: (1) a bottom structure 610 composed of a stack including 12 pairs of alternating n + type InP and n-type InP layers, where n+ (1) A p-type InP layer 610, (2) A thick n-type InP layer 620, (3) A mesa structure from bottom to top including: an active region - InAlGaAs layer 630 providing a target emission wavelength of 1,550 nm; a p-type InAlAs layer 640; a p-type InAlAs layer 650; an n++ type InP layer 660; a current spreading layer 670 on top, wherein the top surface of the current spreading layer 670 includes a staircase feature 680. The mesa structure interior includes a hole region 645, 655, and 665 formed by p-type InAlAs, p ++ type InAlAs, n ++ type InP, and n-type InP, partially shown as regions 645, 655, and 665 below the staircase feature 680. The p-type InAlAs, p ++ type InAlAs, n ++ type InP, and n-type InP regions are ion implanted to reduce conductivity, and subsequent annealing restores the conductivity of at least the n-type InP current spreading layer covering the hole region. Also shown is a SiO2 layer (690) resulting from the fabrication process.

[0032] Figure 13 A non-limiting cross-sectional schematic of a vertical cavity surface emitting laser (VCSEL) 700 is shown, which is constructed from the light emitting structure 600, including a bottom double reflector (DBR), a top dielectric double reflector mirror 710 on top of the mesa structure of the light emitting structure 600, and a metal electrode 720.

[0033] Figure 14 A non-limiting process flow for fabricating a vertical cavity surface emitting laser (such as the VCSEL 700) is shown.

[0034] Figure 15 I-V curves for two light emitting devices: solid line for a 10 μm diameter hole region device formed by an ion implantation process, and dashed line for a device without a hole region.

[0035] Figure 16A L-I or L-J relationship curve for a 1,380 nm NP-type InP VCSEL with a 7 μm hole region, with a threshold current of 0.5 mA.

[0036] Figure 16B Single mode laser spectrum of a 7 μm hole region 1,380 nm NP-type InP vertical cavity surface emitting laser at 8 mA injection current, with a side mode suppression ratio of over 30 dB.

[0037] Figure 17AA plot of L-I or L-J relationship for a 1550 nm NP-type InP VCSEL with a 7 μιη aperture region, and a threshold current of 0.67 mA.

[0038] Figure 17B A plot of single mode lasing spectrum for a 1550 nm NP-type InP vertical cavity surface emitting laser (VCSEL) with a 7 μιη aperture region at 7 mA injection current is shown, with a side mode suppression ratio of over 30 dB. DETAILED DESCRIPTION

[0039] Various semiconductor structures and methods of making and using the same are described herein. For example, the semiconductor structures can be used to make high performance VCSEL light emitting structures including distributed Bragg reflectors that emit light at long wavelengths.

[0040] I. DEFINITIONS "Aperture ratio" in this specification refers to the volume percentage of air in a porous medium (e.g., an InP, GaAs, or GaSb layer), expressed as a percentage.

[0041] "Electropolishing" refers to the complete or substantial removal of n-type doped indium phosphide or gallium arsenide by etching (where "substantial removal" refers to an etch depth of over 95%, 96%, 97%, 98%, or 99%) to form a cavity at the location of the original n-type doped material. The cavity represents a low refractive index medium (i.e., air). The refractive index of air is typically about 1.

[0042] "Refractive index" and "refractive index" are used interchangeably to refer to the ratio of the speed of light in a vacuum to the speed of light in a particular medium (e.g., an InP, GaAs, or GaSb layer), and is calculated as n = c / v, where c is the speed of light in a vacuum and v is the phase velocity of light in the medium.

[0043] "Refractive index contrast" as referred to herein specifically refers to the difference in the relative refractive index of two media that are in contact and form an interface.

[0044] Numerical ranges include thickness ranges, doping concentration ranges, integer ranges, time ranges, voltage ranges, length ranges, diameter ranges, concentration ranges, and the like. These ranges disclose all possible combinations of the range limits, and any sub-ranges included therein, and combinations thereof. For example, a layer having a thickness in the range of about 1 nm to about 10 nm includes the individual thicknesses of 2, 3, 4, 5, 6, 7, 8, 9 nm, and any range between these values (e.g., 3 nm to 8 nm), and all possible combinations of these values.

[0045] The term "about" is intended to describe a range of ±10% around the value being modified; in other instances, the range of variability around a value can be up to about ±5%. When "about" precedes a numerical range (e.g., about 1-5) or a series of numbers (e.g., about 1, 2, 3, 4, etc.), the term is intended to modify each individual number in the range or series, unless otherwise indicated.

[0046] II. Semiconductor structures and devices including buried tunnel junctions (BTJs) Described herein are various semiconductor structures including buried tunnel junctions. These semiconductor structures can be used to fabricate other optoelectronic devices, or to constitute constituent parts thereof, such as light emitting structures including distributed Bragg reflectors (DBRs), and vertical cavity surface emitting lasers (VCSELs). Each of the various semiconductor structures and optoelectronic devices including BTJs will be described in detail below.

[0047] a. Semiconductor structures including buried tunnel junctions (BTJs) In certain instances, non-limiting semiconductor structures including buried tunnel junctions (BTJs) include: a bottom structure including alternating n-type doped layers and undoped (or low doped) semiconductor layers on a semiconductor substrate; an n-type doped first semiconductor layer on top of the bottom structure; a light emitting structure including a multiple quantum well (MQW) on top of the n-type doped first semiconductor layer; a p-type doped first semiconductor layer on top of the light emitting structure; and a buried tunnel junction (BTJ) on top of the p-type doped first semiconductor layer, wherein the buried tunnel junction includes: a p-type doped second semiconductor layer having a p-type doping concentration greater than about 1 x 1018cm-3; 18 cm -3 -3; an n-type doped second semiconductor layer having an n-type doping concentration greater than about 1 x 1018cm-3; 18 cm -3 -3; wherein at least the surface area of the n-type doped second semiconductor layer is less than the surface area of the p-type doped first semiconductor layer; optionally, wherein the p-type doped second semiconductor layer and the n-type doped second semiconductor layer have equal or approximately equal area on the p-type doped first semiconductor layer; and an n-type doped current spreading layer surrounding at least a portion of the n-type doped second semiconductor layer, optionally surrounding at least a portion of the p-type doped second semiconductor layer, and The current diffusion layer, excluding the portion having the n-type doped second semiconductor layer, contacts the p-type doped second semiconductor or the p-type doped first semiconductor; and The surface of the current diffusion layer may optionally include a region above the embedded tunnel junction, which protrudes and forms a stepped feature, thereby producing an optical confinement effect.

[0048] Exemplary non-limiting semiconductor structures including a BTJ are shown in Figures 1a to 1f. The BTJ is formed by a region buried and located within a current diffusion layer. For example, in semiconductor structure 100, the BTJ is defined by layers 150 and 160, which are enclosed by a current diffusion layer 170, which contacts layer 140. In semiconductor structure 100', the BTJ is defined by layer 160', which is enclosed by a current diffusion layer 170', which contacts layer 150'. As described in Embodiment 1, the BTJ defines a region that can generate a current localization effect in a device containing such a tunnel junction. Furthermore, as described above, the top surface of the current diffusion layer of this structure may include a stepped feature (i.e., 180 in Figure 1b) that covers the BTJ and provides an optical localization effect.

[0049] For specific semiconductor materials constituting the semiconductor structure (such as p-type doped second semiconductor layers and n-type doped second semiconductor layers), there are minimum doping concentration requirements, as described above. For the other p-type or n-type doped layers mentioned, there are no particular restrictions on their doping concentration levels. In some cases, different p-type or n-type doped layers can each independently have at least approximately 1 × 10⁻⁶ doping concentrations. 18 cm -3 Or a higher doping concentration level; or at approximately 0.1 × 10⁻⁶. 19 cm -3 Up to 10×10 20 cm -3 The range. In some cases, high doping concentration levels can be approximately 1 × 10⁻⁶. 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 6×10 19 cm -3 8×10 19 cm -3 9×10 19 cm -3 Or 10×10 19 cm -3In certain other cases, the different p-type or n-type doped layers can each independently have a moderate doping concentration level greater than about 1 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , 2 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , 3 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , 4 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , or 5 x 10 18 cm -3 to less than 1 x 10 20 cm -3 . In certain cases, the moderate doping concentration ranges from 1 x 10 19 cm -3 to less than 1 x 10 20 cm -3 , or from about 0.5 x 10 19 cm -3 to less than 10 x 10 19 cm -3 . In certain cases, the moderate doping concentration level is about 1 x 10 18 cm -3 , 2 x 10 18 cm -3 , 3 x 10 18 cm -3 , 4 x 10 18 cm -3 , 5 x 10 18 cm -3 , or 6 x 10 18 cm -3 , 7 x 10 18 cm -3 , 8 x 10 18 cm -3 , 9 x 10 18 cm -3 , or 10 x 10 18 cm -3 . In other cases, however, the different p-type or n-type doped layers can each have a doping concentration level less than about 20 x 10 17 cm -3 , or from about 0.5 x 10 17 cm -3 to 10 x 10 17cm -3 In certain instances, the low doping concentration level can be about 1 x 1010 17 cm -3 , 2 x 1010 17 cm -3 , 3 x 1010 17 cm -3 , 4 x 1010 17 cm -3 , 5 x 1010 17 cm -3 , 6 x 1010 17 cm -3 , 7 x 1010 17 cm -3 , 8 x 1010 17 cm -3 , 9 x 1010 17 cm -3 , or 10 x 1010 17 cm -3 .

[0050] As mentioned above, the surface area of the at least n-doped second semiconductor layer is less than the surface area of the p-doped first semiconductor layer. For example, as seen in FIGS. 1a-1f, the n-doped second semiconductor layer occupies a region or surface area that is less than the surface area of the p-doped first semiconductor layer. In certain non-limiting examples, the n-doped second semiconductor layer can occupy a surface area that is about 1% to about 30% of the total surface area of the p-doped first semiconductor layer, and can include subranges and specific values within this range. In certain instances (as shown in FIG. 1a), the p-doped second semiconductor layer and the n-doped second semiconductor layer occupy equal or approximately equal surface areas on the p-doped first semiconductor layer, as described in more detail below. In other instances, the two do not occupy equal surface areas on the p-doped first semiconductor layer. For example, as shown in FIG. 1b, the p-doped second semiconductor layer can occupy a surface area that is equal to the p-doped first semiconductor layer, while the n-doped second semiconductor layer occupies a surface area that is less than the surface area of the p-doped first semiconductor layer.

[0051] In other cases, the p-doped second semiconductor layer can have any suitable area, can exhibit variable thickness within the same layer, and / or can be completely etched away in certain portions / regions. As shown in FIG. lc, the epitaxial semiconductor structure 100" can include a p-doped second semiconductor layer 150" that is partially etched such that the thickness of the 150" layer under the n-doped second semiconductor layer 160" is greater than the rest of the 150" layer. However, the thickness variation can take other forms and locations. As shown in FIG. Id, the epitaxial semiconductor structure 100"' can be partially or completely etched at different locations of the same layer such that the thickness of the 150" layer under the n-doped second semiconductor layer 160'" is greater than the rest of the 150" layer, and portions of the original layer have been completely etched away, as shown. As shown in FIG. le, the epitaxial semiconductor structure 100" can include a p-doped second semiconductor layer 150" that is uniform in thickness, wherein portions of the original layer have been completely etched away. FIG. le also shows that the n-doped current spreading layer 170" can include additional non-planar features, i.e., portions of the current spreading layer have been locally etched away. Finally, as shown in FIG. If, the epitaxial semiconductor structure 100""' can include a p-doped second semiconductor layer 150"" that has been etched such that its surface area is less than that of the top n-doped second semiconductor layer 160'"". Such a case can be considered as an undercut of the layer.

[0052] In the special case where the n-doped second semiconductor layer and the p-doped second semiconductor layer have equal or approximately equal areas, it is understood that the two layers are on top of each other, collectively forming a bilayer that exists on the p-doped first semiconductor layer. See FIG. la. As used herein, "approximately equal" means that the difference in area between the two layers is less than about 5%, 4%, 3%, 2%, 1%, or less when comparing different regions of the two layers.

[0053] For the semiconductor structure, the semiconductor substrate can be made of indium phosphide, gallium arsenide, or gallium antimonide. In some cases, the alternating layers of the bottom structure include or are made of a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, or gallium antimonide, which has a lattice that matches a selected semiconductor substrate made of any of indium phosphide, gallium arsenide, or gallium antimonide, respectively. In other cases, the alternating layers of the bottom structure include or are made of a ternary semiconductor material that achieves lattice matching with a selected indium phosphide, gallium arsenide, or gallium antimonide semiconductor substrate, respectively. In other cases, the alternating layers of the bottom structure include or are made of a quaternary semiconductor material that lattice matches with a selected indium phosphide, gallium arsenide, or gallium antimonide semiconductor substrate, respectively.

[0054] In some cases, for the semiconductor structure, the n-doped first semiconductor layer, the light emitting structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer can each independently comprise a semiconductor material selected to be lattice matched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimony.

[0055] Without limitation, suitable semiconductor materials that can form all or a portion of the n-doped first semiconductor layer, the light emitting structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer can each independently comprise a material that is lattice matched to an indium phosphide semiconductor substrate, selected from, but not limited to, the group consisting of nP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or a material that is lattice matched to a gallium arsenide semiconductor substrate, selected from, but not limited to, the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or a material that is lattice matched to a gallium antimony semiconductor substrate, selected from, but not limited to, the group consisting of GaSb, AlAsSb, and AlGaAsSb.

[0056] In some cases, the light emitting structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer can each independently comprise a semiconductor material that is lattice mismatched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimony. In such cases, the semiconductor material that is lattice mismatched to an indium phosphide semiconductor substrate can be selected from, but not limited to, the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the semiconductor material that is lattice matched to a gallium arsenide semiconductor substrate can be selected from, but not limited to, the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the semiconductor material that is lattice matched to a gallium antimony semiconductor substrate can be selected from, but not limited to, the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

[0057] In some cases, non-limiting examples of binary semiconductor materials (which can be p- or n-type doped) can be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some cases, non-limiting examples of ternary semiconductor materials (which can be p- or n-type doped) can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some cases, quaternary semiconductor materials (which can be p- or n-type doped) can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is noted that in selecting any binary, ternary, or quaternary semiconductor material for the above-described single or multi-layer structures, lattice matching between the semiconductor material of each layer of the particular structure and the selected semiconductor substrate (which can be made of InP, GaAs, or GaSb) should be considered. Those skilled in the art will be able to select appropriate materials for each layer that are lattice matched to the semiconductor substrate, and determine the desired doping type and concentration level, as described above.

[0058] For each of the above-described layers and structures, the dimensions, shapes, and thicknesses can be set as desired for a particular application. In some cases, the thicknesses of the different structure layers can be as follows: Table 1. Thicknesses

[0059] *where the ranges include sub-ranges and any particular thickness within the ranges listed in Table 1 is included.

[0060] It is noted that the semiconductor structure layers and structure thicknesses (including the double-sided mirror) used to fabricate the light emitting structure, as well as the vertical cavity surface emitting laser (VCSEL) fabricated from the structure, can define the thicknesses of the corresponding layers and structures in the light emitting structure and VCSEL.

[0061] In some cases, for the bottom structure, the n-type doped semiconductor layers present in the alternating layers have the same thickness as one another, and / or the undoped (or low doped) semiconductor layers present in the alternating layers have the same thickness as one another. The n-type doped and undoped (or low doped) semiconductor layers can have the same or different thicknesses. One non-limiting method of fabricating a semiconductor structure including a buried tunnel junction (BTJ) can include the following steps: (i) forming a bottom structure on a semiconductor substrate, the structure including alternating n-type doped layers and undoped (or low doped) semiconductor layers; (ii) depositing an n-type doped first semiconductor layer on top of the bottom structure; (iii) a light emitting structure, the light emitting structure including depositing or forming a multi-quantum well (MQW) on top of the n-type doped first semiconductor layer; (iv) depositing a p-doped first semiconductor layer on top of the light emitting structure; (v) depositing a p-doped second semiconductor layer over the p-doped first semiconductor layer, the p-doped second semiconductor layer having a p-doping concentration greater than about 1 x 1019cm"3; 18 cm -3 (vi) depositing an n-doped semiconductor layer on top of the p-doped second semiconductor layer, the n-doped semiconductor layer having an n-doping concentration greater than about 1 x 1019cm"3; 17 cm -3 (vii) forming or patterning a masking material on a surface region on top of the n-doped semiconductor layer; (viii) etching away at least the n-doped semiconductor layer, and optionally the p-doped second semiconductor layer outside the region covered by the masking material; (ix) removing the masking material; and (x) depositing an n-doped current spreading layer, the n-doped current spreading layer at least encasing a portion of the n-doped second semiconductor layer, and optionally a portion of the p-doped second semiconductor layer, and wherein the current spreading layer outside the surface region contacts the p-doped second semiconductor or the p-doped first semiconductor.

[0062] Detailed fabrication of the bottom structure is described in Section IV below. Figure 2 An exemplary embodiment of the above method is shown in FIG. 6. A tunnel junction is formed by selective etching of layer 160 (and optionally layer 150), followed by covering it with a current spreading layer. The non-planarity resulting from the etching of layer 160 (and optionally layer 150) without the protection of a masking material, causes a step-like feature to be formed on top of the current spreading layer in the region of the BTJ when the current spreading layer is deposited.

[0063] The structures and deposited layers formed in the above method can be independently fabricated by existing deposition techniques, including metal organic chemical vapor deposition (MOCVD). The selection of precursors, the configuration of p / n-dopants, and the process conditions for forming and doping such layers to a specified thickness are well known in the art.

[0064] Methods for depositing / forming light emitting structures including multiple quantum wells (MQW) are well known in the art.

[0065] In some cases, the masking material is not limited to a material selected from the group consisting of a dielectric material (such as silicon dioxide, silicon nitride, aluminum oxide) and / or a photoresist. Such materials can be formed by plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other well known techniques.

[0066] ​​For the method, any suitable technique (e.g., wet chemical etching, plasma etching, inductively coupled plasma reactive ion etching (ICP-RIE)) can be employed for patterning, etching, or material removal as desired.

[0067] For the method, the semiconductor substrate can be made of indium phosphide, gallium arsenide, or gallium antimonide. In some cases, the alternating layers of the bottom structure include or are made of a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, or gallium antimonide, which lattice matches to the selected semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimonide, respectively. In other cases, the alternating layers of the bottom structure include or are made of a ternary semiconductor material which lattice matches to the selected semiconductor substrate (indium phosphide, gallium arsenide, or gallium antimonide), respectively. In other cases, the alternating layers of the bottom structure include or are made of a quaternary semiconductor material which lattice matches to the selected semiconductor substrate of indium phosphide, gallium arsenide, or gallium antimonide, respectively.

[0068] In some cases, for the semiconductor structure formed according to the method, the n-type doped first semiconductor layer, the light emitting structure, the p-type doped first semiconductor layer, the p-type doped second semiconductor layer, the n-type doped second semiconductor layer, and the current spreading layer can each independently include a selected semiconductor material which lattice matches to the semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimonide.

[0069] Without limitation, suitable semiconductor materials which can form all or part of the n-type doped first semiconductor layer, the light emitting structure, the p-type doped first semiconductor layer, the p-type doped second semiconductor layer, the n-type doped second semiconductor layer, and the current spreading layer can each independently include a semiconductor material which lattice matches to the indium phosphide semiconductor substrate, selected from, but not limited to, the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or a semiconductor material which lattice matches to the gallium arsenide semiconductor substrate, selected from, but not limited to, the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or a semiconductor material which lattice matches to the gallium antimonide semiconductor substrate, selected from, but not limited to, the group consisting of GaSb, AlAsSb, and AlGaAsSb.

[0070] In certain embodiments, each of the light emitting structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer can independently comprise a semiconductor material that is lattice mismatched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimony. In such cases, the semiconductor material is lattice mismatched to an indium phosphide semiconductor substrate and is selected from, but not limited to, the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the semiconductor material is lattice matched to a gallium arsenide semiconductor substrate and is selected from, but not limited to, the group consisting of InGaAs, AlGaAs, In(Al)GaP; or the semiconductor material is lattice matched to a gallium antimony semiconductor substrate and is selected from, but not limited to, the group consisting of InAl(As)Sb, AlAsSb, AlGaAsSb, and the like.

[0071] In certain cases, non-limiting examples of binary semiconductor materials (which can be p- or n-type doped) can be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In certain cases, non-limiting examples of ternary semiconductor materials (which can be p- or n-type doped) can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In certain cases, quaternary semiconductor materials (which can be p- or n-type doped) can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is noted that in selecting any binary, ternary, or quaternary semiconductor material for the above-described single or multi-layer structures, lattice matching of the semiconductor material of each layer of the particular structure to the selected semiconductor substrate (which can be made of InP, GaAs, or GaSb) should be considered. Those skilled in the art will be able to select appropriate materials for each layer that are lattice matched to the semiconductor substrate, and determine the desired doping type and concentration level, as described above.

[0072] For the method, each layer, structure, and overall semiconductor structure formed according to the method can have any suitable dimensions, shapes, and thicknesses. Exemplary (non-limiting) thicknesses of each layer and structure in the overall semiconductor structure are provided in Table 1.

[0073] b. Light emitting structure comprising distributed Bragg reflector (DBR) and buried tunnel junction (BTJ) As described above, semiconductor structures comprising a BTJ can be used to fabricate a light emitting structure comprising a distributed Bragg reflector and having a buried tunnel junction (BTJ) therein.

[0074] In one embodiment, the light emitting structure comprises a distributed Bragg reflector (DBR) and a buried tunnel junction (BTJ), which comprises: a bottom structure comprising alternating n-type doped layers and undoped (or low doped) semiconductor layers on a semiconductor substrate, wherein the n-type doped layers are porous and comprise a plurality of pores; and the undoped (or low doped) layers are non-porous or substantially non-porous; an n-type doped first semiconductor layer on top of the bottom structure; a light emitting structure comprising a multiple quantum well (MQW) on top of the n-type doped first semiconductor layer; a p-type doped first semiconductor layer on top of the light emitting structure; and a buried tunnel junction (BTJ) present on a portion (or sub-region) of the p-type doped first semiconductor layer, wherein the buried tunnel junction (BTJ) defines a hole region and comprises: a p-type doped second semiconductor layer having a p-type doping concentration greater than about 1 x 1018cm-3; 18 cm-3; -3 an n-type doped second semiconductor layer on top of the p-type doped second semiconductor layer, the n-type doped second semiconductor layer having an n-type doping concentration greater than about 1 x 1018cm-3; 18 cm-3; -3 wherein at least a surface area of the n-type doped second semiconductor layer is less than a surface area of the p-type doped first semiconductor layer; optionally, wherein the p-type doped second semiconductor layer and the n-type doped second semiconductor layer have equal or substantially equal areas on the p-type doped first semiconductor layer; and an n-type doped current spreading layer that wraps at least a portion of the n-type doped second semiconductor layer, optionally at least a portion of the p-type doped second semiconductor layer, and wherein the current spreading layer outside of the portion on which the n-type doped second semiconductor layer is present contacts the p-type doped second semiconductor or the p-type doped first semiconductor; and wherein the current spreading layer surface optionally comprises a raised region that covers the buried tunnel junction, the region forming a step feature that creates an optical confinement effect.

[0075] Figure 3 A non-limiting example of a light emitting structure 200 comprising the above-described double layer mirror (DBR) is shown, the structure comprising a DBR and a double layer tunnel junction (BTJ).

[0076] In some cases, the n-type doped layer of the bottom structure that is porous has a porosity of at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

[0077] ​​Due to the porous nature of the n-doped layer in the bottom structure, air can fill the pores, resulting in a lower refractive index of the porous n-doped layer than the non-porous or substantially non-porous undoped (or low doped) layer. In some cases, there is a refractive index contrast (Δn) between the porous layers, which can range from about 0.1 to 2, or from about 0.1 to 2.5.

[0078] For the light emitting structure, the semiconductor substrate can be made of indium phosphide, gallium arsenide, or gallium antimony. In certain cases, the alternating layers of the bottom structure include or are composed of a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, or gallium antimony, which has a lattice match to the selected semiconductor substrate (made of indium phosphide, gallium arsenide, or gallium antimony, respectively). In other cases, the alternating layers of the bottom structure include or are composed of a ternary semiconductor material which has a lattice match to the selected indium phosphide, gallium arsenide, or gallium antimony semiconductor substrate, respectively. In yet other cases, the alternating layers of the bottom structure include or are composed of a quaternary semiconductor material which has a lattice match to the selected indium phosphide, gallium arsenide, or gallium antimony semiconductor substrate, respectively.

[0079] In certain cases, for the light emitting structure, the n-doped first semiconductor layer, the light emitting structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer can each independently include a semiconductor material selected to be lattice matched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimony.

[0080] Without limitation, suitable semiconductor materials that can form all or part of the n-doped first semiconductor layer, the light emitting structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer can each independently include a semiconductor material lattice matched to an indium phosphide semiconductor substrate, selected from, but not limited to, the group consisting of InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or a semiconductor material lattice matched to a gallium arsenide semiconductor substrate, selected from, but not limited to, the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or a semiconductor material lattice matched to a gallium antimony semiconductor substrate, selected from, but not limited to, the group consisting of GaSb, AlAsSb, and AlGaAsSb.

[0081] In some cases, the light-emitting structure, the p-type doped second semiconductor layer, and the n-type doped second semiconductor layer may each independently include a semiconductor material whose lattice is mismatched with that of the semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimonide. In such cases, the semiconductor material is lattically mismatched with the indium phosphide semiconductor substrate and is selected from, but not limited to, the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the semiconductor material is lattically matched with the gallium arsenide semiconductor substrate and is selected from, but not limited to, the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the semiconductor material is lattically matched with the gallium antimonide semiconductor substrate and is selected from, but not limited to, the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

[0082] For specific semiconductor materials constituting the light-emitting structure (such as p-type doped second semiconductor layers and n-type doped second semiconductor layers), there are minimum doping concentration requirements, as described above. For the other p-type or n-type doped layers mentioned, there are no particular restrictions on their doping concentration levels. In some cases, different p-type or n-type doped layers may each independently have at least approximately 1 × 10⁻⁶ doping concentrations. 19 cm -3 Or higher doping concentration levels; or approximately 0.1 × 10⁻⁶. 19 cm -3 Up to 10×10 20 cm -3 Within a certain range. In some cases, high doping concentration levels can be approximately 1 × 10⁻⁶. 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 7×10 19 cm -3 8×10 19 cm -3 9×10 19 cm -3 Or 10×10 19 cm -3 In some other cases, different p-type or n-type doped layers can each independently have a moderate doping concentration level, ranging from approximately 1 × 10⁻⁶. 18 cm -3 to less than 1×10 20 cm -3 2×10 18cm -3 to less than 1 x 10 20 cm -3 , 3 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , 4 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , or 5 x 10 18 cm -3 to less than 1 x 10 20 cm -3 . In some cases, the moderate doping concentration level is in a range from 1 x 10 19 cm -3 to less than 1 x 10 20 cm -3 or 0.5 x 10 19 cm -3 to less than 1 x 10 20 cm -3 . In some cases, the moderate doping concentration level is about 1 x 10 18 cm -3 , 2 x 10 18 cm -3 , 3 x 10 18 cm -3 , 4 x 10 18 cm -3 , 5 x 10 18 cm -3 , 6 x 10 18 cm -3 , 7 x 10 18 cm -3 , 8 x 10 18 cm -3 , 9 x 10 18 cm -3 , or 10 x 10 18 cm -3 . In other cases, however, different p-type or n-type doped layers can each have a low doping concentration level of less than about 20 x 10 17 cm -3 or in a range between about 0.5 x 10 17 cm -3 and 10 x 10 17 cm -3 . In some cases, the low doping concentration level can be about 1 x 10 17 cm -3 , 2 x 10 17 cm -3 , 3 x 10 17 cm-3 4×10 17 cm -3 5×10 17 cm -3 6×10 17 cm -3 7×10 17 cm -3 8×10 17 cm -3 9×10 17 cm -3 , or 10×10 17 cm -3 .

[0083] In some cases, non-limiting examples of binary semiconductor materials (which may be p-type or n-type doped) can be freely selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some cases, non-limiting examples of ternary semiconductor materials (which may be p-type or n-type doped) can be freely selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some cases, quaternary semiconductor materials (which may be p-type or n-type doped) can be freely selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It should be noted that when selecting any binary, ternary, or quaternary semiconductor material for the above single-layer or multi-layer structure, it is advisable to achieve lattice matching between the semiconductor material of each layer of the specific structure and the selected semiconductor substrate (which may be made of InP, GaAs, or GaSb). Those skilled in the art can select suitable materials for each layer that are lattice-matched with the semiconductor substrate and determine the required doping type and concentration level, as described above.

[0084] For the above-described light-emitting structure, each layer, structure, and the overall light-emitting structure can have any suitable size, shape, and thickness. Exemplary (non-limiting) thicknesses of each layer and structure in the overall light-emitting structure are shown in Table 1.

[0085] In some cases, such as Figure 3 As shown, BTJ can form part of a mesa structure, the size of which can be larger than BTJ itself. In other words, the mesa structure encloses BTJ.

[0086] A non-limiting method for fabricating a light-emitting structure including a DBR reflector and an embedded tunnel junction (BTJ) may include the following steps: (i') Setting or forming a semiconductor structure including a buried tunnel junction (BTJ), said semiconductor structure comprising: A bottom structure comprising alternating n-type doped layers and undoped or lightly doped semiconductor layers on a semiconductor substrate; a first n-type doped semiconductor layer on top of the bottom structure; a light emitting structure comprising a multiple quantum well (MQW) on top of the first n-type doped semiconductor layer; a first p-type doped semiconductor layer on top of the light emitting structure; and a buried tunnel junction (BTJ) on top of the first p-type doped semiconductor layer, wherein the buried tunnel junction comprises: a second p-type doped semiconductor layer having a p-type doping concentration greater than about 1 x 1019cm-3; 18 cm -3 -3; a second n-type doped semiconductor layer on top of the second p-type doped semiconductor layer, the second n-type doped semiconductor layer having an n-type doping concentration greater than about 1 x 1019cm 18 cm -3 -3; wherein at least a surface area of the second n-type doped semiconductor layer is smaller than a surface area of the first p-type doped semiconductor layer; optionally, wherein the second p-type doped semiconductor layer and the second n-type doped semiconductor layer have an equal or substantially equal area on the first p-type doped semiconductor layer; and a n-type doped current spreading layer, the n-type doped current spreading layer wrapping at least a portion of the second n-type doped semiconductor layer, optionally also wrapping at least a portion of the second p-type doped semiconductor layer. wherein the current spreading layer outside the portion on which the second n-type doped semiconductor layer is present contacts the p-type doped second semiconductor or the first p-type doped semiconductor; and wherein the current spreading layer surface optionally comprises a region above the buried tunnel junction, the region being raised and forming a staircase feature, thereby creating an optical confinement effect; (ii’) forming a mesa structure by etching portions of the current spreading layer, the first p-type doped semiconductor layer, and optionally the second p-type doped semiconductor layer and the light emitting structure; (iii’) depositing a silicon dioxide layer on the mesa structure, wherein at least a portion of the first n-type doped semiconductor layer is not covered by the silicon dioxide layer; (iv’) etching the portion not covered by the silicon dioxide layer to form a trench thereby exposing sidewalls of the alternating layers of the bottom structure; (v’) selectively porosifying the n-type doped semiconductor layers of the bottom structure, wherein a plurality of pores are formed, and wherein the undoped (or lowly doped) semiconductor layers remain non-porous or substantially non-porous; (vi’) depositing one or more materials to cover the trench, the sidewalls and the sidewalls of the mesa structure; (vii') selectively removing the one or more materials to expose at least a portion of the top of the mesa structure and optionally to expose a portion of the covered n-doped first semiconductor layer; and (viii') forming a metal contact on a portion of the top of the mesa structure and optionally on a portion of the n-doped first semiconductor layer.

[0087] The above describes a method of forming a structure comprising a BTJ. Figure 4 A non-limiting example scheme of a light emitting structure comprising a DBR mirror and a BTJ is shown.

[0088] For the structures and layers formed or deposited in the above described methods, they can be formed or deposited independently by prior art deposition methods, including metal organic chemical vapor deposition (MOCVD). The selection of precursors, p-type or n-type dopants, and process conditions for forming and doping such structures and layers are well known in the art.

[0089] For the method of preparing the light emitting structure, any suitable technique can be used for patterning, etching or removing, such as wet chemical etching, plasma etching, inductively coupled plasma reactive ion etching (ICP-RIE).

[0090] In certain embodiments, the one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide, silicon nitride, spin-on glass (SOG); and / or the one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), polyimide, and photoresist; and combinations thereof. Various types of photoresists are known in the art. For the method, the deposition of the silicon dioxide layer and the one or more materials can be achieved by various methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art. Other options for the light emitting structure and its internal layers have been given in Section IIb above.

[0091] In certain embodiments, the porosity formed in step (v') is at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

[0092] In certain embodiments, step (v') is achieved by electrochemical etching in an electrolyte and under an applied bias voltage. In particular cases, the electrolyte can include halide ions, hydrochloric acid (HC1), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)2, NH4OH, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof.

[0093] In certain embodiments, the metal contact formed in step (viii') is comprised of one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. Methods for forming such metal contacts are well known to those skilled in the art.

[0094] With respect to the mesa structure formed in step (ii'), the dimensions thereof are selected to be larger than the dimensions of the BTJ. In other words, the mesa structure completely encompasses the BTJ therein. The mesa structure can be formed by wet etching or plasma etching (e.g., RIE etching), among other methods.

[0095] c. Optoelectronic device comprising a buried tunnel junction (BTJ) As described above, the light emitting structure comprising a DBR and a BTJ can be used to fabricate an optoelectronic device comprising a buried tunnel junction (BTJ).

[0096] In certain instances, the optoelectronic device can comprise: a light emitting structure comprising a bottom distributed Bragg reflector and a buried tunnel junction (BTJ); a top distributed Bragg reflector; and a metal electrode.

[0097] With respect to the optoelectronic device, the light emitting structure thereof comprises a distributed Bragg reflector (DBR) and a bipolar junction (BTJ) as described above. Figure 5 A non-limiting example of an optoelectronic device (e.g., a vertical cavity surface emitting laser (VCSEL)) is shown.

[0098] In certain instances, the top distributed Bragg reflector is comprised of or comprises alternating layers of a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2, or combinations thereof.

[0099] In certain instances, the metal contact layer is made of or comprises one or more metals selected from the group consisting of titanium, platinum, gold, germanium, nickel, palladium, indium, and combinations thereof.

[0100] In certain instances, the optoelectronic device is a vertical cavity surface emitting laser (VCSEL). In certain instances, the vertical cavity surface emitting laser operates in continuous wave mode at room temperature (about 25 °C).

[0101] In other instances, the vertical cavity surface emitting laser can operate at temperatures below about 0 °C, above about 25 °C, or above about 85 °C. In still other instances, the laser can operate in pulsed mode.

[0102] The vertical cavity surface emitting laser includes a BTJ structure that can emit wavelengths covering the infrared and / or visible light region, depending on the choice of light emitting structure materials. In some cases, the vertical cavity surface emitting laser has a power conversion efficiency of at least 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

[0103] A non-limiting method of fabricating an optoelectronic device including a buried tunnel junction (BTJ) can include the following steps: (i”) providing or forming a light emitting structure including a bottom distributed Bragg reflector and an internal buried tunnel junction (BTJ); (ii”) providing or forming a top distributed Bragg reflector on the light emitting structure; and (iii”) providing or forming a metal electrode on the optoelectronic device.

[0104] For an optoelectronic device formed according to the method described above, the light emitting structure includes a distributed Bragg reflector (BDR) and a BTJ as described above. Figure 6 A non-limiting process flow of fabricating an optoelectronic device, such as a VCSEL, is shown.

[0105] In this method, the top distributed Bragg reflector in step (ii”) can include alternating layers of a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2, or combinations thereof. Methods of fabricating such DBRs with the above-mentioned alternating layers are known in the art. The number of alternating layers in such a DBR can depend on the materials chosen. The top DBR mirror can be deposited by methods in the art and can include an annealing process to improve reflectivity. In some cases, the top DBR mirror has a reflectivity of at least about 97% or higher.

[0106] For the method described above, the metal contact layer in step (iii”) can be composed of the following metals or combinations thereof: titanium (Ti), platinum (Pt), gold (Au), germanium (Ge), nickel (Ni), palladium (Pd), indium (In), and combinations thereof.

[0107] For any of the methods described in the second section, it is understood that the order of certain steps can be interchanged, as long as within the allowed range and without affecting the performance of the structure or device formed. For example, steps (ii”) and (iii”) in the method of fabricating an optoelectronic device can be performed in any suitable order.

[0108] III. Light emitting structures and devices with ion implantation formed hole regions A variety of light emitting structures and devices including ion implantation formed aperture regions are described herein. These light emitting structures can be used to fabricate other optoelectronic devices, or to form constituent parts thereof, such as light emitting structures including distributed Bragg reflector (DBR) mirrors, and vertical cavity surface emitting lasers (VCSELs). Each of the various light emitting structures and devices including ion implantation formed aperture regions will be described in detail below.

[0109] a. Light emitting structure including a distributed Bragg reflector (DBR) mirror and an ion implantation formed aperture region In one embodiment, a light emitting structure including a distributed Bragg reflector (DBR) mirror and an aperture region formed by ion implantation includes: a bottom structure including alternating n-type doped layers and undoped (or low doped) semiconductor layers on a semiconductor substrate, wherein the n-type doped layers are porous and include a plurality of pores; and wherein the undoped (or low doped) layers are non-porous or substantially non-porous; an n-type doped first semiconductor layer on top of the bottom structure; a light emitting structure including a multiple quantum well (MQW) on top of the semiconductor layer; a p-type doped first semiconductor layer on top of the light emitting structure; a p-type doped second semiconductor layer on top of the p-type doped first semiconductor layer, the p-type doped second semiconductor layer having a p-type doping concentration greater than about 1 x 1019cm-3; 18 cm -3 an n-type doped second semiconductor layer on top of the p-type doped second semiconductor layer, the n-type doped second semiconductor layer having an n-type doping concentration greater than about 1 x 1019cm-3; 18 cm -3 an n-type doped current spreading layer on top of the n-type doped second semiconductor layer; wherein there is an aperture region, and wherein a portion of the p-type doped first semiconductor layer within the aperture region has a conductivity greater than the p-type doped first semiconductor layer outside the aperture region; wherein the p-type doped first semiconductor layer, and optionally the p-type doped second semiconductor layer and the n-type doped second semiconductor layer, have a higher resistivity outside the aperture region than within the aperture region; wherein the current spreading layer has electrical conductivity both within and outside the aperture region; and wherein the current spreading layer optionally includes a region of a top surface above the aperture region, the region being raised and forming a step feature to provide an optical confinement effect.

[0110] As Figure 12 ​​As shown, the figure presents a non-limiting example including the aforementioned light-emitting structure 600, such as a DBR reflector. As described above and as... Figure 12 As shown, the aperture region defines a portion of the light-emitting structure comprised of a specific layer. This aperture region is formed via ion implantation, where an ion implantation mask protects a specific area of ​​the structure from conductive damage caused by ion irradiation and implantation. This mask-protected area defines the aperture region, as shown... Figure 12 As shown, the region includes at least layers 645, 655, and 665 that have not undergone ion implantation. Annealing restores the conductivity outside the hole region after ion implantation, at least for the n-type doped current diffusion layer. When the light-emitting structure, including the DBR mirror and the hole region, is used in optoelectronic applications, the hole region can provide a current-confining effect—because the implanted region of the p-type doped first semiconductor remains resistive. Furthermore, an optional stepped structure (680) can be formed above the hole region using an etching step with the same mask as the ion implantation, which can produce an optical confinement effect, allowing for greater overlap between the laser mode and the hole region.

[0111] For specific semiconductor materials constituting the light-emitting structure (such as p-type doped semiconductor layers and n-type doped second semiconductor layers), there are minimum doping concentration requirements, as described above. For the other p-type or n-type doped layers mentioned, there are no particular restrictions on their doping concentration levels. In some cases, different p-type or n-type doped layers may each independently have at least approximately 1 × 10⁻⁶ doping concentrations. 19 cm -3 Or higher doping concentration levels; or approximately 0.1 × 10⁻⁶. 19 cm -3 Up to 10×10 20 cm -3 Within a certain range. In some cases, high doping concentration levels can be approximately 1 × 10⁻⁶. 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 6×10 19 cm -3 6×10 19 cm -3 7×10 19 cm -3 8×10 19 cm -3 9×10 19 cm -3 Or 10×10 19 cm -3In some other cases, different p-type or n-type doped layers can each independently have a moderate doping concentration level, ranging from approximately 1 × 10⁻⁶. 18 cm -3 to less than 1×10 20 cm -3 2×10 18 cm -3 to less than 1×10 20 cm -3 3×10 18 cm -3 to less than 1×10 20 cm -3 4×10 18 cm -3 to less than 1×10 20 cm -3 Or 5×10 18 cm -3 to less than 1×10 20 cm -3 In some cases, the medium doping concentration ranges from 1 × 10⁻⁶. 19 cm -3 to less than 1×10 20 cm -3 or approximately 0.5 × 10 19 cm -3 to less than 1×10 20 cm -3 Between. In some cases, a moderate doping concentration level can be approximately 1 × 10⁻⁶. 18 cm -3 2×10 18 cm -3 3×10 18 cm -3 4×10 18 cm -3 6×10 18 cm -3 6×10 18 cm -3 7×10 18 cm -3 8×10 18 cm -3 9×10 18 cm -3 Or 10×10 18 cm -3 However, in other cases, different p-type or n-type doped layers may each have a density lower than approximately 201 × 10⁻⁶. 17 cm -3 Or between approximately 0.5 × 10 17 cm -3 Up to 10×1017 cm -3 In some cases, the low doping concentration level can be about 1 x 10 17 cm -3 , 2 x 10 17 cm -3 , 3 x 10 17 cm -3 , 4 x 10 17 cm -3 , 5 x 10 17 cm -3 , 6 x 10 17 cm -3 , 7 x 10 17 cm -3 , 8 x 10 17 cm -3 , 9 x 10 17 cm -3 , or 10 x 10 17 cm -3 .

[0112] In some cases, the semiconductor substrate is preferably made of indium phosphide, and the p-type doped first semiconductor layer is made of p-type doped InAlAs or p-type doped InAlGaAs. In other cases, the semiconductor substrate can also be made of other semiconductor materials, such as GaAs or GaSb. The choice of semiconductor material should ensure its lattice match with the selected semiconductor substrate.

[0113] In some cases, the alternating layers of the bottom structure comprise or are made of a binary semiconductor material (such as indium phosphide) that is lattice matched to the semiconductor substrate. In other cases, the alternating layers of the bottom structure comprise or are made of a ternary semiconductor material that is lattice matched to the semiconductor substrate. In yet other cases, the alternating layers of the bottom structure comprise or are made of a quaternary semiconductor material that is lattice matched to the semiconductor substrate.

[0114] In some cases, the n-type doped first semiconductor, the light emitting structure, the p-type doped first semiconductor, the p-type doped second semiconductor, the n-type doped second semiconductor, and the current spreading layer each independently comprise or are made of one or more materials that are lattice matched to the semiconductor substrate. In some cases, the one or more materials are lattice matched to, for example, an indium phosphide semiconductor substrate, and are selected from, but not limited to, the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb.

[0115] In other cases, the light emitting structure, the p-doped second semiconductor, and the n-doped second semiconductor each independently comprise one or more materials that are not lattice matched to the indium phosphide semiconductor substrate. In such cases, the material can be selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb.

[0116] In some cases, non-limiting examples of binary semiconductor materials (which can be p- or n-doped) can be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some cases, non-limiting examples of ternary semiconductor materials (which can be p- or n-doped) can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some cases, quaternary semiconductor materials (which can be p- or n-doped) can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is noted that in selecting any binary, ternary, or quaternary semiconductor material for the single or multi-layer structures described above, lattice matching of the semiconductor material of each layer of the particular structure to the selected semiconductor substrate (which can be made of InP, GaAs, or GaSb) should be considered. Those skilled in the art will be able to select a material for each layer that is lattice matched to the semiconductor substrate, and determine the desired doping type and concentration level, as described above.

[0117] In some cases, the p-doped first semiconductor layer outside the grating region, and optionally the p-doped second semiconductor layer and the n-doped second semiconductor layer, have an electrical conductivity that is reduced by about 1-4 orders of magnitude compared to the electrical conductivity inside the grating region. The material comprising the p-doped first semiconductor layer should preferably be a material that, after ion implantation, has a reduced electrical conductivity (increased resistance) and, upon high temperature annealing, does not recover or substantially recover its electrical conductivity. By "substantially recover" is meant that the recovered value is less than about 50%, about 40%, about 30%, about 20%, about 10%, about 5%, about 1% of the original electrical conductivity of the material prior to ion implantation.

[0118] In some cases, the porosity of the n-doped layer in the bottom structure (which is a porous layer) is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

[0119] The porous n-doped semiconductor layer of the bottom structure has a plurality of pores that can be filled with air, such that the refractive index of the porous semiconductor layer is lower than that of a non-porous or substantially non-porous undoped semiconductor layer. In some cases, there is a refractive index contrast (Δn) between the porous layers after porosification, which is in the range of about 0.1 to 2, or about 0.1 to 2.5.

[0120] The dimensions, shape, and thickness of each layer and structure of the aforementioned light-emitting structure can be flexibly set according to actual application requirements. In some cases, the thicknesses of different structures and layers can be as shown in the table below: Table 2. Thickness

[0121] *The ranges mentioned above also include sub-ranges, and any specific thicknesses within the ranges listed in Table 2 are included.

[0122] It is understandable that the thickness of the aforementioned structure used to manufacture VCSELs with a DBR light-emitting structure can also define the thickness of these layers.

[0123] In some cases, for light-emitting structures, the n-type doped semiconductor layers in the alternating layers have the same thickness as each other, and / or the undoped (or lightly doped) semiconductor layers in the alternating layers have the same thickness as each other. The n-type doped and undoped (or lightly doped) semiconductor layers can have the same or different thicknesses.

[0124] In some cases, such as Figure 12 As shown, the hole area is included in the table structure. In this case, the size of the table structure is selected to be larger than the size of the hole area.

[0125] A non-limiting fabrication method for manufacturing a light-emitting structure including a DBR mirror and a aperture region formed by ion implantation may include the following steps: (a) Setting or forming a light-emitting structure, including: A bottom structure comprising alternating n-type doped layers and undoped (or lightly doped) semiconductor layers on a semiconductor substrate; The n-type doped first semiconductor layer is located at the top of the bottom structure; A light-emitting structure, the light-emitting structure comprising multiple quantum wells (MQWs) located on top of a first semiconductor layer; The p-type doped first semiconductor layer is located on top of the light-emitting structure; p-type doped second semiconductor layer, wherein the p-type doped second semiconductor layer has a concentration greater than about 1 × 10⁻⁶. 18 cm -3 The p-type doping is located on top of the p-type doped first semiconductor layer; An n-type doped second semiconductor layer is located on top of the p-type doped second semiconductor layer, the n-type doped second semiconductor layer having a concentration greater than about 1 × 10⁻⁶. 18 cm -3 n-type doping; and An n-type doped current diffusion layer located on top of the n-type doped second semiconductor layer; (b) placing a masking material over a top surface area of the current spreading layer of the structure; (c) performing ion implantation to reduce the electrical conductivity of at least the p-type doped first semiconductor layer not covered by the masking material; (d) etching a portion of the current spreading layer, wherein the etching does not remove the current spreading layer under the masking material; (e) removing the masking material; (f) depositing a first layer of silicon dioxide over a portion of the current spreading layer to cover at least the area where the masking material was present; (g) annealing the structure to increase the electrical conductivity of the current spreading layer; (h) forming a mesa structure by etching portions of the current spreading layer, the n-type doped second semiconductor, the p-type doped second semiconductor, the p-type doped first semiconductor, and the light emitting structure not covered by the first layer of silicon dioxide; (i) depositing a second layer of silicon dioxide over the mesa structure, wherein at least a portion of the n-type doped first semiconductor layer is not covered by the second layer of silicon dioxide; (j) etching the structure not covered by the second layer of silicon dioxide to form a trench to expose sidewalls of the alternating layers of the underlying structure; (k) performing a selective poration process on the n-type doped semiconductor layers in the alternating layers of the underlying structure, wherein the pores formed comprise air, and the undoped semiconductor layers remain either free of pores or substantially free of pores; (l) depositing one or more materials to cover the trench, the sidewalls, and the sidewalls of the mesa structure; (m) selectively removing the one or more materials to expose at least a portion of the top of the mesa structure, and optionally a portion of the semiconductor layers covered by the one or more materials; and (n) forming a metal contact on a portion of the top of the mesa structure and optionally a portion of the semiconductor layers.

[0126] Details of the fabrication of the underlying structure are described in Section IV below. Figure 10 An example flow of the above-described method is shown. The flow begins with Figure 9 the structure 400 shown, Figure 10 The process of placing a masking material on the top layer to protect the area underneath from ion implantation (530) is described. The electrical conductivity of at least the top layer of n-type doped material is selectively restored by an annealing process as described in Example 2.

[0127] Methods of depositing / forming light emitting structures including multiple quantum wells (MQWs) are known in the art.

[0128] The structures and layers formed or deposited in the above-described methods can be formed independently by conventional deposition techniques, including metal organic chemical vapor deposition (MOCVD). The selection of precursors, p-type or n-type dopants, and process conditions for forming and doping such structures and layers at a specified thickness are well known in the art.

[0129] With respect to the annealing process in step (g), the annealing can be performed at any suitable elevated temperature, and for a time sufficient to increase the conductivity of the ion-implanted current spreading layer. In some cases, the annealing can restore the conductivity of the ion-implanted current spreading layer to at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or more of the pre-implant level. In some cases, the annealing temperature can be set to a range of about 250 °C to 450 °C, including sub-ranges or specific temperatures within this range. The annealing time can be adjusted to a range of about 1 minute to 1 hour, or 1 minute to 30 minutes, including sub-ranges or specific times within this range. In some cases, such as when an n-type indium phosphide current spreading layer is used, the annealing temperature can be set to 350 °C, and an annealing time of about 20 minutes can be applied to restore the conductivity of the current spreading layer.

[0130] With respect to the mesa structure formed in step (h), the dimensions of the mesa structure are greater than the dimensions of the aperture region. In other words, the mesa structure completely encompasses the aperture region. The structure can be formed by wet etching or plasma etching, such as RIE etching.

[0131] For the particular semiconductor materials that make up the light emitting structure portion (e.g., the p-doped second semiconductor layer and the n-doped second semiconductor layer), there are minimum requirements for the doping concentration, as described above. For the remaining p-doped or n-doped layers mentioned, there are no particular restrictions on the doping concentration levels. In some cases, different p-doped or n-doped layers can each independently have a doping concentration level of at least about 1 x 1018cm-3or more; or in a range of about 0.1 x 1018cm-3to 10 x 1018cm-3. In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3. 19 cm -3 or more. In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3. 19 cm -3 In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3. 20 cm -3 In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3. 19 cm -3 In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3. 19 cm -3 In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3. 19 cm -3 In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3. 19 cm -3 In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3. 19 cm -3 In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3. 19 cm -3 In some cases, the high doping concentration level can be about 1 x 1018cm-3, 2 x 1018cm-3, 3 x 1018cm-3, 4 x 1018cm-3, 5 x 1018cm-3, 6 x 1018cm-3, 7 x 1018cm-3, 8 x 1018cm-3, 9 x 1018cm-3, or 10 x 1018cm-3.19 cm -3 , 8 x 10 19 cm -3 , 9 x 10 19 cm -3 , or 10 x 10 19 cm -3 . In certain other cases, the different p-type or n-type doped layers can each independently have a moderate doping concentration level ranging from greater than about 1 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , 2 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , 3 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , 4 x 10 18 cm -3 to less than 1 x 10 20 cm -3 , or 5 x 10 18 cm -3 to less than 1 x 10 20 cm -3 . In certain cases, the moderate doping concentration ranges from about 1 x 10 19 cm -3 to less than 1 x 10 20 cm -3 , or from about 0.5 x 10 19 cm -3 to less than 1 x 10 20 cm -3 . In certain cases, the moderate doping concentration level is about 1 x 10 18 cm -3 , 2 x 10 18 cm -3 , 3 x 10 18 cm -3 , 4 x 10 18 cm -3 , 5 x 10 18 cm -3 , or 6 x 10 18 cm -3 , 7 x 10 18 cm -3 , 8 x 10 18 cm -3 , 9 x 10 18 cm -3 , or 10 x 10 18 cm-3 However, in other cases, the different p-type or n-type doped layers can each have a doping level below about 20 x 1018cm"3. 17 cm"3. -3 or between about 0.5 x 1018cm"3. 17 cm"3. -3 and 10 x 1018cm"3. 17 cm"3. -3 In certain cases, the low doping level can be about 1 x 1018cm"3. 17 cm"3. -3 , 2 x 1018cm"3. 17 cm"3. -3 , 3 x 1018cm"3. 17 cm"3. -3 , 4 x 1018cm"3. 17 cm"3. -3 , 5 x 1018cm"3. 17 cm"3. -3 , 6 x 1018cm"3. 17 cm"3. -3 , 7 x 1018cm"3. 17 cm"3. -3 , 8 x 1018cm"3. 17 cm"3. -3 , 9 x 1018cm"3. 17 cm"3. -3 or 10 x 1018cm"3. 17 cm"3. -3 .

[0132] In certain cases, the masking material in step (b) can be selected from the group consisting of, but not limited to, dielectric materials (such as silicon dioxide, silicon nitride, aluminum oxide), metals (such as nickel), and / or photoresists. Such materials can be formed by a variety of methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art.

[0133] For the methods, any material can be patterned, etched, or removed as desired by any suitable technique, such as wet chemical etching, plasma etching, inductively coupled plasma reactive ion etching (ICP-RIE), etc.

[0134] In certain cases, for the light emitting structure, suitable semiconductor materials for the n-type doped first semiconductor layer, the p-type doped first semiconductor layer, the p-type doped second semiconductor layer, the n-type doped second semiconductor layer, and the current spreading layer have been discussed in detail above in Section IIIa.

[0135] For the methods, the individual layers, structures, and overall light emitting structure formed according to the methods can have any suitable dimensions, shapes, and thicknesses. Exemplary (non-limiting) thicknesses for the individual layers and structures in the overall structure are shown in Table 2.

[0136] In some embodiments, the one or more materials are selected from the group consisting of silicon dioxide, alumina, silicon nitride, spin-coated glass, etc.; and / or the one or more materials are selected from organic materials such as benzocyclobutene (BCB), polyimide, photoresist, etc.; and combinations of the above materials. For the method, the deposition of the silicon dioxide layer and one or more materials can be achieved through various processes, such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other known and applicable methods.

[0137] In some embodiments, the porosity formed by step (k) is at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

[0138] In some embodiments, step (k) is performed by electrochemical etching in an electrolyte under an applied bias voltage. In specific cases, the electrolyte may include halide ions, hydrochloric acid (HCl), sulfuric acid (H₂SO₄), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)₂, Ca(OH)₂, Sr(OH)₂, NH₄OH, etc. Sulfuric acid (H₂SO₄), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)₂, Ca(OH)₂, Sr(OH)₂, NH₄OH, NaCl, NaF, nitric acid (HNO₃), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof.

[0139] In some embodiments, the metal contact formed in step (n) is composed of one or more of the following metals: titanium (Ti), platinum (Pt), gold (Au), germanium (Ge), gallium (Ga), nickel (Ni), palladium (Pd), indium (In), and combinations thereof. Methods for preparing such metal contacts are well known to those skilled in the art.

[0140] i. Ion implantation Regarding the ion implantation in step (c), the following details can be provided: The mask material in step (b) can be made from the materials specified above. More specifically, the mask material can be considered as an ion implantation mask material, the size, area, or shape of which can be arbitrarily set, thereby controllably selecting which areas of the surface are protected from ion implantation.

[0141] Such ion implantation masks can be prepared by a variety of methods. Non-limiting examples include, but are not limited to: (1) Photoresist method: A photoresist layer is spin-coated onto a substrate, and then the mask layer is patterned as required by photolithography, electron beam lithography or imprinting technology. Depending on the ion source and ion energy used, the mask layer thickness can be adjusted from less than about 1 μm to more than 10 μm as needed.

[0142] (2) Hard mask etching method: A hard mask material layer is deposited, which can be a dielectric (such as silicon dioxide or silicon nitride) or a metal (such as titanium, aluminum, etc.). Different deposition techniques can be used depending on the material properties, such as thermal evaporation, electron beam evaporation, sputtering, spin coating, chemical vapor deposition, atomic layer deposition, etc. Subsequently, a photoresist layer is spin-coated and patterned on the deposited hard mask layer. Finally, the hard mask layer is removed by chemical or physical etching, and the photoresist pattern is transferred to the underlying material.

[0143] (3) Hard mask stripping method: Similar to the above process (hard mask etching method), but the operation sequence is reversed. First, a photoresist layer is spin-coated to form a pattern, and then a hard mask layer is deposited on top of the photoresist layer using any of the techniques in (2) above. Then, the photoresist is etched to strip off the unmasked areas within the hard mask layer, thereby transferring the pattern to the hard mask layer.

[0144] In the ion implantation step, ions are implanted only into the exposed areas not covered by the mask. Implanted ions can come from a variety of ion sources. Various ion types and sources can be selected, such as aluminum, gold, nitrogen, hydrogen, helium, carbon, oxygen, titanium, iron, etc., to alter (i.e., damage / reduce) the conductivity of the ion-implanted region. In some cases, ions can be selected based on the principle of higher atomic mass. For example, aluminum ions are chosen over hydrogen ions due to their larger atomic mass. The selected energy depends on the desired ion implantation depth, ranging from below approximately 10 keV to above approximately 1 megaeV, to control the implantation depth within the following ranges: below approximately 10 nm to above approximately 1 μm, approximately 10 nm to approximately 750 nm, approximately 10 nm to approximately 500 nm, approximately 10 nm to approximately 250 nm, approximately 10 nm to approximately 100 nm, or any suitable sub-range or single depth value within the above ranges. Ion dosage can also be used to control the number of implanted ions, thereby regulating conductivity changes. Typical ion implantation dosage ranges can cover, but are not limited to, approximately 10 keV. 12 Up to 10 16 cm -3 The specific depth depends on the type of ion and the target depth. The energy of the ion implantation source can be used to control the implantation depth of ions in layered structures.

[0145] b. Optoelectronic devices containing ion-implanted porous regions As described above, light-emitting structures including birefringent lattices (DBRs) and aperture regions can be used to fabricate optoelectronic devices with aperture regions.

[0146] In some cases, optoelectronic devices may include: A light-emitting structure, the light-emitting structure comprising a bottom distributed Bragg reflector and an aperture region; Top distributed Bragg reflector; and Metal electrode.

[0147] For optoelectronic devices, the light-emitting structure includes a bottom distributed Bragg reflector (BDR) mirror and a hole region as described above. Figure 13 A non-limiting example of an optoelectronic device, such as a vertical-cavity surface-emitting laser (VCSEL), is shown.

[0148] In some cases, the top distributed Bragg reflector is composed of or includes alternating layers of any of the following: amorphous silicon / silicon dioxide, titanium dioxide / silicon dioxide, tantalum pentoxide / silicon dioxide, niobium pentoxide / silicon dioxide, zinc selenide / silicon dioxide, amorphous silicon / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2, or combinations thereof.

[0149] In some cases, metal contacts are made of or include one or more metals selected from the group consisting of titanium, platinum, gold, germanium, nickel, palladium, indium, and combinations thereof.

[0150] In some cases, the optoelectronic device is a vertical-cavity surface-emitting laser (VCSEL). In other cases, the VCSEL operates in continuous-wave mode at room temperature (approximately 25°C).

[0151] In other cases, the vertical-cavity surface-emitting laser can operate at temperatures below about 0°C, above about 25°C, or above about 85°C. In still other cases, the vertical-cavity surface-emitting laser can operate in pulsed mode.

[0152] This vertical-cavity surface-emitting laser includes an aperture region that can emit in the infrared and / or red wavelength regions, depending on the choice of the emitting structure material. In some cases, the power conversion efficiency of the vertical-cavity surface-emitting laser reaches at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

[0153] A non-limiting method for manufacturing an optoelectronic device including a hole region may include the following steps: (a') Setting or forming a light-emitting structure including a bottom distributed Bragg reflector and a hole region; (b') To provide or form a top distributed Bragg reflector on the light-emitting structure; and (c') A metal electrode is disposed or formed on the optoelectronic device.

[0154] For optoelectronic devices prepared according to the above method, their light-emitting structure includes a bottom distributed Bragg reflector (BDR) and an aperture region as described above. Figure 14 A non-limiting process flow for fabricating optoelectronic devices, such as vertical-cavity surface-emitting lasers (VCSELs), is shown.

[0155] In this method, the top distributed Bragg reflector in step (b') may comprise alternating layers of any of the following: a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2, or combinations thereof. Methods for fabricating such deep reflective layers with the aforementioned alternating layers are known in the prior art. The number of alternating layers in such deep reflective layers may depend on the selected material. The top deep reflective layer mirror can be deposited using methods in the prior art and may include an annealing treatment to improve reflectivity. In some cases, the reflectivity of the top deep reflective layer mirror is at least about 97% or higher.

[0156] In the above method, the metal contacts in step (c') may be made of or include metals selected from titanium (Ti), platinum (Pt), gold (Au), germanium (Ge), nickel (Ni), palladium (Pd), indium (In), and combinations thereof.

[0157] For any of the methods described in Section III, it should be understood that the order of certain steps may be interchanged, provided that it is within permissible limits and does not affect the performance of the resulting structure or device. For example, steps (b') and (c') in a method for manufacturing an optoelectronic device may be performed in any suitable order.

[0158] IV. Bottom Structure and its Preparation and Porosification Methods The following sections will elaborate on the various structures (such as semiconductor structures and light-emitting structures) as well as the bottom structure of the optoelectronic devices described in Sections 2 and 3 above.

[0159] For semiconductor structures 100, 100', 100'', 100''', 100'''', 10, and 400, each structure includes an alternating bottom structure of doped and undoped (or lightly doped) semiconductor layers on a semiconductor substrate. This semiconductor substrate can be made of materials such as indium phosphide (InP), gallium arsenide (GaAs), or gallium antimonide (GaSb). In these specific structures, the n-type doped semiconductor layers remain intact and have not undergone selective porosification treatments such as electrochemical etching.

[0160] In one non-limiting example, the bottom structure includes a plurality of undoped or lightly doped (see below) semiconductor layers, which may be composed of indium phosphide, gallium arsenide or gallium antimonide layers, wherein at least one n-type doped semiconductor layer is present between at least two undoped or lightly doped semiconductor layers, which can be porosified by electrochemical etching (or electropolishing).

[0161] The bottom structure comprises alternating semiconductor layers on a semiconductor substrate. In some cases, a semiconductor substrate is selected first, followed by a suitable semiconductor material with a lattice-matched structure to form alternating n-type doped and undoped (or lightly doped) layers. For example, the semiconductor substrate for the bottom structure can be made of indium phosphide (InP), gallium arsenide (GaAs), or gallium antimony arsenide (GaSb). It should be noted that the semiconductor substrate and alternating layers of the bottom structure do not necessarily have to be made of the same material, but it is best to choose lattice-matched materials, which is within the scope of options available to those skilled in the art. The size, area, or shape of the semiconductor substrate and its doped or undoped (or lightly doped) layers can be arbitrarily and reasonably set according to the specific application requirements. Typically, the semiconductor substrate and all its layers have the same size, area, and shape. In some cases, the overall dimensions (i.e., length and width) of the bottom structure can reach approximately 100 micrometers × 100 micrometers, including sub-dimensions within it.

[0162] In some cases, the alternating layers of the bottom structure comprise or are composed of a binary semiconductor material selected from, but not limited to, the group consisting of indium phosphide, gallium arsenide, and gallium antimonide, and are lattice-matched with the semiconductor substrate. In other cases, the alternating layers of the bottom structure comprise or are composed of a ternary semiconductor material that is lattice-matched with the semiconductor substrate. In still other cases, the alternating layers of the bottom structure comprise or are composed of a quaternary semiconductor material that is lattice-matched with the semiconductor substrate.

[0163] In some cases, non-limiting examples of binary semiconductor materials (which may be p-type or n-type doped) can be freely selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some cases, non-limiting examples of ternary semiconductor materials (which may be p-type or n-type doped) can be freely selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some cases, quaternary semiconductor materials (which may be p-type or n-type doped) can be freely selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It should be noted that when selecting any binary, ternary, or quaternary semiconductor material for the above single-layer or multi-layer structure, it is advisable to achieve lattice matching between the semiconductor material of each layer of the specific structure and the selected semiconductor substrate (which may be made of InP, GaAs, or GaSb). Those skilled in the art can select suitable semiconductor materials for each layer that are lattice-matched with the semiconductor substrate and determine the required doping type and doping concentration level, as described above.

[0164] In some cases, the bottom structure includes at least 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 or more pairs of n-type doped and undoped (or lightly doped) semiconductor layers, which are at least in contact before electrochemical etching.

[0165] Those skilled in the art are familiar with methods for fabricating such bottom structures, such as existing epitaxial or homoepitaxial methods, such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or liquid phase epitaxy (LPE), and using known reactants, dopants, and precursors to form doped and undoped (or lightly doped) semiconductor layers.

[0166] like Figure 4 As shown, this bottom structure can be placed under electrochemical (EC) etching conditions, in which the present n-type doped semiconductor layer is selectively porosized, forming multiple pores within the n-type doped semiconductor layer. These pores are surrounded and adjacent to undoped or lightly n-type doped semiconductor layers, which remain porosity-free or substantially porosity-free under electrochemical conditions (where "substantially porosity-free" means that the porosity of the doped layer (or lightly doped layer) is less than 25%, 20%, 15%, 10%, 5%, 4%, 3%, 2%, or 1%). In some other cases, the multiple pores are horizontally aligned (i.e., parallel) with the planar direction of the n-type doped semiconductor layer.

[0167] In certain cases, the bottom structure consists of a single type of doped and undoped (or lightly doped) semiconductor. For example, the bottom structure can consist of an all-indium phosphide layer, an all-gallium arsenide layer, or an all-gallium antimonide layer, with these layers alternately doped as described above. However, a hybrid structure of different material types can also be used.

[0168] If the N-type doped semiconductor layer has a sufficiently high doping concentration, it can be selectively treated by the electrochemical etching process described below to achieve selective porosimetry or selective electropolishing (i.e., removal) of specific regions within the doped semiconductor layer. Undoped or poorly doped semiconductor layers are typically not subject to electrochemical etching. The specific conditions for controlling the degree of porosimetry or achieving electropolishing will be further described below. Porosimetry and electropolishing do not require complete removal of the N-type doped semiconductor layer; specific electrochemical processes only require porosimetry or electropolishing of a portion or region. The structures formed by porosimetry or electropolishing during electrochemical etching include (air) pores or channels, which can be formed horizontally—due to selective lateral etching acting on one or more sidewalls of the underlying structure.

[0169] Electrochemical etching requires that the n-type doped semiconductor layer be doped with an n-type dopant. Therefore, existing n-type doped semiconductor layers are formed during deposition / formation processes. Typical dopant includes, but is not limited to, n-type germanium (Ge) and silicon (Si) dopant. Such dopant sources can include silane (SiH4), germanane (GeH4), and isobutylgermanane (IBGe), etc. For n-type doped layers, the n-type doping concentration can remain uniform throughout the layer or form a concentration gradient (i.e., a layer with a gradient doping concentration along the layer axis, such as the width direction). The doping concentration reaches at least approximately 1 × 10¹. 9 cm - A concentration of ³ or higher is considered high; or approximately 0.1 × 10³. 19 cm -3 Up to 10×10 20 cm -3 The range. In some cases, high doping concentration levels can be approximately 1 × 10⁻⁶. 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 7×10 19 cm -3 8×10 19 cm -3 9×10 19 cm -3 Or 10×10 19 cm -3 The doping concentration is 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 Below, 2×10 18 cm -3 Up to 1×10 20 cm -3 Below, 3×10 18 cm -3 Up to 1×10 20 cm -3 Below, 4 4 ×10 18 cm -3 Up to 1×10 20 cm -3 Below, 5×10 18 cm -3 Up to 1×1020 cm -3 Below, 6×10 18 cm -3 Up to 1×10 20 cm -3 Below, 7×10 18 cm -3 Up to 1×10 20 cm -3 Below, 8×10 18 cm -3 Up to 1×10 20 cm -3 Below, 9×10 18 cm -3 Up to 1×10 20 cm -3 Below, 10×10 18 cm -3 Up to 1×10 20 cm -3 The following values ​​are considered medium doping concentrations. In some cases, the medium doping concentration range is 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 Below, or approximately 0.5 × 10 19 cm -3 Up to 1×10 20 cm -3 Between these values. In some cases, a moderate doping concentration level may be approximately 1 × 10⁻⁶. 18 cm -3 2×10 18 cm -3 3×10 18 cm -3 4×10 18 cm -3 5×10 18 cm -3 6×10 18 cm -3 7×10 18 cm -3 8×10 18 cm -3 9×10 18 cm -3 , or 10×10 18 cm -3 Medium to high concentrations of n-type doping can be affected by electrochemical etching processes, leading to controlled porosimetry and / or electropolishing of the doped layer, depending on the operating conditions of the electrochemical etching process.

[0170] As mentioned above, the bottom structure includes undoped semiconductor layers that are unaffected (not porosized or etched) when the bottom structure is electrochemically etched. However, in some cases, the bottom structure may include lightly doped or very lightly doped semiconductor layers, where the doping concentration is considered low, specifically below approximately 20 × 10⁻⁶. 17 cm -3 Or between approximately 0.5 × 10 17 cm -3 Up to 10×10 17 cm -3 Between. In some cases, a moderate doping concentration level may be approximately 1 × 10⁻⁶. 17 cm -3 2×10 17 cm -3 3×10 17 cm -3 4×10 17 cm -3 5×10 17 cm -3 6×10 17 cm -3 7×10 17 cm -3 8×10 17 cm -3 9×10 17 cm -3 Or 10×10 17 cm -3 .

[0171] Prior to electrochemical etching, the thickness of any single n-type doped or undoped (low-doped) layer can independently range from about 50 to 500 nm (including subranges or individual thickness values ​​disclosed herein). In some cases, the total thickness of the bottom structure before or after electrochemical etching can range from about 600 nm to about 8,000 nm or from 600 nm to about 6,000 nm, and include its subranges. The dimensions and / or shape of the individual layers or semiconductor substrate can be any suitable form / size required for the application. In some cases, for the bottom structure, the n-type doped semiconductor layers present in alternating layers have the same or substantially the same thickness; and / or the undoped (or low-doped) semiconductor layers present in alternating layers have the same or substantially the same thickness. "Substantially the same" as used herein means that the thickness of each particular layer differs from the thickness of all other similar layers by less than about 5%, 4%, 3%, 2%, 1%, or less. The n-type doped layer and the undoped (or low-doped) layer can have the same or different thicknesses.

[0172] After being electrochemically etched, the undoped or lightly doped semiconductor layer in the bottom structure is generally not affected (i.e., non-porous or substantially non-porous, where "substantially non-porous" means a porosity below 25%, 20%, 15%, 10%, 10%, 5%, 4%, 3%, 2% or 1%). In some embodiments, unintended porosity may occur in the undoped (or lightly doped) semiconductor layer, i.e., even a lightly n-type doped semiconductor layer may form pores during the electrochemical etching process.

[0173] After being electrochemically etched, the n-type doped semiconductor layer in the bottom structure exhibits porosity characteristics compared to before etching. When the porosity in at least one region of the layer is between about 10% and 90% or higher, the degree of porosity can be significantly increased. In some cases, the porosity can reach at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% or 90% and above. By introducing a low refractive index material (such as air) into the layer (or a part thereof) through porosity, the refractive index can be reduced compared to the bulk semiconductor layer before porosity.

[0174] For the n-type doped semiconductor layer, by changing the type and concentration of the electrolyte, the n-type doping concentration of the layer, and the applied bias voltage, electrochemical etching can produce different degrees of porosity and pore morphology (see details below).

[0175] Electrochemical etching can be used to selectively form lateral or horizontal pores in the hydrophobic n-type doped semiconductor layer of the bottom structure. These pores are selectively formed from the side surface of the multi-layer structure. Without limitation, the lateral or horizontal pores formed during the electrochemical etching process can have any suitable length. The porous semiconductor layer (or a region therein) contained in the multi-layer structure is preferably nanoscale, but can further be defined as micro-, meso-, or macro-pores or any combination of the above structures. The porous layer or region can be further subdivided into micropores (d < 2 nm), mesopores (2 nm < d < 50 nm) or macropores (d > 50 nm), where d is the average pore diameter. The pore morphology within the layer or region can be classified as circular, semi-circular, elliptical or a combination thereof. The average size (i.e., length) of the pores can be between about 5 and 100 nm, 5 and 75 nm, 5 and 50 nm or 5 and 25 nm. In some cases, the average pore diameter can reach about 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 nm or larger. In some cases, depending on the original doping concentration, the etchant used, and the applied voltage during the electrochemical porosification process, the average size of the pores can vary from less than about 20 nm to greater than 50 nm. The spacing between adjacent pores (which can also be regarded as an indicator of the pore wall thickness) can be distributed in the following ranges: about 1 to 50 nm, 5 to 50 nm, 5 to 40 nm, 5 to 30 nm, 5 to 25 nm, 5 to 20 nm, 5 to 15 nm or 5 to 10 nm.

[0176] In a given bottom structure, all or part of the doped semiconductor layer can form a porous structure during electrochemical etching. In some cases, the electrochemical etching begins from the sidewalls, and the porosity of the layer reaches at least 10%, 20%, 30%, 40%, 50%, 60%, 80%, or 90% of the longest planar dimension of the doped layer. In other cases involving electropolishing, the degree of electropolishing of a single layer reaches at least 10%, 20%, 30%, 40%, 50%, 60%, 80%, or 90% of the longest planar dimension of the doped layer. During electrochemical etching, porosity within each doped layer may occur uniformly or non-uniformly. During electrochemical etching, electropolishing may occur uniformly or non-uniformly within each doped layer.

[0177] As mentioned above, in some cases, the n-type doped semiconductor layer is removed (completely removed) by electropolishing, resulting in almost no or no material remaining between the undoped (or lightly doped) layers—that is, where the original doped semiconductor material was located. The size of the voids formed by electropolishing depends on the thickness of the doped semiconductor layer and the amount of material removed by electropolishing. In some cases, electropolishing can create lateral or horizontal (air) pores or channels between the undoped layers where the doped material has been removed.

[0178] a. Optical properties of the bottom structure By selectively introducing low-refractive-index materials (such as air) into specific regions or layers of the bottom structure through electrochemical etching, the refractive index of that region can be reduced to below that of the host semiconductor material constituting the structure. Therefore, the refractive index of porous regions in the bottom structure can be selectively adjusted.

[0179] For example, before electrochemical etching, the refractive index of each layer in the InP-based bottom structure is approximately 3.2. Electrochemical etching can selectively porosilicate or fully electropolish the n-type doped InP layers, thereby reducing the refractive index below 3.2. In some cases, the refractive index of the porous InP layer is approximately 1.5 to 2.7. After the InP layer is removed by electropolishing, the refractive index is approximately 1. Therefore, the refractive index contrast (Δn) between the InP layers after electrochemical etching can reach approximately 0.1 to 2. In some cases, the refractive index contrast (Δn) reaches at least 1.1, 1.2, 1.3, 1.4, or 1.5. In other cases, the refractive index contrast (Δn) reaches at least 1.5.

[0180] Prior to electrochemical etching, the refractive index of each layer in the gallium arsenide (GaAs) bottom structure is approximately 3.95. Electrochemical etching selectively porosilicates or fully electropolishes the doped indium phosphide (INP) layers, thereby reducing the refractive index below 3.95. In some cases, the refractive index of the porosilicated GaAs layers is approximately 1.5 to 3.4. After the GaAs layers are removed by electropolishing, the refractive index is approximately 1. Therefore, the refractive index contrast (Δn) between the GaAs layers after electrochemical etching may be in the range of approximately 0.1 to 2.5. In some cases, the refractive index contrast (Δn) reaches at least 1.1, 1.2, 1.3, 1.4, or 1.5. In other cases, the refractive index contrast (Δn) reaches at least 1.5.

[0181] Before electrochemical etching, the refractive index of each layer in the GaSb bottom structure is approximately 3.85. Electrochemical etching can selectively porosilicate or fully electropolish the doped InP layer, thereby reducing the refractive index below 3.85. In some cases, the refractive index of the porosilicated GaAs layer is approximately 1.2 to 3.4. After the GaAs layer is removed by electropolishing, the refractive index is approximately 1. Therefore, the refractive index contrast (Δn) between the GaAs layers after electrochemical etching may be in the range of approximately 0.1 to approximately 2. In some cases, the refractive index contrast (Δn) reaches at least 1.1, 1.2, 1.3, 1.4, or 1.5. In other cases, the refractive index contrast (Δn) reaches at least 1.5.

[0182] The bottom structure can be used as a reflector with a reflectivity of at least approximately 99%, 99.1%, 99.2%, 99.3%, 99.4%, 99.5%, 99.6%, 99.7%, 99.8%, or 99.9%.

[0183] b. Electrochemical (EC) etching method for bottom structure As described above, methods for forming alternating doped and undoped (or lightly doped) semiconductor layers are known in the prior art. However, methods for forming the bottom structure may include the following non-limiting example steps: (a) Forming a first undoped or lightly doped semiconductor layer over a semiconductor substrate; (b) Deposit a second n-type doped semiconductor layer on the first layer; (c) Deposit a third undoped or lightly doped semiconductor layer over the second layer; (d) Optionally repeat steps (b) and (c) to form additional alternating n-type doped layers with undoped or lightly doped semiconductor layers.

[0184] The resulting bottom structure can be used to manufacture other structures, such as... Figure 2 , 4 As shown in Figure 10. In this type of process, it can be electrochemically (EC) etched, such as...Figure 4 and 10 As shown.

[0185] Electrochemical (EC) etching of an n-type doped semiconductor layer can be performed in an electrolyte and under an applied bias voltage to selectively porosilicate or electropolish at least a portion of the n-type doped semiconductor. Porosity and / or electropolishing occurring during electrochemical (EC) etching can be controlled by adjusting the electrolyte concentration, doping concentration, and applied bias voltage (described below). The applied bias voltage is typically a positive voltage, ranging from approximately 0.1 to 10 V, 1.0 to 5 V, or 1.0 to 2.5 V. In some cases, depending on the initial doping concentration and the type of etchant used, the applied bias voltage range can be less than about 1 V to at least about 10 V or higher. When using lower relative doping concentrations, porosity can be selectively minimized—for example, in a non-limiting example, the sample has a doping concentration of 5 × 10⁻⁶. 18 cm -3 Under the same etching conditions, the doping concentration of [a specific type of material] results in a porosity of less than 2 × 10⁻⁶. 19 cm -3 The doping concentration is a factor to consider. This phenomenon is expected across all relative concentration differences: when other electrochemical etching parameters are constant, higher doping concentrations will produce a more significant porosity effect compared to lower relative concentrations. In some cases, depending on the choice of electrolyte concentration, doping concentration, and applied bias voltage, electrochemical etching conditions can selectively and controllably produce only porosity (introducing approximately 30% to 90% or higher porosity) or achieve complete electropolishing (i.e., complete or near-complete removal of doped material, with a removal rate greater than 95%, 96%, 97%, 98%, or 99%). The electric field direction during electrochemical etching can be used to control the etching direction, thereby modulating the porosity orientation etched into the n-type doped semiconductor layer. For example, the electroetching direction can be determined as a function of the electric field direction. This process preferably produces a lateral etching direction. The lateral etching rate can be set to: approximately 0.1μm / min, 0.2μm / min, 0.3μm / min, 0.4μm / min, 0.5μm / min, 0.6μm / min, 0.7μm / min, 0.8μm / min, 0.9μm / min, 1μm / min , 2μm / min, 3μm / min, 4μm / min, 5μm / min, 6μm / min, 7μm / min, 8μm / min, 9μm / min, 10μm / min, 20μm / min, 30μm / min, 40μm / min or 50μm / min.

[0186] Electrochemical etching can be performed at the applied bias voltage for durations ranging from approximately 1 minute to 24 hours, 1 minute to 12 hours, 1 minute to 6 hours, 1 minute to 4 hours, 1 minute to 2 hours, 1 minute to 1 hour, or 1 minute to 30 minutes. In some cases, electrochemical etching may need to be performed at the applied bias voltage for at least approximately 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, 2 hours, 3 hours, 4 hours, 5 hours, 6 hours, 10 hours, 15 hours, 20 hours, 24 hours, or longer. Electrochemical etching can be performed at room temperature or within a temperature range of approximately 10°C to 50°C at the applied bias voltage. The etching can be performed at room temperature or, alternatively, in an inert atmosphere (such as nitrogen or argon).

[0187] Electrochemical etching can be performed in various types and concentrations of highly conductive electrolytes (salts or acids). Exemplary highly conductive electrolytes include, but are not limited to: halide ions (fluoride, chloride, bromide, iodide), hydrochloric acid (HCl), sulfuric acid (H₂SO₄), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)₂, Ca(OH)₂, Sr(OH)₂, NH₄OH, NaCl, NaF, nitric acid (HNO₃), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof. The electrolyte concentration in a highly conductive electrolyte solution (typically an aqueous solution) ranges from approximately 0.1 to 10 mol / L. In some other cases, the concentration of the electrolyte in a highly conductive electrolyte solution (typically an aqueous solution) may be defined as the volume percentage of the electrolyte to the solvent (such as water), ranging from approximately 0.1% to 30% (volume percentage). In other cases, the concentration of the electrolyte in a highly conductive electrolyte solution (typically an aqueous solution) can be defined as the percentage (by weight / volume) of the electrolyte relative to the solvent (such as water), in which it is dissolved, with a concentration ranging from approximately 0.1% to 30% (by weight). These electrolytes typically do not etch semiconductor materials such as InP, GaAs, or GaSb at room temperature, but can etch such semiconductors when electrochemical anodic conditions are applied.

[0188] It is believed that the electrochemical etching described herein begins by exposing the sidewall edges, preferentially forming horizontal pores, for example, along the lateral direction. Lateral etching leads to porosification, causing pores (typically nanopores) to form horizontally or primarily horizontally within the doped layer. The bottom structure has a vertical axis from the bottommost layer to the top layer, with alternating doped and undoped (or lightly doped) planar structures. When electrochemical etching is initiated, the porosification process of the n-type doped layer occurs perpendicular or primarily perpendicular to this vertical axis. "Primary perpendicular" as used herein refers to an average pore orientation deviating from the vertical axis perpendicular / horizontal plane by approximately 20, 15, 10, or 5 degrees. In other words, porosification occurs horizontally or primarily horizontally, parallel or nearly parallel to the planar orientation of the doped layer. For the bottom structure, after electrochemical etching, vertically aligned pores may be minimal or nonexistent. Pores do not need to be aligned with the vertical axis of the bottom structure. In some cases, vertically aligned pores are not formed in the doped layer; only horizontal pores are formed during the electrochemical etching process. In some cases, undoped (or lightly doped) InP, GaAs, or GaSb materials can also form nm pores in the

[111] crystallographic direction, with these pores tilted at a 45-degree angle to the vertical

[001] plane and the horizontal direction. In other cases, macroscopic nm pores may form in n-type doped semiconductors and diffuse laterally during porosification; while microscopic nm pore formation may occur along specific crystallographic directions (e.g., directions tilted at +45° or -45° relative to the surface of the doped layer).

[0189] Electrochemical etching typically involves two steps: oxide formation and removal (Quill, N. et al., 2013, ECStransactions, 58(8), 25-38). Studies suggest that the presence of free holes at the semiconductor / electrolyte interface is crucial for the oxidation process, and the formed oxides are readily soluble in various electrolytes. Free holes are provided by the electric field-assisted tunneling effect, and their number depends primarily on the anodic bias and doping concentration. In some cases, electrochemical etching conditions prevent electrochemical etching at low anodic bias and / or low doping concentrations (as described above), while electropolishing (i.e., complete etching) is observed at high bias and / or high n-type doping concentrations. Porosity occurs at moderate bias and / or doping concentrations.

[0190] V. Application Methods of Structures and Optoelectronic Devices The various structures and optoelectronic devices described in this article (such as light-emitting structures with DBR mirrors and VCSELs) can be applied in fields such as electronics, photonics, and optoelectronics. Typical applications include, but are not limited to: low-power on-chip laser sources for optoelectronic integrated circuits; eye-friendly optical sensing systems based on VCSELs and VCSEL arrays; low-cost optical links achieving transmission over 1km based on single-mode fiber; free-space (last kilometer or indoor personal network) optical communication for 6G mobile networks and optical wireless networks; the Internet of Things; low-cost optical detection and ranging systems; and biomedical sensing and diagnostic equipment and systems.

[0191] Of particular note is that the vertical-cavity surface-emitting laser (VCSEL) can achieve long-wavelength emission (i.e., emitting red, near-infrared, or infrared light in the 900 to 3,000 nm band, covering sub-bands and specific wavelengths within this range). Under certain conditions, the VCSEL can emit specific wavelengths or bands, such as approximately 650 nm, approximately 850 nm to approximately 940 nm, approximately 1,300 nm to approximately 1,600 nm, or approximately 2,000 nm to approximately 2,400 nm. In some cases, the VCSEL can emit within the red light band of the spectrum. Vertical-cavity surface-emitting lasers (VCSELs) have significant application value in fields such as information processing, micro-displays, micro-projection, laser headlights, high-resolution printing, biophotonics, spectral detection, and atomic clocks.

[0192] Compared to the more commonly used edge-emitting laser diodes (EELDs), the VCSELs described in this article have significant advantages in optical and electrical performance, such as: superior beam quality, compact size, low power consumption, cost-effective wafer-level testing, higher manufacturing yield, and lower manufacturing cost.

[0193] The invention can be further understood by referring to the following non-limiting examples.

[0194] Example 1: nm multi-pore vertical-cavity surface-emitting laser (VCSEL) with buried tunnel junction (BTJ) Materials and Methods: As shown in Figure 1, a semiconductor structure 100 with a buried tunnel junction (BTJ) is derived from... Figure 2 The epitaxial growth structure 10 shown (top leftmost row) is the starting point for fabrication. All layers are grown in a planar continuous manner. From bottom to top, structure 10 comprises six parts: (1) a stack 110 consisting of 12 pairs of alternating layers, where n + Type I indium phosphide (InP) layer (dark band, doping concentration: 5 × 10⁻⁶) 18 cm -3 ) and n - Type InP (light band, lightly doped, doping concentration: <5×10⁻⁶) 18 cm-3 ), where n + (1) InP can be formed by electrochemical etching to form a nm porous (NP) InP layer with a low refractive index (lower than the refractive index of the layer before porosification); (2) Thick n-type InP layer 120 (light gray, doping concentration: 5×10 17 cm -3 (3) The light-emitting structure 130 is composed of InAlGaAs, providing an active region with a target emission wavelength of 1,550 nm; (4) The p-type InP layer 140 (doping concentration: 5×10⁻⁶) has a thickness of at least about 200 nm, forming the main volume of the structure; (5) The light-emitting structure 130 is composed of InAlGaAs, providing an active region with a target emission wavelength of 1,550 nm; (6) The p-type InP layer 140 (doping concentration: 5×10⁻⁶) has a thickness of at least about 200 nm, forming the main volume of the structure; (7) The light-emitting structure 130 is composed of InAlGaAs, providing an active region with a target emission wavelength of 1,550 nm; (8) The p-type InP layer 140 (doping concentration: 5×10⁻⁶) has a thickness of at least 17 cm -3 (5)p ++ Type 150 InGaAs layer (doping concentration > 1 × 10⁻⁶) 19 cm 13 ); and (6)n ++ Type 160 InGaAs layer (black, doping concentration > 1 × 10⁻⁶) 19 cm 13 Structure 10 was grown by metal-organic chemical vapor deposition (MOCVD).

[0195] As shown in Figure 1, the semiconductor structure 100 includes, from bottom to top: (1) a stack 110 composed of 12 pairs of alternating layers, wherein n + Indium phosphide (InP) layer and n - (1) Alternating n-type InP layers; (2) Thick n-type InP layer 120 with a thickness of at least about 200 nm; (3) Light-emitting structure 130 composed of InAlGaAs, providing an active region with a target emission wavelength of 1,550 nm; (4) p-type InP layer 140; (5) Buried tunnel junction composed of p-type InGaAs layer 150 and n++ type InGaAs layer 160; wherein (6) Current diffusion layer 170 encloses the tunnel junction; and optionally (7) the surface of the current diffusion layer has a non-planar structure, forming a stepped feature (180) and producing an optical confinement effect.

[0196] Starting from structure 10, Figure 2 A non-limiting schematic diagram of the process for forming the BTJ structure is shown. This process involves patterning a mask material on the top surface of structure 10. Figure 2 (Top row, middle). Subsequently, a wet etching process was performed using a mixture of citric acid and hydrogen peroxide to remove portions of the outer 150 and 160 layers of the mask area. Figure 2 (Top row, far right). After removing the mask ( Figure 2 (Leftmost in the bottom row), a new n-type indium phosphide layer (middle layer 170 in Figure 1) is regrown, and the patterned tunnel junction below it is embedded in it. Figure 2 (Bottom row, far right). This ultimately forms layer 150 (p) as shown in Figure 1.++ Type InGaAs) and 160 layers (n ++ A tunnel junction (BTJ) is constructed using n-type InGaAs, as shown in Figure 1. This junction is confined to a small region and surrounded by an n-type InP layer (layer 170 in Figure 1). This BTJ structure is considered to have the following characteristics: 1) Current is primarily injected through the BTJ region (also known as the aperture region); in optoelectronic devices, only the carrier-injected region emits light and provides laser gain. Therefore, localized current injection is considered to achieve gain guidance for optical localization; 2) After the regeneration of layer 170, the process results in the top surface of the semiconductor structure 100 not being planarized. In other words, the surface above the BTJ or aperture region is higher than the rest of the peripheral surface of layer 170, which can be considered as a staircase feature 180 in the structure, providing an optical confinement effect for optoelectronic devices fabricated using structure 100.

[0197] like Figure 3 As shown, a light-emitting structure 200 including a distributed Bragg reflector (DBR) mirror is fabricated based on the aforementioned semiconductor structure 100. Figure 3 The fabrication process for providing a DBR for a light-emitting structure is demonstrated. From semiconductor structure 100 ( Figure 4 Starting from the top left, a mesa structure is formed through an etching process. This process can be wet etching (dilute HCl followed by citric acid and H2O2) or dry etching. Figure 4 The top center), where the bottom of the mesa structure is located at layer 120. A SiO2 layer (30) is deposited by plasma-enhanced chemical vapor deposition (PECVD) and patterned so that the layer covers most of the top surface except for the left side. Figure 4 (Top row, far right). In other words, SiO230 covers the entire mesa structure, except for the top surface edge of the sidewalls. The function of the SiO230 layer is: 1) to serve as a dry etching mask for subsequent process steps; 2) to protect the mesa structure from subsequent electrochemical (EC) etching. Deep dry etching (8 sccm CH4, 4 sccm H2, 10 sccm Cl2, HF power 100W, ICP power 1,200W) is then performed, using SiO230 as a mask to form trenches that extend to the bottom of the stacked structure 110. Figure 4 (Middle row, far left). This structure (anode) and platinum (Pt) wire / plate (cathode) were then immersed in an electrolyte for electrochemical (EC) etching. Figure 4(Middle row, centered). Electrochemical etching is initiated from the sidewalls of the trench by applying a positive voltage. The porosilicated region (dark region) extends laterally, eventually covering the entire BTJ or hole region above. Notably, porosilicated regions are confined to the n+ type InP layer of stacked structure 110, while the lightly doped InP layer remains intact (unporosilicated). The selectivity between porosilicated and non-porosilicated regions is achieved through the difference in doping concentration. Porosilicated regions result in the n+ type InP layer being filled with air, with a lower refractive index than the lightly doped InP layer. This alternating structure of high-refractive-index and low-refractive-index layers forms a mirror in the DBR structure for fabricating vertical-cavity surface-emitting lasers (VCSELs).

[0198] After selective porosification of the stacked structure, another PECVD SiO2 layer (40) was deposited on the surface of the porosified sample. Figure 4 The purpose of this 40th layer is to cover and protect the porous stacked structure—the inlet of nanoporous (NP) type InP. However, since PECVD SiO2 is known to induce leakage current (especially through the mesa sidewalls) (Jpn.J.Appl.Phys.38 1195(1999)), buffered oxide etchant was used to remove the SiO2 layers 30 and 40 on the mesa structure. Figure 4 The bottom leftmost row), and an Al2O3 layer is deposited on it by atomic layer deposition (50)( Figure 4 (Bottom row, middle). Finally, the Al2O3 (50) layer was partially removed to expose the top of the mesa structure and at least a portion of the top surface of the 120th layer ( Figure 4 (The rightmost side of the bottom row), thus forming a light-emitting structure including distributed total reflection mirrors.

[0199] Figure 3 The light-emitting structure 200, including the DBR reflector, is shown in detail. From bottom to top, the light-emitting structure 200 consists of the following parts: (1) a bottom structure 210, consisting of 12 pairs of alternating n + Type InP layer and n - It consists of InP layers, where n + (1) Selective porosification of the n-type InP layer by electrochemical etching (as shown by the dark band); (2) A thick n-type InP layer 220 with a thickness of at least about 200 nm; (3) A tapered structure from bottom to top including: an InAlGaAs layer 230, a p-type InAlAs layer 240; a bipolar transistor composed of a p-type InAlAs layer 250 and an n-type InP layer 260; and a top n-type InP current diffusion layer 270. The top surface of the bipolar transistor is composed of a p-type InAlAs layer 250 and an n-type InP layer 260. ++ Type InAlAs layer, p ++ Type InAlAs layer 240, p ++Type InAlAs layer 250 and n ++ The structure consists of a mesa-shaped InP layer 260; the top is an n-type InP current diffusion layer 270, the surface of which has a stepped feature 280. Figure 3 The additional layers shown include an Al2O3 layer (295) and a SiO2 layer (290), which are present due to the manufacturing process but are not required for the light-emitting device or the dual-layer reflector (DBR) function included therein.

[0200] like Figure 5 As shown, the light-emitting structure 200, including a double-layer reflector mirror, is used to form a vertical-cavity surface-emitting laser 300. The light-emitting structure 200, including a double-layer thin-film reflector (DBR), constitutes the bottom DBR reflector of the vertical-cavity surface-emitting laser (VCSEL), while a top dielectric DBR reflector 310 and a metal electrode 320 are located on top of the mesa structure. Figure 5 As shown. Figure 6 The fabrication process of VCSEL300 is demonstrated, specifically including the formation of a top DBR 310 and metal contacts 320 on the light-emitting structure 200. The top DBR reflector is fabricated using a lift-off process: first, a dielectric DBR layer formed by sputtering is uniformly deposited on the surface, followed by patterning with photoresist, and finally, the DBR layer in the photoresist area is lifted off using a solvent. Therefore, the top DBR is only retained in the original photoresist aperture area. The top DBR reflector can also be achieved by overall sputtering deposition followed by patterned dry etching to remove the DBR layer outside the target area. The metal contacts 320 are formed by a metal stack lift-off process using electro-optical evaporation deposition.

[0201] Analysis of the characteristics of light emitting structures with buried tunnel junctions (BTJ) and vertical cavity surface emitting lasers (VCSEL) Discussion: To verify the current aperture effect of the BTJ structure, the current-voltage (IV) characteristics of a DBR reflector light-emitting structure containing BTJ (10 μm in diameter) were compared with those of a control light-emitting structure without BTJ. Measurements were performed on both devices before the top dielectric DBR deposition. The BTJ-free device was used to simulate the structure outside the aperture region. Figure 7The IV curves of these two devices are summarized, showing that the current value of the device with BTJ (solid line) at 2V is 5 times that of the device without BTJ (dashed line). This indicates that the current is mainly confined to the BTJ or aperture region in the light-emitting structure 200 containing the DBR reflector. It is noteworthy that the current of the device without BTJ is much higher than the reported value in the literature (Journal of Applied Physics, Vol. 39, 2000), which may be due to the penetration effect of the p-type InP layer. When a large forward bias (>1.5V) is applied, the pn junction between layers 140 and 170 is in a reverse bias state, and the p-type InP layer (layer 120) is completely depleted. Electrons from the n-type InP layer (layer 120) are swept across the p-type InP layer, resulting in a high current in the device without BTJ.

[0202] On the probe station, multiple VCSEL300 devices (at least 10, up to 10,000 to millions, depending on wafer size) were fabricated and tested at the wafer level. All tests were performed in continuous wave (CW) mode. The current source used for characterization was a Keithley 2400, and optical power measurements were performed using a photodiode (Thorlab S122C) positioned directly above the device under test. This photodiode was calibrated using an independent commercial 1,550 nm EEL light source and compared with factory calibration values, showing good agreement. Figure 8a shows the relationship between the optical output power and the injection current or current density (LI or LJ) of the 6 μm diameter aperture device. A clear laser threshold current density of 2.37 kA / cm² was measured. Figure 8b shows the single-laser mode emission spectrum (wavelength approximately 1,553 nm) acquired using a Thorlab OSA 203, operating above the laser threshold. The linewidth reached 63 pm when the current density exceeded the threshold. The side-mode rejection ratio (SMSR) exceeded 30 dB. The output power is several orders of magnitude lower than the short-wave infrared band value reported in the literature. In addition to the large leakage current outside the hole region, the fabricated VCSEL300 device also has the following problems: 1) The reflectivity of the top dielectric mirror is too high (about 99.9%), which is presumably negatively affected the cavity light extraction; 2) An oxide layer may form at the interface between layers 260 and 270, which hinders effective current injection and may lead to increased device resistance and internal heating.

[0203] In summary, the fabricated VCSEL300 device employs a bottom-mounted DBR mirror based on NP-type InP, with its BTJ structure achieving current confinement. Single-mode VCSEL operation at approximately 1,553 nm wavelength was achieved at room temperature, with a threshold current density of 2.37 kA / cm² and a narrow linewidth of 63 pm observed in continuous-wave operation.

[0204] Example 2: A nm-sized porous vertical-cavity surface-emitting laser (VCSEL) with a porous region formed by ion implantation. Materials and Methods: Unlike the BJT structure used in Example 1, the second VCSEL structure employs a light-emitting structure, including a bottom-sided double-ended reflector (DBR) mirror based on nanopore (NP)InP and a hole region.

[0205] like Figure 9 As shown, a light-emitting structure including a distributed Bragg reflector (DBR) mirror was fabricated based on the epitaxial growth structure 400. All layers were grown in a planar continuous manner. From bottom to top, structure 400 consists of seven parts: (1) a stack 410 consisting of 12 pairs of alternating layers, namely n+ type InP layers (dark band, doping concentration: 5×10⁻⁶). 18 cm -3 ) and n-type InP layer (light-colored band, low doping, doping concentration: <5×10) 18 cm -3 ), where the n+ type InP layer can be electrochemically etched to form NP type InP with a low refractive index (its refractive index is lower than that of the layer before porosification); (2) Thick n type InP layer 420 (light gray, doping concentration: 5×10 17 cm -3 (3) The light-emitting structure 430 is InAlGaAs, which constitutes the active region with a target emission wavelength of 1,550 nm; (4) The p-type InAlAs layer 440 (doping concentration: 1×10⁻⁶) has a thickness of at least about 200 nm; (5) The light-emitting structure 430 is InAlGaAs, which constitutes the active region with a target emission wavelength of 1,550 nm; (6) The p- 18 cm -3 (5)p ++ Type 450 InAlAs layer (doping concentration > 10 × 10) 18 cm -3 (6)n ++ Type 460 InP layer (black, doping concentration > 1 × 10⁻⁶) 18 cm -3 ); and (7) the top n-type InP layer 470 (light gray, doping concentration: 2×10⁻⁶). 18 cm -3 Structure 400 was grown by metal-organic chemical vapor deposition (MOCVD).

[0206] Figure 10 This paper demonstrates a non-limiting fabrication process for an NP InP vertical-cavity surface-emitting laser (VCSEL), starting with an epitaxial structure of 400 ( Figure 10 The top leftmost row), where a SiO2 (510) layer is deposited on the top surface of structure 400 and patterned with photoresist (520) to define the location of the hole region ( Figure 10(Top row, middle). Ion implantation (H+; 530) was then performed to disrupt / reduce the conductivity of the outer 440 layer in the hole region. Ion implantation was performed at 38-45 kEV energies with an implantation dose of 6.4 × 10⁻⁶. 13 cm -3 In other words, ion implantation will not occur in the areas covered by layers 510 and 520. Typical implantation depths can reach 430 layers. For example, Figure 11 The distribution of doping-induced defects is shown based on stop-and-range (SRIM) simulations of ions in the material, with layer boundaries marked by black dashed lines. It is evident that the top n-type InP layer (layer 470) suffers some damage during ion implantation. According to the literature ("Ion Implantation Techniques for Isolation of Group III-V Semiconductors," Materials Science Reports, Vol. 4 (1990)), InAlAs requires a higher annealing temperature than InP to recover its conductivity. Based on this difference, the conductivity of the top n-type InP layer can be selectively restored through annealing while maintaining the resistive properties of the InAlAs layer 440.

[0207] A self-aligned process is employed, in which the patterned mask formed by layers 510 and 520 simultaneously acts as a mask. A portion of layer 470 is removed by dry etching, leaving the patterned mask coverage area above the remaining surface of layer 470. This structure can be considered as having a stepped feature 540, providing an optical confinement effect for optoelectronic devices. The ion implantation region 535 is also illustrated (see figure). Figure 10 (Second row, far left). During dry etching, the area outside the aperture region is etched by approximately 20 nm, thereby forming a refractive index guide for the optical mode and helping to lower the threshold. After removing the mask material, a PECVD SiO2 layer 550 is deposited on a portion of the surface, and the structure is annealed at 350°C for 20 minutes. Figure 10 The second line is centered. Annealing is believed to restore the conductivity of layer 470, which was damaged by ion implantation. Subsequently, a mesa structure 560 is formed using a wet etching process: first, wet chemical etching is performed with a diluted hydrochloric acid solution, followed by treatment with a citric acid + hydrogen peroxide solution, extending the bottom of the steps to layer 420. Figure 10 The rightmost area in the second row. A PECVD SiO2 layer (570) was then deposited and patterned, covering most of the surface except for the leftmost area. This layer serves both as a mask for subsequent dry etching and as a protection for the mesa structure from erosion during electrochemical etching. Figure 10 (Third row, far left). In other words, SiO2570 deposition covers the entire mesa structure, except for the top sidewall edge area which is not covered by SiO2570. Deep dry etching is performed using SiO2570 as a mask to form trenches reaching the bottom of the periodic layers (stack 410). Figure 10 (Middle of the third line). The structure (anode) and platinum (Pt) wire / plate (cathode) were then immersed in the electrolyte for electrochemical (EC) etching. Figure 10(Rightmost line of the third row). By applying a positive bias to the structure, electrochemical etching is initiated from the sidewalls of the trench. The porosity region (dark area) extends laterally, eventually covering the entire hole region above. Notably, the porosity is limited to n of stack 410. + A porous InP layer exists, while a lightly doped InP layer remains intact (unporosized). The selectivity between porous and non-porosized regions is achieved through the difference in doping concentration. Porosity leads to n + The high-refractive-index InP layer is filled with air and has a lower refractive index than the lightly doped InP layer. The alternating high-refractive-index and low-refractive-index layers form a mirror in the DBR structure, which is used to fabricate a vertical-cavity surface-emitting laser (VCSEL). A 600 nm PECVD SiO2 layer (580) is then deposited to form a uniform and complete capping layer on the exposed sidewalls. Figure 10 continued (Left side of bottom row). The SiO2 layer 580 has a dual function: 1) as a passivation layer for the mesa sidewalls; 2) as a protective layer for the electrochemical etching sidewalls, preventing solvents in subsequent wet chemical steps from penetrating into the nanoporous InP structure in the stack 410. Finally, by forming openings in the SiO2 layer 580 on the top and sides of the mesa structure, a light-emitting structure 600 including a DBR reflector is constructed. These openings are used to place metal contacts and deposit the top dielectric DBR, such as... Figure 10 continued As shown at the bottom right of the figure.

[0208] Figure 12 The light-emitting structure 600, including the DBR reflector, is shown in detail. From bottom to top, the light-emitting structure 600 consists of the following parts: (1) a bottom structure 610, consisting of 12 pairs of alternating n + Type InP layer and n - It consists of InP layers, where n + (1) The n-type InP layer is selectively porosified by electrochemical etching (as shown by the dark band); (2) A thick n-type InP layer 620 with a thickness of at least about 200 nm; (3) A tapered structure from bottom to top including: an InAlGaAs layer 630 providing an active region for the target emission wavelength of 1,550 nm; a p-type InAlAs layer 640; a p++ type InAlAs layer 650; n ++ The structure comprises an n-type InP layer 660; an n-type InP current diffusion layer 670 on top, wherein the top surface of the current diffusion layer 670 includes a stepped feature 680. The mesa structure internally comprises p-type InAlAs, p... ++ Type InAlAs, n ++ The aperture region formed by the in-type InP and n-type InP portions is partially shown as regions 645, 655, and 665 below the step feature 680. Outside the aperture region, p-type InAlAs and p-type InAlAs... ++ Type InAlAs, n ++The conductivity of the type-2 InP and n-type InP layers is reduced by ion implantation, and then the conductivity of the n-type InP current diffusion layer, at least covering the hole region, is restored by annealing. Figure 12 The additional layer shown includes a layer of SiO2 (690), which is present due to the manufacturing process but is not essential to the function of the light-emitting structure or the DBR reflector included therein.

[0209] like Figure 13 As shown, a vertical-cavity surface-emitting laser (VCSEL) 700 is formed using a light-emitting structure 600 including a double-layer reflector mirror. The light-emitting structure 600 internally includes a double-layer thin-film reflector, constituting the bottom reflector of the VCSEL; as shown... Figure 13 As shown, the top of the platform structure is provided with a top dielectric double-layer thin film reflector 710 and a metal electrode 720. Figure 14 The fabrication process of the VCSEL300 is demonstrated, specifically including the formation of a top double-layer thin-film reflector 710 and a metal electrode 720 on the light-emitting structure 600. The top DBR reflector is fabricated using a lift-off method: first, a dielectric DBR layer formed by sputtering is uniformly deposited on the surface, followed by DBR deposition in the photoresist patterned area, and finally, the DBR on the photoresist is lifted off using a solvent. Therefore, the top DBR is only retained in the previously formed PR opening area. The top DBR reflector can also be formed by patterned dry etching after overall sputtering deposition to remove the DBR layer outside the target area. The metal contacts 720 are formed by lift-off of a metal stack deposited by electro-optical evaporation.

[0210] Analysis and discussion of the light-emitting structure and characteristics of the vertical-cavity surface-emitting laser in the ion-implanted aperture region: To verify the effectiveness of ion implantation in achieving current confinement, two sets of light-emitting structures were fabricated: one set had a current aperture region with a diameter of 10 μm, while the other set did not have this region. Both sets of structures employed NP-type InP substrate dual-reflective thin-film mirrors with porous regions. Figure 15 The forward IV curves of these two devices are shown. The results show that at 2V, the current value of the device with the current aperture region (such as the light-emitting structure 600 with DBR mirror) is nearly three orders of magnitude higher than that of the device without the aperture region, confirming that the current is successfully confined within the aperture region.

[0211] Two vertical-cavity surface-emitting lasers (VCSELs) with different structures were designed, with emission wavelengths of 1,380 nm and 1,550 nm, respectively. Both employed... Figure 10 The same manufacturing process was used. The fully fabricated VCSEL device was subjected to wafer-level testing on a probe station. All tests were performed in continuous wave (CW) mode. A Keithley 2400 current source was used for characterization, and optical power measurements were performed using a photodiode (Thorlab S122C) positioned directly above the device.

[0212] Figure 16a shows the current-voltage-power curves of a 1,380 nm vertical-cavity surface-emitting laser (VCSEL) device with a 7 μm aperture. Its threshold current is 0.5 mA, equivalent to 1.3 kA / cm². 2 The current density was measured, and the slope efficiency was approximately 0.23 W / A. The power conversion efficiency of the device reached a peak of 10.4% at an injection current of 2.5 mA. The laser spectrum was acquired using a Thorlab OSA 203 acquisition unit, as shown in Figure 16b. Experiments observed that in single-mode operation, the side-mode rejection ratio (SMSR) was close to 30 dB. When the injection current increased from 0.5 mA (threshold) to 8 mA (near the thermal inversion point), a redshift in the laser wavelength occurred due to device heating.

[0213] Similarly, a 1,550 nm VCSEL was also achieved for room-temperature continuous-wave operation by scaling all dimensions to wavelength using another InP VCSEL structure. Figures 17a and 17b show the LIV curves and laser spectrum of the 7 μm aperture device, respectively. The threshold current is 0.67 mA, equivalent to 1.7 kA / cm². 2 The current density was [not specified], and the slope efficiency was approximately 0.15 W / A. The threshold current density of the 1,550 nm VCSEL was significantly higher, and the slope efficiency was lower (compared to the 1,380 nm device). This was likely due to the unoptimized process of the top dielectric DBR (a-Si:H / SiO2) mirror during the deposition of the 1,550 nm device, which was subsequently corrected in the subsequent processes of the 1,380 nm device. Nevertheless, the device still achieved single-mode operation with a side-mode rejection ratio (SMSR) exceeding 30 dB.

[0214] in conclusion: Examples 1 and 2 above illustrate the concept of constructing a light-emitting structure containing an NP-type InP dual-sided reflector (DBR) using two different current-limited forming processes, thereby enabling an operational demonstration of a continuous-wave vertical-cavity surface-emitting laser (CW VCSEL). These exemplary VCSELs achieve room-temperature continuous-wave operation in the short-wave infrared (SWIR) band, with a threshold current density of approximately 1 kA / cm², milliwatt-level output power, and a power conversion efficiency (PCE) of 10%.

[0215] Unless otherwise defined, all technical terms used herein have the meanings generally accepted by those skilled in the art to which this invention pertains. All references and materials cited herein are explicitly incorporated by way of reference.

[0216] Those skilled in the art will recognize, or can be determined through routine experiments, that numerous equivalent solutions exist for specific embodiments of the present invention. All such equivalent solutions should be covered by the following claims.

Claims

1. A semiconductor structure including a buried tunnel junction (BTJ), said semiconductor structure comprising: The bottom structure comprises alternating n-type doped layers and undoped or lightly doped semiconductor layers on a semiconductor substrate; The n-type doped first semiconductor layer is located at the top of the bottom structure; A light-emitting structure, the light-emitting structure comprising multiple quantum wells (MQWs) located on top of the n-type doped first semiconductor layer; The p-type doped first semiconductor layer is located on top of the light-emitting structure; as well as A buried tunnel junction (BTJ) exists on the p-type doped first semiconductor layer. The embedded tunnel structure includes: p-type doped second semiconductor layer, the p-type doped second semiconductor layer having a density greater than about 1 × 10⁻⁶ 18 cm -3 p-type doping level; An n-type doped second semiconductor layer is located on top of the p-type doped second semiconductor layer, the n-type doped second semiconductor layer having a density greater than approximately 1 × 10⁻⁶. 18 cm -3 n-type doping level; Wherein at least the n-type doped second semiconductor layer has a surface area smaller than the surface area of ​​the p-type doped first semiconductor layer; Optionally, the p-type doped second semiconductor layer and the n-type doped second semiconductor layer have equal or substantially equal areas on the p-type doped first semiconductor layer; An n-type doped current diffusion layer is provided, wherein the n-type doped current diffusion layer encapsulates at least a portion of the n-type doped second semiconductor layer, and optionally also encapsulates at least a portion of the p-type doped second semiconductor layer; The current diffusion layer, excluding the portion thereof having the n-type doped second semiconductor layer, contacts the p-type doped second semiconductor or the p-type doped first semiconductor; and The surface of the current diffusion layer may optionally include a region above the embedded tunnel junction, the region being raised and forming a stepped feature to provide an optical confinement effect.

2. The semiconductor structure of claim 1, wherein the semiconductor substrate is composed of indium phosphide, gallium arsenide, or gallium antimonide.

3. The semiconductor structure according to any one of claims 1-2, wherein the n-type doped semiconductor layers in the bottom structure each have the same thickness; and / or the undoped or lightly doped semiconductor layers in the bottom structure each have the same thickness.

4. The semiconductor structure according to any one of claims 1 to 3, wherein the alternating layers of the bottom structure comprise a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, and gallium antimonide; and wherein the alternating layers are lattice-matched with the semiconductor substrate.

5. The semiconductor structure according to any one of claims 1 to 4, wherein, The alternating layers of the bottom structure comprise ternary semiconductor materials that match the lattice of the semiconductor substrate.

6. The semiconductor structure according to any one of claims 1 to 4, wherein the alternating layers of the bottom structure comprise a quaternary semiconductor material that matches the lattice of the semiconductor substrate.

7. The semiconductor structure according to any one of claims 1 to 6, wherein the n-type doped first semiconductor, the light-emitting structure, the p-type doped first semiconductor, the p-type doped second semiconductor, the n-type doped second semiconductor, and the current diffusion layer comprise one or more semiconductor materials that are lattice-matched with the semiconductor substrate.

8. The semiconductor structure of claim 7, wherein the one or more semiconductor materials are lattice-matched with an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or the semiconductor material is lattice-matched with a gallium arsenide semiconductor substrate and is selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or the semiconductor material is lattice-matched with a gallium antimonide semiconductor substrate and is selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

9. The semiconductor structure according to any one of claims 1 to 6, wherein the light-emitting structure, the p-type doped second semiconductor layer and the n-type doped second semiconductor layer each comprise one or more semiconductor materials that are lattice mismatched with the semiconductor substrate.

10. The semiconductor structure of claim 9, wherein the one or more semiconductor materials are lattice mismatched with the indium phosphide semiconductor substrate and are selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the one or more semiconductor materials are lattice mismatched with the gallium arsenide semiconductor substrate and are selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the one or more semiconductor materials are lattice mismatched with the gallium arsenide semiconductor substrate and are selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

11. A method for manufacturing a semiconductor structure including a buried tunnel junction (BTJ), the method comprising the steps of: (i) A bottom structure is formed on a semiconductor substrate, the bottom structure comprising alternating n-type doped layers and undoped or lightly doped semiconductor layers; (ii) Deposit an n-type doped first semiconductor layer on top of the bottom structure; (iii) Depositing or forming a light-emitting structure including multiple quantum wells (MQWs) on top of the first semiconductor layer; (iv) Deposit a p-type doped first semiconductor layer on top of the light-emitting structure; (v) A p-type doped second semiconductor layer is deposited on top of the p-type doped first semiconductor layer, the p-type doped second semiconductor layer having a density greater than approximately 1 × 10⁻⁶. 18 cm -3 p-type doping concentration; (vi) Deposit an n-type doped second semiconductor layer on top of the p-type doped second semiconductor layer, the n-type doped second semiconductor layer having a density greater than approximately 1 × 10⁻⁶. 18 cm -3 n-type doping concentration; (vii) A mask material is formed or patterned over the top surface region of the n-type doped second semiconductor layer; (viii) At least the n-type doped second semiconductor layer is removed by etching, and optionally the p-type doped second semiconductor layer thereon other than the surface portion having the mask material is removed; (ix) Remove the mask material; as well as (x) Deposit an n-type doped current diffusion layer, wherein the n-type doped current diffusion layer at least covers a portion of the n-type doped second semiconductor layer, and optionally covers a portion of the p-type doped second semiconductor layer, wherein the current diffusion layer outside the surface portion contacts the p-type doped second semiconductor layer or the p-type doped first semiconductor layer.

12. The method of claim 11, wherein any structure or layer can be independently formed or deposited by metal-organic vapor deposition (MOCVD), molecular beam epitaxy (MBE), or liquid phase epitaxy (LPE).

13. The method of any one of claims 11-12, wherein the mask material is selected from the group consisting of dielectric materials and / or photoresists, such as silicon dioxide, silicon nitride, and aluminum oxide.

14. The method of any one of claims 11-13, wherein the semiconductor substrate is composed of indium phosphide, gallium arsenide, or gallium antimonide.

15. The method of any one of claims 11-14, wherein the n-type doped semiconductor layers in the bottom structure each have the same thickness; and / or the undoped or lightly doped semiconductor layers in the bottom structure each have the same thickness.

16. The method of any one of claims 11 to 15, wherein the alternating layers of the bottom structure comprise a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, or gallium antimonide; and the alternating layers are lattice-matched with the semiconductor substrate.

17. The method of any one of claims 11 to 15, wherein the alternating layers of the bottom structure comprise a ternary semiconductor material that matches the lattice of the semiconductor substrate.

18. The method of any one of claims 11 to 15, wherein the alternating layers of the bottom structure comprise a quaternary semiconductor material that matches the lattice of the semiconductor substrate.

19. The method of any one of claims 11 to 18, wherein the n-type doped first semiconductor, the light-emitting structure, the p-type doped first semiconductor, the p-type doped second semiconductor, the n-type doped second semiconductor, and the current diffusion layer comprise one or more semiconductor materials that are lattice-matched with the semiconductor substrate.

20. The method of claim 19, wherein the one or more semiconductor materials are lattice-matched with an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or the semiconductor material is lattice-matched with a gallium arsenide semiconductor substrate and is selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or the semiconductor material is lattice-matched with a gallium antimonide semiconductor substrate and is selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

21. The method of any one of claims 11-18, wherein the light-emitting structure, the p-type doped second semiconductor layer, and the n-type doped second semiconductor layer each comprise one or more semiconductor materials that are lattice mismatched with the semiconductor substrate.

22. The method of claim 21, wherein the one or more semiconductor materials are lattice mismatched with the indium phosphide semiconductor substrate and are selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the one or more semiconductor materials are lattice mismatched with the gallium arsenide semiconductor substrate and are selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the one or more semiconductor materials are lattice mismatched with the gallium arsenide semiconductor substrate and are selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

23. A light-emitting structure comprising an embedded tunnel junction (BTJ), the light-emitting structure comprising: A bottom reflector structure comprising alternating n-type doped layers and undoped or lightly doped semiconductor layers on the semiconductor substrate; The n-type doped layer is a porous structure and includes multiple pores; and the undoped or low-doped semiconductor layer is a non-porous or substantially non-porous structure. An n-type doped first semiconductor layer disposed on top of the bottom structure; A light-emitting structure, the light-emitting structure comprising multiple quantum wells (MQWs) located on top of the semiconductor layer; The p-type doped first semiconductor layer is located on top of the light-emitting structure; as well as A buried tunnel junction (BTJ) existing on a portion of the p-type doped first semiconductor layer. The embedded tunnel junction defines a borehole region and includes: p-type doped second semiconductor layer, wherein the p-type doped second semiconductor layer has a concentration greater than about 1 × 10⁻⁶. 18 cm -3 p-type doping; The n-type doped second semiconductor layer has a concentration greater than about 1 × 10⁻⁶. 18 cm -3 The n-type doping is located on top of the p-type doped second semiconductor layer; Wherein at least the n-type doped second semiconductor layer has a surface area smaller than the surface area of ​​the p-type doped first semiconductor layer; Optionally, the p-type doped second semiconductor layer and the n-type doped second semiconductor layer have equal or substantially equal areas on the p-type doped first semiconductor layer; An n-type doped current diffusion layer is provided, wherein the n-type doped current diffusion layer encapsulates at least a portion of the n-type doped second semiconductor layer, and optionally encapsulates at least a portion of the p-type doped second semiconductor layer; The current diffusion layer, excluding the portion thereof having the n-type doped second semiconductor layer, contacts the p-type doped second semiconductor or the p-type doped first semiconductor; and The surface of the current diffusion layer may optionally include a region above the embedded tunnel junction, the region being raised and forming a stepped feature, thereby producing an optical confinement effect.

24. The light-emitting structure of claim 23, wherein the semiconductor substrate is composed of indium phosphide, gallium arsenide, or gallium antimonide.

25. The light-emitting structure according to any one of claims 23-24, wherein the n-type doped semiconductor layers in the bottom structure each have the same thickness; and / or the undoped or lightly doped semiconductor layers in the bottom structure each have the same thickness.

26. The light-emitting structure according to any one of claims 23-25, wherein the alternating layers of the bottom structure comprise a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, or gallium antimonide; and the alternating layers are lattice-matched with the semiconductor substrate.

27. The light-emitting structure according to any one of claims 23-25, wherein the alternating layers of the bottom structure comprise a ternary semiconductor material that matches the lattice of the semiconductor substrate.

28. The light-emitting structure of any one of claims 23 to 25, wherein the alternating layers of the bottom structure comprise a quaternary semiconductor material lattice-matched to the semiconductor substrate.

29. The light-emitting structure according to any one of claims 23-28, wherein the n-type doped first semiconductor, the light-emitting structure, the p-type doped first semiconductor, the p-type doped second semiconductor, the n-type doped second semiconductor, and the current diffusion layer comprise one or more semiconductor materials that are lattice-matched with the semiconductor substrate.

30. The light-emitting structure of claim 29, wherein the one or more semiconductor materials are lattice-matched with an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or the semiconductor material is lattice-matched with a gallium arsenide semiconductor substrate and is selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or the semiconductor material is lattice-matched with a gallium antimonide semiconductor substrate and is selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

31. The light-emitting structure according to any one of claims 23-28, wherein the light-emitting structure, the p-type doped second semiconductor layer and the n-type doped second semiconductor layer each comprise one or more semiconductor materials that are lattice mismatched with the semiconductor substrate.

32. The light-emitting structure of claim 31, wherein the one or more semiconductor materials are lattice mismatched with the indium phosphide semiconductor substrate and are selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the one or more semiconductor materials are lattice mismatched with the gallium arsenide semiconductor substrate and are selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the one or more semiconductor materials are lattice mismatched with the gallium arsenide semiconductor substrate and are selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

33. The light-emitting structure according to any one of claims 23-32, wherein the porosity is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% or 90%.

34. The light-emitting structure according to any one of claims 23-33, wherein there is a refractive index contrast (Δn) between the alternating layers, which ranges from about 0.1 to 2 or from about 0.1 to 2.

5.

35. A method for forming a light-emitting structure, comprising the following steps: (i') Setting up or forming a structure including an embedded tunnel junction (BTJ), said structure comprising: The bottom structure comprises alternating n-type doped layers and undoped or lightly doped semiconductor layers on a semiconductor substrate; The n-type doped first semiconductor layer is located at the top of the bottom structure; A light-emitting structure, the light-emitting structure comprising multiple quantum wells (MQWs) located on top of the n-type doped first semiconductor layer; The p-type doped first semiconductor layer located on top of the light-emitting structure; and A buried tunnel junction (BTJ) exists on the p-type doped first semiconductor layer. The embedded tunnel structure includes: p-type doped second semiconductor layer, the p-type doped second semiconductor layer having a density greater than about 1 × 10⁻⁶ 18 cm -3 p-type doping concentration; An n-type doped second semiconductor layer is located on top of the p-type doped second semiconductor layer, the n-type doped second semiconductor layer having a density greater than approximately 1 × 10⁻⁶. 18 cm -3 n-type doping concentration; Wherein at least the surface area of ​​the n-type doped second semiconductor layer is smaller than the surface area of ​​the p-type doped first semiconductor layer; Optionally, the p-type doped second semiconductor layer and the n-type doped second semiconductor layer have equal or substantially equal areas on the p-type doped first semiconductor layer; and An n-type doped current diffusion layer is provided, wherein the n-type doped current diffusion layer encapsulates at least a portion of the n-type doped second semiconductor layer, and optionally encapsulates at least a portion of the p-type doped second semiconductor layer; The current diffusion layer, excluding the portion thereof having the n-type doped second semiconductor layer, contacts the p-type doped second semiconductor or the p-type doped first semiconductor; and The surface of the current diffusion layer may optionally include a region above the embedded tunnel junction, the region being raised and forming a stepped feature to produce an optical confinement effect; (ii') A mesa structure is formed by etching the current diffusion layer, the light-emitting structure, the p-type doped first semiconductor layer, and optionally a portion of the p-type doped second semiconductor layer; (iii') A silicon dioxide layer is deposited over the mesa structure, wherein at least a portion of the n-type doped first semiconductor layer is not covered by the silicon dioxide layer; (iv') Etch the portion not covered by the silicon dioxide layer to form a trench thereby exposing the sidewalls of the alternating layers of the bottom structure; (v') Selectively porosilicate the n-type doped semiconductor layer in the alternating layers of the bottom structure, wherein a plurality of pores are formed, and wherein the undoped or low-doped semiconductor layer is kept pore-free or substantially pore-free. (vi') Deposit one or more materials to cover the trench, the sidewalls, and the sidewalls of the platform structure; (vii') Selectively remove the one or more materials to expose at least a portion of the top of the mesa structure, and optionally expose a portion of the n-type doped first semiconductor covered by the one or more materials; and (viii') Metal contacts are formed on a portion of the top of the mesa structure and optionally on a portion of the n-type doped first semiconductor.

36. The method of claim 35, wherein the porosity formed in step (v') is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

37. The method of any one of claims 35-36, wherein step (v') is performed by electrochemical etching in an electrolyte solution and under an applied bias voltage.

38. The method of claim 37, wherein the electrolyte solution comprises halide ions, hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)2, NH4OH, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof.

39. The method of any one of claims 35-38, wherein the one or more materials are selected from the group consisting of silicon dioxide, alumina, silicon nitride, and spin-coated glass; and / or the one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), polyimide, and photoresist; and combinations thereof.

40. The method of any one of claims 35-39, wherein the metal contact formed in step (viii') comprises a metal selected from Ti, Pt, Au, Ge, Ni, Pd, In and combinations thereof.

41. An optoelectronic device, comprising: The light-emitting structure according to any one of claims 23-34; Top-distributed Bragg reflectors; as well as Metal contacts.

42. The optoelectronic device of claim 41, wherein the top distributed Bragg reflector comprises alternating layers of any of the following: a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2, or combinations thereof.

43. The optoelectronic device according to any one of claims 41-42, wherein the metal contact comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In and combinations thereof.

44. The optoelectronic device according to any one of claims 41-43, wherein the optoelectronic device is a vertical cavity surface-emitting laser (VCSEL).

45. The optoelectronic device of claim 44, wherein the vertical cavity surface-emitting laser operates in continuous wave mode at room temperature (about 25°C).

46. ​​The optoelectronic device of claim 44, wherein the vertical cavity surface-emitting laser operates at a temperature below about 0°C, above about 25°C, or above about 85°C.

47. The optoelectronic device of claim 44, wherein the vertical cavity surface-emitting laser operates in pulsed mode.

48. The optoelectronic device of claim 44, wherein the vertical cavity surface-emitting laser emits in the infrared wavelength region.

49. The optoelectronic device of claim 44, wherein the power conversion efficiency of the vertical cavity surface-emitting laser is at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5% or 10%.

50. A method for manufacturing an optoelectronic device, comprising the following steps: (i”) Setting or forming a light-emitting structure, the light-emitting structure comprising: A bottom reflector structure comprising alternating n-type doped layers and undoped or lightly doped semiconductor layers on a semiconductor substrate; wherein the n-type doped layers are porous and include multiple pores; and wherein the undoped or lightly doped semiconductor layers are non-porous or substantially non-porous. The n-type doped first semiconductor layer is located at the top of the bottom structure; A light-emitting structure, the light-emitting structure comprising multiple quantum wells (MQWs) located on top of the semiconductor layer; The p-type doped first semiconductor layer located on top of the light-emitting structure; and A buried tunnel junction (BTJ) existing on a portion of the p-type doped first semiconductor layer. The embedded tunnel junction defines a borehole region and includes: p-type doped second semiconductor layer, wherein the p-type doped second semiconductor layer has a concentration greater than about 1 × 10⁻⁶. 18 cm -3 p-type doping; The n-type doped second semiconductor layer has a concentration greater than about 1 × 10⁻⁶. 18 cm -3 The n-type doping is located on top of the p-type doped second semiconductor layer; Wherein at least the surface area of ​​the n-type doped second semiconductor layer is smaller than the surface area of ​​the p-type doped first semiconductor layer; Optionally, the p-type doped second semiconductor layer and the n-type doped second semiconductor layer have equal or substantially equal areas on the p-type doped first semiconductor layer; An n-type doped current diffusion layer is provided, wherein the n-type doped current diffusion layer encapsulates at least a portion of the n-type doped second semiconductor layer, and optionally also encapsulates at least a portion of the p-type doped second semiconductor layer; The current diffusion layer, excluding the portion having the n-type doped second semiconductor layer thereon, covers and contacts the p-type doped second semiconductor or the p-type doped first semiconductor; and The surface of the current diffusion layer may optionally include a region above the embedded tunnel junction, the region being raised and forming a stepped feature to produce an optical confinement effect; (ii”) A top distributed Bragg reflector is disposed or formed on the light-emitting structure; and (iii) Metal contacts are provided or formed on the optoelectronic device.

51. The method of claim 50, wherein the top distributed Bragg reflector in step (ii”) comprises alternating layers of any of the following: a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2, or combinations thereof.

52. The method according to any one of claims 50-51, wherein the metal contact in step (iii”) comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In and combinations thereof.

53. The method of any one of claims 50 to 52, wherein the optoelectronic device is a vertical cavity surface-emitting laser (VCSEL).

54. A light-emitting structure, comprising: A bottom reflector structure comprising alternating n-type doped layers and undoped or lightly doped semiconductor layers on a semiconductor substrate; wherein the n-type doped semiconductor layers are porous and include multiple pores; and wherein the undoped or lightly doped semiconductor layers are non-porous or substantially non-porous. The n-type doped first semiconductor layer is located at the top of the bottom structure; A light-emitting structure, the light-emitting structure comprising multiple quantum wells (MQWs) located on top of the semiconductor layer; The p-type doped first semiconductor layer is located on top of the light-emitting structure; A p-type doped second semiconductor layer is located on top of the p-type doped first semiconductor layer, the p-type doped second semiconductor layer having a concentration greater than about 1 × 10⁻⁶. 18 cm -3 p-type doping; An n-type doped second semiconductor layer is located on top of the p-type doped second semiconductor layer, the n-type doped second semiconductor layer having a concentration greater than about 1 × 10⁻⁶. 18 cm -3 n-type doping; An n-type doped current diffusion layer located on top of the n-type doped second semiconductor layer; There exists a hole region, wherein the conductivity of the p-type doped first semiconductor layer within the hole region is greater than the conductivity of the p-type doped first semiconductor layer outside the hole region; Wherein, the resistivity of the p-type doped first semiconductor layer, the optional p-type doped second semiconductor layer, and the optional n-type doped semiconductor layer outside the hole region is higher than that inside the hole region; The current diffusion layer is conductive both inside and outside the hole; and The current diffusion layer may optionally include a region on the top surface above the aperture region, the region being raised and forming a stepped feature to provide an optical confinement effect.

55. The light-emitting structure of claim 54, wherein the semiconductor substrate is composed of indium phosphide, gallium arsenide, or gallium antimonide.

56. The light-emitting structure according to any one of claims 54-55, wherein the n-type doped semiconductor layers in the bottom structure each have the same thickness; and / or the undoped or lightly doped semiconductor layers in the bottom structure each have the same thickness.

57. The light-emitting structure of claim 54, wherein the alternating layers of the bottom structure comprise a binary semiconductor material lattice-matched to the semiconductor substrate.

58. The light-emitting structure of claim 54, wherein the alternating layers of the bottom structure comprise a ternary semiconductor material lattice-matched to the semiconductor substrate.

59. The light-emitting structure of claim 54, wherein the alternating layers of the bottom structure comprise a quaternary semiconductor material lattice-matched to the semiconductor substrate.

60. The light-emitting structure according to any one of claims 54 to 59, wherein the n-type doped first semiconductor, the light-emitting structure, the p-type doped first semiconductor, the p-type doped second semiconductor, the n-type doped second semiconductor, and the current diffusion layer each independently comprise one or more materials lattice-matched with the semiconductor substrate.

61. The light-emitting structure of claim 60, wherein the one or more materials are lattice-matched with an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or the one or more semiconductor materials are lattice-matched with a gallium arsenide semiconductor substrate and are selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or the one or more semiconductor materials are lattice-matched with a gallium arsenide semiconductor substrate and are selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

62. The light-emitting structure as described in claims 54-59, wherein the light-emitting structure, the p-type doped second semiconductor, and the n-type doped second semiconductor each independently comprise one or more materials that are lattice mismatched with the indium phosphide semiconductor substrate.

63. The light-emitting structure of claim 62, wherein the one or more semiconductor materials are lattice mismatched with the indium phosphide semiconductor substrate and are selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the one or more semiconductor materials are lattice mismatched with the gallium arsenide semiconductor substrate and are selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the one or more semiconductor materials are lattice mismatched with the gallium arsenide semiconductor substrate and are selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

64. The light-emitting structure according to any one of claims 54-63, wherein the conductivity of the p-type doped first semiconductor layer outside the aperture region, and optionally the p-type doped second semiconductor layer and optionally the n-type doped second semiconductor layer is about 1-4 orders of magnitude lower than that of the aperture region.

65. The light-emitting structure according to any one of claims 54-64, wherein the porosity is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% or 90%.

66. The light-emitting structure according to any one of claims 54-65, wherein the refractive index contrast (Δn) between the alternating layers in the bottom reflector structure is about 0.1 to 2 or 0.1 to 2.

5.

67. A method for forming a light-emitting structure, comprising the following steps: (a) Setting up or forming a structure that includes the following: A bottom structure comprising alternating n-type doped layers and undoped or lightly doped semiconductor layers on a semiconductor substrate; The n-type doped first semiconductor layer is located at the top of the bottom structure; A light-emitting structure, the light-emitting structure comprising multiple quantum wells (MQWs) located on top of the first semiconductor layer; The p-type doped first semiconductor layer is located on top of the light-emitting structure; p-type doped second semiconductor layer, wherein the p-type doped second semiconductor layer has a concentration greater than about 1 × 10⁻⁶. 18 cm -3 The p-type doping is located on top of the p-type doped first semiconductor layer; The n-type doped second semiconductor layer has a concentration greater than about 1 × 10⁻⁶. 18 cm -3 The n-type doping is located on top of the p-type doped second semiconductor layer; as well as An n-type doped current diffusion layer located on top of the n-type doped second semiconductor layer; (b) Place a mask material above the top surface region of the current diffusion layer of the structure; (c) Perform ion implantation to reduce the conductivity of at least the p-type doped first semiconductor layer not covered by the mask material; (d) Etching a portion of the current diffusion layer, wherein the etching does not remove the current diffusion layer beneath the mask material; (e) Remove the mask material; (f) Deposit a first layer of silicon dioxide over a portion of the current diffusion layer to cover the area where at least the mask material is present; (g) Annealing the structure to improve the conductivity of the top layer of the current diffusion layer; (h) A mesa structure is formed by etching the current diffusion layer, the n-type doped second semiconductor, the p-type doped second semiconductor, the p-type doped first semiconductor, and the portion of the light-emitting structure not covered by the first silicon dioxide; (i) depositing a second layer of silicon dioxide over the mesa structure, wherein at least a portion of the n-type doped first semiconductor is not covered by the second layer of silicon dioxide; (j) etching the structure not covered by the second layer of silicon dioxide to form trenches that expose the sidewalls of the alternating layers of the bottom structure; (k) Selectively porosilicate the n-type doped semiconductor layer in the alternating layers of the bottom structure, wherein the formed pores include air, and wherein the undoped or low-doped semiconductor layer remains in a pore-free or substantially pore-free state. (l) Deposit one or more materials to cover the trench, the sidewalls of the trench, and the sidewalls of the platform structure; (m) Selectively remove the one or more materials to expose at least a portion of the top of the mesa structure and optionally expose portions of the semiconductor layer covered by the one or more materials; as well as (n) Metal contacts are formed on a portion of the top of the mesa structure and optionally on a portion of the semiconductor layer.

68. The method of claim 67, wherein the mask material is selected from the group consisting of insulating materials composed of silicon dioxide, aluminum oxide and silicon nitride; or an organic material (such as photoresist); or a metal (such as nickel); or a combination thereof.

69. The method of any one of claims 67-68, wherein the porosity formed in step (k) is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% or 90%.

70. The method of any one of claims 67-69, wherein step (k) is performed by electrochemical etching in an electrolyte solution and under an applied bias voltage.

71. The method of claim 70, wherein the electrolyte solution comprises halide ions, hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)2, NH4OH, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof.

72. The method of any one of claims 67-71, wherein the one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide and silicon nitride; and / or the one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), polyimide and photoresist; and combinations thereof.

73. The method of any one of claims 67-72, wherein the metal contact comprises a metal selected from Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

74. An optoelectronic device, comprising: The light-emitting structure according to any one of claims 54-66; Top-distributed Bragg reflectors; as well as Metal contacts.

75. The optoelectronic device of claim 74, wherein the top distributed Bragg reflector comprises alternating layers consisting of any one of the following: a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2, or combinations thereof.

76. The optoelectronic device according to any one of claims 74-75, wherein the metal contact comprises a metal selected from Ti, Pt, Au, Ge, Ni, Pd, In and combinations thereof.

77. The optoelectronic device according to any one of claims 74-76, wherein the optoelectronic device is a vertical cavity surface-emitting laser (VCSEL).

78. The optoelectronic device of claim 77, wherein the vertical cavity surface-emitting laser operates in continuous wave mode at room temperature (about 25°C).

79. The optoelectronic device of claim 77, wherein the vertical cavity surface-emitting laser operates at a temperature below about 0°C, above about 25°C, or above about 85°C.

80. The optoelectronic device of claim 77, wherein the vertical cavity surface-emitting laser operates in pulsed mode.

81. The optoelectronic device of claim 77, wherein the vertical cavity surface-emitting laser emits in the infrared and / or red wavelength region.

82. The optoelectronic device of claim 77, wherein the power conversion efficiency of the vertical cavity surface-emitting laser is at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

83. A method for manufacturing an optoelectronic device, comprising the following steps: (a') Setting or forming a light-emitting structure, including: A bottom reflector structure comprising alternating n-type doped layers and undoped or lightly doped semiconductor layers on a semiconductor substrate; wherein the n-type doped semiconductor layers are porous and include multiple pores; and the undoped or lightly doped semiconductor layers are non-porous or substantially non-porous. The n-type doped first semiconductor layer is located at the top of the bottom structure; A light-emitting structure, the light-emitting structure comprising multiple quantum wells (MQWs) located on top of the semiconductor layer; The p-type doped first semiconductor layer is located on top of the light-emitting structure; A p-type doped second semiconductor layer is located on top of the p-type doped first semiconductor layer, the p-type doped second semiconductor layer having a concentration greater than about 1 × 10⁻⁶. 18 cm -3 p-type doping; An n-type doped second semiconductor layer is located on top of the p-type doped second semiconductor layer, the n-type doped second semiconductor layer having a concentration greater than about 1 × 10⁻⁶. 18 cm -3 n-type doping; An n-type doped current diffusion layer located on top of the n-type doped second semiconductor layer; There exists a hole region, wherein the conductivity of the p-type doped first semiconductor layer within the hole region is greater than the conductivity of the p-type doped first semiconductor layer outside the hole region; The p-type doped first semiconductor layer, the optional p-type doped second semiconductor layer, and the optional n-type doped second semiconductor layer have higher resistivity outside the hole region than inside the hole region. The current diffusion layer is conductive both inside and outside the aperture region; and The current diffusion layer may optionally include a region on the top surface above the aperture region, the region being raised and forming a stepped feature to provide an optical confinement effect; (b') To provide or form a top distributed Bragg reflector on the light-emitting structure; and (c') A metal contact is provided or formed on the optoelectronic device.

84. The method of claim 83, wherein the top distributed Bragg reflector in step (b') comprises alternating layers of any of the following: a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2, or combinations thereof.

85. The method of any one of claims 83-84, wherein the metal contact in step (c') comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In and combinations thereof.

86. The method of any one of claims 83-85, wherein the optoelectronic device is a vertical-cavity surface-emitting laser (VCSEL).

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