Pre-voltage-stabilizing circuit and high-voltage driving chip

Abstract

The invention is suitable for the field of integrated circuits, and provides a pre-voltage-stabilizing circuit and a high-voltage driving chip. The pre-voltage-stabilizing circuit comprises a bias current generating circuit, a current comparison circuit and a power level circuit, and the bias current generating circuit comprises a first PMOS power tube, a second PMOS power tube, a first NMOS power tube, a first triode and a first resistor. The current comparison circuit comprises a third PMOS (P-channel Metal Oxide Semiconductor) power tube, a fourth PMOS power tube, a fifth PMOS power tube, a sixth PMOS power tube, a second NMOS (N-channel Metal Oxide Semiconductor) power tube, a third NMOS power tube, a fourth NMOS power tube, a fifth NMOS power tube, a sixth NMOS power tube and a first voltage stabilizing diode; and the power level circuit comprises a seventh PMOS power tube, a seventh NMOS power tube, a second voltage stabilizing diode and a first capacitor. The pre-voltage-stabilizing circuit can provide voltage equal to an input power supply to supply power to an internal circuit when working at low voltage, the low-voltage performance of a high-voltage driving chip is improved, the working voltage range of a system is widened, the circuit structure is simple, oscillation sources such as a charge pump are not needed, the EMI characteristic is good, the integration degree is high, and the cost is low.

Description

Technical Field

[0001] This application belongs to the field of integrated circuits, and in particular relates to a pre-regulated circuit and a high-voltage driver chip. Background Technology

[0002] In high-voltage driver chips, a typical architecture includes a power drive output stage located in the high-voltage domain and a logic control section (such as a reference source and protection circuits) located in the low-voltage domain. To provide a supply voltage of approximately 5V to the logic control section under high supply voltage conditions, the traditional solution is to use a pre-regulator circuit, the general structure of which is as follows: Figure 1 As shown: Resistors Zener diode This forms a voltage bias, which becomes a high-voltage power transistor after the input power supply VM is powered on. Providing a gate voltage enables the pre-regulated output voltage. ,in, Zener diode Reverse breakdown voltage when operating in reverse breakdown mode High-voltage power transistor The threshold voltage. Due to the Zener diode. When operating in reverse breakdown mode, the voltage across its terminals remains around 6V, therefore A stable voltage of around 5V can be obtained. However, when the input power supply voltage is lower than that of the Zener diode... At the breakdown voltage, Only output The voltage, one Voltage loss limits the low-voltage performance of high-voltage driver chips.

[0003] To address the issue of voltage loss limiting the low-voltage performance of high-voltage driver chips, oscillators and charge pump circuits are often added to boost the performance of the high-voltage power transistor. Gate voltage, such as Figure 2 As shown, although this solution improves the low-voltage performance of the high-voltage driver chip, the additional circuitry increases the chip area, which is not conducive to integration, and the addition of oscillation sources such as charge pumps will worsen the EMI characteristics of the high-voltage driver chip. Summary of the Invention

[0004] The purpose of this application is to provide a pre-regulator circuit and a high-voltage driver chip, which aims to solve the problems that the pre-regulator circuit of the prior art limits the low-voltage performance of the high-voltage driver chip, or although it improves the low-voltage performance of the high-voltage driver chip, the additional circuit increases the chip area, which is not conducive to integration, and the addition of oscillation sources such as charge pumps will worsen the EMI characteristics of the high-voltage driver chip.

[0005] In a first aspect, this application provides a pre-regulator circuit, including a bias current generating circuit, a current comparison circuit, and a power stage circuit, wherein the bias current generating circuit includes a first PMOS power transistor. Second PMOS power transistor First NMOS power transistor First transistor and the first resistor The current comparison circuit includes a third PMOS power transistor. Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor Second NMOS power transistor Third NMOS power transistor Fourth NMOS power transistor Fifth NMOS power transistor The sixth NMOS power transistor and the first Zener diode The power stage circuit includes the seventh PMOS power transistor. 7th NMOS power transistor Second Zener diode and the first capacitor Among them, the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor and the seventh PMOS power transistor The source and the seventh NMOS power transistor The drains of both transistors are connected to the input power supply VM; the first transistor... emitter, first resistor One end, the second NMOS power transistor The source of the third NMOS power transistor The source of the fourth NMOS power transistor The source of the sixth NMOS power transistor The source, the first capacitor One end and the second Zener diode The anodes of all transistors are grounded; the first PMOS power transistor The drain of the first transistor is connected collector and first NMOS power transistor The gate of the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor and the fourth PMOS power transistor The gate of the second PMOS power transistor is connected to the gate of the first PMOS power transistor. The gate and drain of the second PMOS power transistor are connected. The drain of the first NMOS power transistor is connected. The drain of the first NMOS power transistor The source and the first transistor The base of each is connected to the first resistor. The other end; the third PMOS power transistor The drain of the second NMOS power transistor is connected. The drain of the second NMOS power transistor The gate and drain of the second NMOS power transistor are connected. The gate is also connected to the sixth NMOS power transistor. The gate of the fourth PMOS power transistor; The drain is connected to the first Zener diode. Cathode, fifth NMOS power transistor The gate and the seventh NMOS power transistor The gate of the first Zener diode; The anode is connected to the third NMOS power transistor. The drain of the third NMOS power transistor The gate and drain of the third NMOS power transistor are connected. The gate of the fourth NMOS power transistor is connected. The gate of the fifth PMOS power transistor; The gate of the sixth PMOS power transistor is connected The gate of the fifth PMOS power transistor The gate and drain are connected, the fifth PMOS power transistor The drain of the fifth NMOS power transistor is connected. The drain of the fifth NMOS power transistor The source is connected to the fourth NMOS power transistor The drain of the sixth PMOS power transistor. The drain of the sixth NMOS power transistor is connected. The drain and the seventh PMOS power transistor The gate of the seventh NMOS power transistor. The source is connected to the first capacitor At the other end, the seventh PMOS power transistor The drain is connected to the second Zener diode. Cathode; Seventh PMOS power transistor The drain and the seventh NMOS power transistor The source terminals are all connected to the pre-regulated output terminals.

[0006] Secondly, this application provides a pre-regulatory circuit, which includes a bias current generation circuit, a current comparison circuit, and a power stage circuit, wherein the bias current generation circuit includes a first PMOS power transistor. Second PMOS power transistor First NMOS power transistor Eighth NMOS power transistor and the first resistor The current comparison circuit includes a third PMOS power transistor. Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor Second NMOS power transistor Third NMOS power transistor Fourth NMOS power transistor Fifth NMOS power transistor The sixth NMOS power transistor The power stage circuit consists of multiple NMOS power transistors connected in series via diodes, with the gate and drain of each NMOS power transistor connected together. The source of the first NMOS power transistor is connected to the drain of the next NMOS power transistor, and so on, until the drain of the last NMOS power transistor is reached. The power stage circuit also includes a seventh PMOS power transistor. 7th NMOS power transistor Second Zener diode and the first capacitor Among them, the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor and the seventh PMOS power transistor The source and the seventh NMOS power transistor The drains of all transistors are connected to the input power supply VM; the eighth NMOS power transistor The source, the first resistor One end, the second NMOS power transistor The source of the third NMOS power transistor The source of the fourth NMOS power transistor The source of the sixth NMOS power transistor The source, the first capacitor One end and the second Zener diode The anodes of all transistors are grounded; the first PMOS power transistor The drain of the eighth NMOS power transistor is connected. The drain and the first NMOS power transistor The gate of the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor and the fourth PMOS power transistor The gate of the second PMOS power transistor is connected to the gate of the first PMOS power transistor. The gate and drain of the second PMOS power transistor are connected. The drain of the first NMOS power transistor is connected. The drain of the first NMOS power transistor The source and the eighth NMOS power transistor The gate of each is connected to the first resistor. The other end; the third PMOS power transistor The drain of the second NMOS power transistor is connected. The drain of the second NMOS power transistor The gate and drain of the second NMOS power transistor are connected. The gate is also connected to the sixth NMOS power transistor. The gate of the fourth PMOS power transistor; The drain of the first NMOS power transistor is connected to the drain of the fifth NMOS power transistor. The gate and the seventh NMOS power transistor The gate of the last NMOS power transistor is connected to the source of the third NMOS power transistor. The drain of the third NMOS power transistor The gate and drain of the third NMOS power transistor are connected. The gate of the fourth NMOS power transistor is connected. The gate of the fifth PMOS power transistor; The gate of the sixth PMOS power transistor is connected The gate of the fifth PMOS power transistor The gate and drain are connected, the fifth PMOS power transistor The drain of the fifth NMOS power transistor is connected. The drain of the fifth NMOS power transistor The source is connected to the fourth NMOS power transistor The drain of the sixth PMOS power transistor. The drain of the sixth NMOS power transistor is connected. The drain and the seventh PMOS power transistor The gate of the seventh NMOS power transistor. The source is connected to the first capacitor At the other end, the seventh PMOS power transistor The drain is connected to the second Zener diode. Cathode; Seventh PMOS power transistor The drain and the seventh NMOS power transistor The source terminals are all connected to the pre-regulated output terminals.

[0007] Thirdly, this application provides a high-voltage driving chip, which includes the aforementioned pre-regulatory circuit.

[0008] The pre-regulator circuit of this application is due to the first Zener diode. The reverse breakdown characteristic and multiple PMOS power transistors, or multiple PMOS power transistors and multiple NMOS power transistors connected in series in a diode configuration. This allows the pre-regulator circuit to provide a voltage equivalent to the input power supply to power the internal circuit even when operating at low voltage, improving the low-voltage performance of the high-voltage driver chip, widening the operating voltage range of the system, and featuring a simple circuit structure, no need for oscillation sources such as charge pumps, good EMI characteristics, high integration, and low cost. Attached Figure Description

[0009] Figure 1 and 2 This is a circuit diagram of a pre-regulated voltage circuit in the prior art.

[0010] Figure 3 This is a schematic diagram of the pre-regulator circuit provided in the first embodiment of this application.

[0011] Figure 4 This is a schematic diagram of the pre-regulator circuit provided in the second embodiment of this application. Detailed Implementation

[0012] To make the objectives, technical solutions, and beneficial effects of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0013] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0014] Please see Figure 3 The pre-regulator circuit provided in the first embodiment of this application includes a bias current generation circuit, a current comparison circuit, and a power stage circuit, wherein the bias current generation circuit includes a first PMOS power transistor. Second PMOS power transistor First NMOS power transistor First transistor and the first resistor The current comparison circuit includes a third PMOS power transistor. Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor Second NMOS power transistor Third NMOS power transistor Fourth NMOS power transistor Fifth NMOS power transistor The sixth NMOS power transistor and the first Zener diode The power stage circuit includes the seventh PMOS power transistor. 7th NMOS power transistor Second Zener diode and the first capacitor Among them, the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor and the seventh PMOS power transistor The source and the seventh NMOS power transistor The drains of both transistors are connected to the input power supply VM; the first transistor... emitter, first resistor One end, the second NMOS power transistor The source of the third NMOS power transistor The source of the fourth NMOS power transistor The source of the sixth NMOS power transistor The source, the first capacitor One end and the second Zener diode The anodes of all transistors are grounded; the first PMOS power transistor The drain of the first transistor is connected collector and first NMOS power transistor The gate of the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor and the fourth PMOS power transistor The gate of the second PMOS power transistor is connected to the gate of the first PMOS power transistor. The gate and drain of the second PMOS power transistor are connected. The drain of the first NMOS power transistor is connected. The drain of the first NMOS power transistor The source and the first transistor The base of each is connected to the first resistor. The other end; the third PMOS power transistor The drain of the second NMOS power transistor is connected. The drain of the second NMOS power transistor The gate and drain of the second NMOS power transistor are connected. The gate is also connected to the sixth NMOS power transistor. The gate of the fourth PMOS power transistor; The drain is connected to the first Zener diode. Cathode, fifth NMOS power transistor The gate and the seventh NMOS power transistor The gate of the first Zener diode; The anode is connected to the third NMOS power transistor. The drain of the third NMOS power transistor The gate and drain of the third NMOS power transistor are connected. The gate of the fourth NMOS power transistor is connected. The gate of the fifth PMOS power transistor; The gate of the sixth PMOS power transistor is connected The gate of the fifth PMOS power transistor The gate and drain are connected, the fifth PMOS power transistor The drain of the fifth NMOS power transistor is connected. The drain of the fifth NMOS power transistor The source is connected to the fourth NMOS power transistor The drain of the sixth PMOS power transistor. The drain of the sixth NMOS power transistor is connected. The drain and the seventh PMOS power transistor The gate of the seventh NMOS power transistor. The source is connected to the first capacitor At the other end, the seventh PMOS power transistor The drain is connected to the second Zener diode. Cathode; Seventh PMOS power transistor The drain and the seventh NMOS power transistor The source terminals are all connected to the pre-regulated output terminals.

[0015] The working principle of the pre-regulator circuit provided in the first embodiment of this application is as follows: When the input power supply VM is powered on, the first resistor This will generate the first bias current. , It is the first transistor. The base voltage of the seventh PMOS power transistor. The gate voltage will be the mirror current of the bias current. Under the influence of this, the pre-regulated output voltage is pulled low, causing the output voltage to be lowered. As the voltage of the input power supply VM gradually increases, when it exceeds that of the first Zener diode... reverse breakdown voltage and the third NMOS power transistor of When the sum of the voltages between the gate and source is reached, the second bias current is... It will gradually increase from 0, and under the action of the current mirror, the sixth PMOS power transistor will... Generate current When the current > At that time, the seventh PMOS power transistor The gate will be pulled up to put it in the off state. By the seventh PMOS power transistor supply, , It is the seventh PMOS power transistor The threshold voltage. Second Zener diode. Its function is when <VM< At that time, the pre-regulated output voltage is made Clamped in the second Zener diode reverse breakdown voltage The above can be summarized in Table 1 below: Table 1 Comparison of Pre-regulated Output Voltages Please see Figure 4 The difference between the pre-regulator circuit provided in the second embodiment of this application and the pre-regulator circuit provided in the first embodiment of this application is that: the first transistor... The eighth NMOS power transistor Replacement, first Zener diode It is replaced by multiple NMOS power transistors connected in series in the form of diodes.

[0016] The pre-regulator circuit provided in the second embodiment of this application includes a bias current generation circuit, a current comparison circuit, and a power stage circuit, wherein the bias current generation circuit includes a first PMOS power transistor. Second PMOS power transistor First NMOS power transistor Eighth NMOS power transistor and the first resistor The current comparison circuit includes a third PMOS power transistor. Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor Second NMOS power transistor Third NMOS power transistor Fourth NMOS power transistor Fifth NMOS power transistor The sixth NMOS power transistor The power stage circuit consists of multiple NMOS power transistors connected in series via diodes, with the gate and drain of each NMOS power transistor connected together. The source of the first NMOS power transistor is connected to the drain of the next NMOS power transistor, and so on, until the drain of the last NMOS power transistor is reached. The power stage circuit also includes a seventh PMOS power transistor. 7th NMOS power transistor Second Zener diode and the first capacitor Among them, the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor and the seventh PMOS power transistor The source and the seventh NMOS power transistor The drains of all transistors are connected to the input power supply VM; the eighth NMOS power transistor The source, the first resistor One end, the second NMOS power transistor The source of the third NMOS power transistor The source of the fourth NMOS power transistor The source of the sixth NMOS power transistor The source, the first capacitor One end and the second Zener diode The anodes of all transistors are grounded; the first PMOS power transistor The drain of the eighth NMOS power transistor is connected. The drain and the first NMOS power transistor The gate of the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor and the fourth PMOS power transistor The gate of the second PMOS power transistor is connected to the gate of the first PMOS power transistor. The gate and drain of the second PMOS power transistor are connected. The drain of the first NMOS power transistor is connected. The drain of the first NMOS power transistor The source and the eighth NMOS power transistor The gate of each is connected to the first resistor. The other end; the third PMOS power transistor The drain of the second NMOS power transistor is connected. The drain of the second NMOS power transistor The gate and drain of the second NMOS power transistor are connected. The gate is also connected to the sixth NMOS power transistor. The gate of the fourth PMOS power transistor; The drain of the first NMOS power transistor is connected to the drain of the fifth NMOS power transistor. The gate and the seventh NMOS power transistor The gate of the last NMOS power transistor is connected to the source of the third NMOS power transistor. The drain of the third NMOS power transistor The gate and drain of the third NMOS power transistor are connected. The gate of the fourth NMOS power transistor is connected. The gate of the fifth PMOS power transistor; The gate of the sixth PMOS power transistor is connected The gate of the fifth PMOS power transistor The gate and drain are connected, the fifth PMOS power transistor The drain of the fifth NMOS power transistor is connected. The drain of the fifth NMOS power transistor The source is connected to the fourth NMOS power transistor The drain of the sixth PMOS power transistor. The drain of the sixth NMOS power transistor is connected. The drain and the seventh PMOS power transistor The gate of the seventh NMOS power transistor. The source is connected to the first capacitor At the other end, the seventh PMOS power transistor The drain is connected to the second Zener diode. Cathode; Seventh PMOS power transistor The drain and the seventh NMOS power transistor The source terminals are all connected to the pre-regulated output terminals.

[0017] The working principle of the pre-regulator circuit provided in the second embodiment of this application is as follows: When the input power supply VM is powered on, the first resistor This will generate the first bias current. , It is the eighth NMOS power transistor The gate-source voltage, and the seventh PMOS power transistor The gate voltage will be the mirror current of the bias current. Under the influence of this, the pre-regulated output voltage is pulled low, causing the output voltage to be lowered. As the input power supply voltage VM gradually increases, when it exceeds the voltage of multiple NMOS power transistors connected in series in a diode configuration... and the third NMOS power transistor of When the sum of the two, the second bias current It will gradually increase from 0, and under the action of the current mirror, the sixth PMOS power transistor will... Generate current When the current > At that time, the seventh PMOS power transistor The gate will be pulled up to put it in the off state. By the seventh PMOS power transistor supply, , It is the seventh PMOS power transistor The threshold voltage, in order to Figure 4 For example, It consists of two NMOS power transistors connected in series. The sum of the numbers, and the number of NMOS power transistors will vary depending on the actual design. Second Zener diode. Its function is when <VM< At that time, the pre-regulated output voltage is made Clamped in the second Zener diode reverse breakdown voltage .

[0018] One embodiment of this application also provides a high-voltage driving chip, which includes the pre-stabilized voltage circuit provided in the first or second embodiment of this application.

[0019] In one embodiment of this application, the first PMOS power transistor Third PMOS power transistor Fourth PMOS power transistor and the seventh PMOS power transistor It is a PLDMOS power transistor capable of withstanding high voltage, and the first NMOS power transistor. Fourth NMOS power transistor Fifth NMOS power transistor The sixth NMOS power transistor and the seventh NMOS power transistor It is an NLDMOS power transistor capable of withstanding high voltage.

[0020] High-voltage driver chips can be used in fields such as motor driving, power conversion, and display driving.

[0021] The pre-regulator circuit of this application is due to the first Zener diode. The reverse breakdown characteristic and multiple PMOS power transistors, or multiple PMOS power transistors and multiple NMOS power transistors connected in series in a diode configuration. This allows the pre-regulator circuit to provide a voltage equivalent to the input power supply to power the internal circuit even when operating at low voltage, improving the low-voltage performance of the high-voltage driver chip, widening the operating voltage range of the system, and featuring a simple circuit structure, no need for oscillation sources such as charge pumps, good EMI characteristics, high integration, and low cost.

[0022] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0023] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A pre-regulated voltage circuit, characterized in that, It includes a bias current generation circuit, a current comparison circuit, and a power stage circuit. The bias current generation circuit includes a first PMOS power transistor. Second PMOS power transistor First NMOS power transistor First transistor and the first resistor The current comparison circuit includes a third PMOS power transistor. Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor Second NMOS power transistor Third NMOS power transistor Fourth NMOS power transistor Fifth NMOS power transistor The sixth NMOS power transistor and the first Zener diode The power stage circuit includes the seventh PMOS power transistor. 7th NMOS power transistor Second Zener diode and the first capacitor Among them, the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor and the seventh PMOS power transistor The source and the seventh NMOS power transistor The drains of both transistors are connected to the input power supply VM; the first transistor... emitter, first resistor One end, the second NMOS power transistor The source of the third NMOS power transistor The source of the fourth NMOS power transistor The source of the sixth NMOS power transistor The source, the first capacitor One end and the second Zener diode The anodes of all transistors are grounded; the first PMOS power transistor The drain of the first transistor is connected collector and first NMOS power transistor The gate of the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor and the fourth PMOS power transistor The gate of the second PMOS power transistor is connected to the gate of the first PMOS power transistor. The gate and drain of the second PMOS power transistor are connected. The drain of the first NMOS power transistor is connected. The drain of the first NMOS power transistor The source and the first transistor The base of each is connected to the first resistor. The other end; the third PMOS power transistor The drain of the second NMOS power transistor is connected. The drain of the second NMOS power transistor The gate and drain of the second NMOS power transistor are connected. The gate is also connected to the sixth NMOS power transistor. The gate of the fourth PMOS power transistor; The drain is connected to the first Zener diode. Cathode, fifth NMOS power transistor The gate and the seventh NMOS power transistor The gate of the first Zener diode; The anode is connected to the third NMOS power transistor. The drain of the third NMOS power transistor The gate and drain of the third NMOS power transistor are connected. The gate of the fourth NMOS power transistor is connected. The gate of the fifth PMOS power transistor; The gate of the sixth PMOS power transistor is connected The gate of the fifth PMOS power transistor The gate and drain are connected, the fifth PMOS power transistor The drain of the fifth NMOS power transistor is connected. The drain of the fifth NMOS power transistor The source is connected to the fourth NMOS power transistor The drain of the sixth PMOS power transistor. The drain of the sixth NMOS power transistor is connected. The drain and the seventh PMOS power transistor The gate of the seventh NMOS power transistor. The source is connected to the first capacitor At the other end, the seventh PMOS power transistor The drain is connected to the second Zener diode. Cathode; Seventh PMOS power transistor The drain and the seventh NMOS power transistor The source terminals are all connected to the pre-regulated output terminals.

2. A high-voltage driver chip, characterized in that, The high-voltage drive chip includes the pre-regulator circuit as described in claim 1.

3. The high-voltage driver chip as described in claim 2, characterized in that, First PMOS power transistor Third PMOS power transistor Fourth PMOS power transistor and the seventh PMOS power transistor It is a PLDMOS power transistor capable of withstanding high voltage, and the first NMOS power transistor. Fourth NMOS power transistor Fifth NMOS power transistor The sixth NMOS power transistor and the seventh NMOS power transistor It is an NLDMOS power transistor capable of withstanding high voltage.

4. A pre-regulated voltage circuit, characterized in that, The pre-regulator circuit includes a bias current generation circuit, a current comparison circuit, and a power stage circuit. The bias current generation circuit includes a first PMOS power transistor. Second PMOS power transistor First NMOS power transistor Eighth NMOS power transistor and the first resistor The current comparison circuit includes a third PMOS power transistor. Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor Second NMOS power transistor Third NMOS power transistor Fourth NMOS power transistor Fifth NMOS power transistor The sixth NMOS power transistor The power stage circuit consists of multiple NMOS power transistors connected in series via diodes, with the gate and drain of each NMOS power transistor connected together. The source of the first NMOS power transistor is connected to the drain of the next NMOS power transistor, and so on, until the drain of the last NMOS power transistor is reached. The power stage circuit also includes a seventh PMOS power transistor. 7th NMOS power transistor Second Zener diode and the first capacitor Among them, the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor Fourth PMOS power transistor Fifth PMOS power transistor The sixth PMOS power transistor and the seventh PMOS power transistor The source and the seventh NMOS power transistor The drains of all transistors are connected to the input power supply VM; the eighth NMOS power transistor The source, the first resistor One end, the second NMOS power transistor The source of the third NMOS power transistor The source of the fourth NMOS power transistor The source of the sixth NMOS power transistor The source, the first capacitor One end and the second Zener diode The anodes of all transistors are grounded; the first PMOS power transistor The drain of the eighth NMOS power transistor is connected. The drain and the first NMOS power transistor The gate of the first PMOS power transistor Second PMOS power transistor Third PMOS power transistor and the fourth PMOS power transistor The gate of the second PMOS power transistor is connected to the gate of the first PMOS power transistor. The gate and drain of the second PMOS power transistor are connected. The drain of the first NMOS power transistor is connected. The drain of the first NMOS power transistor The source and the eighth NMOS power transistor The gate of each is connected to the first resistor. The other end; the third PMOS power transistor The drain of the second NMOS power transistor is connected. The drain of the second NMOS power transistor The gate and drain of the second NMOS power transistor are connected. The gate is also connected to the sixth NMOS power transistor. The gate of the fourth PMOS power transistor; The drain of the first NMOS power transistor is connected to the drain of the fifth NMOS power transistor. The gate and the seventh NMOS power transistor The gate of the last NMOS power transistor is connected to the source of the third NMOS power transistor. The drain of the third NMOS power transistor The gate and drain of the third NMOS power transistor are connected. The gate of the fourth NMOS power transistor is connected. The gate of the fifth PMOS power transistor; The gate of the sixth PMOS power transistor is connected The gate of the fifth PMOS power transistor The gate and drain are connected, the fifth PMOS power transistor The drain of the fifth NMOS power transistor is connected. The drain of the fifth NMOS power transistor The source is connected to the fourth NMOS power transistor The drain of the sixth PMOS power transistor. The drain of the sixth NMOS power transistor is connected. The drain and the seventh PMOS power transistor The gate of the seventh NMOS power transistor. The source is connected to the first capacitor At the other end, the seventh PMOS power transistor The drain is connected to the second Zener diode. Cathode; Seventh PMOS power transistor The drain and the seventh NMOS power transistor The source terminals are all connected to the pre-regulated output terminals.

5. A high-voltage driver chip, characterized in that, The high-voltage driver chip includes the pre-regulatory circuit as described in claim 4.

6. The high-voltage driver chip as described in claim 5, characterized in that, First PMOS power transistor Third PMOS power transistor Fourth PMOS power transistor and the seventh PMOS power transistor It is a PLDMOS power transistor capable of withstanding high voltage, and the first NMOS power transistor. Fourth NMOS power transistor Fifth NMOS power transistor The sixth NMOS power transistor and the seventh NMOS power transistor It is an NLDMOS power transistor capable of withstanding high voltage.

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