Circuit board and server

Abstract

The invention discloses a circuit board and a server, and relates to the technical field of servers, the circuit board comprises a processor, a plurality of memory devices, a plurality of high-speed connectors, a flash memory device and a programmable control unit, and the processor comprises a plurality of configuration pins; wherein the processor is respectively connected with the plurality of memory devices, the plurality of high-speed connectors, the flash memory device and the programmable control unit; the programmable control unit is used for supplying power to the processor and controlling the level values of the configuration pins, and the level values of the configuration pins are used for indicating the working mode of the processor. The level values of the configuration pins are dynamically adjusted through the programmable control unit, so that the same mainboard can adapt to different server architectures without hardware change, and the hardware development and maintenance cost is reduced.

Description

Technical Field

[0001] This application relates to the field of server technology, and more particularly to a circuit board and a server. Background Technology

[0002] Servers are the core hardware carriers supporting technologies such as cloud computing, big data, and artificial intelligence, with functions covering key areas such as data storage, processing, network services, and security. With the continuous increase in the number of Central Processing Unit (CPU) cores, memory channels, and heterogeneous computing demands, server architectures are showing a diversified development trend. Among them, single-socket servers, with their compact hardware design, lower procurement costs, and ease of maintenance, are widely used in lightweight workload scenarios. Dual-socket servers, through dual-processor collaboration, extended Global Memory Interconnect (xGMI) interconnect technology, and multi-channel memory expansion capabilities, can be applied to scenarios with stringent requirements for computing power, memory bandwidth, and scalability, such as High Performance Computing (HPC), Artificial Intelligence (AI) training, distributed databases, and ultra-large-scale virtualization clusters.

[0003] In related technologies, two separate motherboards need to be developed to adapt to single-socket and dual-socket servers, resulting in high hardware development and maintenance costs. Summary of the Invention

[0004] This application provides a circuit board and a server to reduce hardware development and maintenance costs.

[0005] In a first aspect, this application provides a circuit board, which includes a processor, multiple memory devices, multiple high-speed connectors, a flash memory device, and a programmable control unit. The processor includes multiple configuration pins; wherein,

[0006] The processor is connected to multiple memory devices, multiple high-speed connectors, flash memory devices, and a programmable control unit.

[0007] The programmable control unit is used to power the processor and control the voltage levels of multiple configuration pins, which are used to indicate the processor's operating mode.

[0008] Secondly, this application provides a server, which includes the circuit board of the first aspect.

[0009] Thirdly, this application provides a method for configuring the voltage levels of processor pins, including:

[0010] Obtain the level signal;

[0011] The server architecture and processor type are determined based on the level signal. The server architecture includes a single-processor server architecture or a dual-processor server architecture, and the processor type includes a first processor type, a second processor type, or a third processor type.

[0012] Based on the server architecture and processor type, determine the voltage levels of multiple configuration pins in the processor. These voltage levels are used to indicate the processor's operating mode.

[0013] Fourthly, this application provides a level configuration device for processor pins, including:

[0014] The acquisition module is used to acquire level signals;

[0015] The first determining module is used to determine the server architecture and processor type based on the level signal. The server architecture includes a single-processor server architecture or a dual-processor server architecture, and the processor type includes a first processor type, a second processor type, or a third processor type.

[0016] The second determining module is used to determine the voltage levels of multiple configuration pins in the processor based on the server architecture and processor type. The voltage levels of the multiple configuration pins are used to indicate the operating mode of the processor.

[0017] Fourthly, this application provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the step of the above-described processor pin level configuration method when executing the computer program.

[0018] Fifthly, this application provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described processor pin level configuration method.

[0019] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described processor pin level configuration methods.

[0020] This application provides a circuit board and a server. The circuit board includes a processor, multiple memory devices, multiple high-speed connectors, a flash memory device, and a programmable control unit. The processor includes multiple configuration pins. The processor is connected to the multiple memory devices, the multiple high-speed connectors, the flash memory device, and the programmable control unit. The programmable control unit is used to supply power to the processor and control the voltage levels of the multiple configuration pins. The voltage levels of the multiple configuration pins are used to indicate the processor's operating mode. By dynamically adjusting the voltage levels of the multiple configuration pins through the programmable control unit, the same motherboard can be adapted to different server architectures without hardware changes, reducing hardware development and maintenance costs. Attached Figure Description

[0021] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the structure of a CPU motherboard adapted for a single-socket server in related technologies;

[0023] Figure 2 A schematic diagram of the structure of a CPU motherboard adapted for dual-socket servers in related technologies;

[0024] Figure 3 A schematic diagram of a circuit board provided in an embodiment of this application;

[0025] Figure 4 A schematic diagram of another circuit board structure provided in an embodiment of this application;

[0026] Figure 5 A schematic diagram of a power board provided in an embodiment of this application;

[0027] Figure 6 This is a schematic diagram of a resistor unit provided in an embodiment of this application;

[0028] Figure 7 This is a schematic diagram of another structure of the resistor unit provided in an embodiment of this application;

[0029] Figure 8 This is a schematic diagram of the structure of a single-path server provided in an embodiment of this application;

[0030] Figure 9 This is a schematic diagram of the structure of a dual-socket server provided in an embodiment of this application;

[0031] Figure 10A flowchart illustrating the processor pin level configuration method provided in an embodiment of this application;

[0032] Figure 11 A schematic diagram of the structure of the processor pin level configuration device provided in the embodiments of this application;

[0033] Figure 12 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, other embodiments obtained by those of ordinary skill in the art without creative effort are all within the protection scope of this application.

[0035] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "installed," "connected," and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements. The terms "parallel," "perpendicular," and "equal" include the described situation and situations similar to the described situation, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism can be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality can be, for example, a difference between the two equal items being less than or equal to 5% of either one. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0037] To facilitate understanding, the relevant technologies involved in this application will be explained first.

[0038] A single-socket server refers to a server whose motherboard supports only one CPU. It is a common choice for entry-level and small-to-medium-sized scenarios. It has a streamlined structure, low power consumption, and relatively controllable hardware costs and maintenance difficulty. Its core performance can meet the needs of light workloads such as daily data processing, small website deployment, and office collaboration, making it suitable for users with limited budgets or small-scale businesses.

[0039] A dual-socket server refers to a server whose motherboard supports two CPUs. The two CPUs work together through multi-socket interconnect technology, providing stronger computing power, multitasking efficiency, and scalability. They can also be paired with larger capacity memory and storage, making them suitable for heavy-load scenarios such as large database operation, virtualization deployment, and high-concurrency business processing, meeting the enterprise-level needs for high stability and performance.

[0040] Figure 1 This is a schematic diagram of the structure of a CPU motherboard adapted for single-socket servers in related technologies. For example... Figure 1 As shown, it includes a CPU, multiple dual-inline-memory modules (DIMMs), multiple mini-coolhedge input / output (MCIO) connectors, a voltage regulator (VR), a complex programmable logic device (CPLD), a serial peripheral interface (SPI), flash memory, and pull-up / pull-down resistors.

[0041] The CPU includes multiple data transfer ports and multiple configuration pins (CPU Strap). P0, P1, and P2 are Peripheral Component Interconnect Express (PCIe) interfaces, while G0, G1, and G2 can be either PCIe interfaces or xGMI interfaces.

[0042] Pull-up / pull-down resistors are connected to multiple configuration pins to provide voltage levels for these pins. Multiple DIMMs are connected to the CPU via Double Data Rate 5 (DDR5) (the CPU includes multiple memory interfaces, one of which can connect to one DIMM). Multiple MCIOs are connected to the CPU via printed circuit board (PCB) traces; two MCIOs x8 form a PCIe x16 bandwidth group. VR is connected to both the CPLD and the CPU. The CPLD sends an enable signal (Power EN) to VR, which then supplies power to the CPU.

[0043] Figure 2 This is a schematic diagram of the CPU motherboard adapted for dual-socket servers in related technologies. (Example:) Figure 2 As shown, the system includes CPU0, CPU1, multiple DIMMs, multiple MCIOs, CPU0 VR, CPU1 VR, CPLD, SPI flash memory, and multiple pull-up / pull-down resistors. CPU0 includes multiple data transfer ports and multiple configuration pins, as does CPU1. P0, P1, and P2 in both CPU0 and CPU1 are PCIe interfaces, while G0, G1, and G2 in both CPU0 and CPU1 are either PCIe interfaces or xGMI interfaces.

[0044] One pull-up / pull-down resistor is connected to multiple configuration pins of CPU0 to provide voltage levels for these pins; another pull-up / pull-down resistor is connected to multiple configuration pins of CPU1 to provide voltage levels for these pins; multiple MCIOs are connected to CPU0 and CPU1 via PCB traces, with two MCIOs x8 forming a PCIe x16 bandwidth group; multiple DIMMs are connected to CPU0 and CPU1 via DDR5 (CPU0 and CPU1 include multiple memory interfaces, one of which can connect to one DIMM); SPI flash memory is connected to CPU0; the CPLD is connected to CPU0 VR and CPU1 VR respectively; CPU0 VR is connected to CPU0; CPU1 VR is connected to CPU1; CPU0's G0 is connected to CPU1's G2; CPU0's G2 is connected to CPU1's G0; the CPLD sends enable signals (Power EN) to CPU0 VR and CPU1 VR respectively; CPU0 VR provides power to CPU0; and CPU1 VR provides power to CPU1.

[0045] The aforementioned CPU requires specific configuration pin combinations to identify and configure single / dual-socket server architectures. Key control registers include: ① Multiplex Configuration Identification Registers (SA0, SA1): used to determine the CPU's single / dual-socket operating mode and socket number; ② xGMI Link Training Register: controls the physical layer parameters and link training status of the Infinity Fabric inter-CPU wireless architecture bus.

[0046] Figure 1 The CPU motherboard shown features a compact layout, integrating 16-channel memory and a 6-channel x16 bandwidth PCIe expansion interface, providing a cost-effective hardware platform specifically designed for lightweight computing scenarios.

[0047] Figure 2 The CPU motherboard shown supports dual-processor collaboration through xGMI interconnect technology and is equipped with 32-channel memory and 8-channel x16 bandwidth PCIe expansion interfaces to meet the high concurrency and scalability requirements of complex tasks such as high-performance computing and distributed databases.

[0048] In other words, the relevant technologies require the development of two separate motherboards to adapt to single-socket and dual-socket servers, resulting in high hardware development and maintenance costs. Furthermore, the configuration pin level settings in these technologies rely on fixed hardware configurations, making it impossible to dynamically adjust the processor's operating mode according to the application scenario.

[0049] To address the aforementioned technical issues, this application provides a circuit board that allows the same motherboard to adapt to different server architectures without hardware changes, thus resolving the current technical problem of high hardware development and maintenance costs.

[0050] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Figure 3 This is a schematic diagram of a circuit board structure provided in an embodiment of this application. Please refer to... Figure 3 The circuit board includes a processor, multiple memory devices, multiple high-speed connectors, a flash memory device, and a programmable control unit. The processor includes multiple configuration pins. The processor is connected to the multiple memory devices, multiple high-speed connectors, the flash memory device, and the programmable control unit. The programmable control unit is used to supply power to the processor and control the voltage levels of the multiple configuration pins. The voltage levels of the multiple configuration pins are used to indicate the operating mode of the processor.

[0052] Specifically, the processor can be a CPU. The CPU can send address signals for memory / peripherals (such as accessing a memory module) through the address bus, transmit actual data (such as 32-bit or 64-bit data blocks) through the data bus, and send read / write instructions, clock signals (CLK), reset signals (RESET#), and other control signals through the control bus.

[0053] Memory devices are used to provide memory resources to the processor. Memory devices can connect to the processor via DDR5. A memory device can refer to a memory module; for example, a DIMM memory device.

[0054] The number of memory devices can be 16, or other values, which are not limited in this application.

[0055] The processor also includes multiple memory interfaces, through which it connects to multiple memory devices. Each memory interface corresponds one-to-one with a memory device.

[0056] The circuit board is configured with multiple memory channels (such as 16 memory channels), and each memory channel supports DDR5-12800 specifications.

[0057] The number of high-speed connectors can be 12, or other values, which are not limited in this application. For example, the high-speed connector can be MCIO.

[0058] The processor also includes multiple data transfer ports, which connect to multiple high-speed connectors to provide high-speed peripheral component interconnection channels to external devices, enabling flexibility for external expansion.

[0059] Multiple data transmission ports can be connected to multiple high-speed connectors via PCB traces.

[0060] The data transfer port can be a PCIe interface or an xGMI interface. A single data transfer port can connect to two high-speed connectors. For example, it can integrate six sets of x16 bandwidth PCIe lanes with 12 MCIO x8 integrated processors. Each set of PCIe x16 bandwidth can be split into two MCIO x8 lanes, supporting simultaneous connection of high-speed graphics processing unit (GPU) accelerator cards, smart network cards, and non-volatile memory express (NVMe) storage arrays to meet the hardware requirements of heterogeneous computing and storage-intensive scenarios.

[0061] Flash memory devices are non-volatile storage chips primarily used to store firmware programs (such as Basic Input Output System (BIOS) programs and Unified Extensible Firmware Interface (UEFI) firmware) and boot code. Flash memory devices can connect to the processor via the SPI bus. For example, a flash memory device could be SPI flash memory, which is small, consumes little power, has a simple interface, and can quickly read and execute initialization programs during the CPU power-on boot phase, completing critical processes such as hardware self-test and booting the operating system.

[0062] Multiple configuration pins can include multiple socket address (SA) pins and multiple training pins. For example, the multiple SA pins can be SA0 and SA1, and the training pins can be xGMI training pins.

[0063] In one possible implementation, such as Figure 4 As shown, the programmable control unit may include a sideband connector, a power connector, a voltage regulator, and a programmable controller; wherein, the voltage regulator is connected to the power connector, the programmable controller, and the processor respectively; the sideband connector is connected to the programmable controller and is used to provide the programmable controller with level signals, which are used to indicate the server architecture and processor type; the programmable controller is connected to multiple configuration pins and is used to control the level values ​​of the multiple configuration pins.

[0064] Server architecture can include single-processor server architecture or dual-processor server architecture. A single-processor server architecture includes one CPU, while a dual-processor server architecture includes two CPUs. Therefore, a single-processor server architecture can also be called a single-CPU server architecture, and a dual-processor server architecture can also be called a dual-CPU server architecture; this application does not impose any limitations on this.

[0065] The processor type can include a first processor type, a second processor type, or a third processor type. Specifically, the first processor type is the CPU in a single-processor server architecture; the second processor type is the master CPU in a dual-processor server architecture; and the third processor type is the slave CPU in a dual-processor server architecture.

[0066] In a dual-socket server, the master CPU is responsible for: reading and executing the first UEFI / BIOS instruction from the SPI flash memory; detecting and initializing system memory, PCIe devices, etc.; initiating and training the high-speed interconnect link with the slave CPUs; and coordinating and triggering the initialization process of the slave CPUs. The slave CPUs in the dual-socket server wait for the master CPU to wake them up and issue configuration instructions; once woken up, they initialize the local resources under their control and respond to the link training request initiated by the master CPU.

[0067] Power connectors can be used to power voltage regulators, voltage regulators can be used to power processors, and programmable controllers can be used to enable voltage regulators.

[0068] For example, a programmable controller can enable a voltage regulator by sending a power enable signal (power EN) to the voltage regulator.

[0069] Programmable controllers can be field-programmable gate arrays (FPGAs), CPLDs, micro controller units (MCUs), etc.

[0070] In this embodiment, the programmable control unit can dynamically control the level values ​​of multiple configuration pins, enabling the same motherboard to adapt to different server architectures without hardware changes, thus solving the technical problem of high hardware development and maintenance costs.

[0071] This application also provides a server that may include at least one of the aforementioned circuit boards. For example, a single-socket server includes one of the aforementioned circuit boards, a dual-socket server includes two of the aforementioned circuit boards, and a quad-socket server includes four of the aforementioned circuit boards.

[0072] The server also includes a power supply board, which is connected to at least one programmable control unit in the aforementioned circuit board.

[0073] In one possible implementation, such as Figure 5 As shown, the power board includes a resistor unit, a power connector, a power connector, and a sideband connector; wherein, the resistor unit is connected to the sideband connector to provide a level signal to the sideband connector, and the level signal is used to indicate the server architecture; the power connector is connected to the power connector to supply power to the power connector.

[0074] A resistor unit may include multiple resistors.

[0075] Level signals can indicate not only server architecture but also processor type.

[0076] In one possible implementation, such as Figure 6 As shown, the resistor unit includes a first resistor subunit and a second resistor subunit, which are connected in parallel.

[0077] In one possible implementation, the first resistor subunit includes multiple resistors, and the second resistor subunit includes multiple resistors. For example, such as... Figure 7 As shown, the resistor unit includes a first resistor subunit and a second resistor subunit. The first resistor subunit includes two resistors, and the second resistor subunit includes two resistors. Either pair of resistors includes one pull-up resistor and one pull-down resistor. The pull-up resistor can be connected to the common collector voltage (VCC), and the pull-down resistor can be grounded.

[0078] By pulling up the pull-up resistor in the first resistor subunit, or the pull-up resistor in the second resistor subunit, or pulling down the pull-down resistor in the first resistor subunit, or pulling down the pull-down resistor in the second resistor subunit, different level signals can be generated. Different level signals can indicate different server architectures. In the case of a dual-processor server architecture, different level signals can also indicate the processor type.

[0079] For example, when the signal level is the first level, the corresponding server architecture is a single-processor server architecture; when the signal level is the second level, the corresponding server architecture is a dual-processor server architecture, and the processor type is the second processor type; when the signal level is the third level, the corresponding server architecture is a dual-processor server architecture, and the processor type is the third processor type.

[0080] The first, second, and third level signals are all different. For example, the first level signal can be 00, the second level signal can be 01, and the third level signal can be 10. It should be noted that the above level signals are only examples, and the various level signals can be interchanged; this application does not impose any restrictions on this.

[0081] Based on the power supply board and circuit board described above, the architecture of a single-socket server and a dual-socket server will be explained in detail below.

[0082] In one possible implementation, the single-processor server includes the aforementioned circuit board and power board. The power board's sideband connector is connected to a sideband connector in the programmable control unit (PLU), and the power board's power connector is connected to a power connector in the PLU. For example, the structure of the single-processor server is as follows: Figure 8 As shown.

[0083] The resistor unit in power board 0 generates a first-level signal through pull-up and pull-down resistors. The first-level signal is transmitted to the programmable controller through the sideband server of the power board and the sideband server of the circuit board. The programmable controller determines that the server architecture is a single-channel server architecture based on the first-level signal, sets multiple slot address pins to the first-level value, and sets multiple training pin devices to the second-level value. The processor knows the working mode based on the first-level value and the second-level value, and then obtains the configuration file from the flash memory device to complete the hardware initialization.

[0084] In one possible implementation, the dual-socket server includes two circuit boards and a power supply board. Sideband connectors on the circuit boards are respectively connected to sideband connectors in the programmable control units (ECUs) of the two circuit boards, and power connectors on the power supply board are respectively connected to power connectors in the programmable control units (ECUs) of the two circuit boards. For example, the structure of the dual-socket server is as follows: Figure 9 As shown.

[0085] The two data transmission ports on the processors in the two circuit boards are cross-connected to form a physical connection channel for the xGMI signal.

[0086] The two circuit boards are designated as Circuit Board 0 and Circuit Board 1, respectively. The processor in Circuit Board 0 is designated as Processor 0, and the processor in Circuit Board 1 is designated as Processor 1. The resistor unit in Power Board 1 generates a second-level signal and a third-level signal through pull-up and pull-down resistors. The second-level signal is transmitted to the Programmable Controller (PLC) via the sideband server of Power Board 1 and Circuit Board 0. Based on the second-level signal, the PLC determines the server architecture to be a dual-processor architecture and the processor type to be the second processor type. Then, it sets multiple slot address pins to the third-level value and multiple training pin devices to the fourth-level value. Processor 0 determines the operating mode based on the third and fourth-level values ​​and then retrieves the configuration file from the flash memory device to complete hardware initialization. The third-level signal is transmitted to the PLC via the sideband server of Power Board 1 and Circuit Board 1. Based on the third-level signal, the PLC determines the server architecture to be a dual-processor architecture and the processor type to be the third processor type. Then, it sets multiple slot address pins to the fifth-level value and multiple training pin devices to the fourth-level value. Processor 1 determines the operating mode based on the fifth and fourth-level values ​​and then retrieves the configuration file from the flash memory device to complete hardware initialization.

[0087] In other words, the power supply board provides different voltage levels to the programmable control unit (PCU). The PCU determines the server architecture and processor type based on these voltage levels, and then determines the voltage levels of multiple configuration pins. These configuration pin values ​​indicate the processor's operating mode. Specifically, the combination of the power supply board and the PCU allows for dynamic configuration of the voltage levels of multiple configuration pins. For a single-socket server architecture, power supply board 0 is used; for a dual-socket server architecture, power supply board 1 is used. By dynamically analyzing the voltage differences of the logic signals within the two power supply boards and the PCU, the voltage levels of multiple configuration pins are dynamically configured, achieving non-invasive adaptive differentiation between single and dual-socket server architectures.

[0088] The multiple configuration pins include multiple slot address pins and multiple training pins. For example, in the case of a single-socket server architecture and a first processor type, the voltage level of the multiple slot address pins is determined to be a first voltage level, and the voltage level of the multiple training pins is determined to be a second voltage level; in the case of a dual-socket server architecture and a second processor type, the voltage level of the multiple slot address pins is determined to be a third voltage level, and the voltage level of the multiple training pins is determined to be a fourth voltage level; in the case of a dual-socket server architecture and a third processor type, the voltage level of the multiple slot address pins is determined to be a fifth voltage level, and the voltage level of the multiple training pins is determined to be a fourth voltage level.

[0089] Among them, the first level value and the third level value can be the same or different; the fifth level value is different from the first level value and / or the second level value; the second level value is different from the fourth level value.

[0090] If the above circuit board is configured with 16 DIMM memory channels, each channel supports DDR5-12800 specifications. The total memory bandwidth of a dual-socket server can reach nearly twice that of a single-socket server, and it supports a maximum of 32 DIMMs, meeting the memory pooling requirements of ultra-large-scale virtualization clusters and distributed databases.

[0091] Based on the above, the following section details the method for configuring the voltage levels of the processor pins.

[0092] Figure 10 This is a flowchart illustrating a method for configuring the level of processor pins according to an embodiment of this application. Please refer to... Figure 10 It includes the following steps:

[0093] S1001, Obtain the level signal.

[0094] The level signal can be obtained from the power board.

[0095] S1002. Determine the server architecture and processor type based on the level signal. The server architecture includes a single-processor server architecture or a dual-processor server architecture, and the processor type includes a first processor type, a second processor type, or a third processor type.

[0096] The descriptions of single-socket server architecture, dual-socket server architecture, first processor type, second processor type, and third processor type can be found in the corresponding descriptions above, and will not be repeated here.

[0097] In one possible implementation, the server architecture and processor type can be determined based on the level signal, including any of the following:

[0098] (1) If the level signal is the first level signal, then the server architecture is determined to be a single-path server architecture and the processor type is the first processor type.

[0099] It should be noted that because there is only one processor type for a single-processor service architecture, namely the first processor type, the default processor type is the first processor type when the server architecture is determined to be a single-processor server architecture.

[0100] (2) If the level signal is the second level signal, then the server architecture is determined to be a dual-path server architecture and the processor type is the second processor type.

[0101] (3) If the level signal is the third level signal, then the server architecture is determined to be a dual-processor server architecture and the processor type is the third processor type.

[0102] The first, second, and third level signals are all different. For example, the first level signal can be 00, the second level signal can be 01, and the third level signal can be 10. It should be noted that the above level signals are only examples, and the various level signals can be interchanged; this application does not impose any restrictions on this.

[0103] The first, second, and third level signals are generated by resistor units in the power supply board and transmitted to the programmable controller via sideband connectors on the power supply board and the circuit board. The resistor unit can be considered as two General Purpose Input / Output (GPIO) pins, and the level values ​​of these two GPIO pins are the aforementioned level signals. For example, the level values ​​of the two GPIO pins can be shown in Table 1.

[0104] Table 1

[0105]

[0106] Power board 0 is adapted to a single-socket server architecture, while power board 1 is adapted to a dual-socket server architecture. Power board 0 and power board 1 have the same structure, but they generate different voltage levels.

[0107] S1003. Based on the server architecture and processor type, determine the voltage levels of multiple configuration pins in the processor. The voltage levels of the multiple configuration pins are used to indicate the processor's operating mode.

[0108] The configuration pins include multiple slot address pins and multiple training pins. For example, the multiple slot address pins can be SA0 and SA1, and the training pins can be xGMI training pins.

[0109] The processor can operate in either single-socket or dual-socket mode.

[0110] In one possible implementation, the voltage levels of multiple configuration pins in the processor can be determined based on the server architecture and processor type, including any of the following:

[0111] ① When the server architecture is a single-processor server architecture and the processor type is the first processor type, determine the level value of multiple slot address pins as the first level value and the level value of multiple training pins as the second level value.

[0112] Since the single-processor architecture corresponds to only one processor type, when the server architecture is a single-processor server architecture, the voltage level of multiple slot address pins can be directly determined as the first voltage level and the voltage level of multiple training pins as the second voltage level.

[0113] Setting the voltage levels of multiple training pins to the second voltage level can prevent accidental activation of the dual-link training process and reduce system power consumption.

[0114] ② In the case of a dual-processor server architecture and a second processor type, determine the level values ​​of multiple slot address pins as the third level value and the level values ​​of multiple training pins as the fourth level value.

[0115] The first and third voltage levels can be the same or different. The second and fourth voltage levels are different.

[0116] Setting the voltage levels of multiple training pins to a fourth voltage level can activate xGMI signal communication, thereby enabling inter-processor communication.

[0117] ③ In the case of a dual-processor server architecture and a third processor type, determine that the voltage level of multiple slot address pins is the fifth voltage level and the voltage level of multiple training pins is the fourth voltage level.

[0118] The fifth level value is different from the first level value, and / or the fifth level value is different from the second level value.

[0119] For example, suppose the multiple slot address pins are SA0 and SA1, and the multiple training pins can be xGMI training pin 1 and xGMI training pin 2.

[0120] In a single-path server architecture, the voltage levels of multiple configuration pins are shown in Table 2.

[0121] Table 2

[0122]

[0123] In a dual-socket server architecture, the voltage levels of multiple configuration pins are shown in Table 3.

[0124] Table 3

[0125]

[0126] This application embodiment combines a power board and a programmable control unit to dynamically configure the level values ​​of multiple configuration pins, achieving non-intrusive adaptive differentiation between single / dual-path server architectures.

[0127] After configuring the levels of multiple configuration pins, the processor can load the configuration file from the flash memory device to complete the processor's hardware initialization.

[0128] Figure 11 This is a schematic diagram of the structure of a processor pin level configuration device provided in an embodiment of this application. For example... Figure 11 As shown, the level configuration device 1100 includes: an acquisition module 1101, a first determination module 1102, and a second determination module 1103.

[0129] Acquisition module 1101 is used to acquire level signals;

[0130] The first determining module 1102 is used to determine the server architecture and processor type based on the level signal. The server architecture includes a single-processor server architecture or a dual-processor server architecture, and the processor type includes a first processor type, a second processor type, or a third processor type.

[0131] The second determining module 1103 is used to determine the level values ​​of multiple configuration pins in the processor according to the server architecture and processor type. The level values ​​of the multiple configuration pins are used to indicate the operating mode of the processor.

[0132] In one possible implementation, the first determining module 1102 is configured to perform any of the following:

[0133] If the level signal is the first level signal, then the server architecture is determined to be a single-processor server architecture, and the processor type is the first processor type;

[0134] If the level signal is the second level signal, then the server architecture is determined to be a dual-processor server architecture, and the processor type is the second processor type;

[0135] If the level signal is the third level signal, then the server architecture is determined to be a dual-processor server architecture, and the processor type is the third processor type.

[0136] In one possible implementation, the multiple configuration pins include multiple slot address pins and multiple training pins; the second determination module 1103 is configured to perform any of the following:

[0137] In the case of a single-processor server architecture and a first processor type, the voltage levels of multiple slot address pins are determined to be the first voltage level, and the voltage levels of multiple training pins are determined to be the second voltage level.

[0138] In the case of a dual-processor server architecture and a second processor type, the voltage levels of multiple slot address pins are determined to be the third voltage level, and the voltage levels of multiple training pins are determined to be the fourth voltage level.

[0139] In the case of a dual-socket server architecture and a third processor type, the voltage levels of multiple slot address pins are determined to be the fifth voltage level, and the voltage levels of multiple training pins are determined to be the fourth voltage level.

[0140] For a description of the features in the embodiment corresponding to the level configuration device 1100, please refer to the relevant description in the embodiment corresponding to the level configuration method, which will not be repeated here.

[0141] Figure 12 A schematic diagram of the structure of the electronic device provided in this application. Figure 12 As shown, the electronic device 1200 provided in this embodiment includes at least one processor 1201 and a memory 1202. Optionally, the electronic device 1200 further includes a communication component 1203. The processor 1201, memory 1202, and communication component 1203 are connected by a wire.

[0142] In a specific implementation, at least one processor 1201 executes computer execution instructions stored in memory 1202, causing at least one processor 1201 to execute the above-described level configuration method embodiment.

[0143] The specific implementation process of processor 1201 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0144] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0145] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0146] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0147] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the processor pin level configuration method embodiments described above when running.

[0148] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0149] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the processor pin level configuration method embodiments described above.

[0150] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the processor pin level configuration method embodiments described above.

[0151] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for various specific applications, but such implementations should not be considered beyond the scope of this application.

[0152] The above provides a detailed description of a processor pin level configuration method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A circuit board, characterized in that, The circuit board includes a processor, multiple memory devices, multiple high-speed connectors, a flash memory device, and a programmable control unit. The processor includes multiple configuration pins; wherein, The processor is connected to the plurality of memory devices, the plurality of high-speed connectors, the flash memory device, and the programmable control unit, respectively. The programmable control unit is used to supply power to the processor and control the level values ​​of the plurality of configuration pins, the level values ​​of the plurality of configuration pins being used to indicate the operating mode of the processor.

2. The circuit board according to claim 1, characterized in that, The programmable control unit includes a sideband connector, a power connector, a voltage regulator, and a programmable controller; wherein... The voltage regulator is connected to the power connector, the programmable controller, and the processor, respectively. The sideband connector is connected to the programmable controller and is used to provide an electrical signal to the programmable controller, the electrical signal being used to indicate the server architecture and processor type; The programmable controller is connected to the plurality of configuration pins and is used to control the voltage levels of the plurality of configuration pins.

3. The circuit board according to claim 1, characterized in that, The processor also includes multiple memory interfaces, through which the processor is connected to multiple memory devices.

4. The circuit board according to claim 1, characterized in that, The processor also includes multiple data transmission ports, which are connected to multiple high-speed connectors to provide high-speed peripheral component interconnection channels to external devices.

5. A server, characterized in that, The server includes at least one circuit board as described in any one of claims 1-4.

6. The server according to claim 5, characterized in that, The server also includes a power board, which is connected to at least one programmable control unit in the circuit board.

7. The server according to claim 6, characterized in that, The power board includes resistor units, power connectors, power connectors, and sideband connectors; wherein... The resistor unit is connected to the sideband connector and is used to provide a level signal to the sideband connector, the level signal being used to indicate the server architecture; The power connector is connected to the power connector and is used to supply power to the power connector.

8. The server according to claim 7, characterized in that, The resistor unit includes a first resistor subunit and a second resistor subunit, wherein the first resistor subunit and the second resistor subunit are connected in parallel.

9. The server according to claim 8, characterized in that, The first resistor subunit includes multiple resistors, and the second resistor subunit includes multiple resistors.

10. The server according to any one of claims 7-9, characterized in that, The server includes a circuit board, the power board's sideband connector is connected to the sideband connector in the programmable control unit, and the power board's power connector is connected to the power connector in the programmable control unit.

11. The server according to any one of claims 7-9, characterized in that, The server includes two circuit boards, the sideband connectors of which are respectively connected to the sideband connectors in the programmable control units of the two circuit boards, and the power connectors of the power supply board are respectively connected to the power connectors in the programmable control units of the two circuit boards.

12. The server according to claim 11, characterized in that, The two data transmission ports on the processors in the two circuit boards are cross-connected.

13. A method for configuring the voltage levels of a processor pin, characterized in that, include: Obtain the level signal; The server architecture and processor type are determined based on the level signal, wherein the server architecture includes a single-processor server architecture or a dual-processor server architecture, and the processor type includes a first processor type, a second processor type, or a third processor type. Based on the server architecture and the processor type, the voltage levels of multiple configuration pins in the processor are determined, and the voltage levels of the multiple configuration pins are used to indicate the operating mode of the processor.

14. The method according to claim 13, characterized in that, The step of determining the server architecture and processor type based on the level signal includes any one of the following: If the level signal is a first level signal, then the server architecture is determined to be the single-path server architecture, and the processor type is the first processor type; If the level signal is the second level signal, then the server architecture is determined to be the dual-processor server architecture, and the processor type is the second processor type; If the level signal is the third level signal, then the server architecture is determined to be the dual-processor server architecture, and the processor type is the third processor type.

15. The method according to claim 14, characterized in that, The plurality of configuration pins includes a plurality of slot address pins and a plurality of training pins; determining the level values ​​of the plurality of configuration pins in the processor according to the server architecture and the processor type includes any one of the following: When the server architecture is the single-processor server architecture and the processor type is the first processor type, the voltage level of the plurality of slot address pins is determined to be a first voltage level, and the voltage level of the plurality of training pins is determined to be a second voltage level. When the server architecture is the dual-socket server architecture and the processor type is the second processor type, the voltage level of the plurality of slot address pins is determined to be a third voltage level, and the voltage level of the plurality of training pins is determined to be a fourth voltage level. When the server architecture is the dual-socket server architecture and the processor type is the third processor type, the voltage level of the plurality of slot address pins is determined to be the fifth voltage level, and the voltage level of the plurality of training pins is determined to be the fourth voltage level.

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