Layered heat dissipation method and apparatus based on image processor, electronic device, and medium

Abstract

Embodiments of the present disclosure disclose an image processor-based layered heat dissipation method, device, electronic equipment and medium. A specific embodiment of the method comprises: performing device identification on a set of image processors to obtain a set of image processor identification information; performing data collection on the set of image processors to obtain a set of processor performance information, a set of processor running scenario information and a set of running environment information; determining processor load information; performing layered heat dissipation on the image processors to obtain initial heat dissipation information; performing multi-dimensional risk identification on the image processors to obtain processor temperature risk information, and controlling an alarm device to perform risk alarm processing; performing dynamic adjustment processing on the initial heat dissipation information to obtain target heat dissipation information; and controlling a heat dissipation device to perform heat dissipation operation for heat dissipation. The embodiment can perform targeted heat dissipation operation on different types of image processors, improve system heat dissipation efficiency, reduce waste of heat dissipation resources, and improve system stability and performance.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of computer technology, and more specifically to a layered heat dissipation method, apparatus, electronic device, and medium based on an image processor. Background Technology

[0002] With the rapid development of high-performance computing applications such as artificial intelligence, big data analytics, and graphics rendering, the performance and stability of GPUs (Graphics Processing Units) significantly impact server operation. This is especially true in systems with multiple GPUs deployed under high load, where GPUs generate substantial heat. If this heat is not dissipated effectively and promptly, overheating can lead to server performance degradation, system instability, and even hardware damage. A typical approach for layered cooling methods based on GPUs involves determining the appropriate cooling execution information based on the acquired GPU temperature data. Then, this information is used to activate corresponding cooling devices for heat dissipation.

[0003] However, in practice, it has been found that when using the above method to perform layered heat dissipation operations based on image processors, the following technical problems often exist: Since the heat dissipation execution information is determined solely by the GPU's temperature information, the influencing factors are considered too simplistically, resulting in low accuracy of the heat dissipation execution information. Furthermore, the heat dissipation execution information is usually executed using fixed thresholds, making it difficult to achieve real-time adjustment and differentiation between different types of image processors. This leads to a waste of heat dissipation resources or insufficient heat dissipation effect of the image processing equipment, reducing the performance and stability of the heat dissipation equipment.

[0004] The information disclosed in this background section is only intended to enhance the understanding of the background of the present disclosure concept, and therefore may contain information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0006] Some embodiments of this disclosure propose a layered heat dissipation method, apparatus, electronic device, and medium based on an image processor to solve one or more of the technical problems mentioned in the background section above.

[0007] In a first aspect, some embodiments of this disclosure provide a layered heat dissipation method based on image processors, comprising: performing device identification on an image processor set included in a heterogeneous hardware compatible system to obtain an image processor identification information set; acquiring data from the image processor set through a processor driver adapter and a system environment sensor to obtain a processor performance information set, a processor operating scenario information set, and an operating environment information set; for each image processor, performing the following layered heat dissipation steps: determining processor load information based on the processor operating scenario information and processor performance information corresponding to the image processor; performing layered heat dissipation processing on the image processor based on the processor load information and the corresponding image processor identification information to obtain initial heat dissipation information; performing multi-dimensional risk identification on the image processor based on the processor load information, the corresponding processor performance information, and the operating environment information to obtain processor temperature risk information, and controlling an alarm device to perform risk alarm processing based on the processor temperature risk information; dynamically adjusting the initial heat dissipation information based on the processor temperature risk information to obtain target heat dissipation information; and controlling a heat dissipation device to perform heat dissipation operations to perform system heat dissipation processing on the heterogeneous hardware compatible system based on the obtained target heat dissipation information set.

[0008] Secondly, some embodiments of this disclosure provide a layered heat dissipation device based on an image processor, comprising: a device identification unit configured to identify an image processor set included in a heterogeneous hardware compatible system, thereby obtaining an image processor identification information set; a data acquisition unit configured to acquire data from the image processor set via a processor driver adapter and a system environment sensor, thereby obtaining a processor performance information set, a processor operating scenario information set, and an operating environment information set; and an execution unit configured to perform the following layered heat dissipation steps for each image processor: determining processor load information based on the processor operating scenario information and processor performance information corresponding to the image processor; and based on... The aforementioned processor load information and corresponding image processor identification information are used to perform layered heat dissipation processing on the image processor to obtain initial heat dissipation information. Based on the aforementioned processor load information, corresponding processor performance information, and operating environment information, multi-dimensional risk identification is performed on the image processor to obtain processor temperature risk information. Based on the processor temperature risk information, the alarm device is controlled to perform risk alarm processing. Based on the aforementioned processor temperature risk information, the aforementioned initial heat dissipation information is dynamically adjusted to obtain target heat dissipation information. The control unit is configured to control the heat dissipation device to perform heat dissipation operations to perform system heat dissipation processing on the aforementioned heterogeneous hardware compatible system based on the obtained target heat dissipation information set.

[0009] Thirdly, some embodiments of this disclosure provide an electronic device, including: one or more processors; and a storage device having one or more programs stored thereon, such that when the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any implementation of the first aspect.

[0010] Fourthly, some embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method as described in any implementation of the first aspect.

[0011] The above embodiments of this disclosure have the following beneficial effects: The image processor-based layered heat dissipation method of some embodiments of this disclosure can perform targeted heat dissipation operations for different types of image processors, improve system heat dissipation efficiency, reduce waste of heat dissipation resources, and improve system stability and performance. Specifically, the reasons for the waste of related heat dissipation resources or insufficient heat dissipation effect of image processing devices, which reduces the performance and stability of heat dissipation devices, are as follows: Since the heat dissipation execution information is determined solely by the single temperature information of the GPU, the influencing factors considered are too singular, resulting in low accuracy of the heat dissipation execution information. Furthermore, the heat dissipation execution information is usually executed using a fixed threshold, making it difficult to achieve real-time adjustment response and differential recognition of different types of image processors, leading to waste of heat dissipation resources or insufficient heat dissipation effect of image processing devices, thus reducing the performance and stability of heat dissipation devices. Based on this, the image processor-based layered heat dissipation method of some embodiments of this disclosure can first perform device identification on the set of image processors included in the heterogeneous hardware compatible system to obtain an image processor identification information set. Here, device identification can accurately identify image processors of different types and performance levels, so that targeted heat dissipation operations can be performed on different types of image processing devices to improve heat dissipation efficiency. Secondly, data is collected from the aforementioned image processor set via the processor driver adapter and system environment sensors to obtain processor performance information, processor operating scenario information, and operating environment information. Here, by collecting data representing image processors from different dimensions, the load status of the image processors can be accurately grasped, improving the comprehensiveness of the data. Then, for each image processor, the following layered heat dissipation steps are performed: First, based on the processor operating scenario information and processor performance information corresponding to the aforementioned image processor, the processor load information is determined. Here, fusing data from multiple dimensions improves the accuracy of processor load information determination. Second, based on the aforementioned processor load information and the corresponding image processor identification information, layered heat dissipation processing is performed on the aforementioned image processors to obtain initial heat dissipation information. Here, by including processor load information under different scenarios, heat dissipation strategies are determined for different types of image processors with varying characteristics, improving the accuracy and relevance of the initial heat dissipation information, reducing the waste of heat dissipation resources consumed in executing the initial heat dissipation information, and lowering costs. Third, based on the aforementioned processor load information, corresponding processor performance information, and operating environment information, multi-dimensional risk identification is performed on the aforementioned image processors to obtain processor temperature risk information, and based on the processor temperature risk information, alarm devices are controlled to perform risk alarm processing. Here, multidimensional risk identification identifies risks from different dimensions, which can improve the accuracy of risk identification, effectively reduce false alarms and missed alarms, improve the accuracy and timeliness of alarms, and enhance the security and stability of the image processor.The fourth step involves dynamically adjusting the initial heat dissipation information based on the aforementioned processor temperature risk information to obtain the target heat dissipation information. Here, the initial heat dissipation information is further adjusted to account for the multi-dimensional processor temperature risk information, further enhancing the ability to dynamically adjust heat dissipation resources corresponding to the initial heat dissipation information to adapt to the operating conditions of the image processor and reduce storage resource waste. Finally, based on the obtained target heat dissipation information set, the heat dissipation equipment is controlled to perform heat dissipation operations to cool the heterogeneous hardware compatible system. Here, an adaptive overall adjustment is made to the entire heterogeneous hardware compatible system, improving the overall stability and security of the system. Therefore, this layered heat dissipation method based on image processors can perform targeted heat dissipation operations for different types of image processors, improving system heat dissipation efficiency, reducing heat dissipation resource waste, and enhancing system stability and performance. Attached Figure Description

[0012] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0013] Figure 1 This is a flowchart of some embodiments of the image processor-based layered heat dissipation method according to the present disclosure;

[0014] Figure 2 This is a schematic diagram of the structure of some embodiments of the image processor-based layered heat dissipation device according to the present disclosure;

[0015] Figure 3 This is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present disclosure. Detailed Implementation

[0016] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0017] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0018] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0019] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0020] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0021] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] Figure 1 A flow 100 of some embodiments of a layered heat dissipation method based on an image processor according to the present disclosure is shown. This layered heat dissipation method based on an image processor includes the following steps:

[0023] Step 101: Perform device identification on the set of image processors included in the heterogeneous hardware compatible system to obtain the image processor identification information set.

[0024] In some embodiments, the executing entity (e.g., an electronic device) of the above-described image processor-based layered heat dissipation method can perform device identification on the set of image processors included in the heterogeneous hardware compatible system to obtain an image processor identification information set. The heterogeneous hardware compatible system can be a system that hybridizes and deploys multiple different types of image processors to improve system computing performance. The image processor can be a GPU used for processing image and graphics operations. The different types of image processors can include, but are not limited to, at least one of the following: NVIDIA's RTX 3080, 3090, 4080, and AMD's RX 6800XT, 6900XT, 7900XTX. The image processor identification information in the image processor identification information set can be device information and device parameter information for identifying the image processor. The device parameter information can include, but is not limited to, at least one of the following: load information, power consumption information, high-speed rotation, and the maximum temperature that the GPU can withstand during operation.

[0025] In some optional implementations of certain embodiments, the above-described device identification of the image processor set included in the heterogeneous hardware compatible system to obtain an image processor identification information set may include the following steps:

[0026] First, for each image processor in the above image processor set, perform the following recognition steps:

[0027] Sub-step 1 involves performing hardware identification on the aforementioned image processor set to obtain an image processor hardware information set. This set may include information about the brand and model of the image processor.

[0028] Sub-step 2: Based on the aforementioned image processor hardware information set, the acquired processor text information set is subjected to double-byte encoding to obtain a processor word vector sequence. The processor text information in the aforementioned processor text information set can be text information related to the image processor that has been formally obtained through web scraping technology. For example, the aforementioned processor text information can include, but is not limited to, at least one of the following: official documentation of the image processor, image processor web page information. The processor byte vectors in the aforementioned processor byte vector sequence can be vectors representing the character information in the processor text information set in vector form. In practice, the aforementioned execution entity can first use the WordPiece algorithm in the aforementioned dynamic byte encoding model to segment the processor text information set into characters, obtaining a word sequence. The aforementioned dynamic byte encoding model can be a model that encodes the logical relationships between various clauses. Then, by querying the word vector table, each character in the aforementioned word sequence is converted into a one-dimensional vector to obtain the processor word vector sequence. The word vectors in the aforementioned word vector sequence consist of word vectors, segment vectors, and position vectors. The aforementioned segment vectors can be vectors that are automatically learned during model training, used to divide clauses, and fused with the semantic information of the word vectors. The aforementioned position vectors are used to represent the differences in semantic information carried by words at different positions in the text.

[0029] Sub-step 3 involves inputting the aforementioned processor word vector sequence into a bidirectional self-attention encoding network to obtain bidirectional dynamic word feature vectors. The bidirectional self-attention encoding network can be a model that performs context-dependent processing on the input processor word vector sequence to output bidirectional dynamic word feature vectors. This network can include a preset threshold of transformer encoders. The preset threshold can be 12. The transformer encoders can include a word vector and position encoding layer, a multi-head self-attention mechanism layer, a residual connection layer, a normalization layer, and a feedforward network layer. The word vector and position encoding layer can provide positional information for each word in the processor text information set, and identify the dependencies and temporal relationships of each word within the set. The multi-head self-attention mechanism layer can determine the relationships between each word in the processor text information set and the remaining words in the sentence, ensuring that each word vector contains information about the word vectors included in the processor text information set. The normalization layer can accelerate model training and convergence. The residual connection layer can address gradient vanishing and network degradation issues. The aforementioned feedforward network consists of two layers. The activation function of the first feedforward layer is ReLU (Rectified Linear Unit), and the activation function of the second feedforward layer is a non-linear activation function. The bidirectional dynamic word feature vectors described above can represent contextual and semantic features.

[0030] Sub-step 4 involves inputting the aforementioned bidirectional dynamic word feature vector into the processor parameter recognition model to obtain initial processor parameter recognition information. This model includes a bidirectional long short-term memory network, a multi-head attention mechanism layer, a multi-layer convolutional extraction layer, a multi-layer gating unit layer, and a classification layer. The processor parameter recognition model can be a model that identifies the specific device model and core parameters of the input bidirectional dynamic word feature vector to output initial processor parameter recognition information. This initial processor parameter recognition information can be information related to the execution status and performance of the image processor. It may include, but is not limited to, at least one of the following: processor power consumption, processor operating temperature alarm threshold, fan speed adjustment step size, video memory usage, and core load rate.

[0031] In practice, the aforementioned execution entity can first input the bidirectional dynamic word feature vector into a bidirectional long short-term memory network to obtain a global temporal feature vector. This global temporal feature vector can be a feature vector containing contextual semantic information. The bidirectional long short-term memory network, including the forward and backward long short-term memory networks, does not share states; the forward long short-term memory network propagates state in the forward order, and the backward long short-term memory network propagates state in the reverse order. Secondly, the aforementioned global temporal feature vector is input into the aforementioned multi-head attention mechanism layer to obtain a weighted global temporal feature vector. This multi-head attention mechanism layer can be a network layer that assigns different attention weights to the aforementioned global temporal feature vector and considers textual context information. The weighted global temporal feature vector can be a global temporal feature vector representing different weight information. The aforementioned global temporal feature vector can be obtained through the following steps: The global temporal feature vector is subjected to three linear transformations to obtain a query vector, a key vector, and a value vector. The query vector can be the vector corresponding to the product of the global temporal feature vector and a preset query weight vector; the key vector can be the vector corresponding to the product of the global temporal feature vector and a preset key vector; and the value vector can be the vector corresponding to the product of the global temporal feature vector and a preset value vector. The query vector, key vector, and value vector are then linearly projected to obtain a preset threshold of parallel subspaces. The preset threshold can be the dimension value of the query vector, key vector, and value vector. Attention weights for the preset threshold of parallel subspaces are calculated using multi-head attention to obtain a preset threshold of weight vectors. The preset threshold of weight vectors are then concatenated to obtain the weighted global temporal feature vector. Next, the aforementioned bidirectional dynamic word feature vector is input into the first convolutional extraction layer, the first gating unit, the second convolutional extraction layer, the second gating unit, the third convolutional extraction layer, and the third gating unit to obtain the third local feature vector. The first convolutional extraction layer can be a 3x3 convolutional layer. The first gating unit described above can be used to control the propagation strength of the first local feature perception vector, alleviate the gradient vanishing problem, and enhance the local features using a GRU (Gated Recurrent Unit). The second convolutional extraction layer described above can be a 5*5 convolutional layer. The third convolutional extraction layer described above can be a 7*7 convolutional layer. Subsequently, the first local feature vector output by the first convolutional extraction layer, the second local feature vector output by the second convolutional extraction layer, and the third local feature vector output by the third convolutional extraction layer are input into an average pooling layer to obtain a multi-granularity local feature vector. This multi-granularity local feature vector can be a feature vector representing different local features. Then, the weighted global temporal feature vector and the multi-granularity local feature vector are fused to obtain a multi-level semantic feature vector. This multi-level semantic feature vector can be a feature vector obtained after fusing the multi-granularity local features.Finally, the multi-level semantic feature vectors are input into the fully connected layer to obtain the processor's initial parameter recognition information.

[0032] Sub-step 6: The above-mentioned image processor hardware information set and the above-mentioned processor initial parameter identification information are determined as image processor identification information.

[0033] Step 102: Collect data from the image processor set through the processor driver adapter and system environment sensors to obtain processor performance information set, processor operating scenario information set, and operating environment information set.

[0034] In some embodiments, the aforementioned execution entity can acquire data from the aforementioned image processor set through a processor driver adapter and system environment sensors to obtain a processor performance information set, a processor operating scenario information set, and an operating environment information set. The processor driver adapter can be a driver adaptation module adapted to different types of image processors, a software tool that directly acquires multi-dimensional operating data of the image processor without requiring large-scale modifications. For example, the processor driver adapter can be Intel oneAPI (an open-source cross-architecture programming toolkit). The system environment sensors can be sensors used to acquire temperature and humidity data for heterogeneous hardware compatible systems. The processor performance information in the processor performance information set can be information characterizing the operating state and performance of the image processor. The processor performance information can include, but is not limited to, at least one of the following: processor memory capacity, processor computation time (e.g., floating-point operations per second), frame rate, throughput, and graphics rendering performance. The processor operating scenario information in the processor operating scenario information set can be scenario information characterizing the resource consumption characteristics of the image processor. For example, the processor operating scenario information set can include, but is not limited to, at least one of the following: deep learning scenarios, graphics rendering scenarios, game scenarios, and video encoding / decoding scenarios. The operating environment information in the above-mentioned operating environment information set can be the temperature and humidity information of the space area where the heterogeneous hardware compatible system is located.

[0035] In practice, the aforementioned execution entity can first obtain processor performance information through the processor driver adapter's RESTful API via the BMC (Baseboard Management Controller) of the image processor set, and obtain the operating environment information of the heterogeneous hardware-compatible system from system environment sensors. Then, it queries a scene performance mapping table using the processor performance information to obtain the processor's running scene information. This scene performance mapping table can be a form used to record scene information corresponding to different processor performance information sets. For example, a record in the scene performance mapping table could be: if the processor performance information includes an average computational workload greater than or equal to 70 and an average memory utilization greater than or equal to 60%, then the processor's running scene information is deep learning scene information.

[0036] In some optional implementations of certain embodiments, the above-mentioned data acquisition of the image processor set through the processor driver adapter and system environment sensors to obtain processor performance information set, processor operating scene information set, and operating environment information set may include the following steps:

[0037] The first step is to obtain the interface documentation information set of the aforementioned image processor set. This interface documentation information set can be documents that record the interface specifications and performance information of the aforementioned image processor set.

[0038] The second step involves performing interface association mapping and encapsulation on the aforementioned processor driver adapters based on the interface documentation information set, resulting in an encapsulated processor driver adapter. This encapsulated processor driver adapter can be an adapter that uniformly encapsulates the aforementioned processor driver adapters into a recognizable standardized interface, thereby masking the interface differences between processor driver adapters.

[0039] In practice, the aforementioned execution entity can first parse the interface documentation information set to obtain the interface parameter information set. This interface parameter information may include, but is not limited to, at least one of the following: interface function name, interface parameter requirements, interface return value format, and interface call permission information. Then, a generic adapter layer is developed to encapsulate the aforementioned interface parameter information set, resulting in a post-encapsulated processor driver adapter.

[0040] The third step involves optimizing the resource data of the encapsulated post-processor driver adapter to obtain an optimized post-processor driver adapter. This resource data optimization may include, but is not limited to, at least one of the following: data calibration, low-latency optimization using asynchronous acquisition and cache updates, exception handling, and resource thread usage optimization. Data calibration can prevent deviations in data acquired by different GPUs. Low-latency optimization can meet the needs of real-time monitoring. Exception handling can prevent data interruptions caused by temporary GPU offline. Resource thread usage optimization can ensure that it does not affect core GPU operations (e.g., deep learning, graphics rendering).

[0041] The fourth step is to perform device synchronization processing on the optimized post-processor driver adapter and the system environment sensor to obtain the synchronized post-processor driver adapter and the synchronized system environment sensor.

[0042] The fifth step involves using the aforementioned post-synchronization processor driver adapter and the aforementioned post-synchronization system environment sensor to collect data from the aforementioned image processor set based on the aforementioned image processor identification information set, thereby obtaining an initial processor performance information set, a processor operating scenario information set, and an operating environment information set. The initial processor performance information set can be multi-dimensional performance information of the image processor set collected through the post-synchronization processor driver adapter. In practice, the executing entity can first determine the connection between the post-synchronization processor driver adapter and the image processor set's BMC's Restful API using the image processor identification information set to obtain the initial processor performance information set. Then, it can determine the processor operating scenario information set using the initial processor performance information set. Finally, it can collect the operating environment information set using the post-synchronization system environment sensor.

[0043] The sixth step involves identifying the feature importance of each performance feature set included in the initial processor performance information set, thus obtaining a performance feature importance set. The performance feature importance within this set characterizes the degree of importance of the performance feature information. This feature importance identification can be performed using principal component analysis.

[0044] Step 7: Based on the aforementioned performance characteristic importance groups, sort and filter the initial processor performance information set to obtain the processor performance information set. In practice, the execution entity can sort the performance characteristics in descending order according to their importance in the aforementioned performance characteristic importance groups to obtain a performance characteristic importance sequence set. Then, from each performance characteristic importance sequence set, select the initial processor performance information groups corresponding to the top preset number of performance characteristic importance groups to obtain the processor performance information set. The preset number of importance groups can be a pre-set value, which can be determined according to specific circumstances and will not be elaborated further here.

[0045] Step 103, for each image processor, perform the following layered heat dissipation steps:

[0046] Step 1031: Determine the processor load information based on the processor running scene information and processor performance information corresponding to the image processor.

[0047] In some embodiments, the execution entity can determine the processor load information based on the processor operating scenario information and processor performance information corresponding to the image processor. The processor load information can characterize the resource utilization and computing power of the image processor.

[0048] In some optional implementations of certain embodiments, the processor performance information includes: computational workload information, video memory usage information, and rendering frame rate information. The computational workload information characterizes the efficiency of the graphics processor when performing computational tasks, i.e., the number of floating-point operations per second. The video memory usage information characterizes the performance of the graphics processor, i.e., the percentage of video memory resources currently occupied by the graphics processor relative to the total video memory capacity. The rendering frame rate information can be a measure used to measure the number of displayed frames.

[0049] The above determination of processor load information based on the processor operating scene information and processor performance information corresponding to the image processor may include the following steps:

[0050] The first step is to standardize the above-mentioned computational workload information, video memory usage information, and rendering frame rate information to obtain standardized computational workload information, standardized video memory usage information, and standardized rendering frame rate information.

[0051] The second step involves determining the initial load weight set for the standardized computational workload, standardized memory usage, and standardized rendering frame rate information based on the aforementioned processor runtime information. This initial load weight set can be the numerical values ​​used to determine the weights of these three information within the context of the processor runtime information. For example, if the processor runtime information is a deep learning scenario, the initial load weight set could be 0.4, 0.35, and 0.25. If the processor runtime information is a graphics rendering scenario, the initial load weight set could be 0.45, 0.30, and 0.25. This determination can be performed using a subjective-objective assignment method.

[0052] The third step involves real-time deviation correction of the initial load weight value set based on the aforementioned processor performance information, resulting in a corrected load weight value set. In practice, the execution entity can utilize a correction rule engine to perform real-time deviation correction of the initial load weight value set based on the aforementioned processor performance information, thereby obtaining a corrected load weight value set. The correction rule engine can be a rule engine that includes correction rule constraint information. For example, the correction rule constraint information could be a rule that states, "When the mean of the standardized memory usage information is greater than or equal to 80, and the mean of the standardized computational workload information is less than 50, then the weight of the standardized memory usage information is increased by 5%, and the weight of the standardized computational workload information is decreased by 5%."

[0053] The fourth step is to perform a weighted summation of the above-mentioned corrected load weight value set, the above-mentioned standardized computational task information, the above-mentioned standardized video memory usage information, and the above-mentioned standardized rendering frame rate information to obtain the processor load information.

[0054] Step 1032: Based on the processor load information and the corresponding image processor recognition information, perform layered heat dissipation processing on the image processor to obtain initial heat dissipation information.

[0055] In some embodiments, the execution entity can perform layered heat dissipation processing on the image processor based on the processor load information and the corresponding image processor identification information to obtain initial heat dissipation information. This initial heat dissipation information can be information about the heat dissipation operations performed on the image processor. In practice, firstly, the load level information of the image processor is determined using the image processor identification information. This load level information can include: low load information, medium load information, and high load information. It should be noted that due to the different performance differences of different types of image processors, the load levels that the same processor load information can withstand are also different. When the processor load information is low load information (the load value corresponding to the processor load information is between 0 and 30), the initial heat dissipation information can be information about using a low-speed fan or turning off the fan for heat dissipation. For example, the initial heat dissipation information can be information about the fan rotating at a speed of 1000 revolutions per minute. When the processor load information is medium load information (the load value corresponding to the processor load information is between 31 and 70), the initial heat dissipation information can be information about starting a medium-speed fan or turning on auxiliary cooling equipment to enhance the heat dissipation effect. For example, initial cooling information could be that the fan speed is 2500 RPM while auxiliary cooling is activated. When the processor load information is high (the corresponding load value is between 71 and 100), the above initial cooling information could be that all cooling resources, including liquid cooling systems, are activated to ensure the GPU can operate stably in high-temperature environments. For example, the above initial cooling information could be that the fan speed is 4000 RPM while liquid cooling is activated.

[0056] In some optional implementations of certain embodiments, the above-mentioned layered heat dissipation processing of the image processor based on the processor load information and the corresponding image processor identification information to obtain initial heat dissipation information may include the following steps:

[0057] The first step involves comparing the processor load information with the load level classification threshold set corresponding to the image processor recognition information to obtain a comparison result set. The load level classification thresholds in the above load level classification threshold set can be pre-set thresholds for classifying processor load information levels. For example, the load level classification thresholds could be 30 and 70 points. The comparison results in the above comparison result set represent the magnitude relationship between the processor load information and the load level classification thresholds.

[0058] The second step is to determine the load level information of the image processor based on the comparison result set.

[0059] The third step involves determining the target cooling execution information for the image processor based on the aforementioned load level information and cooling rule engine. This target cooling execution information can be the operation information to be performed to cool the image processor. For example, it could be the execution information of starting the fan for cooling at a speed of 2500 rpm. The cooling rule engine can be a rule engine formed by expert experience regarding the cooling operations performed on the image processor under different load levels. In practice, the executing entity can use the load level information to match the cooling rule engine to obtain the target cooling rule information, which serves as the target cooling execution information.

[0060] The fourth step involves a hysteresis interval switching process. In response to the determination that the target heat dissipation execution information and the current heat dissipation execution information differ, the heat dissipation device set corresponding to the current heat dissipation execution information is switched to the operating state of the heat dissipation device set corresponding to the target heat dissipation execution information, serving as the initial heat dissipation information. Here, the current heat dissipation execution information is the heat dissipation execution information being executed by the image processor. This hysteresis interval switching process can optimize the switching mechanism by introducing a hysteresis value, reducing unnecessary heat dissipation switching, avoiding mechanical impact on the fan, and improving safety. The hysteresis value can be a value obtained through expert experience and statistics. For example, when the switching process is from a low load level to a medium load level, 30% is used as the threshold; however, when switching from a medium load level to a low load level, 25% (i.e., 30% minus the hysteresis value of 5%) is used as the threshold.

[0061] Fifth step: In response to the determination that the target heat dissipation execution information and the current heat dissipation execution information are the same, the current heat dissipation execution information is determined as the initial heat dissipation information.

[0062] Step 1033: Based on the processor load information, the corresponding processor performance information, and the operating environment information, perform multi-dimensional risk identification on the image processor to obtain processor temperature risk information, and control the alarm device to perform risk alarm processing based on the processor temperature risk information.

[0063] In some embodiments, the execution entity can perform multi-dimensional risk identification on the image processor based on the processor load information, corresponding processor performance information, and operating environment information to obtain processor temperature risk information, and control an alarm device to perform risk alarm processing based on the processor temperature risk information. The processor temperature risk information characterizes the degree of risk present in the image processor under the given processor load and performance information. The alarm device can be a hardware device that performs alarm operations based on the processor temperature risk information. The alarm device can be an audible and visual alarm device. The risk alarm processing can involve activating an audible and visual alarm and sending an SMS message to the corresponding maintenance personnel's terminal device (e.g., a mobile phone), as well as an email containing processor temperature risk information, processor load information, processor performance information, and a risk analysis process.

[0064] As an example, the aforementioned execution entity can first use a subjective and objective assignment method to determine the risk weight value set of the processor load information, the corresponding processor performance information, and the operating environment information. Then, it can perform a weighted summation of the risk weight value set, the processor load information, the corresponding processor performance information, and the operating environment information to obtain the processor temperature risk information, and control the alarm device to perform risk alarm processing based on the processor temperature risk information.

[0065] In some optional implementations of certain embodiments, the process of performing multi-dimensional risk identification on the image processor based on the processor load information, corresponding processor performance information, and operating environment information to obtain processor temperature risk information, and controlling the alarm device to perform risk alarm processing based on the processor temperature risk information, may include the following steps:

[0066] The first step involves preprocessing the aforementioned processor performance information, operating environment information, and processor load information to obtain preprocessed processor performance information, preprocessed operating environment information, and preprocessed processor load information. The processor performance information further includes: processor operating temperature, heat dissipation device operating status information, and processor power consumption information. The data preprocessing may include, but is not limited to, at least one of the following: missing value handling, outlier handling, and data normalization. The processor operating temperature can be the operating temperature of the image processor chip. The processor power consumption information can be information about the energy consumed by the image processor during operation. The heat dissipation device operating status information can be information about the heat dissipation device's operation.

[0067] The second step is to determine the threshold set of membership parameters for the risk fuzzy membership trigonometric function. This risk fuzzy membership trigonometric function can be used to map the preprocessor performance information, preprocessor operating environment information, and preprocessor load information to one or more fuzzy sets (e.g., low, medium, and high), and to provide the degree of membership to the respective fuzzy set. For example, the risk fuzzy membership trigonometric function can be a triangular function. The membership parameter thresholds in the threshold set can be used to determine the boundary values ​​and representative values ​​of the fuzzy set. This threshold set can include: the lower bound of the fuzzy set (i.e., the left vertex of the triangle), the peak point of the fuzzy set (i.e., the vertex of the triangle), and the upper bound of the fuzzy set (i.e., the right vertex of the triangle).

[0068] The third step involves performing fuzzy partitioning on the preprocessed processor performance information, preprocessed operating environment information, and preprocessed processor load information based on the aforementioned membership parameter threshold set and risk fuzzy membership trigonometric function. This yields three fuzzy information sets: processor performance fuzzy information set, operating environment fuzzy information set, and processor load fuzzy information set. Specifically, the processor performance fuzzy information set can be multiple fuzzy sets to which the preprocessed processor performance information belongs after partitioning, along with their membership value sets. The operating environment fuzzy information set can be multiple fuzzy sets to which the preprocessed processor performance information belongs after partitioning, along with their membership degree sets. The processor load fuzzy information set can be multiple fuzzy sets to which the preprocessed processor performance information belongs after partitioning, along with their membership value sets. In practice, the preprocessed processor performance information, preprocessed operating environment information, and preprocessed processor load information are input into a risk fuzzy membership trigonometric function with membership parameter thresholds to obtain the processor performance fuzzy information set, operating environment fuzzy information set, and processor load fuzzy information set.

[0069] The fourth step involves defuzzifying the processor performance fuzzy information set, the operating environment fuzzy information set, and the processor load fuzzy information set based on the constructed fuzzy inference rule base to obtain the processor risk level. This processor risk level characterizes the risk level of the graphics processor set. The fuzzy inference rule base can be a set of IF-THEN fuzzy rules designed based on GPU operating mechanisms and thermal management expertise. A single rule in the fuzzy inference rule base could be: IF T_norm=H AND L_core_norm=H AND T_env_norm=HTHEN R=H, meaning that high ambient temperature and high load indicate high risk. The defuzzification process can involve fuzzy inference using the Mamdani inference method followed by defuzzification using the Centroid method.

[0070] Fifth, based on the aforementioned fuzzy information sets of processor performance, operating environment, processor load, and processor risk levels, construct a directed graph of processor risk. This directed graph can be constructed using the aforementioned fuzzy information sets of processor performance and operating environment as intermediate nodes, the aforementioned fuzzy information set of processor load as the root node, and the processor risk level as the target node.

[0071] Step 6: Based on the acquired historical image processor information set, perform probabilistic inference on the aforementioned processor risk directed graph to obtain a node fuzzy state information set. This historical image processor information set can be a set of processor performance information, processor operating scenario information, and operating environment information collected from image processor operations prior to the current time. The node fuzzy state information in this set can be the posterior probability distribution set of the aforementioned processor risk directed graph under the historical image processor information set.

[0072] As an example, the aforementioned execution entity can use the maximum likelihood estimation method and variable elimination method to perform probabilistic reasoning on the aforementioned processor risk directed graph based on the acquired historical image processor information set, thereby obtaining the node fuzzy state information set.

[0073] Step 7: Input the aforementioned fuzzy state information set of nodes into the risk probability graph inference model to obtain processor temperature risk information, and control the alarm device to perform risk alarm processing based on the processor temperature risk information. The aforementioned risk probability graph inference model can be a model that fuses multi-source data to perform causal relationship inference on the input fuzzy state information set of nodes to output processor temperature risk information. For example, the aforementioned risk probability graph inference model can be a Bayesian network model. The aforementioned risk alarm processing can be as follows: when the processor temperature risk information is high-risk, trigger a level 1 alarm and send a command to reduce the load; when the processor temperature risk information is medium-risk, trigger a level 2 alarm and continue monitoring; when the processor temperature risk information is low-risk, no alarm processing is triggered.

[0074] Step 1034: Based on the processor temperature risk information, dynamically adjust the initial heat dissipation information to obtain the target heat dissipation information.

[0075] In some embodiments, the execution entity can dynamically adjust the initial heat dissipation information based on the processor temperature risk information to obtain target heat dissipation information. The target heat dissipation information can be information on a heat dissipation strategy that fine-tunes the initial heat dissipation information to satisfy both the processor temperature risk information and the processor load information of the image processor. In practice, the execution entity can utilize a TFT model (Temporal...) FusionTransformer dynamically adjusts the initial heat dissipation information based on the processor temperature risk information to obtain the target heat dissipation information.

[0076] In addressing the aforementioned technical problems in the application scenario—the heat dissipation of image processors in data centers—the following challenges arise: image processors in data centers experience significant changes every second, making static heat dissipation strategies unsuitable for real-time fluctuations. Furthermore, the various heat dissipation-influencing factors—processor performance information, operating environment information, and processor temperature risk information—are non-linear and high-dimensional, leading to low accuracy in the generated target heat dissipation information for the image processor, reducing its security and wasting heat dissipation resources. Based on the characteristics of this application scenario—dynamic adjustment of heat dissipation information, dynamic time-varying nature of various heat dissipation influencing factors, low latency, multi-objective collaborative optimization, and non-linear and high-dimensional relationships among these factors—we have decided to adopt the following solution:

[0077] In some optional implementations of certain embodiments, the above-mentioned dynamic adjustment of the initial heat dissipation information based on the processor temperature risk information to obtain target heat dissipation information, and the control of the image processor to perform heat dissipation processing according to the target heat dissipation information, may include the following steps:

[0078] The first step involves inputting the aforementioned processor temperature risk information, initial heat dissipation information, corresponding processor performance information, and operating environment information into a risk-based thermal mapping model to obtain corrected processor temperature risk information, corrected heat dissipation information, corrected processor performance information, and corrected operating environment information. This risk-based thermal mapping model can be a model that corrects the input processor temperature risk information, initial heat dissipation information, corresponding processor performance information, and operating environment information to adapt to the processor temperature risk information and energy-saving thermal resources, outputting the corrected processor temperature risk information, corrected heat dissipation information, corrected processor performance information, and corrected operating environment information. For example, the risk-based thermal mapping model can be an XGBoost model. The model parameters of the risk-based thermal mapping model can be a model with 100-200 trees, a learning rate of 0.05-0.1, and a maximum depth of 5-8. The training process of the risk-based thermal mapping model can be a training process that first trains the model using a preset training set, then evaluates the risk control rate and energy consumption reduction rate corresponding to each corrected data point using a validation set, and finally optimizes the model using a grid search parameter tuning algorithm. The aforementioned preset training set may include sample processor temperature risk information, sample initial heat dissipation information, sample processor performance information, and sample operating environment information.

[0079] The second step involves determining the heat dissipation state space information, heat dissipation action space information, heat dissipation temperature control resource reward function, and heat dissipation agent for the aforementioned image processor. The heat dissipation agent can be an agent that dynamically adjusts the initial heat dissipation information using the heat dissipation state space information, heat dissipation action space information, heat dissipation temperature control resource reward function, and heat dissipation agent. The heat dissipation state space information can be a set of various states of the heat dissipation agent in the environment corresponding to the processor temperature risk information. This information may include: corrected processor temperature risk information, corrected heat dissipation information, corrected processor performance information, and corrected operating environment information. The heat dissipation action space information can be a set of all possible actions that the heat dissipation agent can execute in each heat dissipation state included in the heat dissipation state space information. This information may include: continuous actions such as the speed correction amount of the heat dissipation device and the liquid cooling start-up risk threshold correction amount; discrete actions may include heat dissipation resource energy saving and heat dissipation risk control. The heat dissipation temperature control resource reward function can be a function of the immediate reward obtained by the heat dissipation agent from the environment after executing any action included in the heat dissipation action space information. The aforementioned heat dissipation and temperature control resource reward function can be a function of the difference between 1 and the risk exceedance rate, the weighted sum of the difference between 1 and the relative energy consumption of heat dissipation resources, and the weighted difference of the correction step size. For example, the weight values ​​for the aforementioned weighted processing can be 0.7, 0.2, and 0.1, respectively. The aforementioned risk exceedance rate can be the ratio of the duration of the image processor's high-risk processor temperature risk information to the total duration. The aforementioned relative energy consumption of heat dissipation resources can be the ratio of the corrected resource energy consumption to the energy consumption of the resource corresponding to the initial heat dissipation information. The aforementioned correction step size can be a penalty component used to avoid excessively large single correction magnitudes.

[0080] The third step involves inputting the corrected processor temperature risk information, corrected heat dissipation information, corrected processor performance information, and corrected operating environment information into the heat dissipation strategy network based on the aforementioned heat dissipation state space information and heat dissipation action space information. This yields heat dissipation action probability distribution information and heat dissipation sampling action information. The heat dissipation strategy network can be a deep neural network model that selects actions from the input corrected processor temperature risk information, corrected heat dissipation information, corrected processor performance information, and corrected operating environment information to output heat dissipation action probability distribution information and heat dissipation sampling action information. This heat dissipation strategy network can be an Actor model in a near-end policy optimization algorithm. The heat dissipation action probability distribution information can be the probability values ​​of each heat dissipation action included in the aforementioned heat dissipation action space information. The heat dissipation sampling action information can be action information output based on the mean and standard deviation of a Gaussian distribution. For example, the heat dissipation sampling action information can be information on the correction amount of the cooling fan speed.

[0081] As an example, the aforementioned execution entity can first perform state encoding concatenation on the corrected processor temperature risk information, corrected heat dissipation information, corrected processor performance information, and corrected operating environment information to obtain a heat dissipation concatenation feature vector. Then, based on the aforementioned heat dissipation state space information and heat dissipation action space information, the aforementioned heat dissipation concatenation feature vector is input into the heat dissipation strategy network to obtain initial action probability distribution information and initial sampling action information. Finally, action constraint verification is performed on the initial action probability distribution information and initial sampling action information to output initial action probability distribution information and initial sampling action information that conform to the action constraints, thus obtaining heat dissipation action probability distribution information and heat dissipation sampling action information. The aforementioned action constraint verification can be performed using safety constraint information of the heat dissipation equipment and energy-saving constraint information of heat dissipation resources.

[0082] Fourth, based on the aforementioned heat dissipation temperature control resource function, the heat dissipation agent is controlled to execute the heat dissipation action corresponding to the aforementioned heat dissipation sampling action information, thereby obtaining the current heat dissipation state information set and the action reward function value. The aforementioned action reward function value can be the value obtained by inputting the heat dissipation action into the heat dissipation temperature control resource function after the heat dissipation agent executes the heat dissipation action. The aforementioned current heat dissipation state information set can be the processor temperature risk information at the current time after the image processor executes the action corresponding to the heat dissipation sampling action information, the aforementioned initial heat dissipation information, the corresponding processor performance information, and the operating environment information.

[0083] The fifth step involves inputting the corrected processor temperature risk information, corrected heat dissipation information, corrected processor performance information, corrected operating environment information, and the current heat dissipation state information set into the heat dissipation value network to obtain a first cumulative heat dissipation expectation value and a second cumulative heat dissipation expectation value. The heat dissipation value network can be a deep neural network model that evaluates the state value of the input corrected processor temperature risk information, corrected heat dissipation information, corrected processor performance information, corrected operating environment information, and the current heat dissipation state information set to output the first and second cumulative heat dissipation expectation values. For example, the heat dissipation value network can be the Critic model in a near-end policy optimization algorithm. The first cumulative heat dissipation expectation value can be the numerical value output by the heat dissipation value network for the corrected processor temperature risk information, corrected heat dissipation information, corrected processor performance information, and corrected operating environment information, i.e., the mathematical expectation of the long-term cumulative reward in the original state. The second cumulative heat dissipation expectation value can be the mathematical expectation of the long-term cumulative reward corresponding to the current heat dissipation state information set by the heat dissipation value network.

[0084] Step 6: Based on the first and second cumulative heat dissipation expectation values, determine the action execution value. This action execution value characterizes the performance of the heat dissipation agent's heat dissipation action to measure its quality. In practice, the executing entity can determine the action execution value by summing the product of the image processor's state feedback value, the value weight, and the first cumulative heat dissipation expectation value after the heat dissipation agent executes the heat dissipation sampling action information, and then by calculating the difference between this sum and the second cumulative heat dissipation expectation value. The value weight can be a pre-set value, and its range can be any value within [0.9, 0.99].

[0085] Step 7: Based on the aforementioned action execution value, dynamically update the heat dissipation strategy network and heat dissipation value network to obtain the updated heat dissipation strategy network and the updated heat dissipation value network. The dynamic update can be achieved by using an action execution value + strategy pruning mechanism to update the heat dissipation strategy network, and by using a mean squared error loss function to update the heat dissipation value network.

[0086] Step 8: Based on the updated heat dissipation strategy network and the updated heat dissipation value network, the initial heat dissipation information is dynamically adjusted to obtain the target heat dissipation information, and the image processor is controlled to perform heat dissipation processing according to the target heat dissipation information. In practice, the executing entity can input the initial heat dissipation information into the updated heat dissipation strategy network to obtain the target heat dissipation information.

[0087] The above-described technical solution and its related content, as an inventive point of this disclosure, solve the technical problem of "low accuracy of generated target heat dissipation information, reducing image processor security and wasting heat dissipation resources." Factors leading to low accuracy of generated target heat dissipation information, reducing image processor security and wasting heat dissipation resources are often as follows: In data centers, image processors undergo significant changes every second; static heat dissipation strategies cannot adapt to these real-time changes. Furthermore, the various heat dissipation influencing factors affecting image processor heat dissipation—processor performance information, operating environment information, and processor temperature risk information—are non-linear and high-dimensional data, resulting in low accuracy of generated target heat dissipation information, reducing image processor security and wasting heat dissipation resources. Solving these factors can improve the accuracy of generated target heat dissipation information, enhance image processor security, and reduce heat dissipation resource waste. To achieve this effect, this disclosure first determines the initially corrected heat dissipation influencing data through a risk-based heat dissipation mapping model. This improves the accuracy and quality of the corrected heat dissipation influencing data, facilitating a reduction in subsequent heat dissipation agent search costs and avoiding meaningless random actions. Secondly, based on the heat dissipation state space information, heat dissipation action space information, and the heat dissipation agent, the probability distribution information of heat dissipation actions and the heat dissipation sampling action information are determined through the heat dissipation strategy network. This improves the accuracy of the heat dissipation sampling action information, making it closer to the optimal solution and avoiding random exploration by the heat dissipation agent. Next, based on the heat dissipation temperature control resource function and the heat dissipation value network, the execution value of actions is determined. The heat dissipation temperature control resource function uses a multi-objective optimization function to balance energy saving of heat dissipation resources and image processor risk, which can improve the safety of the image processor and reduce the waste of heat dissipation resources. Furthermore, the execution value of actions can quantify the merits of heat dissipation actions, clarifying the update direction for subsequent model updates. Finally, the heat dissipation strategy network and the heat dissipation value network are dynamically updated to generate target heat dissipation information, and the image processor is controlled to perform heat dissipation processing according to the target heat dissipation information. This improves the quality and accuracy of the target heat dissipation information, thereby enhancing the adaptability between the image processor and the target heat dissipation information, improving the safety and stability of the image processor, and reducing the waste of heat dissipation resources.

[0088] Step 104: Based on the obtained target heat dissipation information set, control the heat dissipation equipment to perform heat dissipation operations to perform system heat dissipation treatment on the heterogeneous hardware compatible system.

[0089] In some embodiments, the executing entity can control a heat dissipation device to perform heat dissipation operations to cool the heterogeneous hardware compatible system based on the obtained target heat dissipation information set. The heat dissipation device can be a device for cooling the heterogeneous hardware compatible system and the image processor. For example, the heat dissipation device may include, but is not limited to, at least one of the following: a cooling fan, a liquid cooling system. As an example, the executing entity can perform weighted fusion processing on the target heat dissipation information set to obtain global heat dissipation information, and then control the heat dissipation device to perform heat dissipation operations to cool the heterogeneous hardware compatible system.

[0090] In addressing the aforementioned technical problems in the application scenario—a data center with mixed types of image processors—the following technical issues often arise: The single-sided discretization algorithm only considers a single boundary curve of the airflow region, failing to account for the overall complexity of the airflow region and the complexity of complex areas. Furthermore, the forward propagation algorithm, being a greedy algorithm, suffers from global convergence problems and requires manual specification of the airflow region's size field, introducing subjectivity. This results in low mesh density and accuracy, low generation efficiency, and consequently, low accuracy and quality of the target heat dissipation information set. This reduces the heat dissipation efficiency of the heterogeneous hardware compatible system, lowers system stability and security, and wastes heat dissipation resources. Based on the characteristics of this application scenario—diverse image processor types, dynamic adjustment of heat dissipation information, low latency, and complex geometry of the data center and image processors—we have decided to adopt the following solution:

[0091] In some optional implementations of certain embodiments, controlling the heat dissipation device to perform heat dissipation operations to perform system heat dissipation processing on the heterogeneous hardware compatible system based on the obtained target heat dissipation information set may include the following steps:

[0092] The first step involves representing the geometric structure of the image processor set within the heterogeneous hardware compatible system using surface boundaries, resulting in a set of processor geometric surface parameters. These parameters may include: a first tangent vector metric, a tangent vector correlation metric, and a second tangent vector metric. The first tangent vector metric characterizes the length of the tangent vectors in the u-direction of the surface set corresponding to the geometric structure. The tangent vector correlation metric characterizes the inner product of the tangent vectors in the u-direction and v-direction of the surface set corresponding to the geometric structure, representing the correlation between the moving velocities of points in the two directions. The second tangent vector metric characterizes the length of the tangent vectors in the v-direction of the surface set corresponding to the geometric structure. This surface boundary representation can be achieved using B-Rep (Boundary Representation) algorithms.

[0093] The second step is to determine the set of parameters for the heat dissipation airflow region of the heterogeneous hardware compatible system. This heat dissipation airflow region can be any area within the heterogeneous hardware compatible system where heat dissipation gas flows. The set of parameters can include: global size, target size, adaptive angle, growth rate, and fusion tolerance. The global size can be the maximum value of the mesh size for the heat dissipation airflow region. The target size can be the minimum value of the mesh size for the heat dissipation airflow region. The adaptive angle characterizes the sensitivity of the mesh at points of change in the heat dissipation airflow region and is used to adjust the mesh size. A larger adaptive angle results in smoother mesh adjustments. An adaptive angle of 10 degrees is acceptable. The growth rate characterizes the magnitude of mesh size adjustment. A smaller growth rate results in smoother mesh size filtering. A growth rate of 1.2 is acceptable. The fusion tolerance characterizes the degree of aggregation of the vertices of the heat dissipation region parameters.

[0094] As an example, the aforementioned execution entity can first use the AABB (Axis-Aligned Bounding Box) algorithm to determine the diagonal length for the aforementioned heat dissipation region parameters. Then, the product of 0.05 and the aforementioned diagonal length is determined as the global dimension. Next, the product of 0.05 and the aforementioned global dimension is determined as the target dimension. Finally, the product of 0.05 and the aforementioned target dimension is used as the fusion tolerance.

[0095] The third step involves performing virtual fusion clustering on the set of fusion tolerances for the aforementioned heat dissipation region parameters, thereby obtaining a set of heat dissipation boundary vertex clusters. Specifically, each heat dissipation boundary vertex cluster in this set can be a vertex cluster obtained by placing any two heat dissipation boundary vertices whose distance is less than the fusion tolerance into the same cluster. The boundary vertices in this set can be key coordinate points describing the boundaries of the heat dissipation-related geometric structures (e.g., GPU, heatsink, liquid cooling pipes, air ducts, etc.) within the heat dissipation airflow region.

[0096] Fourth, for each heat dissipation boundary vertex in the above heat dissipation boundary vertex cluster set, perform the following filtering steps:

[0097] Sub-step 1: Based on the aforementioned set of surface representation parameters, determine the curve curvature and surface curvature sets of the aforementioned heat dissipation boundary vertices at the corresponding curved edges and surfaces. The curve curvature characterizes the degree of bending of the heat dissipation boundary vertex at the curve. The surface curvature in the aforementioned surface curvature set characterizes the degree of bending of the heat dissipation boundary vertex on the surface of the heat dissipation airflow region. In practice, the executing entity substitutes the aforementioned set of surface representation parameters into the three-dimensional curve curvature formula and the three-dimensional surface curvature formula to obtain the curve curvature and surface curvature sets.

[0098] Sub-step 2 involves filtering the curve curvature and surface curvature groups to obtain the filtered curvature. The filtered curvature can be the curvature with the largest numerical value.

[0099] Sub-step 3 involves converting the filtered curvature into a size value to obtain the curvature feature size value. In practice, the executing entity can first determine the ratio of 1 to the filtered curvature as the curvature radius. Then, it can determine the intersection point of the tangent vector measured by the first tangent vector and the circle corresponding to the curvature radius as the target point. Finally, it can determine the distance between the target point and the vertex of the heat dissipation boundary as the curvature feature size value.

[0100] Sub-step 4: Based on the vertex-edge distance set, determine the neighboring feature size value of the aforementioned heat dissipation boundary vertex, wherein the vertex-surface distance in the aforementioned vertex-edge distance set is the distance from the aforementioned heat dissipation boundary vertex to the opposite fluid domain edge. The aforementioned neighboring feature size value can characterize the degree of adjacency of the heat dissipation boundary vertex on adjacent edges.

[0101] As an example, the aforementioned execution entity can first select the vertex-curved edge distance with the smallest value from the set of vertex-curved edge distances, and use it as the target vertex-curved edge distance. Then, it determines the product of 0.5 and the target vertex-curved edge distance as the neighboring feature size value.

[0102] Sub-step 5 involves filtering the curvature feature size value, the neighboring feature size value, the target size, and the global size to obtain a filtered size value, which is then used as the endpoint size value. In practice, the executing entity can first filter the size value with the smallest value from the curvature feature size value, the neighboring feature size value, and the global size, and use this as the filtered size value. Then, it can filter the size value with the largest value from the filtered size value and the target size to obtain the filtered size value, which is then used as the endpoint size value.

[0103] Fifth, based on the aforementioned growth rate, adaptive boundary discretization is performed on each boundary curve in the set of boundary curves for the heat dissipation airflow region, resulting in a set of discrete points for the boundary curves. Here, the aforementioned boundary curves for the heat dissipation airflow region can be fluid domain surface curves whose endpoint dimensions are greater than the side length of the curved edge where the heat dissipation boundary vertex is located. The discrete points in the aforementioned set of discrete points for the boundary curves can characterize the size of the subsequently generated mesh.

[0104] The sixth step is to perform boundary point smoothing on the aforementioned discrete point set of the boundary curve to obtain a smoothed discrete point set. This smoothed discrete point set can be obtained by selecting the edge with more discrete points from the curve that simultaneously represents multiple surfaces.

[0105] Step 7: Based on the smoothed discrete point set described above, adaptive mesh generation and optimization are performed on the aforementioned heat dissipation airflow region to obtain heat dissipation mesh information. The optimization process can utilize the Laplace smoothing algorithm.

[0106] Step 8: Based on the aforementioned heat dissipation grid information, optimize and adjust the target heat dissipation information set, and control the heat dissipation equipment to perform heat dissipation operations to process the system heat dissipation of the heterogeneous hardware compatible system. In practice, the execution entity can utilize heuristic algorithms to optimize and adjust the target heat dissipation information set based on the aforementioned grid information, obtain system heat dissipation information, and control the heat dissipation equipment to perform heat dissipation operations based on the system heat dissipation information to process the system heat dissipation of the heterogeneous hardware compatible system. The heuristic algorithm can be an algorithm that optimizes the target heat dissipation information set from four dimensions: differentiated adaptation of different types of image processors, refinement of hierarchical strategies, thermal overlay avoidance, and resource balancing. The refinement of hierarchical strategies can be achieved by refining the heat dissipation resource configuration of each load level through the parameters of different types of image processors obtained from differentiated adaptation, balancing the cooling effect with energy-saving goals. The thermal overlay avoidance and resource balancing can be achieved by combining grid flow field data to optimize layout suggestions and heat dissipation coordination strategies for thermal overlay problems in the deployment of different types of image processors.

[0107] The above-described technical solution and its related content, as an inventive point of this disclosure, solve the technical problem of "reducing the heat dissipation efficiency of heterogeneous hardware compatible systems, reducing system stability and security, and wasting heat dissipation resources." Factors leading to reduced heat dissipation efficiency, stability, security, and wasted heat dissipation resources in heterogeneous hardware compatible systems are often as follows: One-sided discretization algorithms only target a single boundary curve of the heat dissipation airflow area, failing to consider the overall complexity of the heat dissipation airflow area and the complexity of complex regions; the forward propagation method is a greedy algorithm with global convergence problems, and requires manual specification of the size field of the heat dissipation airflow area, introducing a degree of subjectivity. This results in lower generated mesh density and accuracy, lower generation efficiency, and consequently, lower accuracy and quality of the target heat dissipation information set, reducing the heat dissipation efficiency, stability, security, and wasting heat dissipation resources in heterogeneous hardware compatible systems. Solving these factors can improve the heat dissipation efficiency, stability, security, and reduce the waste of heat dissipation resources in heterogeneous hardware compatible systems. To achieve this effect, this disclosure first determines the surface boundary representation and the heat dissipation region parameter set, which can control the mesh generation density and achieve reasonable mesh density transitions at complex boundaries with multi-sided associations. Secondly, adaptive boundary discretization of the surface representation parameter set maintains good endpoint size values, avoids conflicts with growth rate and feature size, and improves the ability of the boundary curve discrete point set to better represent the geometric characteristics of the fluid domain, as well as the mesh density in complex regions. Subsequently, boundary point smoothing improves the smoothness of transitions between discrete points and the coordination of regional boundaries, thereby enhancing the connectivity integrity of the subsequently generated mesh. Then, by combining the front-end propulsion algorithm and the Delaunay algorithm, adaptive mesh generation and optimization are performed on the heat dissipation airflow region based on the smoothed discrete point set. This improves the conformity and accuracy of the generated mesh, reduces a large number of intersection calculations, minimizes computational resource waste, and increases mesh generation efficiency. Finally, based on the mesh information, the target heat dissipation information set is optimized and adjusted to control the heat dissipation equipment to perform heat dissipation operations for the heterogeneous hardware compatible system. This improves the heat dissipation effect of the heterogeneous hardware compatible system, reduces the waste of heat dissipation resources, and enhances the performance and stability of the image processor and the heterogeneous hardware compatible system.

[0108] Further reference Figure 2 As an implementation of the methods shown in the above figures, this disclosure provides some embodiments of a layered heat dissipation device based on an image processor. These device embodiments are similar to... Figure 1 Corresponding to the method embodiments shown, this image processor-based layered heat dissipation device can be specifically applied to various electronic devices.

[0109] like Figure 2 As shown, a layered heat dissipation device 200 based on an image processor includes: a device identification unit 201, a data acquisition unit 202, an execution unit 203, and a control unit 204. The device identification unit 201 is configured to: perform device identification on the image processor set included in the heterogeneous hardware compatible system, obtaining an image processor identification information set. The data acquisition unit 202 is configured to: acquire data from the aforementioned image processor set through a processor driver adapter and system environment sensors, obtaining a processor performance information set, a processor operating scenario information set, and an operating environment information set. Execution unit 203 is configured to perform the following layered heat dissipation steps for each image processor: determine processor load information based on the processor operating scenario information and processor performance information corresponding to the image processor; perform layered heat dissipation processing on the image processor based on the processor load information and the corresponding image processor identification information to obtain initial heat dissipation information; perform multi-dimensional risk identification on the image processor based on the processor load information, the corresponding processor performance information, and the operating environment information to obtain processor temperature risk information, and control the alarm device to perform risk alarm processing based on the processor temperature risk information; and dynamically adjust the initial heat dissipation information based on the processor temperature risk information to obtain target heat dissipation information. Control unit 204 is configured to control the heat dissipation device to perform heat dissipation operations to perform system heat dissipation processing on the heterogeneous hardware compatible system based on the obtained target heat dissipation information set.

[0110] It is understandable that the units described in the image processor-based layered heat dissipation device 200 and the reference Figure 1 The steps in the described method correspond to each other. Therefore, the operations, features, and beneficial effects described above for the method also apply to the image processor-based layered heat dissipation device 200 and the units contained therein, and will not be repeated here.

[0111] The following is for reference. Figure 3 It shows a schematic diagram of the structure of an electronic device (e.g., an electronic device) 300 suitable for implementing some embodiments of the present disclosure. Figure 3 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this disclosure.

[0112] like Figure 3As shown, the electronic device 300 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage device 308 into a random access memory (RAM) 303. The RAM 303 also stores various programs and data required for the operation of the electronic device 300. The processing unit 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0113] Typically, the following devices can be connected to I / O interface 305: input devices 306 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 308 including, for example, magnetic tapes, hard disks, etc.; and communication devices 309. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 3 An electronic device 300 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 3 Each box shown can represent a device or multiple devices as needed.

[0114] In particular, according to some embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 309, or installed from storage device 308, or installed from ROM 302. When the computer program is executed by processing device 301, it performs the functions defined in the methods of some embodiments of this disclosure.

[0115] It should be noted that, in some embodiments of this disclosure, the computer-readable medium described above may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In some embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0116] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0117] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more programs. When the aforementioned one or more programs are executed by the electronic device, the electronic device causes the following: it performs hardware identification on the image processor set included in the heterogeneous hardware compatible system to obtain an image processor identification information set; it collects data from the image processor set through a processor driver adapter and system environment sensors to obtain a processor performance information set, a processor operating scenario information set, and an operating environment information set; for each image processor, it performs the following layered heat dissipation steps: it determines processor load information based on the processor operating scenario information and processor performance information corresponding to the image processor; it performs layered heat dissipation processing on the image processor based on the processor load information and the corresponding image processor identification information to obtain initial heat dissipation information; it performs multi-dimensional risk identification on the image processor based on the processor load information, the corresponding processor performance information, and the operating environment information to obtain processor temperature risk information, and controls an alarm device to perform risk alarm processing based on the processor temperature risk information; it dynamically adjusts the initial heat dissipation information based on the processor temperature risk information to obtain target heat dissipation information; and it controls a heat dissipation device to perform heat dissipation operations to perform system heat dissipation processing on the heterogeneous hardware compatible system based on the obtained target heat dissipation information set.

[0118] Computer program code for performing operations of some embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0119] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0120] The units described in some embodiments of this disclosure can be implemented in software or in hardware. The described units can also be housed in a processor; for example, a processor may be described as including a device identification unit, a data acquisition unit, an execution unit, and a control unit. The names of these units do not necessarily limit the specific unit; for example, a device identification unit may also be described as "a unit that performs hardware identification on a set of image processors included in a heterogeneous hardware compatible system to obtain an image processor identification information set."

[0121] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0122] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A layered heat dissipation method based on an image processor, comprising: Device identification is performed on the set of image processors included in the heterogeneous hardware compatible system to obtain the image processor identification information set; Data is collected from the image processor set through the processor driver adapter and system environment sensors to obtain processor performance information set, processor operating scenario information set and operating environment information set; For each image processor, perform the following layered thermal management steps: The processor load information is determined based on the processor operating scenario information and processor performance information corresponding to the image processor; Based on the processor load information and the corresponding image processor identification information, the image processor undergoes layered heat dissipation processing to obtain initial heat dissipation information. This includes: comparing the processor load information and the load level division threshold set corresponding to the image processor identification information to obtain a comparison result set; determining the load level information of the image processor based on the comparison result set; determining the target heat dissipation execution information of the image processor based on the load level information and the heat dissipation rule engine; in response to determining that the target heat dissipation execution information and the current heat dissipation execution information are different, performing hysteresis interval switching processing on the heat dissipation device set corresponding to the current heat dissipation execution information to switch to the running state of the heat dissipation device set corresponding to the target heat dissipation execution information, as the initial heat dissipation information, wherein the current heat dissipation execution information is the heat dissipation execution information being executed by the image processor; and in response to determining that the target heat dissipation execution information and the current heat dissipation execution information are the same, determining the current heat dissipation execution information as the initial heat dissipation information. Based on the processor load information, the corresponding processor performance information, and the operating environment information, the image processor is subjected to multi-dimensional risk identification to obtain processor temperature risk information, and based on the processor temperature risk information, the alarm device is controlled to perform risk alarm processing. Based on the processor temperature risk information, the initial heat dissipation information is dynamically adjusted to obtain the target heat dissipation information; Based on the obtained target heat dissipation information set, control the heat dissipation equipment to perform heat dissipation operations to perform system heat dissipation treatment on the heterogeneous hardware compatible system.

2. The method according to claim 1, wherein, The process involves acquiring data from the image processor set via the processor driver adapter and system environment sensors to obtain a processor performance information set, a processor operating scenario information set, and an operating environment information set, including: Obtain the interface documentation information set of the image processor set; Based on the interface document information set, the processor driver adapter is encapsulated by interface association mapping to obtain the encapsulated processor driver adapter; The resource data of the packaged post-processor driver adapter is optimized to obtain an optimized post-processor driver adapter; The optimized post-processor driver adapter and the system environment sensor are subjected to device synchronization processing to obtain a synchronized post-processor driver adapter and a synchronized system environment sensor. Using the synchronized post-processor driver adapter and the synchronized post-system environment sensor, data is collected from the image processor set based on the image processor identification information set to obtain an initial processor performance information set, a processor operating scenario information set, and an operating environment information set; The importance of each performance feature information set included in the initial processor performance information set is identified to obtain a set of performance feature importance groups. Based on the importance set of the performance characteristics, the initial processor performance information set is sorted and filtered to obtain the processor performance information set.

3. The method according to claim 1, wherein, The processor performance information includes: computational workload information, video memory usage information, and rendering frame rate information; and The step of determining the processor load information based on the processor operating scene information and processor performance information corresponding to the image processor includes: The computational workload information, the video memory usage information, and the rendering frame rate information are standardized to obtain standardized computational workload information, standardized video memory usage information, and standardized rendering frame rate information. Based on the processor running scenario information, determine the initial load weight value set of the standardized computing task information, the standardized video memory usage information, and the standardized rendering frame rate information; Based on the processor performance information, the initial load weight value set is corrected in real time to obtain the corrected load weight value set. The processor load information is obtained by weighting and summing the corrected load weight value set, the standardized computational task amount information, the standardized video memory usage information, and the standardized rendering frame rate information.

4. The method according to claim 1, wherein, The process of identifying the image processor set included in the heterogeneous hardware compatible system to obtain an image processor identification information set includes: For each image processor in the image processor set, perform the following recognition steps: Hardware identification is performed on the image processor set to obtain the image processor hardware information set; Based on the image processor hardware information set, the acquired processor text information set is subjected to double-byte encoding to obtain the processor word vector sequence; The processor word vector sequence is input into a bidirectional self-attention coding network to obtain bidirectional dynamic word feature vectors; The bidirectional dynamic character feature vector is input into the processor parameter recognition model to obtain the processor initial parameter recognition information. The processor parameter recognition model includes: a bidirectional long short-term memory network, a multi-head attention mechanism layer, a multi-layer convolutional extraction layer, a multi-layer gating unit layer, and a classification layer. The image processor hardware information set and the processor initial parameter identification information are determined as image processor identification information.

5. The method according to claim 1, wherein, The step of performing multi-dimensional risk identification on the image processor based on the processor load information, corresponding processor performance information, and operating environment information to obtain processor temperature risk information, and controlling the alarm device to perform risk alarm processing based on the processor temperature risk information, includes: The processor performance information, the operating environment information, and the processor load information are preprocessed to obtain preprocessed processor performance information, preprocessed operating environment information, and preprocessed processor load information. The processor performance information further includes: processor operating temperature, heat dissipation device operating status information, and processor power consumption information. Determine the threshold set of membership parameters for the risk fuzzy membership trigonometric function; Based on the membership parameter threshold set and the risk fuzzy membership trigonometric function, the preprocessed processor performance information, the preprocessed operating environment information and the preprocessed processor load information are divided into fuzzy information sets, processor performance fuzzy information sets, and operating environment fuzzy information sets, respectively. Based on the constructed fuzzy inference rule base, the processor performance fuzzy information set, the operating environment fuzzy information set, and the processor load fuzzy information set are subjected to defuzzy inference processing to obtain the processor risk level; Based on the processor performance fuzzy information set, the operating environment fuzzy information set, the processor load fuzzy information set, and the processor risk level, a processor risk directed graph is constructed; Based on the acquired historical image processor information set, probabilistic reasoning is performed on the processor risk directed graph to obtain the node fuzzy state information set; The node fuzzy state information set is input into the risk probability graph inference model to obtain processor temperature risk information, and based on the processor temperature risk information, the alarm device is controlled to perform risk alarm processing.

6. A layered heat dissipation device based on an image processor, comprising: The device identification unit is configured to perform device identification on the set of image processors included in the heterogeneous hardware compatible system, and obtain the image processor identification information set. The data acquisition unit is configured to acquire data from the image processor set through the processor driver adapter and system environment sensors to obtain a processor performance information set, a processor operating scenario information set, and an operating environment information set. The execution unit is configured to perform the following layered heat dissipation steps for each image processor: determine the processor load information based on the processor running scene information and processor performance information corresponding to the image processor; Based on the processor load information and the corresponding image processor recognition information, the image processor undergoes layered heat dissipation processing to obtain initial heat dissipation information. This includes: comparing the processor load information and the load level division threshold set corresponding to the image processor recognition information to obtain a comparison result set; determining the load level information of the image processor based on the comparison result set; determining the target heat dissipation execution information of the image processor based on the load level information and the heat dissipation rule engine; and, in response to the determination that the target heat dissipation execution information and the current heat dissipation execution information are different, performing hysteresis interval switching processing on the heat dissipation device set corresponding to the current heat dissipation execution information to switch to the target heat dissipation... The operating status of the heat dissipation device set corresponding to the thermal execution information is used as the initial heat dissipation information, wherein the current heat dissipation execution information is the heat dissipation execution information being executed by the image processor; in response to determining that the target heat dissipation execution information and the current heat dissipation execution information are the same, the current heat dissipation execution information is determined as the initial heat dissipation information; based on the processor load information, the corresponding processor performance information, and the operating environment information, multi-dimensional risk identification is performed on the image processor to obtain processor temperature risk information, and based on the processor temperature risk information, the alarm device is controlled to perform risk alarm processing; based on the processor temperature risk information, the initial heat dissipation information is dynamically adjusted to obtain the target heat dissipation information; The control unit is configured to control the heat dissipation device to perform heat dissipation operations to perform system heat dissipation processing on the heterogeneous hardware compatible system based on the obtained target heat dissipation information set.

7. An electronic device, comprising: One or more processors; Storage device, on which one or more programs are stored, When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-5.

8. A computer-readable medium having a computer program stored thereon, wherein, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-5.

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