Data redundancy storage control system

Abstract

The invention discloses a data redundancy storage control system, and relates to the technical field of electronic circuit control, the system realizes memory selection and memory sharing through a controller, and the data storage capacity is increased; key data are respectively stored in different memories, so that data redundancy control is realized, and the reliability of the data is improved; the processors report the occupation condition of the memories in real time through the I / O interfaces, the occupied memories are released after processing is completed, the capacity of rapidly obtaining multi-memory data is provided, and the task processing real-time performance is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit control, in particular to a data redundancy storage control system for embedded processing system. BACKGROUND

[0002] The data reliability and correctness of embedded control system are the basis for effective work of the system, and the existing control system usually adopts a single storage configured for data storage and management, and each single storage is configured for multi-processing system, so that the data cannot be directly shared and must be accessed through the respective configured processors and then shared through inter-processor communication.

[0003] The abnormal data stored in the storage configured for the processor will cause the system to be unable to work effectively, and even the control is out of control, resulting in irreparable loss. Meanwhile, since the existing technology adopts the processor configured with the special storage, the data sharing must be forwarded twice through the processor, which not only wastes time but also affects the real-time performance of processing other tasks. SUMMARY

[0004] In view of the above problems, the present application provides a data redundancy storage control system for overcoming the above problems or at least partially solving the above problems.

[0005] The present application provides the following solutions:

[0006] A data redundancy storage control system, comprising:

[0007] At least two sets of storage control units; each set of the storage control unit comprises an interface and other control circuit, a processor, a control circuit and a storage connected in sequence; the control circuit of each set of the storage control unit is connected with the storage of another set of the storage control unit;

[0008] The storage is used for storing the key parameters required by the processor contained in each set of the storage control unit;

[0009] The control circuit is used for realizing the channel switching and switch control between the processor and the storage;

[0010] The processor realizes external communication and control function through the interface and other control circuit;

[0011] The processor stores and reads the data of each storage through the control circuit connected therewith, realizes data sharing and redundancy control.

[0012] Preferably, one set of the storage control unit comprises a first processor, a first control circuit and a first storage, and another set of the storage control unit comprises a second processor, a second control circuit and a second storage;

[0013] The first processor and the second processor access data in the first memory and the second memory through the first control circuit and the second control circuit, the first processor and the first control circuit share the first memory and the second memory, and data redundancy and shared control are realized.

[0014] Preferably, the PE5 pin of the first processor is connected to the PE6 pin of the second processor, the PE6 pin of the first processor is connected to the PE5 pin of the second processor, and the PE5 pin and the PE6 pin of the first processor and the PE6 pin and the PE5 pin of the second processor are connected to the pull-up resistor R17 and the resistor R18, so that the input and output of the PE5 pin and the PE6 pin of the first processor and the PE6 pin and the PE5 pin of the second processor are high or low.

[0015] Preferably, the PF0 pin of the first processor is connected to the Y-COM pin of the first control circuit, the PF1 pin of the first processor is connected to the X-COM pin of the first control circuit, the PF2 pin of the first processor is connected to the INH pin of the first control circuit, the PF3 pin of the first processor is connected to the A pin of the first control circuit, the PF4 pin of the first processor is connected to the B pin of the first control circuit U2, the PF0 pin, the PF1 pin, the PF2 pin, the PF3 pin and the PF4 pin of the first processor U1 are connected to the pull-up resistors R1, R2, R3, R4 and R5, and the VBAT pin and the VDD1-VDD12 pin of the first processor are connected to the decoupling capacitors C1 and C2.

[0016] Preferably, the PF0 pin of the second processor is connected to the Y-COM pin of the second control circuit, the PF1 pin of the second processor is connected to the X-COM pin of the second control circuit, the PF2 pin of the second processor is connected to the INH pin of the second control circuit, the PF3 pin of the second processor is connected to the A pin of the second control circuit, the PF4 pin of the second processor is connected to the B pin of the second control circuit, the PF0 pin, the PF1 pin, the PF2 pin, the PF3 pin and the PF4 pin of the second processor are connected to the pull-up resistors R9, R10, R11, R12 and R13, and the VBAT pin and the VDD1-VDD12 pin of the second processor are connected to the decoupling capacitors C7 and C8.

[0017] Preferably: the Y0 pin of the first control circuit is connected with the SDA pin of the first memory and the Y1 pin of the second control circuit, the X0 pin of the first control circuit is connected with the SCK pin of the first memory and the X1 pin of the second control circuit, the Y1 pin of the first control circuit is connected with the SDA pin of the second memory, the X1 pin of the first control circuit is connected with the SCL pin of the second memory, and the VDD of the first control circuit is connected with the decoupling capacitor C3 and C4.

[0018] Preferably: the Y0 pin of the second control circuit is connected with the SDA pin of the second memory and the Y1 pin of the first control circuit, the X0 pin of the second control circuit is connected with the SCK pin of the second memory and the X1 pin of the first control circuit, the Y1 pin of the second control circuit is connected with the SDA pin of the first memory, the X1 pin of the second control circuit is connected with the SCL pin of the first memory, and the VDD pin of the second control circuit is connected with the decoupling capacitor C9 and C10.

[0019] Preferably: the SDA pin and the SCL pin of the first memory are connected with the pull-up resistors R6 and R7, the E0 pin, the E1 pin and the E2 pin of the first memory are grounded, the WC pin of the first memory is connected with the resistor R8, the other end of the resistor R8 is connected with the power supply, and the VCC pin of the first memory is connected with the decoupling capacitor C5 and C6.

[0020] Preferably: the SDA pin and the SCL pin of the second memory are connected with the pull-up resistors R14 and R15, the E0 pin, the E1 pin and the E2 pin of the second memory are grounded, the WC pin of the second memory is connected with the resistor R16, the other end of the resistor R16 is connected with the power supply, and the VCC pin of the second memory is connected with the decoupling capacitor C11 and C12.

[0021] According to the embodiments of the present application, the following technical effects are achieved.

[0022] The data redundancy storage control system provided by the embodiments of the present application realizes memory selection and memory sharing through the controller, thereby increasing the data storage capacity; the key data are stored in different memories respectively, thereby realizing data redundancy control and improving the reliability of the data; the memory occupation conditions are reported in real time between the processors through the I / O interface, and the occupied memory is released after the processing is completed, thereby providing the ability of quickly acquiring the data of multiple memories and improving the real-time performance of the task processing.

[0023] Of course, any product implementing the present application does not necessarily need to achieve all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described below are only some of the embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art without creative effort based on these drawings.

[0025] Figure 1 is a circuit schematic diagram of a data redundancy storage control system provided by an embodiment of the present application;

[0026] Figure 2 is a detailed circuit schematic diagram of a data redundancy storage control system provided by an embodiment of the present application;

[0027] Figure 3 is a data redundancy sharing access flowchart provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0029] Referring to Figure 1 , a data redundancy storage control system provided by an embodiment of the present application, as shown in the figure, the system can include: Figure 1

[0030] at least two sets of storage control units; each set of the storage control unit includes an interface and other control circuit, a processor, a control circuit and a memory connected in sequence; the control circuit of each set of the storage control unit is connected with the memory of another set of the storage control unit;

[0031] the memory is used to store the key parameters required by the processor contained in each set of the storage control unit;

[0032] the control circuit is used to realize channel switching and switch control between the processor and the memory;

[0033] the processor realizes external communication and control function through the interface and other control circuit;

[0034] the processor stores and reads the data of each memory through the control circuit connected therewith, realizes data sharing and redundancy control.

[0035] ​The data redundancy storage control system provided by the embodiment of the application increases the data storage capacity by realizing memory selection and memory sharing through the controller; the key data is stored in different memories respectively, thereby realizing data redundancy control and improving the reliability of the data; the processors inform each other of the memory occupation in real time through the I / O interface, release the occupied memory after processing, thereby providing the ability of quickly obtaining the data of multiple memories and improving the real-time performance of task processing.

[0036] It can be understood that the storage control unit provided by the embodiment of the application can be provided in multiple sets according to actual needs, and when being configured, the control circuits of the sets only need to be connected with adjacent or all the memories. For example, in an implementation manner, the storage control unit provided by the embodiment of the application can include a first processor, a first control circuit and a first memory, and another storage control unit includes a second processor, a second control circuit and a second memory.

[0037] The first processor and the second processor access data in the first memory and the second memory through the first control circuit and the second control circuit, and the first processor and the first control circuit share the first memory and the second memory, thereby realizing the control of data redundancy and sharing.

[0038] Further, the PE5 pin of the first processor is connected with the PE6 pin of the second processor, the PE6 pin of the first processor is connected with the PE5 pin of the second processor, and the PE5 pin and the PE6 pin of the first processor and the PE6 pin and the PE5 pin of the second processor are both connected with a pull-up resistor R17 and a resistor R18, so that the input and output of the PE5 pin and the PE6 pin of the first processor and the PE6 pin and the PE5 pin of the second processor are high level or low level.

[0039] The PF0 pin of the first processor is connected with the Y-COM pin of the first control circuit, the PF1 pin of the first processor is connected with the X-COM pin of the first control circuit, the PF2 pin of the first processor is connected with the INH pin of the first control circuit, the PF3 pin of the first processor is connected with the A pin of the first control circuit, the PF4 pin of the first processor is connected with the B pin of the first control circuit U2, the PF0 pin, the PF1 pin, the PF2 pin, the PF3 pin and the PF4 pin of the first processor U1 are connected with pull-up resistors R1, R2, R3, R4 and R5, and the VBAT pin and the VDD1-VDD12 pin of the first processor are connected with decoupling capacitors C1 and C2.

[0040] The second processor's PF0 pin is connected to the Y-COM pin of the second control circuit, the second processor's PF1 pin is connected to the X-COM pin of the second control circuit, the second processor's PF2 pin is connected to the INH pin of the second control circuit, the second processor's PF3 pin is connected to the A pin of the second control circuit, and the second processor's PF4 pin is connected to the B pin of the second control circuit. The second processor's PF0, PF1, PF2, PF3, and PF4 pins are connected to pull-up resistors R9, R10, R11, R12, and R13. The second processor's VBAT pin and VDD1-VDD12 pins are connected to decoupling capacitors C7 and C8.

[0041] The Y0 pin of the first control circuit is connected to the SDA pin of the first memory and the Y1 pin of the second control circuit. The X0 pin of the first control circuit is connected to the SCK pin of the first memory and the X1 pin of the second control circuit. The Y1 pin of the first control circuit is connected to the SDA pin of the second memory. The X1 pin of the first control circuit is connected to the SCL pin of the second memory. The VDD pin of the first control circuit is connected to decoupling capacitors C3 and C4.

[0042] The Y0 pin of the second control circuit is connected to the SDA pin of the second memory and the Y1 pin of the first control circuit. The X0 pin of the second control circuit is connected to the SCK pin of the second memory and the X1 pin of the first control circuit. The Y1 pin of the second control circuit is connected to the SDA pin of the first memory. The X1 pin of the second control circuit is connected to the SCL pin of the first memory. The VDD pin of the second control circuit is connected to decoupling capacitors C9 and C10.

[0043] The SDA and SCL pins of the first memory are connected to pull-up resistors R6 and R7. The E0, E1, and E2 pins of the first memory are grounded. The WC pin of the first memory is connected to resistor R8, and the other end of resistor R8 is connected to the power supply. The VCC pin of the first memory is connected to decoupling capacitors C5 and C6.

[0044] The SDA and SCL pins of the second memory are connected to pull-up resistors R14 and R15. The E0, E1, and E2 pins of the second memory are grounded. The WC pin of the second memory is connected to resistor R16, and the other end of R16 is connected to the power supply. The VCC pin of the second memory is connected to decoupling capacitors C11 and C12.

[0045] The following describes in detail the system provided in the embodiments of this application, taking the setting of two sets of storage control units as an example.

[0046] like Figure 1 As shown, each storage control unit includes a processor, control circuit, memory, interface and other control circuits, power conversion circuit, etc. The processor, control circuit, memory, interface and other control circuits comprise at least two sets to achieve multi-functional communication and control. The processor implements external communication and control functions through the interface and other control circuits. The processor stores and retrieves data from multiple memories through the control circuits, achieving data sharing and redundant control.

[0047] like Figure 2 As shown, the processor is connected to the interface and other control circuits to achieve communication and control with the outside world. The PE5 pin of the first processor U1 is connected to the PE6 pin of the second processor U4, and the PE6 pin of the first processor U1 is connected to the PE5 pin of the second processor U4. Pull-up resistors R17 and R18 are connected to the PE5 and PE6 pins of the first processor U1 to ensure that the input and output of the PE5 and PE6 pins of the first processor U1 are reliably high or low. The PF0 pin of the first processor U1 is connected to the Y-COM of the first control circuit U2, and the PF1 pin of the first processor U1... The X-COM pin of the first control circuit U2 is connected to the INH pin of the first control circuit U2, the PF2 pin of the first processor U1 is connected to the A pin of the first control circuit U2, the PF4 pin of the first processor U1 is connected to the B pin of the first control circuit U2, the PF0 pin, PF1 pin, PF2 pin, PF3 pin, and PF4 pin of the first processor U1 are connected to pull-up resistors R1, R2, R3, R4, and R5, and the VBAT pin and VDD1-VDD12 pins of the first processor U1 are connected to decoupling capacitors C1 and C2.

[0048] The first control circuit U2 realizes channel switching and switch control between the processor and the memory. The Y0 pin of the first control circuit U2 is connected to the SDA pin of the first memory U3 and the Y1 pin of the second control circuit U5. The X0 pin of the first control circuit U2 is connected to the SCK pin of the first memory U3 and the X1 pin of the second control circuit U5. The Y1 pin of the first control circuit U2 is connected to the SDA pin of the second memory U6. The X1 pin of the first control circuit U2 is connected to the SCL pin of the second memory U6. The VDD pin of the first control circuit U2 is connected to decoupling capacitors C3 and C4.

[0049] The first memory U3 performs data storage. The SDA pin of the first memory U3 is connected to the Y0 pin of the first control circuit U2 and the Y1 pin of the second control circuit U5. The SCL pin of the first memory U3 is connected to the X0 pin of the first control circuit U2 and the X1 pin of the second control circuit U5. The SDA pin and SCL pin of the first memory U3 are connected to pull-up resistors R6 and R7. The E0 pin, E1 pin and E2 pin of the first memory U3 are grounded. The WC pin of the first memory U3 is connected to resistor R8, and the other end of R8 is connected to the power supply. The VCC pin of the first memory U3 is connected to decoupling capacitors C5 and C6.

[0050] The second processor U4 enables communication and control with the outside world. The PE5 pin of the second processor U4 is connected to the PE6 pin of the first processor U1, and the PE6 pin of the second processor U4 is connected to the PE5 pin of U1. Pull-up resistors R17 and R18 are connected to the PE6 and PE5 pins of the second processor U4 to ensure that the input and output of the PE5 and PE6 pins of the second processor U4 are reliably high or low. The PF0 pin of the second processor U4 is connected to the Y-COM pin of the second control circuit U5, the PF1 pin is connected to the X-COM pin of the second control circuit U5, the PF2 pin is connected to the INH pin of the second control circuit U5, the PF3 pin is connected to the A pin of the second control circuit U5, and the PF4 pin is connected to the B pin of the second control circuit U5. Pull-up resistors R9, R10, R11, R12, and R13 are connected to the PF0, PF1, PF2, PF3, and PF4 pins of the second processor U4. The VBAT pin and VDD1-VDD12 pins of the second processor U4 are connected to decoupling capacitors C7 and C8.

[0051] The second control circuit U5 realizes channel switching and switch control between the processor and the memory. The Y0 pin of the second control circuit U5 is connected to the SDA pin of the second memory U6 ​​and the Y1 pin of the first control circuit U2. The X0 pin of the second control circuit U5 is connected to the SCK pin of the second memory and the X1 pin of the first control circuit U2. The Y1 pin of the second control circuit U5 is connected to the SDA pin of the first memory U3. The X1 pin of the second control circuit U5 is connected to the SCL pin of the first memory U3. The VDD pin of the second control circuit U5 is connected to decoupling capacitors C9 and C10.

[0052] The second memory U6 ​​is connected to realize data storage. The SDA pin of the second memory U6 ​​is connected to the Y0 pin of the second control circuit U5 and the Y1 pin of the first control circuit U2. The SCL pin of the second memory U6 ​​is connected to the X0 pin of the second control circuit U5 and the X1 pin of the first control circuit U2. The SDA and SCL pins of the second memory U6 ​​are connected to pull-up resistors R14 and R15. The E0, E1 and E2 pins of the second memory U6 ​​are grounded. The WC pin of the second memory U6 ​​is connected to resistor R16, and the other end of R16 is connected to the power supply. The VCC pin of the second memory U6 ​​is connected to decoupling capacitors C11 and C12.

[0053] The first processor U1 and the second processor U4 access data in the first memory U3 and the second memory U6 ​​through the first control circuit U2 and the second control circuit U5. The first processor U1 and the first control circuit U2 share the first memory U3 and the second memory U6.

[0054] like Figure 3 As shown, the control steps to achieve data redundancy and sharing are as follows:

[0055] 1. Based on the size of the core key data of the control circuit, plan the storage capacity and storage address range, and determine a certain amount of storage space for the first memory U3 and the second memory U6 ​​as common shared storage space.

[0056] 2. Data Access by First Processor U1: First, the PE5 and PE6 pins of the first processor U1 are used to check whether the second processor U4 is accessing data in a certain memory (first memory U3 or second memory U6). If no data is being accessed, the PE5 and PE6 pins are used to notify the second processor U4 to reserve the memory to be accessed. Second, the PF2, PF3, and PF4 pins of the first processor U1 control the INH, A, and B pins of the controller U2 to select the memory. Then, the first processor U1 accesses the data in the selected first memory U3 or second memory U6. Finally, the PF2, PF3, and PF4 pins of the first processor U1 control the INH, A, and B pins of the controller U2 to release the selected memory. The first processor U1 then notifies the second processor U4 through its PE5 and PE6 pins that data storage has been completed, and the second processor U4 can access the data.

[0057] 3. Second processor U4 accesses data: First, it queries whether the first processor U1 is accessing data in a memory (U3 or U6) via the PE5 and PE6 pins of the second processor U4. If no data is being accessed, it notifies the first processor U1 via the PE5 and PE6 pins to reserve the memory to be accessed. Second, it controls the INH, A, and B pins of the controller U5 via the PF2, PF3, and PF4 pins of the second processor U4 to select the memory. Then, the second processor U4 accesses the data in the selected first memory U3 or second memory U6. Finally, it controls the INH, A, and B pins of the controller U5 via the PF2, PF3, and PF4 pins of the second processor U4 to release the selected memory. The second processor U4 then notifies the first processor U1 via its PE5 and PE6 pins that data storage is complete, and the first processor U1 can access the data.

[0058] 4. Data redundancy control: The first processor U1 or the second processor U4 stores key data in the designated address spaces of the first memory U3 and the second memory U6 ​​respectively. If a problem occurs in one memory, the other memory can be accessed.

[0059] In summary, the data redundancy storage control system provided in this application increases data storage capacity by employing a shared memory approach. The data redundancy control improves data reliability. Furthermore, it provides the ability to quickly acquire data from multiple storage devices, enhancing the real-time performance of task processing.

[0060] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0061] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0062] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0063] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A data redundancy storage control system, characterized in that, It includes at least two sets of storage control units; each set of storage control units includes interfaces and other control circuits, a processor, a control circuit, and a memory connected in sequence; the control circuit of each set of storage control units is connected to the memory of the other set of storage control units; The memory is used to store the key parameters required by the processor contained in each of the storage control units; The control circuit is used to realize channel switching and switch control between the processor and the memory; The processor implements external communication and control functions through interfaces and other control circuits; The processor stores and reads data from each of the memories through the control circuit connected to it, thereby achieving data sharing and redundancy control.

2. The data redundancy storage control system according to claim 1, characterized in that, One set of the storage control unit includes a first processor, a first control circuit, and a first memory; the other set of the storage control unit includes a second processor, a second control circuit, and a second memory. The first processor and the second processor access data in the first memory and the second memory through the first control circuit and the second control circuit, and the first processor and the first control circuit share the first memory and the second memory to achieve data redundancy and sharing control.

3. The data redundancy storage control system according to claim 2, characterized in that, The PE5 pin of the first processor is connected to the PE6 pin of the second processor, and the PE6 pin of the first processor is connected to the PE5 pin of the second processor. The PE5 and PE6 pins of the first processor and the PE6 and PE5 pins of the second processor are all connected to pull-up resistors R17 and R18, so that the input and output of the PE5 and PE6 pins of the first processor and the PE6 and PE5 pins of the second processor are high or low.

4. The data redundancy storage control system according to claim 3, characterized in that, The PF0 pin of the first processor is connected to the Y-COM pin of the first control circuit, the PF1 pin of the first processor is connected to the X-COM pin of the first control circuit, the PF2 pin of the first processor is connected to the INH pin of the first control circuit, the PF3 pin of the first processor is connected to the A pin of the first control circuit, and the PF4 pin of the first processor is connected to the B pin of the first control circuit U2. The PF0, PF1, PF2, PF3, and PF4 pins of the first processor U1 are connected to pull-up resistors R1, R2, R3, R4, and R5. The VBAT pin and VDD1-VDD12 pins of the first processor are connected to decoupling capacitors C1 and C2.

5. The data redundancy storage control system according to claim 3, characterized in that, The second processor's PF0 pin is connected to the Y-COM pin of the second control circuit, the second processor's PF1 pin is connected to the X-COM pin of the second control circuit, the second processor's PF2 pin is connected to the INH pin of the second control circuit, the second processor's PF3 pin is connected to the A pin of the second control circuit, and the second processor's PF4 pin is connected to the B pin of the second control circuit. The second processor's PF0, PF1, PF2, PF3, and PF4 pins are connected to pull-up resistors R9, R10, R11, R12, and R13. The second processor's VBAT pin and VDD1-VDD12 pins are connected to decoupling capacitors C7 and C8.

6. The data redundancy storage control system according to claim 2, characterized in that, The Y0 pin of the first control circuit is connected to the SDA pin of the first memory and the Y1 pin of the second control circuit. The X0 pin of the first control circuit is connected to the SCK pin of the first memory and the X1 pin of the second control circuit. The Y1 pin of the first control circuit is connected to the SDA pin of the second memory. The X1 pin of the first control circuit is connected to the SCL pin of the second memory. The VDD pin of the first control circuit is connected to decoupling capacitors C3 and C4.

7. The data redundancy storage control system according to claim 2, characterized in that, The Y0 pin of the second control circuit is connected to the SDA pin of the second memory and the Y1 pin of the first control circuit. The X0 pin of the second control circuit is connected to the SCK pin of the second memory and the X1 pin of the first control circuit. The Y1 pin of the second control circuit is connected to the SDA pin of the first memory. The X1 pin of the second control circuit is connected to the SCL pin of the first memory. The VDD pin of the second control circuit is connected to decoupling capacitors C9 and C10.

8. The data redundancy storage control system according to claim 2, characterized in that, The SDA and SCL pins of the first memory are connected to pull-up resistors R6 and R7. The E0, E1, and E2 pins of the first memory are grounded. The WC pin of the first memory is connected to resistor R8, and the other end of resistor R8 is connected to the power supply. The VCC pin of the first memory is connected to decoupling capacitors C5 and C6.

9. The data redundancy storage control system according to claim 2, characterized in that, The SDA and SCL pins of the second memory are connected to pull-up resistors R14 and R15. The E0, E1, and E2 pins of the second memory are grounded. The WC pin of the second memory is connected to resistor R16, and the other end of R16 is connected to the power supply. The VCC pin of the second memory is connected to decoupling capacitors C11 and C12.

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