Data transmission method and device in computing system, electronic equipment and storage medium

Abstract

The data transmission method and device in the computing system, the electronic equipment and the storage medium provided by the embodiments of the present application, the method comprises the following steps: first, in response to the block-level data transmission instruction initiated by the meta-thread running in the first computing component, the target data block information of the block-level data transmission instruction is determined, and the transmission information pointing to the second computing component is generated based on the target data block information; the block-level data transmission instruction is used to represent the data transmission between the first computing component and the second computing component, and the running of the meta-thread is independent of the ordinary work thread; then, the transmission information is sent to the second computing component, so that the target data block represented by the transmission information is transmitted between the first computing component and the second computing component; by using the meta-thread running in the first computing component and independent of the ordinary work thread to initiate the block-level data transmission instruction, the hardware resource decoupling of data transmission control and intensive computing task is realized, and the resource utilization and parallel cooperation efficiency are improved.

Description

Technical Field

[0001] This application relates to the field of computational data processing technology, and in particular to data transmission methods, apparatus, electronic devices and storage media in computing systems. Background Technology

[0002] With the surge in demand for large-scale model training and high-performance computing, computing systems are rapidly evolving towards chip-based wafer-level packaging and multi-device interconnect clusters to overcome the bottlenecks in single-chip computing power and bandwidth. In this distributed and heterogeneous architecture, maintaining data consistency and parallel collaboration between computing components (such as data exchange in tensor parallelism and pipelined parallelism) requires frequent and large-scale block-level data transfers between different computing components (such as different chips within a package or physically separated computing devices). Currently, these data transfer tasks are typically initiated by general-purpose parallel computing threads (i.e., SIMT worker threads) running on the computing components, and assisted by specific hardware direct memory access (DMA) engines.

[0003] However, since general-purpose parallel computing threads are mainly designed for fine-grained vector computation, they are allocated expensive hardware resources such as independent, large-capacity vector register files when they start up. When these worker threads are scheduled to perform data transfer tasks, even if they are in a blocked state waiting for data to return or performing simple data transfer logic, the register resources they occupy cannot be released. As a result, the computational tasks that actually need to perform mathematical operations in the computing components cannot start due to the lack of register resources. This leads to low resource utilization in existing data transfer task schemes when using general-purpose parallel computing threads to drive data transfer. Summary of the Invention

[0004] This application provides a data transmission method, apparatus, electronic device, and storage medium in a computing system, which can improve resource utilization when data is transmitted between computing components.

[0005] To achieve the above objectives, a first aspect of this application proposes a data transmission method in a computing system, the method comprising:

[0006] In response to a block-level data transfer instruction initiated by a meta-thread running in the first computing component, the target data block information of the block-level data transfer instruction is determined, and transmission information pointing to the second computing component is generated based on the target data block information; the block-level data transfer instruction is used to characterize data transfer between the first computing component and the second computing component, and the meta-thread runs independently of ordinary worker threads;

[0007] The transmission information is sent to the second computing component to enable the transmission of the target data block represented by the transmission information between the first computing component and the second computing component.

[0008] In some embodiments, the block-level data transfer instruction includes a block storage instruction, and the generation of transfer information pointing to the second computing component based on the target data block information includes:

[0009] The target data block is obtained from the first memory associated with the first computing component based on the target data block information;

[0010] The transmission information is generated based on the target data block, the target address of the second computing component, and the block storage instruction.

[0011] In some embodiments, sending the transmission information to the second computing component to transmit the target data block represented by the transmission information between the first computing component and the second computing component includes:

[0012] Using the interconnection link between the first computing component and the second computing component, the transmission information is transmitted to the second computing component based on the target address, so that the second computing component receives the target data block and stores the target data block in the associated second memory.

[0013] In some embodiments, the block-level data transfer instruction includes a block loading instruction, and the generation of transfer information pointing to the second computing component based on the target data block information includes:

[0014] The request data block information of the target data block is determined based on the target data block information;

[0015] The transmission information is generated based on the source address of the first computing component, the target address of the second computing component, the requested data block information, and the block loading instruction.

[0016] In some embodiments, sending the transmission information to the second computing component to transmit the target data block represented by the transmission information between the first computing component and the second computing component includes:

[0017] The transmission information is transmitted to the second computing component based on the target address, so that the second computing component can obtain the target data block from the associated second memory based on the request data block information;

[0018] Using the interconnection link between the first computing component and the second computing component, the target data block sent by the second computing component is received and stored in the first memory associated with the first computing component.

[0019] In some embodiments, the first computing component and the second computing component are different computing chips within the same chip, and sending the transmission information to the second computing component includes:

[0020] The transmission information is sent to the second computing component using the interconnect structure between the computing chips in the chip.

[0021] In some embodiments, the first computing component and the second computing component are two physically separate computing devices, and sending the transmission information to the second computing component includes:

[0022] The transmission information is sent to the second computing component using the inter-device network where the first computing component and the second computing component are located.

[0023] In some embodiments, the block-level data transfer instruction is an asynchronous instruction, and the block-level data transfer instruction includes a barrier identifier. The method further includes:

[0024] After the meta-thread initiates the block-level data transfer instruction, it continues to execute subsequent data processing instructions;

[0025] When the subsequent data processing instruction indicates an access operation to the target data block, the access operation to the target data block is executed only after the target data block has been transmitted, based on the barrier identifier.

[0026] The first computing component includes a meta-thread instruction scheduler and a load-memory structure. The meta-thread generation process includes:

[0027] Based on the received kernel function start instruction by the meta-thread instruction scheduler, a meta-thread corresponding to the kernel function start instruction is generated.

[0028] The block-level data transfer instruction initiated in response to a meta-thread running in the first computing component includes:

[0029] The meta-thread instruction scheduler responds to the block-level data transfer instruction initiated by the meta-thread and sends the meta-thread to the load storage structure for execution.

[0030] To achieve the above objectives, a second aspect of this application provides a data transmission apparatus in a computing system, comprising:

[0031] A response module is used to respond to a block-level data transfer instruction initiated by a meta-thread running in the first computing component, determine the target data block information of the block-level data transfer instruction, and generate transmission information pointing to the second computing component based on the target data block information; the block-level data transfer instruction is used to characterize data transfer between the first computing component and the second computing component, and the meta-thread runs independently of ordinary worker threads;

[0032] A transmission module is configured to send the transmission information to the second computing component, so as to transmit the target data block represented by the transmission information between the first computing component and the second computing component.

[0033] To achieve the above objectives, a third aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the data transmission method in the computing system as described in the first aspect.

[0034] To achieve the above objectives, a fourth aspect of the present application provides a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the data transmission method in the computing system described in the first aspect.

[0035] The data transmission method, apparatus, electronic device, and storage medium in the computing system proposed in this application include: first, in response to a block-level data transmission instruction initiated by a meta-thread running in a first computing component, determining target data block information of the block-level data transmission instruction, and generating transmission information pointing to a second computing component based on the target data block information; the block-level data transmission instruction is used to characterize data transmission between the first computing component and the second computing component, and the meta-thread runs independently of ordinary worker threads; then, the transmission information is sent to the second computing component so that the target data block characterized by the transmission information is transmitted between the first computing component and the second computing component. This application embodiment utilizes a meta-thread running in the first computing component and independent of ordinary worker threads (such as SIMT threads) to initiate block-level data transmission instructions. This decouples data transmission control from the hardware resources of intensive computing tasks. Since the meta-thread does not require expensive hardware resources such as independent, large-capacity vector register files that are necessary for ordinary worker threads, it can release valuable ordinary worker threads and their associated register resources from communication tasks during frequent large-scale data interactions between chips or devices. These resources can then be used to execute core mathematical operations or enter a low-power state. This solves the resource "deadlock" problem in the prior art, where computing resources are ineffectively occupied and cannot serve computing tasks due to the use of general-purpose parallel computing threads to drive data transmission. This significantly improves resource utilization and parallel collaboration efficiency in distributed heterogeneous computing systems.

[0036] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0037] Figure 1(a) is a schematic diagram of the interconnection topology architecture between computing chips in a first chip packaging scenario provided by an embodiment of this application.

[0038] Figure 1(b) is a schematic diagram of the interconnection topology between computing chips in a second chip packaging scenario provided by an embodiment of this application.

[0039] Figure 1(c) is a schematic diagram of the interconnection topology architecture between computing chips in a third chip packaging scenario provided by an embodiment of this application.

[0040] Figure 2 This is a schematic diagram of a network interconnection topology between computing devices in a distributed computing cluster scenario, provided by another embodiment of this application.

[0041] Figure 3This is a schematic diagram of the structure of the first computing system provided in another embodiment of this application.

[0042] Figure 4 This is a schematic diagram of the structure of a second computing system provided in another embodiment of this application.

[0043] Figure 5 This is a flowchart of a data transmission method in a computing system provided in another embodiment of this application.

[0044] Figure 6 This is a flowchart of the generation and response of a meta-thread provided in another embodiment of this application.

[0045] Figure 7 This is a flowchart of the transmission information generation process corresponding to a block storage instruction provided in another embodiment of this application.

[0046] Figure 8 This is a flowchart illustrating the transmission information corresponding to a block storage instruction provided in another embodiment of this application.

[0047] Figure 9 This is a schematic diagram of a process for performing cross-chip block storage operations at the computing chip level, provided in another embodiment of this application.

[0048] Figure 10 This is a schematic diagram of a process for performing cross-device block storage operations at the computing device level, provided in another embodiment of this application.

[0049] Figure 11 This is a flowchart of the transmission information generation process corresponding to the block loading instruction provided in another embodiment of this application.

[0050] Figure 12 This is a flowchart of the transmission information corresponding to the block loading instruction provided in another embodiment of this application.

[0051] Figure 13 This is a schematic diagram of a process for performing cross-device block storage operations at the computing device level, provided in another embodiment of this application.

[0052] Figure 14 This is a schematic diagram of a process for performing cross-device block storage operations at the computing device level, provided in another embodiment of this application.

[0053] Figure 15 This is a schematic diagram of an on-chip interconnect architecture for a computing chip provided in another embodiment of this application.

[0054] Figure 16 This is a schematic diagram of the interconnection structure of a computing device provided in another embodiment of this application.

[0055] Figure 17This is a flowchart of the access to the target data block provided in another embodiment of this application.

[0056] Figure 18 This is a schematic diagram of the structure of a data transmission device in a computing system provided in another embodiment of this application.

[0057] Figure 19 This is a schematic diagram of the hardware structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0059] It should be noted that although functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0061] With the surge in demand for large-scale model training and high-performance computing, computing systems are rapidly evolving towards chip-based wafer-level packaging and multi-device interconnect clusters to overcome the bottlenecks in single-chip computing power and bandwidth. In this distributed and heterogeneous architecture, maintaining data consistency and parallel collaboration between computing components (such as data exchange in tensor parallelism and pipelined parallelism) requires frequent and large-scale block-level data transfers between different computing components (such as different chips within a package or physically separated computing devices). Currently, these data transfer tasks are typically initiated by general-purpose parallel computing threads (i.e., SIMT worker threads) running on the computing components, and assisted by specific hardware direct memory access (DMA) engines.

[0062] Referring to Figures 1(a), 1(b), and 1(c), these are schematic diagrams of interconnection topologies between computing chips under three chip packaging scenarios provided in this application. As shown in Figures 1(a), 1(b), and 1(c), when data transmission is required between different computing chips within the same chip package, a die-to-die fabric is used to implement the corresponding data transmission between on-chip or off-chip memory associated with different computing chips. These die-to-die fabrics can present various topologies depending on system scale and bandwidth requirements, including but not limited to: point-to-point full interconnection or mesh direct connection between multiple computing chips (as shown in Figure 1(a)), star connection through a shared input / output chip (IO-Die) as a routing hub (as shown in Figure 1(b)), and tree or hierarchical cascaded connection built through multi-level IO-Dies (as shown in Figure 1(c)).

[0063] Reference Figure 2 This is a schematic diagram of a network interconnection topology between computing devices in a distributed computing cluster scenario, provided by an embodiment of this application. Figure 2 As shown, when data needs to be transferred between physically separate independent computing devices (such as independent GPU accelerator cards or server nodes), a device-to-device network is needed to perform the corresponding data transfer between SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) across devices.

[0064] As shown in Figure 1(a), Figure 1(b), Figure 1(c) and Figure 2 The computing components shown (computing chips as shown in Figure 1(a), Figure 1(b), and Figure 1(c) or as...) Figure 2During data transmission between computing devices (as shown), the general-purpose parallel computing threads within these computing components are primarily designed for fine-grained vector computation. Upon startup, these threads are allocated independent, large-capacity vector register files and other expensive hardware resources. When these threads are scheduled to execute data transmission tasks, even when they are in a blocked state waiting for data returns or performing simple data transfer logic, the register resources they occupy cannot be released. This results in the computational tasks that actually require mathematical operations failing to start due to a lack of register resources. Consequently, existing data transmission schemes suffer from low resource utilization when using general-purpose parallel computing threads to drive data transmission. Furthermore, this thread-granular discrete control method generates significant instruction sending overhead when handling large-scale data transmissions, making it difficult to fully utilize the bandwidth potential of inter-chip or inter-device interconnect links.

[0065] To improve resource utilization during data transfer between computing components, this application embodiment utilizes a meta-thread running in the first computing component and independent of ordinary worker threads (such as SIMT threads) to initiate block-level data transfer instructions. This decouples data transfer control from the hardware resources of intensive computing tasks. Since the meta-thread does not require expensive hardware resources such as independent, large-capacity vector register files that are necessary for ordinary worker threads, it frees up valuable ordinary worker threads and their associated register resources from communication tasks during frequent large-scale data interactions between chips or devices. These resources can then be used to execute core mathematical operations or enter a low-power state. This solves the resource "deadlock" problem in the prior art, where computing resources are ineffectively occupied and cannot serve computing tasks due to the use of general-purpose parallel computing threads to drive data transfer. This significantly improves resource utilization and parallel collaboration efficiency in distributed heterogeneous computing systems.

[0066] The data transmission method, apparatus, electronic device, and storage medium in the computing system provided in the embodiments of this application will be further described below. First, the computing processor will be described.

[0067] The architecture of the computing system provided in this application is first described below. The computing system includes at least two computing components that need to transmit data. (Refer to...) Figure 3 This is a schematic diagram of the structure of the first computing system provided in the embodiments of this application. Figure 3As shown, the two computing components (including the first computing component and the second computing component) are different computing chips within the same chip package. Each computing chip integrates one or more computing units, each running a meta-thread independent of the ordinary worker threads. When the first computing chip (i.e., the first computing component) uses the meta-thread, which acts as the control core, to initiate block-level data transfer instructions to the load / store hierarchy, it drives the load / store hierarchy to communicate with the other computing chip (i.e., the second computing component) through the die-to-die link / fabric, thereby enabling efficient data block transfer between local and remote on-die memory or off-die memory. The on-die memory includes memory dedicated to each computing unit and memory shared by all computing units within the chip. The off-die memory can be 3D memory vertically stacked on the computing chips.

[0068] Reference Figure 4 This is a schematic diagram of the structure of the second computing system provided in the embodiments of this application. Figure 4 As shown, the two computing components (including the first computing component and the second computing component) are physically separate independent computing devices, each containing computing chips and computing units. The first computing device (i.e., the first computing component) uses a meta-thread running in the computing unit as an initiator to generate transmission information through a load / store structure. This transmission information is transmitted to the other computing device via an external network (such as a PCIe or dedicated interconnect network), triggering a response from the load / store structure of the remote device (i.e., the second computing component). This enables large-scale data block transfers between SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) associated with different computing devices. The DRAM memory can be 3D memory vertically stacked on the computing chips.

[0069] Based on the computing system provided above, the following describes a data transmission method applied to this computing system. This data transmission method can be applied to the first computing component in the computing system (including computing components of any size, such as computing chips, computing devices, etc.), or it can be applied to the control and processing scheduler within the computing system (such as smart terminals, servers, computing processors, etc.). (Refer to...) Figure 5 This is an optional flowchart of a data transmission method in a computing system provided in an embodiment of this application. Figure 5 The method may include, but is not limited to, steps 501 to 502. It is also understood that this embodiment... Figure 5The order of steps 501 to 502 is not specifically limited. The order of steps can be adjusted or some steps can be reduced or added according to actual needs.

[0070] Step 501: In response to a block-level data transfer instruction initiated by a meta-thread running in the first computing component, determine the target data block information of the block-level data transfer instruction, and generate transfer information pointing to the second computing component based on the target data block information; the block-level data transfer instruction is used to characterize data transfer between the first computing component and the second computing component, and the meta-thread runs independently of the ordinary worker thread.

[0071] Step 501 is described in detail below.

[0072] In some embodiments, the system first responds to a block-level data transfer instruction initiated by a meta-thread running in the first computing component, parses the instruction to determine the corresponding target data block information, and further generates transfer information pointing to the second computing component based on the target data block information. The block-level data transfer instruction is a control instruction characterizing data transfer between the first and second computing components; its operation target is a data block rather than a single data element, which helps reduce the frequency of instruction issuance and improve resource utilization. The target data block information specifically includes key parameters such as the address and size of the target data block to be transferred in memory.

[0073] Understandably, the operation of meta-threads is independent of ordinary worker threads. This "independence" means that meta-threads, as lightweight control threads, are generated and scheduled by the meta-thread instruction scheduler and do not occupy expensive computing resources such as vector register files that are exclusive to ordinary worker threads (such as single instruction multiple threads (SIMT) worker threads in GPUs), thereby achieving hardware resource decoupling between control flow and computation flow.

[0074] The process of generating and applying meta-threads will be described below.

[0075] Reference Figure 6 The generation process of meta-threads includes step 601: receiving kernel function start instructions based on the meta-thread instruction scheduler and generating meta-threads corresponding to the kernel function start instructions.

[0076] Step 601 will be described in detail below.

[0077] In some embodiments, a meta-thread instruction scheduler and a load memory structure are provided in the first computing component (including computing chips and computing devices). The meta-thread instruction scheduler, as the core control component in the first computing component, is responsible for receiving kernel function start instructions from the upper layer of the computing system (such as the command processor), and instantiating and generating corresponding meta-threads according to the configuration information in the kernel function start instructions.

[0078] Understandably, the meta-thread instruction scheduler is a hardware logic unit specifically designed to manage the lifecycle and scheduling of meta-threads, while the kernel function startup instruction is the starting signal that triggers parallel computing tasks or data transmission tasks. Through this step, the system can quickly establish independent meta-thread entities for subsequent task management at the hardware level, preparing the context for subsequent data transmission control. Moreover, this generation process is completely completed automatically by the scheduler hardware, without the intervention of traditional SIMT worker threads.

[0079] Specifically, the generation process of meta-threads begins with the execution of code at the upper layers of the computing system (such as the command controller or host). When the upper layers of the computing system execute the kernel function startup instruction, this instruction is first passed to the driver running at the upper layers of the computing system. The driver parses the configuration parameters of the kernel function, converts them into a command format that the hardware (such as a GPU or dedicated accelerator) can understand, and sends them to the command processor in the hardware via the bus. The command processor, acting as the control center, schedules the kernel function startup instruction to the meta-thread instruction scheduler.

[0080] Upon receiving the kernel function's startup instruction and related configuration information, the meta-thread scheduler does not immediately launch a massive number of ordinary worker threads. Instead, it first generates a meta-thread that corresponds one-to-one with the kernel function's startup instruction. This meta-thread, as a lightweight execution or management entity, is designed to represent the kernel function task in subsequent scheduling and resource allocation. In this way, the system avoids excessive consumption of execution unit resources in the early stages of a task, achieving on-demand allocation.

[0081] Reference Figure 6 In response to a block-level data transfer instruction initiated by a meta-thread running in the first computing component, step 602 is included: the meta-thread instruction scheduler sends the meta-thread to the load storage structure for execution in response to the block-level data transfer instruction initiated by the meta-thread.

[0082] Step 602 will be described in detail below.

[0083] In some embodiments, when a running metathread issues a block-level data transfer instruction for a specific data block operation, the metathread instruction scheduler responds to the block-level data transfer instruction in real time and schedules the metathread (and its associated task context) to the load memory structure (i.e., such as...). Figure 3 or Figure 4 The load / store architecture shown is used for specific physical execution.

[0084] Understandably, the load storage structure is a functional hardware specifically designed for performing data reading, writing, and movement. After receiving the dispatch from the meta-thread instruction scheduler, it can directly drive the underlying interconnect interface to perform data transmission. This scheduling mechanism ensures that the abstract control instructions issued by the meta-thread can be accurately mapped to specific hardware execution units, achieving an efficient transformation from software-defined control flow to hardware execution flow.

[0085] Specifically, when a generated meta-thread initiates a block-level data transfer instruction during its execution (this is a specific type of thread task, such as a block operation task), the meta-thread instruction scheduler monitors and responds to this behavior in real time. The meta-thread instruction scheduler first parses the instruction, identifying that the current thread task type of the meta-thread is a data transfer task (i.e., block-level data transfer). Based on this identification, the meta-thread instruction scheduler no longer schedules the meta-thread to a general-purpose computing unit, but instead precisely sends it to a load-memory structure specifically responsible for data access (i.e., ...). Figure 3 or Figure 4 (As shown in the load / store structure). Subsequently, the load / store structure takes over the execution context of the meta-thread, utilizing its proprietary high-bandwidth channel or direct memory access (DMA) mechanism to perform specific data block movement operations. This mechanism ensures the decoupling and parallel execution of computationally intensive tasks and data transfer tasks on the hardware, greatly improving the system's bus utilization and execution efficiency.

[0086] Through steps 601 to 602 above, the centralized management of the meta-thread instruction scheduler achieves full-process hardware automation from meta-thread creation to instruction distribution and execution. This not only ensures that meta-threads can quickly respond to kernel function startup requests and establish a runtime environment, but also achieves hardware-level collaboration between control logic and execution logic by precisely scheduling the meta-thread that initiates the transmission instruction to the loading memory structure for execution. This enables data transmission tasks to be completed efficiently using dedicated hardware resources (i.e., loading memory structures), thereby ensuring the timeliness of data transmission while achieving fine-grained scheduling and utilization of the internal resources of the computing component.

[0087] Step 502: Send the transmission information to the second computing component so that the target data block represented by the transmission information is transmitted between the first computing component and the second computing component.

[0088] Step 502 is described in detail below.

[0089] In some embodiments, after generating transmission information, the first computing component sends the transmission information to the second computing component to enable the transfer of the target data block represented by the transmission information between the first and second computing components. Specifically, the transmission information carrying control semantics (and possibly data payload) is passed to the second computing component via a physical interconnect link (such as an inter-chip interconnect structure or an inter-device network) between the first and second computing components. Upon receiving the transmission information, the second computing component interacts with the first computing component according to the instructions therein, thereby completing the physical transfer of the target data block between the associative memories of the two nodes. This process achieves efficient data interoperability across nodes through asynchronous initiation of meta-threads and routing and forwarding of transmission information.

[0090] The process of generating and transmitting information will be further described below.

[0091] Reference Figure 7 The block-level data transfer instruction includes a block storage instruction, which generates transfer information pointing to the second computing component based on the target data block information, including the following steps 701 to 702.

[0092] Step 701: Obtain the target data block from the first memory associated with the first computing component based on the target data block information.

[0093] Step 702: Generate transmission information based on the target data block, the target address of the second computing component, and the block storage instructions.

[0094] Steps 701 to 702 are described in detail below.

[0095] In some embodiments, when the executed block-level data transfer instruction includes a block storage instruction characterizing the first computing component to transfer a target data block to the second computing component for data storage, in order to perform the block storage operation, the first computing component first performs a data acquisition action, that is, based on the target data block information, it uses the loading storage structure of the first computing component to acquire the target data block from the first memory associated with the first computing component.

[0096] It is understandable that the first memory refers to local storage resources that are physically integrated within the first computing component (such as on-chip memory) or logically managed by the first computing component (such as off-chip memory); the target data block information provides location parameters such as the specific index address, offset, and data length of the data to be transmitted in the first memory. The first computing component uses the loading storage structure to extract the entity data that needs to be transmitted across nodes into the buffer of the loading storage structure by reading local storage resources, thus preparing the data for subsequent encapsulation and transmission.

[0097] After acquiring the entity data (i.e., the target data block), transmission information is generated based on the target data block, the target address pointing to the storage space of the second computing component, and the block storage instructions defining the operation type. Specifically, this step is essentially a data encapsulation or packaging process. The generated transmission information (e.g., a data packet containing the data payload) not only carries the payload to be transmitted (i.e., the target data block), but also carries routing and address information indicating the transmission destination and control semantics indicating that the operation is "storage," thereby constructing a self-contained information unit with complete transmission elements, enabling it to be independently routed and parsed in the Internet.

[0098] Reference Figure 8 The transmission information is sent to the second computing component to transmit the target data block represented by the transmission information between the first computing component and the second computing component, including step 801: using the interconnection link between the first computing component and the second computing component, the transmission information is transmitted to the second computing component based on the target address, so that the second computing component receives the target data block and stores the target data block in the associated second memory.

[0099] Step 801 will be described in detail below.

[0100] In some embodiments, when the block-level data transfer instruction being executed includes a block storage instruction characterizing that the first computing component transfers a target data block to the second computing component for data storage, after generating the transmission information, the first computing component, using the interconnection link between the first computing component and the second computing component, transmits the transmission information to the second computing component based on the target address according to the routing indication in the transmission information, so as to drive the second computing component to receive the target data block and store the target data block in the associated second memory.

[0101] Understandably, this process utilizes the high bandwidth of interconnect links (such as inter-chip interconnect structures or inter-device networks) to transmit data from the source to the destination. The second computing component, as the receiver, after parsing the write instructions and data in the transmitted information, directly writes the data payload to the designated address of the second memory (i.e., the local storage resource of the second computing component), thereby completing the cross-node data storage operation.

[0102] Through steps 701, 702, and 801 above, an efficient "block storage" data transmission mechanism is constructed. By directly packaging the data entity and the target address at the source end to generate transmission information containing complete semantics, and sending it to the destination end for direct storage through the interconnection link, a transmission mode that can complete writing without frequent handshakes is realized. This enables full utilization of the physical bandwidth of the interconnection link, greatly reduces the overhead of the communication protocol and transmission latency, and significantly improves the throughput of large-scale data migration in the distributed computing system.

[0103] Reference Figure 9 This is a schematic diagram illustrating a process for performing cross-chip storage operations at the computing chip level, provided in an embodiment of this application. For example... Figure 9 The diagram shows the block storage operation process when the two computing components performing data transmission are two computing chips within the same chip. The execution of this process includes the following stages and steps.

[0104] Instruction initiation phase (i.e.) Figure 9 Arrow ① in the diagram: The meta-thread, running in the computing unit located in the first computing chip (i.e., the first computing component) on the left, initiates block-level data transfer instructions (i.e., block storage instructions) to the local load / store structure (i.e., the load-store structure). At this time, the meta-thread is only responsible for issuing control signals and does not occupy the register resources of ordinary worker threads.

[0105] Data acquisition phase (i.e.) Figure 9 Arrow ② in the middle): The local load / store structure of the first computing chip responds to the block storage instruction and reads the target data block to be transferred from the on-die memory associated with the first computing chip or the vertically stacked off-die memory according to the target data block information.

[0106] Information generation and transmission phase (i.e. Figure 9(Arrow ③ in the image): The load / store structure encapsulates the acquired target data block with the target write address (i.e., the target address) of the second computing chip to generate transmission information. Subsequently, using the chip's internal die-to-die link / fabric interconnect structure, this transmission information is sent to the second computing chip (i.e., the second computing component) on the right.

[0107] The receiving and storage phase (i.e.) Figure 9 (Arrows ④ and ⑤ in the diagram): The loading / storage structure of the second computing chip receives the transmission information from the interconnect structure, parses out the target data block corresponding to the data payload, and directly writes the target data block into its associated on-chip memory or off-chip memory.

[0108] Reference Figure 10 This is a schematic diagram illustrating a process for performing cross-device block storage operations at the computing device level, provided in an embodiment of this application. For example... Figure 10 The diagram shows the block storage operation process when the two computing components performing data transmission are two independent computing devices. The execution of this process includes the following stages and steps.

[0109] Instruction initiation phase (i.e.) Figure 10 Arrow ① in the diagram: The meta-thread within the first computing device (i.e., the first computing component) on the left initiates a block-level data transfer instruction to the load / store structure. This block-level data transfer instruction specifies the target data block that needs to be transferred from the local location to the address of the remote computing device.

[0110] Data acquisition phase (i.e.) Figure 10 Arrow ② in the diagram): The load / store structure within the first computing device extracts the target data block from the local SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) according to the instructions.

[0111] Network transmission phase (i.e.) Figure 10 Arrow ③ in the middle): The load / storage structure of the first computing device generates transmission information based on the target data block and the target address of the remote computing device (i.e., the second computing component), and routes the transmission information to the second computing device (second computing component) on the right through the inter-device network (such as PCIE, NVLink or Ethernet).

[0112] Remote storage phase (i.e.) Figure 10 (Arrow ④ in the diagram): The remote computing device (i.e., the second computing component) receives the transmitted information through the network interface. Its internal load / store structure responds to the request, storing the parsed target data block into local SRAM or DRAM memory. This process supports asynchronous operation; the meta-thread can process subsequent tasks without waiting for the transmission to complete after initiating the instruction.

[0113] Reference Figure 11 The block-level data transfer instruction includes a block loading instruction, which generates transfer information pointing to the second computing component based on the target data block information, including the following steps 1101 to 1102.

[0114] Step 1101: Determine the requested data block information of the target data block based on the target data block information.

[0115] Step 1102: Generate transmission information based on the source address of the first computing component, the target address of the second computing component, the requested data block information, and the block loading instruction.

[0116] Steps 1101 to 1102 are described in detail below.

[0117] In some embodiments, when the executed block-level data transfer instruction includes a block loading instruction characterizing that the first computing component needs to acquire a target data block from the second computing component, in order to execute the block loading instruction operation, the first computing component first needs to utilize a loading memory structure (i.e., such as...) Figure 3 or Figure 4 The load / store structure shown parses the intent of the block load instruction, that is, to determine the requested data block information of the target data block based on the target data block information.

[0118] Understandably, the target data block information is the descriptive information carried in the original instruction issued by the meta-thread, while the request data block information is a set of parameters that has been parsed and used to explicitly indicate "how much data needs to be acquired" and "the specific characteristics of the data" at the hardware level. This transforms the high-level logic requirements of the meta-thread into request parameters that can be recognized by the underlying transmission protocol, laying the foundation for generating subsequent communication messages.

[0119] Subsequently, the first computing component further integrates routing and control elements, namely, generating transmission information based on the source address of the first computing component, the destination address of the second computing component, the requested data block information, and the block loading instruction. In this scenario, the transmission information essentially constitutes a "Read Request Packet," where the "destination address of the second computing component" indicates the specific location where the data is stored on the remote node, the "source address of the first computing component" indicates the receiving location or initiator identifier when the data is returned, and the "requested data block information" defines the data length. By encapsulating these elements together with the opcode of the block loading instruction, a complete transmission information corresponding to a control message capable of driving the remote node to perform a read operation is constructed.

[0120] Reference Figure 12Sending transmission information to a second computing component to transmit the target data block represented by the transmission information between the first computing component and the second computing component includes the following steps 1201 to 1202.

[0121] Step 1201: Transmit the transmission information to the second computing component based on the target address, so that the second computing component can obtain the target data block from the associated second memory based on the requested data block information.

[0122] Step 1202: Using the interconnection link between the first computing component and the second computing component, receive the target data block sent by the second computing component and store it in the first memory associated with the first computing component.

[0123] Steps 1201 to 1202 are described in detail below.

[0124] In some embodiments, when the executed block-level data transfer instruction includes a block loading instruction that characterizes the first computing component's need to obtain a target data block from the second computing component, and after the first computing component generates the transmission information, the first computing component initiates a sending process, that is, based on the target address, it transmits the transmission information to the second computing component, which is the peer, using the routing function of the interconnect structure, so that after receiving the information, the loading storage structure of the second computing component directly addresses and reads its associated second memory (such as remote on-chip memory or DRAM) according to the instructions therein, thereby extracting the data entity of the target data block required by the request.

[0125] Then, after the second computing component completes the reading of the target data block, it uses the interconnection link between the first and second computing components to return the target data block to the first computing component. As the initiator, the first computing component, upon receiving the returned target data block, writes it to a designated location in its associated first memory (i.e., local storage resource), thus completing the closed-loop process of "initiating request - remote reading - data return - local storage".

[0126] Through steps 1101, 1102, 1201, and 1202 above, an efficient "Block Load" data transmission mechanism is constructed. By having the first computing component actively generate transmission information (request packet) containing complete return addresses and read parameters, and driving the second computing component to perform responsive reading and return, a data loading mode transmission based on a request-response model is realized. This allows the meta-thread running on the first computing component to easily obtain the storage resources of remote nodes, and the entire remote reading process is automatically processed by hardware logic without the need for software intervention from the computing units of remote nodes, greatly improving the convenience of cross-node data access and system throughput.

[0127] Reference Figure 13 This is a schematic diagram illustrating a process for performing cross-device block storage operations at the computing device level, provided in an embodiment of this application. For example... Figure 13 The diagram shows the block loading operation process when the two computing components that perform data transmission are two computing chips within the same chip. The execution of this process includes the following stages and steps.

[0128] Instruction initiation and parsing phase (i.e.) Figure 13 Arrow ① in the diagram: The meta-thread running in the computing unit within the first computing core (i.e., the first computing component) on the left initiates a block-level data transfer instruction (i.e., a block loading instruction) to the local load / store hierarchy. The load / store hierarchy first parses the instruction and determines the length and characteristics of the data to be read based on the target data block information, i.e., requests the data block information.

[0129] The information generation stage (i.e.) Figure 13 (The internal logic of arrow ① in the image): The loading / storage structure of the first computing core integrates the source address of the first computing core (used for data backhaul), the target address of the second computing core, and the request data block information to generate transmission information containing complete read request semantics (i.e., a read request packet).

[0130] Request sending phase (i.e.) Figure 13 Arrows ② and ③ in the image: The loading / storage structure of the first computing die uses the high-speed die-to-die link / fabric structure inside the chip to send the transmission information to the second computing die (second computing component) on the right.

[0131] Remote reading and return phase (i.e.) Figure 13 (Arrows ④ and ⑤ in the diagram): After receiving a request, the load / store structure of the second computing chip automatically addresses and reads its associated on-die memory or off-die memory. Subsequently, the acquired target data block is sent back to the first computing chip through the interconnect structure.

[0132] Data reception and storage stage (i.e. Figure 13 (Arrows ⑥ and ⑦ in the text): The load / store structure of the first computing chip receives the target data block issued by the second computing chip and writes it into the locally associated on-chip memory or off-chip memory, completing the process of loading data from the remote chip.

[0133] Reference Figure 14This is a schematic diagram illustrating a process for performing cross-device block storage operations at the computing device level, provided in an embodiment of this application. For example... Figure 14 The diagram shows the block loading operation process when the two computing components performing data transmission are two independent computing devices. The execution of this process includes the following stages and steps.

[0134] Instruction initiation and generation phase (i.e. Figure 14 Arrow ① in the diagram: The meta-thread within the first computing device (i.e., the first computing component) on the left initiates a block loading instruction. The load / store structure within the first computing device determines the requested data block information based on the instruction, and combines the source address and the remote target address to generate transmission information (i.e., a read request packet) to drive remote reading.

[0135] Network transmission phase (i.e.) Figure 14 Arrow ② in the middle): The load / storage structure of the first computing device routes the transmission information to the second computing device (i.e., the second computing component) on the right through an inter-device network (such as PCIe or Ethernet).

[0136] Remote response phase (i.e.) Figure 14 Arrow ③ in the image): The load / storage structure of the second computing device receives the transmission information and, based on the instructions therein, reads the target data block from its local SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0137] Data backhaul phase (i.e.) Figure 14 Arrows ④ and ⑤ in the diagram indicate step 1202): The second computing device transmits the read target data block back to the first computing device via the network. The first computing device's load / store structure receives the data and stores it in its local DRAM or SRAM memory. Throughout the process, the meta-thread can continue executing other instructions that do not depend on the data after initiating the request, achieving efficient asynchronous data retrieval.

[0138] Reference Figure 15 This is a schematic diagram of an on-chip interconnect architecture for a computing chip provided in an embodiment of this application. Figure 15As shown, when the two computing components transmitting data are two computing granules within the same chip, the computing granule initiating the data transmission (i.e., the first computing component) integrates at least one computing unit. The meta-thread within the computing unit acts as the basic execution unit, and the resulting data or instruction streams are scheduled by the meta-thread instruction scheduler and converge to the single-granule loading / storage hub module (i.e., the aforementioned loading-storage structure). When the target object of the transmitted information (i.e., the second computing component) is located within the same physical chip as the first computing component but belongs to a different computing granule, the single-granule loading / storage hub module outputs the information to the inter-granule interconnect structure (this inter-granule link / interconnect structure may or may not include IO granules). Utilizing the high-speed channel built within the chip using this interconnect structure, the transmitted information is then precisely sent to the other computing granule, which is the second computing component, thereby achieving efficient data interaction and collaborative computing between different granules within the same chip package.

[0139] Reference Figure 16 This is a schematic diagram of the interconnection structure of a computing device provided in an embodiment of this application. Figure 16 As shown, when the two computing components transmitting data are two independent computing devices, the computing device initiating the data transmission (i.e., the first computing component) integrates at least one computing core, each containing several computing units. The meta-threads within these computing units act as the execution entities, and the data or instructions they generate are scheduled and output through a meta-thread instruction scheduler, converging to a single-core loading / storage hub module (i.e., the aforementioned loading-storage structure). To achieve higher-level interconnection, information from each computing core is further transmitted to the single-device loading / storage hub module. Furthermore, for cross-device communication scenarios, i.e., when the first and second computing components are two physically separate computing devices, the single-device loading / storage hub module of the first computing component sends the transmission information to be transmitted to the inter-device network where the first and second computing components reside (this inter-device network may or may not include a switch). Then, it uses this network to send the transmission information to the physically separate second computing component, thus completing the entire data link transmission from the micro-execution unit within the chip to the macro-physical inter-device network.

[0140] In addition, refer to Figure 17 The block-level data transfer instruction is an asynchronous instruction, and the block-level data transfer instruction includes a barrier identifier. The data transfer method in the computing system provided in this application also includes the following steps 1701 to 1702.

[0141] Step 1701: After the meta-thread initiates a block-level data transfer instruction, continue executing subsequent data processing instructions.

[0142] Step 1702: When a subsequent data processing instruction indicates an access operation on the target data block, the access operation on the target data block is executed only after the target data block has been transmitted, based on the barrier identifier.

[0143] Steps 1701 to 1702 are described in detail below.

[0144] In some embodiments, the metathread acts as the execution subject, and its own instruction execution logic is asynchronous. After issuing a block-level data transfer instruction, it will not block or pause the current execution flow because the target data block has not yet been moved. Instead, it will continue to run downwards to execute subsequent data processing instructions.

[0145] Understandably, because block-level data transfer instructions are specifically configured as asynchronous instructions, the data transfer operation triggered by these instructions can be performed independently in the background, overlapping in time with the parsing and execution of the instructions by the computing unit. Therefore, the meta-thread can utilize the transmission time of this data transfer to process logical tasks that do not depend on the data currently being transferred in parallel, thereby avoiding the waste of computing resources due to waiting for I / O operations.

[0146] When a subsequent data processing instruction executed by the meta-thread represents an access operation on the target data block (i.e., the data object transported by the aforementioned asynchronous instruction), the first computation component checks the data readiness status of the operation. In this case, based on the barrier flag carried in the block-level data transfer instruction, the first computation component determines whether the corresponding data transfer has ended. If it has not ended, a waiting action is forcibly executed until the target data block transfer is completely completed before the block is unblocked and access to the target data block is allowed.

[0147] As can be understood, a barrier identifier is a synchronization marker attached to asynchronous block-level data transfer instructions, used to establish a logical association between transfer operations and subsequent data access operations in a parallel execution flow. Essentially, the barrier identifier acts as a fine-grained synchronization primitive, used to enforce timing synchronization of operations at specific nodes in an asynchronous environment. When a subsequent instruction needs to access the target data being transferred, the system uses this identifier to force the execution flow into a waiting state, allowing execution to continue only after confirming that the data transfer is complete, thus masking transmission delays while ensuring data consistency.

[0148] Through steps 1701 to 1702 above, by combining asynchronous transmission with an explicit barrier synchronization mechanism, the meta-thread is allowed to execute subsequent data processing instructions without data dependencies in parallel during data transmission, thereby significantly improving the utilization of the computing pipeline and the overall throughput of the system. At the same time, by using barrier markers to precisely block and wait only when data is required, performance loss caused by blind waiting is avoided, and data consistency and security are strictly guaranteed when accessing the target data block.

[0149] The data transfer method in the computing system provided in this application decouples computational tasks from control tasks by introducing meta-threads as lightweight control entities. Meta-threads require minimal control state resources during creation and do not require the allocation of large-capacity vector registers. When executing block-level data transfer tasks, the meta-thread instruction scheduler can identify the task type and directly send the meta-thread to the load memory structure (or block operation structure) for execution, rather than occupying general-purpose computing cores or execution units (EUs). This allows computing unit and vector register resources to be completely released during data transfer (especially remote transfers across cores or devices) for executing other genuine mathematical operations, thus avoiding hardware resource idleness and waste caused by "waiting for data."

[0150] Furthermore, the solution in this application utilizes a meta-thread instruction scheduler as an intelligent distribution hub, which can accurately route data transfer requests involving physically separated computing devices or different computing chips within the same chip to a dedicated single-chip loading / storage hub module or inter-device network interface based on the "communication task type" or "block operation task type." This separates "data movement" from "data computation," further freeing the computational functional units from the heavy overhead of I / O instruction issuance. Moreover, the dedicated loading / storage unit fully leverages the high bandwidth characteristics of on-chip interconnect structures or inter-device networks, filling the links with an efficient block transfer mode. This significantly overcomes the bandwidth utilization bottleneck caused by single-threaded discrete control, effectively supporting the high-concurrency data exchange requirements of tensor parallelism and pipeline parallelism in large model training.

[0151] Furthermore, the solution proposed in this application supports asynchronous block-level data transfer instructions initiated by meta-threads, and uses a barrier identification mechanism for synchronization. In distributed architectures across chips or devices, data round-trip latency is significant. The solution proposed in this application utilizes the fact that meta-threads can immediately continue executing subsequent independent instructions after initiating a transfer, only waiting based on barriers when the target data must be accessed. This mechanism allows the computing system to naturally implement "computation masking transmission" at the hardware level, maximizing the hiding of communication latency caused by physical distance or network congestion while maintaining logical correctness, thereby significantly improving the parallel processing efficiency of the entire high-performance computing cluster.

[0152] Finally, the solution in this application generates meta-threads by responding to kernel function startup instructions through the meta-thread instruction scheduler, and combined with the inter-chip interconnection structure, it endows meta-threads with the ability to access memory across physical boundaries. This enables them not only to access the memory of other computing chips within the same chip package, but also to further extend to access the memory of other physically separated computing devices. This effectively breaks through the storage limitations of single-point computing and greatly enhances the data interoperability and collaboration capabilities under the distributed architecture.

[0153] This application also provides a data transmission device in a computing system, which can implement the data transmission method in the above-described computing system, referring to... Figure 18 The device 1800 includes:

[0154] The response module 1810 is used to respond to a block-level data transfer instruction initiated by a meta-thread running in the first computing component, determine the target data block information of the block-level data transfer instruction, and generate transmission information pointing to the second computing component based on the target data block information; the block-level data transfer instruction is used to characterize data transfer between the first computing component and the second computing component, and the meta-thread runs independently of the ordinary worker thread;

[0155] The transmission module 1820 is used to send transmission information to the second computing component so as to transmit the target data block represented by the transmission information between the first computing component and the second computing component.

[0156] In some embodiments, the response module 1810 is further configured to:

[0157] The target data block is obtained from the first memory associated with the first computing component based on the target data block information;

[0158] Based on the target data block, the target address of the second computing component, and the block storage instructions, transmission information is generated.

[0159] In some embodiments, the transmission module 1820 is further configured to:

[0160] Using the interconnection link between the first computing component and the second computing component, the transmission information is transmitted to the second computing component based on the target address, so that the second computing component receives the target data block and stores the target data block in the associated second memory.

[0161] In some embodiments, the response module 1810 is further configured to:

[0162] Determine the requested data block information of the target data block based on the target data block information;

[0163] Based on the source address of the first computing component, the target address of the second computing component, the requested data block information, and the block loading instructions, transmission information is generated.

[0164] In some embodiments, the transmission module 1820 is further configured to:

[0165] The transmission information is transmitted to the second computing component based on the target address, so that the second computing component can obtain the target data block from the associated second memory based on the requested data block information;

[0166] Using the interconnection link between the first computing component and the second computing component, the target data block sent by the second computing component is received and stored in the first memory associated with the first computing component.

[0167] In some embodiments, the transmission module 1820 is further configured to:

[0168] By utilizing the interconnect structure between computing chips in the chip, the transmission information is sent to the second computing component.

[0169] In some embodiments, the transmission module 1820 is further configured to:

[0170] The information is transmitted to the second computing component using the inter-device network where the first and second computing components are located.

[0171] In some embodiments, the transmission module 1820 is further configured to:

[0172] After the metathread initiates a block-level data transfer instruction, it continues to execute subsequent data processing instructions.

[0173] When a subsequent data processing instruction indicates an access operation to the target data block, the access operation to the target data block is executed only after the target data block has been transmitted, based on the barrier identifier.

[0174] In some embodiments, the response module 1810 is further configured to:

[0175] The meta-thread instruction scheduler receives kernel function start instructions and generates meta-threads corresponding to the kernel function start instructions.

[0176] In response to a block-level data transfer instruction initiated by a meta-thread running in the first computing component, including:

[0177] The meta-thread instruction scheduler responds to block-level data transfer instructions initiated by the meta-thread and sends the meta-thread to the load memory structure for execution.

[0178] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, the specific implementation of the data transmission device in the computing system is basically the same as the specific implementation of the data transmission method in the computing system described above, and will not be repeated here.

[0179] This application also provides an electronic device, including:

[0180] At least one memory;

[0181] At least one processor;

[0182] At least one program;

[0183] The program is stored in memory, and the processor executes at least one program to implement the data transmission method in the computing system described above. The electronic device can be any smart terminal, including mobile phones, tablets, personal digital assistants (PDAs), and in-vehicle computers.

[0184] Please see Figure 19 , Figure 19 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes:

[0185] The processor 1901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0186] The memory 1902 can be implemented in the form of ROM (Read Only Memory), static storage device, dynamic storage device, or RAM (Random Access Memory). The memory 1902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1902 and is called and executed by the processor 1901 to execute the data transmission method in the computing system of the embodiments of this application.

[0187] The input / output interface 1903 is used to implement information input and output;

[0188] The communication interface 1904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0189] Bus 1905 transmits information between various components of the device (e.g., processor 1901, memory 1902, input / output interface 1903, and communication interface 1904);

[0190] The processor 1901, memory 1902, input / output interface 1903, and communication interface 1904 are connected to each other within the device via bus 1905.

[0191] This application also provides a storage medium, which is a computer-readable storage medium, storing a computer program that, when executed by a processor, implements the data transmission method described above in the computing system.

[0192] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0193] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0194] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0195] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0196] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0197] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0198] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0199] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, or indirect coupling or communication connection between the apparatus or units, and may be electrical, mechanical, or other forms.

[0200] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0201] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0202] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0203] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A data transmission method in a computing system, characterized in that, include: In response to a block-level data transfer instruction initiated by a meta-thread running in the first computing component, the target data block information of the block-level data transfer instruction is determined, and transfer information pointing to the second computing component is generated based on the target data block information. The block-level data transfer instruction is used to characterize data transfer between the first computing component and the second computing component, and the meta-thread runs independently of the ordinary worker thread; The transmission information is sent to the second computing component to enable the transmission of the target data block represented by the transmission information between the first computing component and the second computing component. The first computing component includes a meta-thread instruction scheduler and a load-memory structure. The meta-thread generation process includes: Based on the received kernel function start instruction by the meta-thread instruction scheduler, a meta-thread corresponding to the kernel function start instruction is generated. The block-level data transfer instruction initiated in response to a meta-thread running in the first computing component includes: The meta-thread instruction scheduler responds to the block-level data transfer instruction initiated by the meta-thread and sends the meta-thread to the load storage structure for execution.

2. The data transmission method in the computing system according to claim 1, characterized in that, The block-level data transfer instructions include block storage instructions, and the generation of transfer information pointing to the second computing component based on the target data block information includes: The target data block is obtained from the first memory associated with the first computing component based on the target data block information; The transmission information is generated based on the target data block, the target address of the second computing component, and the block storage instruction.

3. The data transmission method in the computing system according to claim 2, characterized in that, Sending the transmission information to the second computing component to transmit the target data block represented by the transmission information between the first computing component and the second computing component includes: Using the interconnection link between the first computing component and the second computing component, the transmission information is transmitted to the second computing component based on the target address, so that the second computing component receives the target data block and stores the target data block in the associated second memory.

4. The data transmission method in the computing system according to claim 1, characterized in that, The block-level data transfer instruction includes a block loading instruction, and the step of generating transfer information pointing to the second computing component based on the target data block information includes: The request data block information of the target data block is determined based on the target data block information; The transmission information is generated based on the source address of the first computing component, the target address of the second computing component, the requested data block information, and the block loading instruction.

5. The data transmission method in the computing system according to claim 4, characterized in that, Sending the transmission information to the second computing component to transmit the target data block represented by the transmission information between the first computing component and the second computing component includes: The transmission information is transmitted to the second computing component based on the target address, so that the second computing component can obtain the target data block from the associated second memory based on the request data block information; Using the interconnection link between the first computing component and the second computing component, the target data block sent by the second computing component is received and stored in the first memory associated with the first computing component.

6. The data transmission method in the computing system according to claim 1, characterized in that, The first computing component and the second computing component are different computing chips within the same chip. Sending the transmission information to the second computing component includes: The transmission information is sent to the second computing component using the interconnect structure between the computing chips in the chip.

7. The data transmission method in the computing system according to claim 1, characterized in that, The first computing component and the second computing component are two physically separate computing devices. Sending the transmission information to the second computing component includes: The transmission information is sent to the second computing component using the inter-device network where the first computing component and the second computing component are located.

8. The data transmission method in the computing system according to claim 1, characterized in that, The block-level data transmission instruction is an asynchronous instruction, and the block-level data transmission instruction includes a barrier identifier. The method further includes: After the meta-thread initiates the block-level data transfer instruction, it continues to execute subsequent data processing instructions; When the subsequent data processing instruction indicates an access operation to the target data block, the access operation to the target data block is executed only after the target data block has been transmitted, based on the barrier identifier.

9. A data transmission device in a computing system, characterized in that, include: A response module is used to respond to a block-level data transfer instruction initiated by a meta-thread running in the first computing component, determine the target data block information of the block-level data transfer instruction, and generate transfer information pointing to the second computing component based on the target data block information. The block-level data transfer instruction is used to characterize data transfer between the first computing component and the second computing component, and the meta-thread runs independently of the ordinary worker thread; A transmission module is configured to send the transmission information to the second computing component, so as to transmit the target data block represented by the transmission information between the first computing component and the second computing component; The first computing component includes a meta-thread instruction scheduler and a load-memory structure. The meta-thread generation process includes: Based on the received kernel function start instruction by the meta-thread instruction scheduler, a meta-thread corresponding to the kernel function start instruction is generated. The block-level data transfer instruction initiated in response to a meta-thread running in the first computing component includes: The meta-thread instruction scheduler responds to the block-level data transfer instruction initiated by the meta-thread and sends the meta-thread to the load storage structure for execution.

10. An electronic device, characterized in that, The system includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the data transmission method in the computing system according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the data transmission method in the computing system according to any one of claims 1 to 8.

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