Physical memory access method, electronic equipment, storage medium and program product

Abstract

The invention discloses a physical memory access method, electronic equipment, a storage medium and a program product, and the method comprises the steps: receiving a physical memory access request of a first access party, the physical memory access request comprising a first equipment identifier, a target physical memory address and a target access permission, the first device identifier comprises a device function number of the first access party in the bus structure; determining a first source identifier corresponding to the first device identifier according to a mapping relationship between a plurality of device identifiers and a plurality of source identifiers, the plurality of device identifiers including device function numbers of a plurality of access parties in the bus structure; according to the first source identifier and the target physical memory address, searching a plurality of IOPMP entries to obtain a target IOPMP entry; performing permission check on the target access permission according to the target IOPMP entry to obtain a check result; and returning a physical memory access response to the first access party according to the check result. Therefore, the control accuracy of the IOPMP unit on the access permission of the physical memory is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer technology, and particularly relate to a physical memory access method, an electronic device, a storage medium and a program product. BACKGROUND

[0002] In a cloud computing scenario in which peripherals frequently interact with memories, a system on chip (SoC) chip based on a fifth-generation reduced instruction set computer (RISC-V) architecture needs to cope with complex security challenges of peripheral access to memories.

[0003] A physical memory protection (PMP) unit and an input / output physical memory protection (physical memory protection unit of input / output devices, IOPMP) unit are hardware units in a bus structure of the RISC-V architecture, and provide a hardware-level memory security protection mechanism. The PMP unit controls physical memory access behavior of a processor core, and the IOPMP unit controls physical memory access behavior of non-core hardware (such as peripherals), and the two complement each other to form a physical memory protection system of the SoC chip.

[0004] However, a hardware-level identity mechanism adopted by the IOPMP unit has defects in a hardware adaptation layer, cannot be compatible with conventional devices based on the bus structure, and causes the IOPMP unit to be difficult to accurately control physical memory access permissions. SUMMARY

[0005] Embodiments of the present application provide a physical memory access method, an electronic device, a storage medium and a program product, and at least solve the problem that a hardware-level identity mechanism adopted by an IOPMP unit has defects in a hardware adaptation layer, cannot be compatible with conventional devices based on a bus structure, and causes the IOPMP unit to be difficult to accurately control physical memory access permissions.

[0006] In a first aspect, an embodiment of the present application provides a physical memory access method applied to an IOPMP unit, and including: receiving a physical memory access request of a first access party, the physical memory access request including a first device identifier, a target physical memory address to be accessed and a target access permission to be requested, and the first device identifier including a device function number of the first access party in a bus structure related to the IOPMP unit; According to a mapping relationship between a plurality of device identifiers and a plurality of source identifiers configured, a first source identifier corresponding to the first device identifier is determined, the plurality of device identifiers include device function numbers of a plurality of access parties in the bus structure respectively, and the plurality of source identifiers respectively identify a plurality of bus hosts or bus host groups on the bus structure; According to the first source identifier and the target physical memory address, a target IOPMP entry is found in a plurality of IOPMP entries configured, a source identifier in the target IOPMP entry matches the first source identifier, and a memory address range in the target IOPMP entry includes the target physical memory address; According to the target IOPMP entry, permission checking is performed on the target access permission, and a checking result is obtained; According to the checking result, a physical memory access response is returned to the first access party, and the physical memory access response indicates that the physical memory access request is allowed or the physical memory access request is rejected.

[0007] In a second aspect, an embodiment of the present application provides an electronic device, including: One or more processors; A memory having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement as: The physical memory access method in the first aspect.

[0008] In a third aspect, an embodiment of the present application provides a computer readable storage medium having a computer program stored thereon, when the program is executed by a processor, the program implements as: The physical memory access method in the first aspect.

[0009] In a fourth aspect, an embodiment of the present application provides a computer program product including a computer program, when the computer program is executed by a processor, the computer program implements as: The physical memory access method in the first aspect.

[0010] In the physical memory access request of the first access party in the embodiment of the application, the first device identifier includes a device function number of the first access party in the bus structure, and in the mapping relationship between the plurality of device identifiers and the plurality of source identifiers, the plurality of device identifiers include device function numbers of the plurality of access parties in the bus structure. It can be seen that the hardware identity mechanism of the IOPMP is that the device function number of the access party in the bus structure is used as the device identifier of the access party, and the mapping of the plurality of device function numbers to the plurality of source identifiers is established through the mapping relationship between the plurality of device identifiers and the plurality of source identifiers. Compared with directly identifying the access party by using the source identifier, the device function number in the bus structure has better compatibility at the hardware adaptation level, and the device function number in the bus structure can be used to accurately mark the peripheral device. After receiving the physical access request of the first access party, the first source identifier corresponding to the first device identifier can be determined based on the mapping relationship between the plurality of device identifiers and the plurality of source identifiers, and then the target IOPMP entry is searched in the plurality of IOPMP entries according to the first source identifier and the target physical memory address, the target access right is checked according to the target IOPMP entry, and the physical memory access response is returned to the first access party according to the checking result, so as to accurately control the physical memory right of the first access party. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings are used to provide a further understanding of the technical scheme of the application, and constitute a part of the specification, and are used to explain the technical scheme of the application together with the embodiments of the application, and do not constitute a limitation on the technical scheme of the application.

[0012] Figure 1 An example structure diagram of an SoC integrated with an IOPMP.

[0013] Figure 2 A flowchart of a physical memory access method provided in the embodiment of the application Figure 1 .

[0014] Figure 3 An example diagram for mapping a device identifier to a source identifier.

[0015] Figure 4 An example of mapping a device identifier to a memory domain Figure 1 .

[0016] Figure 5 An example of mapping a device identifier to a memory domain Figure 2 .

[0017] Figure 6 A flowchart of an address matching process of an IOPMP unit provided in the embodiment of the application.

[0018] Figure 7Figure 1 is a flowchart of a physical memory access method according to an embodiment of the present application Figure 2 .

[0019] Figure 8 Figure 4 is a flowchart of a process for reporting errors by an IOPMP unit according to an embodiment of the present application

[0020] Figure 9 Figure 5 is a flowchart of a process for reporting interrupts by an IOPMP unit according to an embodiment of the present application

[0021] Figure 10 Figure 6 is a block diagram of a module structure of an IOPMP unit according to an embodiment of the present application

[0022] Figure 11 Figure 7 is a diagram of signal configuration during dynamic reconfiguration of an IOPMP unit according to an embodiment of the present application

[0023] Figure 12 Figure 8 is a block diagram of an embodiment of an electronic device according to an embodiment of the present application DETAILED DESCRIPTION

[0024] In order to make the skilled in the art better understand the technical solutions of the present application, the technical solutions provided by the present application will be described in detail below with reference to the drawings.

[0025] In the following, example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0026] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0028] In the following description, reference is made to the "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0029] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in the embodiments of this application.

[0030] In cloud computing scenarios, cloud servers need to handle multi-tenant tasks simultaneously. During this process, the high-frequency interaction between peripherals such as storage controllers and network acceleration units and memory poses a risk of being maliciously exploited to bypass software protection mechanisms and directly steal or tamper with sensitive data. For example, attackers can use uncontrolled direct memory access (DMA) operations to read information across virtual machines beyond their bounds. Alternatively, attackers can hijack shared memory regions using spoofed devices.

[0031] The Physical Memory Protection Unit of Input / Output Devices (IOPMP) defined in the Reduced Instruction Set Computer-Version Five (RISC-V) architecture is a crucial component of the physical memory protection system. The primary function of the IOPMP is to implement fine-grained access control over physical memory access requests from non-core devices on the system bus (such as DMA controllers and peripherals). Within the IOPMP, the source ID, target physical address, and operation type (e.g., read / write / execute) of the physical memory access request are examined, and a decision is made based on preset rules to allow the operation. Registers within the IOPMP (such as access permissions and corresponding memory address segments) are typically configured and managed by privileged software to ensure that critical memory areas (such as the operating system kernel space and sensitive peripheral registers) are protected from unauthorized or malicious DMA access.

[0032] However, the IOPMP unit has some unresolved technical issues. One of these issues is that in the hardware-level identity mechanism of the IOPMP unit, the IOPMP unit uses a source ID to mark the access source. The source ID has defects at the hardware adaptation level and cannot be compatible with conventional devices based on bus architecture. It is difficult to accurately mark peripherals, which makes it impossible for the IOPMP unit to accurately control the physical memory access permissions of peripherals.

[0033] This application provides a physical memory access method, an electronic device, a storage medium, and a program product. It uses the device function number of the accessing party in the bus structure as the accessing party's device identifier. By establishing a mapping relationship between the device identifier and the source identifier, the corresponding source identifier can be found based on the accessing party's device function number after receiving a physical memory access request. Compared to the source identifier, the device function number in the bus structure can accurately identify peripherals, solving the problem that the hardware-level identification mechanism of the IOPMP unit is difficult to accurately identify peripherals. Upon receiving a physical memory access request, the corresponding source identifier is determined based on the device function number in the physical memory access request. Then, based on the source identifier and the target physical memory address requested by the physical memory access request, the target IOPMP entry is searched among multiple IOPMP entries. Permission checks are performed on the target IOPMP entry, and a physical memory access response is returned based on the check result. Therefore, by solving the problem that the hardware-level identification mechanism of the IOPMP unit is difficult to accurately identify peripherals, the accuracy of the IOPMP unit in controlling the physical memory access permissions of peripherals is effectively improved. In particular, when malicious access enters the IOPMP unit from the IO end, the IOPMP unit can detect the violation and block it, thus implementing permission specifications for peripheral access to physical memory.

[0034] Please see Figure 1 , Figure 1 This is an example structural diagram of a SoC integrating IOPMP. (See diagram for example.) Figure 1 As shown, the SoC integrates a compute subsystem, a system interconnect system, an I / O subsystem (i.e., an input / output subsystem), and system memory. The compute subsystem, I / O subsystem, and system memory are connected to the system interconnect system.

[0035] like Figure 1As shown, the computing subsystem may include multiple central processing units (CPUs), each integrating a physical memory protection (PMP) unit. Memory access initiated by the CPUs is checked by the PMP unit. The I / O subsystem includes I / O devices, peripheral component interconnect express (PCIe) ports, and an input / output memory management unit (IOMMU). The IOPMP unit is integrated within the IOMMU. The IOMMU translates virtual addresses (VAs) into physical addresses (PAs). When an I / O device requests access to a memory address through a PCIe port, the IOMMU translates the virtual address into a physical address and sends the physical address to the IOPMP unit. The IOPMP unit then checks the physical address to determine if the I / O device's access request carries any unauthorized permissions before deciding whether to grant the request.

[0036] Since the embodiments in this application all describe memory access, the physical address will be referred to as the physical memory address thereafter.

[0037] Please see Figure 2 , Figure 2 This is a flowchart illustrating the physical memory access method provided in the embodiments of this application. Figure 1 This is applied to the IOPMP unit. For example... Figure 2 As shown, the physical memory access method includes at least the following steps S201 to S205.

[0038] Step S201: Receive a physical memory access request from the first accessing party. The physical memory access request includes a first device identifier, the target physical memory address to be accessed, and the target access permission requested. The first device identifier includes the device function number of the first accessing party in the bus structure related to the IOPMP unit.

[0039] The first accessor can be a peripheral device requesting physical memory access.

[0040] Among them, the bus structure related to the IOPMP unit is the bus structure on the SoC where the IOPMP unit is located; the device function number in the bus structure related to the IOPMP unit is used to distinguish the hardware components connected to the SoC where the IOPMP unit is located through the bus port. These hardware components are peripherals. The first access party is connected to the SoC where the IOPMP unit is located through the bus port. Therefore, the device function number of the first access party in the bus structure can accurately identify the first access party.

[0041] In some embodiments, the bus port is a PCIe port, and the first access party is a PCIe device.

[0042] In the IOPMP unit, PCIe devices are identified by their device function number on the PCIe bus. This solves the problem that the hardware-level identification mechanism, which uses source identifiers to directly represent the access source, lacks support for PCIe device function numbers and cannot be compatible with PCIe devices when configuring source identifiers.

[0043] In some embodiments, the device function number includes a Bus-Device-Function (BDF) number, which uniquely identifies the first accessing party through its BDF number in the bus structure.

[0044] In some embodiments, the device function number includes a segment-bus-device-function (SBDF) number, and the first accessing party is uniquely identified by its SBDF number in the bus structure.

[0045] For example, the SBDF number includes an 8-bit segment number, an 8-bit bus number, a 5-bit device number, and a 3-bit function number, which can accurately identify and distinguish where in the bus structure the physical memory access request comes from, thereby accurately identifying the device requesting physical memory access.

[0046] The target access permissions can be read permissions and / or write permissions for the target physical memory address.

[0047] In this step, the IOPMP unit receives the physical memory access request from the first accessing party and can parse the first device identifier, the target physical memory address to be accessed, and the target access permissions to be requested from the physical memory access request.

[0048] Step S202: Based on the configured mapping relationship between multiple device identifiers and multiple source identifiers, determine the first source identifier corresponding to the first device identifier. The multiple device identifiers include the device function numbers of multiple access parties in the bus structure, and the multiple source identifiers respectively identify multiple bus hosts or bus host groups on the bus structure.

[0049] In the mapping relationship between multiple device identifiers and multiple source identifiers, one device identifier can correspond to one or more source identifiers, and one source identifier can correspond to one or more device identifiers.

[0050] The device function numbers of multiple access parties in the bus structure can be referred to the explanation of device function numbers in the aforementioned embodiments, and will not be repeated here. A source identifier can be used to identify bus hosts or bus host groups with the same permissions (i.e., the same physical memory access permissions) in the bus structure, and a bus host group includes multiple bus hosts.

[0051] In this step, the first device identifier is used as the query keyword. Based on the mapping relationship between multiple device identifiers and multiple source identifiers, the source identifier corresponding to the first device identifier is searched among the multiple source identifiers. For ease of distinction, the source identifier corresponding to the first device identifier is referred to as the first source identifier. Since one device identifier can correspond to one or more source identifiers, one or more first source identifiers can be found based on the first device identifier.

[0052] In some embodiments, the mapping relationship between multiple device identifiers and multiple source identifiers can be stored in a register in the IOPMP unit. The first source identifier can be obtained by inputting the first device identifier into the register and querying the register. The register used to store the mapping relationship between multiple device identifiers and multiple source identifiers can be one or more.

[0053] As an example, Figure 3 This is an example diagram illustrating the mapping of device identifiers to source identifiers. For example... Figure 3 As shown, the device identifier is input into register A. Register A stores multiple mapping relationships between device identifiers and multiple source identifiers according to serial numbers #0 to #31. The corresponding source identifier is found from this mapping relationship.

[0054] Step S203: Based on the first source identifier and the target physical memory address, find the target IOPMP entry among the configured multiple IOPMP entries. The source identifier in the target IOPMP entry matches the first source identifier, and the memory address range in the target IOPMP entry includes the target physical memory address.

[0055] Among them, the IOPMP entry is a configuration item for physical memory access rules.

[0056] Each IOPMP entry may include a source identifier, a memory address range, and the access permission rules corresponding to that memory address range. When accessing physical memory addresses within that memory address range, the access party associated with the source identifier (i.e., the access party identified by the device identifier corresponding to the source identifier) ​​must comply with the access permission rules.

[0057] The access permissions specified in an IOPMP entry can include permitted access permissions and / or prohibited access permissions.

[0058] In this step, among multiple IOPMP entries, the target IOPMP entry is obtained by searching for an IOPMP entry whose source identifier matches the first source identifier and whose memory address range includes the target physical memory address. Different IOPMP entries may contain the same or different source identifiers, and the physical memory addresses in different IOPMP entries may or may not overlap. There may be more than one IOPMP entry whose source identifier matches the first source identifier and more than one IOPMP entry whose memory address range includes the target physical memory address. Therefore, the number of target IOPMP entries can be one or more.

[0059] Step S204: Perform a permission check on the target access permissions based on the target IOPMP entry, and obtain the check result.

[0060] In this step, the access permissions of the target can be checked by referring to the access permission provisions in the target IOPMP entry, and the check result can be obtained. The check result indicates that the first accessing party has the target access permission for the target physical memory address, or that the first accessing party does not have the target access permission for the target physical memory address.

[0061] Step S205: Based on the inspection results, return a physical memory access response to the first accessing party. The physical memory access response indicates whether the physical memory access request is allowed or denied.

[0062] In this step, if the check result indicates that the first accessing party has the target access permission to the target physical memory address, a physical memory access response indicating that the physical memory access request is allowed can be returned to the first accessing party; if the check result indicates that the first accessing party does not have the target access permission to the target physical memory address, a physical memory access response indicating that the physical memory access request is denied can be returned to the first accessing party.

[0063] In this embodiment, by mapping multiple device identifiers to multiple source identifiers, upon receiving a physical memory access request from a first accessor, the device identifier of the first accessor—that is, the device function number of the first accessor on the bus structure—can be mapped to the corresponding source identifier. Then, using the source identifier and the target physical address requested by the first accessor, the target IOPMP entry is queried, a permission check is performed based on the IOPMP entry, and a physical memory access response is returned to the first accessor based on the check result. Therefore, the entire scheme, by using the accessor's device function number on the structure as the device identifier and adding a mapping relationship between device identifiers and source identifiers, solves the problem that source identifiers cannot accurately identify peripherals, thus improving the accuracy of the IOPMP unit in controlling physical memory access permissions.

[0064] Below are some embodiments of the above steps.

[0065] In some embodiments, finding the target IOPMP entry among a configured set of IOPMP entries based on a first source identifier and a target physical memory address includes: determining a first memory domain identifier corresponding to the first source identifier based on a configured mapping relationship between multiple source identifiers and multiple memory domain identifiers, where each memory domain identifier identifies multiple memory domains, and each memory domain includes a list of IOPMP entries; and searching for an IOPMP entry whose memory address range includes the target physical memory address within the list of IOPMP entries contained in the first memory domain, based on the first memory domain identifier, to obtain the target IOPMP entry. Thus, on the one hand, providing corresponding memory domain identifiers for each of the multiple source identifiers allows for personalized design of memory domains for the accessors identified by the device identifiers corresponding to the multiple source identifiers, i.e., personalized configuration of physical memory access rules. On the other hand, by utilizing the mapping relationship between multiple source identifiers and multiple memory domain identifiers, performing a memory domain query first and then an IOPMP entry query improves the accuracy and efficiency of IOPMP entry lookup.

[0066] Within the multiple memory domains (MDs), each memory domain contains a list of IOPMP entries, and each IOPMP entry list contains multiple IOPMP entries.

[0067] The memory domain ID (MDID) is used to uniquely identify a memory domain.

[0068] This involves the mapping relationship between multiple source identifiers and multiple memory domain identifiers, which is equivalent to the mapping relationship between multiple source identifiers and multiple memory domains. In this mapping relationship, one source identifier can correspond to at least one memory domain identifier, and one memory domain identifier can correspond to at least one source identifier.

[0069] In this embodiment, using the first source identifier as the query keyword, and based on the mapping relationship between multiple source identifiers and multiple memory domain identifiers, the memory domain identifier corresponding to the first source identifier is queried among the multiple memory domain identifiers. For ease of distinction, the memory domain identifier corresponding to the first source identifier is called the first memory domain identifier, and the memory domain identified by the first memory domain identifier is called the first memory domain. Based on the first memory domain identifier, the first memory domain can be queried among multiple memory domains. Then, in the list of IOPMP entries contained in the first memory domain, the memory address range in each IOPMP entry is compared with the target physical memory address. The IOPMP entry whose memory address range contains the target physical memory address is determined, and this IOPMP entry whose memory address range contains the target physical memory address is the target IOPMP entry.

[0070] In one implementation, the mapping relationship between multiple source identifiers and multiple memory domain identifiers can be stored in a register in the IOPMP unit. The first memory domain identifier can be obtained by inputting the first source identifier into the register and querying the register. The register used to store the mapping relationship between the multiple source identifiers and the multiple memory domain identifiers can be one or more.

[0071] As an example, Figure 4 Example of mapping from device identifier to memory domain Figure 1 .like Figure 4 As shown, register A stores multiple device identifiers and multiple source identifiers in sequence numbers #0~#30, and register B stores multiple source identifiers and multiple memory domain identifiers in sequence numbers #0~#30. First, the device identifier is input into register A to retrieve the corresponding source identifier; then, the source identifier is input into register B to retrieve the corresponding memory domain identifier. For example, two memory domain identifiers are retrieved: MDID 0 and MDID 1; finally, the identifiers can be retrieved from multiple memory domains (…). Figure 4 Taking the memory domains identified by MDID 0 to MDID 30 as an example, the memory domain identified by MDID 0 and the memory domain identified by MDID 1 were found.

[0072] In one implementation, among multiple memory domains, there exists a memory domain configured separately for at least one of the multiple accessors. This provides a customized memory domain for the accessor; this customized memory domain is a separate memory domain, meaning it can only be mapped to by the accessor's device identifier (which corresponds to a unique source identifier, which in turn corresponds to a unique memory domain identifier). Particularly in cloud computing scenarios, this approach can customize memory domains for tenants, configuring the memory address range allocated to each tenant within the customized memory domain. This memory domain can be progressively queried using the tenant's device identifier, allowing the IOPMP unit to provide tenants with secure and independent physical address partitions for individual access, effectively improving tenant data security in cloud computing scenarios.

[0073] As an example, Figure 5 Example of mapping from device identifier to memory domain Figure 2 .like Figure 5 As shown, register A stores multiple device identifiers and multiple source identifiers in sequence numbers #0~#30, while register B stores multiple source identifiers and multiple memory domain identifiers in sequence numbers #0~#30. In a memory domain customization scenario, inputting a device identifier into register A retrieves a unique corresponding source identifier; then, inputting the source identifier into register B retrieves a unique corresponding memory domain identifier, such as MDID30; finally, in multiple memory domains ( Figure 5 Taking the memory domains identified by MDID1 to MDID130 as an example, the memory domain identified by MDID30 is found.

[0074] As an example, a system-on-a-chip (SoC) is provided with some physical address ranges at the factory. The IOPMP unit can be used to allocate one or more memory domains to configure the access permissions for these physical address ranges. These one or more memory domains are non-custom memory domains, such as... Figure 4 The memory domains identified by MDID 0 and MDID 1 are shown in the diagram. During SOC usage, customized memory domains can be provided for tenants, such as... Figure 5 The memory domain identified by MDID30 is shown.

[0075] As a further example, the IOPMP unit has a total of 32 memory domains. The factory partition occupies 2 memory domains, and the remaining 30 memory domains can be used for tenant memory domain customization.

[0076] In one implementation, the memory address range in an IOPMP entry is represented by an address mode and an address code. The address modes include a first mode, a second mode, and a third mode. In the first mode, the IOPMP entry has no address, that is, the address code in the IOPMP entry does not cover any physical memory address. In the second mode, the address code includes a base address and an address size starting from that base address to represent an address range. In the third mode, the address code indicates the address range between the previous IOPMP entry and the current IOPMP entry.

[0077] Figure 6 A flowchart illustrating the address matching process of the IOPMP unit provided in this application embodiment is shown below. Figure 6 As shown, searching for an IOPMP entry whose memory address range includes the target physical memory address in the IOPMP entry list contained in the first memory domain may include the following steps S601 to S608: Step S601: In the list of IOPMP entries contained in the first memory domain, match the memory address range in the i-th IOPMP entry with the target physical memory address. Here, i is a positive integer starting from 1.

[0078] In this step, after mapping the device identifier of the first accessor to the first source identifier, the first memory domain identifier, and the first memory domain in sequence, multiple IOPMP entries in the IOPMP entry list contained in the first memory domain can be matched with the target physical memory address in turn. During the first match, i equals 1, and i is incremented by 1 for each match, until all IOPMP entries in the IOPMP entry list contained in the first memory domain have been matched with the target physical memory address.

[0079] Step S602: Determine the address pattern in the memory address range of the i-th IOPMP entry.

[0080] If the address mode in the memory address range of the i-th IOPMP entry is the first mode, execute S605.

[0081] If the address mode in the memory address range of the i-th IOPMP entry is the second mode, execute S603.

[0082] If the address mode in the memory address range of the i-th IOPMP entry is the third mode, execute S604.

[0083] Step S603: Based on the base address in the address encoding contained in the i-th IOPMP entry and the address size starting from the base address, determine whether the memory address range in the i-th IOPMP entry contains the target physical memory address.

[0084] In this step, if the address mode in the memory address range of the i-th IOPMP entry is the second mode, it is determined whether the address range formed by the base address in the address encoding and the address size starting from the base address contains the target physical memory address. If the address range contains the target physical memory address, it is determined that the memory address range in the i-th IOPMP entry contains the target physical memory address, i.e., step S606 is executed; otherwise, it is determined that the memory address range in the i-th IOPMP entry does not contain the target physical memory address, i.e., step S605 is executed. S604, determine whether the address range between the (i-1)th IOPMP entry and the i-th IOPMP entry, indicated by the address encoding contained in the i-th IOPMP entry, contains the target physical memory address.

[0085] In this step, if the address mode in the memory address range of the i-th IOPMP entry is the third mode, the address encoding contained in the i-th IOPMP entry indicates the address range between the (i-1)-th IOPMP entry and the i-th IOPMP entry. If the address range contains the target physical memory address, it is determined that the memory address range in the i-th IOPMP entry includes the target physical memory address, i.e., step S606 is executed; otherwise, it is determined that the memory address range in the i-th IOPMP entry includes the target physical memory address, i.e., step S605 is executed. Step S605: Determine that the memory address range in the i-th IOPMP entry does not include the target physical memory address.

[0086] After step S605, step S607 can be executed.

[0087] Step S606: Determine that the memory address range in the i-th IOPMP entry contains the target physical memory address.

[0088] Step S607: Determine whether the i-th IOPMP entry is the last IOPMP entry in the list of IOPMP entries contained in the first memory domain.

[0089] If the i-th IOPMP entry is the last IOPMP entry in the list of IOPMP entries contained in the first memory domain, then proceed to step S608; otherwise, increment i by one and jump to step S601.

[0090] Step S608: Complete the matching of the list of IOPMP entries contained in the first memory domain with the target physical memory address.

[0091] For example, the first mode is the off mode in the IOPMP unit, the second mode is the napot mode in the IOPMP unit, and the third mode is the tor mode in the IOPMP unit.

[0092] In this embodiment, the IOPMP unit uses different address matching methods when the IOPMP entries are represented in different modes to match the memory address range with the target physical memory address in the physical memory access request. This improves the accuracy of address matching and thus improves the accuracy of finding the target IOPMP entry hit by the physical memory access request.

[0093] Please see Figure 7 , Figure 7 This is a flowchart illustrating the physical memory access method provided in the embodiments of this application. Figure 2 This is applied to the IOPMP unit. For example... Figure 7 As shown, the physical memory access method includes at least the following steps S701 to S706.

[0094] Step S701: Receive a physical memory access request from the first accessing party. The physical memory access request includes a first device identifier, the target physical memory address to be accessed, and the target access permission requested. The first device identifier includes the device function number of the first accessing party in the bus structure related to the IOPMP unit.

[0095] Step S702: Based on the configured mapping relationship between multiple device identifiers and multiple source identifiers, determine the first source identifier corresponding to the first device identifier. The multiple device identifiers include the device function numbers of multiple access parties in the bus structure, and the multiple source identifiers respectively identify multiple bus hosts or bus host groups on the bus structure.

[0096] Step S703: Based on the first source identifier and the target physical memory address, find the target IOPMP entry among the configured multiple IOPMP entries. The source identifier in the target IOPMP entry matches the first source identifier, and the memory address range in the target IOPMP entry includes the target physical memory address.

[0097] The implementation principles and technical effects of S701 to S703 can be referred to in the aforementioned embodiments, and will not be repeated here.

[0098] Step S704: Identify the current scene type based on the priority number in the target IOPMP entry and the set priority threshold. The current scene type is either a priority scene or a no-priority scene.

[0099] Steps S704 and S705 are one implementation of "performing a permission check on the target access permissions based on the target IOPMP entry and obtaining the check result".

[0100] Priority-based and non-priority-based scenarios represent different operating modes of the IOPMP unit, with each mode employing different permission checking strategies. In priority-based scenarios, physical memory access permissions are strictly controlled, while in non-priority-based scenarios, control is more lenient.

[0101] The priority number in the target IOPMP entry indicates the priority of the target IOPMP entry.

[0102] In this embodiment, the priority number in the target IOPMP entry can be compared with a set priority threshold to obtain a comparison result. This comparison result reflects whether the priority of the target IOPMP entry hit by the physical memory access request of the first accessor belongs to a priority scenario or a no-priority scenario. Therefore, based on the comparison result, the current scenario type can be determined, which is either a priority scenario or a no-priority scenario.

[0103] In one implementation, step S704 identifies the current scenario type based on the priority number in the target IOPMP entry and a set priority threshold. This includes: when there are multiple target IOPMP entries, obtaining the smallest target priority number from the priority numbers contained in each of the multiple target IOPMP entries (the smaller the priority number in the target IOPMP entry, the higher the priority of the target IOPMP entry); if the target priority number is less than the priority threshold, determining the current scenario type as a priority scenario; and if the target priority number is greater than or equal to the priority threshold, determining the current scenario type as a no-priority scenario. Thus, when a smaller priority number in an IOPMP entry indicates a higher priority, by comparing the smallest target priority number with the set priority threshold, it is determined whether the priority of the target IOPMP entry hit by the physical memory access request of the first accessor exceeds the set priority threshold. If so, the current scenario type is determined to be a priority scenario; otherwise, the current scenario type is determined to be a no-priority scenario, effectively improving the efficiency and accuracy of determining priority and no-priority scenarios.

[0104] Among multiple target IOPMP entries, the target IOPMP entry with the smallest target priority number is the target IOPMP entry with the highest priority among the multiple target IOPMP entries.

[0105] Step S705: Based on the permission check policy set for the current scenario type and the access permission provisions in the target IOPMP entry, perform a permission check on the target access permission and obtain the check result.

[0106] In this embodiment, when the current scenario type is a priority scenario, the target access permission is checked according to the permission check policy set for priority scenarios and the access permission provisions in the target IOPMP entry, and the check result is obtained. When the current scenario type is a non-priority scenario, the target access permission is checked according to the permission check policy set for non-priority scenarios and the access permission provisions in the target IOPMP entry, and the check result is obtained. Thus, by distinguishing between priority scenarios and non-priority scenarios, and adopting corresponding permission check policies for the finally determined scenario type, the accuracy of the IOPMP unit's permission check of the target access permission based on the target IOPMP entry is improved.

[0107] In one implementation, there are multiple target IOPMP entries. Based on the permission check policy set for the current scenario type and the access permission rules in the target IOPMP entries, a permission check is performed on the target access permissions to obtain the check result, i.e., step S705. This includes: checking whether the target access permissions violate the access permission rules in the reference IOPMP entries. In a priority scenario, the reference IOPMP entries are the IOPMP entries with the highest priority among the multiple target IOPMP entries; in a no-priority scenario, the reference IOPMP entries are all target IOPMP entries. If the target access permissions violate the access permission rules in the reference IOPMP entries, the check result is determined to be that the first accessing party does not have target access permissions to the target physical memory address; if the target access permissions do not violate the access permission rules in the reference IOPMP entries, the check result is determined to be that the first accessing party has target access permissions to the target physical memory address.

[0108] Whether the target access permissions violate the access permission provisions in the referenced IOPMP entry refers to whether the target access permissions conflict with the access permission provisions in the referenced IOPMP entry.

[0109] In this implementation, in priority scenarios, the highest-priority IOPMP entry among multiple target IOPMP entries is used as the reference IOPMP entry to determine whether the target access permission requested in the first accessor's physical memory access request violates the access permission rules in the reference IOPMP entry. If the target access permission exceeds the access permission configured in the reference IOPMP entry for the memory address range containing the target physical memory address, then it is determined that the target access permission violates the access permission rules in the reference IOPMP entry, and the check result is that the first accessor does not have the target access permission for the target physical memory address. For example, if the target access permission requests read permission, the access permission rules in the reference IOPMP entry... If read permissions are not configured in the IOPMP entry or read permissions are disabled, the target access permission violates the access permission rule, and the check result is that the first accessing party does not have read permissions to the target physical memory address. If the target access permission does not exceed the access permission rule in the reference IOPMP entry, the target access permission does not violate the access permission rule in the reference IOPMP entry, and the check result is that the first accessing party has the target access permission to the target physical memory address. For example, if the target access permission requests write permissions, but the access permission rule in the reference IOPMP entry allows write permissions, then the target access permission does not violate the access permission rule, and the check result is that the first accessing party has write permissions to the target physical memory address. Therefore, in priority scenarios, the target access permission is strictly judged based on the highest priority IOPMP entry among multiple target IOPMP entries, improving the security of physical memory access.

[0110] In this implementation, in a no-priority scenario, the reference IOPMP entry is used as all target IOPMP entries. It can be determined whether the target access permission requested in the physical memory access request of the first access party violates the access permission rules in the reference IOPMP entry, that is, the access permission rules in all target IOPMP entries. If the target access permission violates the access permission rules in all target IOPMP entries, the check result is determined to be that the first access party does not have target access permission to the target physical memory address. If the target access permission does not violate the access permission rules in any target IOPMP entry, the check result is determined to be that the first access party has target access permission to the target physical memory address.

[0111] In one implementation, after checking whether the target access permission violates the access permission provisions in the reference IOPMP entry, the physical memory access method further includes: if the target access permission violates the access permission provisions in the reference IOPMP entry, performing a reporting operation under the condition that multiple set conditions are met in sequence. The reporting operation includes reporting errors and / or reporting interruptions. The multiple set conditions include: the IOPMP unit allows the reporting operation; the reference IOPMP entry allows the reporting operation; and at least one access permission provision violated by the target access permission in the reference IOPMP entry allows the reporting operation. Thus, the error reporting / suppression mechanism and the interruption triggering / suppression mechanism are refined to the granularity of each permission in each reference IOPMP entry for permission checking, solving the problem of insufficient granularity in IOPMP unit interrupt triggering and / or error reporting, and enabling precise location of violations in cloud computing scenarios.

[0112] As an example, Figure 8 A flowchart illustrating the process of reporting errors to the IOPMP unit. (Example:) Figure 8 As shown, during the permission check, if any violation is found, no error is reported; otherwise, the next step is performed. A violation is found when checking the target's access permissions based on the reference IOPMP entry; if no violation is found, the target's access permissions violate the access permission rules in the reference IOPMP entry; if so, it is confirmed whether the IOPMP unit as a whole allows error reporting; if so, the next step is performed; otherwise, no error is reported; if the IOPMP entry currently being checked (i.e., the reference IOPMP entry) allows error reporting, if so, an error is reported or the next step is performed. Figure 8 (Taking the next step of judgment as an example), otherwise no error is reported; confirm whether the IOPMP entry being checked for the current permission allows reporting errors for the currently violating permission. If it allows, an error is reported; otherwise, no error is reported. Here, the currently violating permission refers to the permission in the IOPMP entry being checked for that conflicts with the target's access permission. If there are multiple currently violating permissions, if at least one of the currently violating permissions allows reporting errors, an error is reported; otherwise, no error is reported.

[0113] As an example, Figure 9 A flowchart illustrating the process of reporting an interrupt to an IOPMP unit. (Example:) Figure 9As shown, during the permission check, if any violation is found, no interruption is reported; otherwise, the next step is performed. A violation is found when checking the target's access permissions based on the reference IOPMP entry; if no violation is found, the target's access permissions violate the access permission rules in the reference IOPMP entry; if so, it is confirmed whether the IOPMP unit as a whole allows interruption reporting; if so, the next step is performed; otherwise, no interruption is reported; if the IOPMP entry currently being checked (i.e., the reference IOPMP entry) allows interruption reporting; if so, an interruption is reported or the next step is performed. Figure 8 (Taking the next step of judgment as an example), otherwise no interruption is reported; confirm whether the IOPMP entry being checked for the current permission allows an interruption to be reported for the currently violating permission. If it does, an interruption is reported; otherwise, no interruption is reported. Here, the currently violating permission refers to the permission in the IOPMP entry being checked for that conflicts with the target access permission. If there are multiple currently violating permissions, if at least one of the currently violating permissions allows an interruption to be reported, an interruption is reported; otherwise, no interruption is reported.

[0114] Step S706: Based on the inspection result, return a physical memory access response to the first accessing party. The physical memory access response indicates whether the physical memory access request is allowed or denied.

[0115] The implementation principle and technical effect of step S706 can be referred to the aforementioned embodiments, and will not be repeated here.

[0116] In this embodiment, based on the target IOPMP entry named in the physical memory access request of the first accessing party, the system distinguishes between a priority scenario and a non-priority scenario. In a priority scenario, a permission check strategy designed for priority scenarios is used to check the target access permissions in the physical memory access request. In a non-priority scenario, a permission check strategy designed for non-priority scenarios is used to check the target access permissions in the physical memory access request. Then, based on the check results, a physical memory access response is returned to the first accessing party. This effectively improves the accuracy of the IOPMP unit's control over physical memory access permissions and enhances the security of physical memory access.

[0117] For an example, please see Figure 10 , Figure 10 This is an example diagram of the module structure for an IOPMP unit. (Example:) Figure 10 As shown, the IOPMP unit includes a device identifier-source identifier mapping submodule 1001, a source identifier-memory domain mapping submodule 1002, an entry address matching submodule 1003, a priority judgment submodule 1004, and a permission check submodule 1005, wherein: The device identifier-source identifier mapping submodule 1001 is used to map device identifiers to source identifiers. Specifically, it can be used to determine the first source identifier corresponding to the first device identifier based on the configured mapping relationship between multiple device identifiers and multiple source identifiers. The device identifier-source identifier mapping submodule 1001 may include a register file for storing the mapping relationship between multiple device identifiers and multiple source identifiers.

[0118] The source identifier-memory domain mapping submodule 1002 is used to map source identifiers to memory domain identifiers. Specifically, it can be used to determine the first memory domain identifier corresponding to the first source identifier based on the configured mapping relationship between multiple source identifiers and multiple memory domain identifiers. The source identifier-memory domain mapping submodule 1002 may include a register file for storing the mapping relationship between the multiple source identifiers and multiple memory domain identifiers.

[0119] The entry address matching submodule 1003 is used for address matching between the memory address range in the IOPMP entry and the physical memory address in the physical memory access request. Specifically, it can be used to search for IOPMP entries whose memory address range includes the target physical memory address in the list of IOPMP entries contained in the first memory domain, based on the first memory domain identifier, to obtain the target IOPMP entry.

[0120] The priority determination submodule 1004 is used to determine whether the IOPMP entry that matches the physical memory address in the physical memory access request has a priority. Specifically, it can be used to determine whether the priority is based on the priority number in the target IOPMP entry and the set priority threshold, and the current scenario type, which is either a priority scenario or a no-priority scenario.

[0121] The permission check submodule 1005 is used to check the access permissions in physical memory access requests based on matching IOPMP entries, and ultimately allow or deny access. Specifically, it can be used to perform permission checks on target access permissions based on target IOPMP entries, obtain the check results, and return a physical memory access response to the first accessing party based on the check results.

[0122] The RISC-V protocol does not explicitly define a dynamic configuration scheme for IOPMP units. The following examples illustrate a dynamic configuration scheme for IOPMP units regarding physical memory access.

[0123] In some embodiments, the physical memory access method further includes: receiving an accessor update request, the accessor update request indicating the addition or deletion of a second accessor; configuring the ready signal at the input of the IOPMP unit to a low-level signal; performing information updates related to the second accessor; and configuring the ready signal to a high-level signal after the information updates related to the second accessor are completed. On the one hand, this accurately defines the business requirement corresponding to the dynamic configuration scheme of the IOPMP unit as the addition or deletion of accessors, making the business scenario of the dynamic configuration scheme of the IOPMP unit clearer; on the other hand, by configuring the ready signal at the input of the IOPMP unit to a low level, the data flow in the IOPMP unit is paused, avoiding interference with the normal operation of the IOPMP unit during the dynamic reconfiguration process.

[0124] As an example, Figure 11 This is an example diagram illustrating signal configuration during the dynamic reconfiguration of an IOPMP unit. (Example:) Figure 11 As shown, before dynamic reconfiguration, the software configures the ready signal at the input terminal to a low level, preventing the valid signal and the ready signal at the input terminal from interlocking (the valid signal is high but the ready signal is low). Data cannot enter the IOPMP unit, and the working data flow of the IOPMP unit is paused. After reconfiguring the IOPMP unit whose working data flow is paused (e.g., adding or deleting a visitor), the ready signal at the input terminal can be configured to a high level via a key, restoring the working data flow of the IOPMP unit.

[0125] This application also provides an IOPMP unit, which is used to execute the physical memory access method provided in any of the foregoing method embodiments.

[0126] This application also provides a chip, which includes the IOPMP unit provided in any of the foregoing embodiments.

[0127] Please see Figure 12 , Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example... Figure 12 As shown, the electronic device includes: One or more processors 1210; The memory 1220 stores one or more programs that, when executed by one or more processors 1210, cause the one or more processors 1210 to implement the physical memory access method described in any of the above embodiments.

[0128] Memory 1220, as a non-transitory network system, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory 1220 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 1220 may optionally include remotely located memories 1220 relative to processor 1210, which can be connected to processor 1210 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0129] The memory 1220 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1220 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1220 and is called and executed by the processor 1210.

[0130] The processor 1210 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0131] In some embodiments, the electronic device further includes: Input / output interfaces are used to implement information input and output; The communication interface is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). The bus transmits information between various components of the device (e.g., processor 1210, memory 1220, input / output interface, and communication interface); The processor 1210, memory 1220, input / output interface, and communication interface can communicate with each other within the device via a bus.

[0132] One embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions for performing the physical memory access method described in any of the embodiments above.

[0133] An embodiment of this application also provides a computer program product, including a computer program or computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform a physical memory access method as described in any of the above embodiments.

[0134] The system architecture and application scenarios described in this application are intended to more clearly illustrate the technical solutions of this application and do not constitute a limitation on the technical solutions provided in this application. Those skilled in the art will understand that as system architectures evolve and new application scenarios emerge, the technical solutions provided in this application are also applicable to similar technical problems.

[0135] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0136] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0137] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0138] The above description, with reference to the accompanying drawings, illustrates some embodiments of this application, but does not limit the scope of this application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of this application shall be within the scope of this application.

Claims

1. A physical memory access method, characterized in that, Applications to IOPMP units for input / output physical memory protection include: Receive a physical memory access request from a first accessor, the physical memory access request including a first device identifier, the target physical memory address to be accessed, and the target access permission requested, the first device identifier including the device function number of the first accessor in the bus structure related to the IOPMP unit; Based on the mapping relationship between multiple device identifiers and multiple source identifiers configured, the first source identifier corresponding to the first device identifier is determined. The multiple device identifiers include the device function numbers of multiple access parties in the bus structure, and the multiple source identifiers respectively identify multiple bus hosts or bus host groups on the bus structure. Based on the first source identifier and the target physical memory address, a target IOPMP entry is found among multiple configured IOPMP entries, wherein the source identifier in the target IOPMP entry matches the first source identifier, and the memory address range in the target IOPMP entry includes the target physical memory address; Based on the target IOPMP entry, perform a permission check on the target access permissions to obtain the check result; Based on the inspection results, a physical memory access response is returned to the first accessing party, indicating whether the physical memory access request is allowed or denied.

2. The method according to claim 1, characterized in that, The step of finding the target IOPMP entry among multiple configured IOPMP entries based on the first source identifier and the target physical memory address includes: Based on the configured mapping relationship between the multiple source identifiers and the multiple memory domain identifiers, the first memory domain identifier corresponding to the first source identifier is determined. The multiple memory domain identifiers respectively identify multiple memory domains, and each memory domain includes an IOPMP entry list. The first memory domain identifier is used to identify the first memory domain. Based on the first memory domain identifier, in the list of IOPMP entries contained in the first memory domain, find the IOPMP entry whose memory address range includes the target physical memory address, and obtain the target IOPMP entry.

3. The method according to claim 2, characterized in that, Among the plurality of memory domains, there exists a memory domain configured separately for at least one of the plurality of accessors.

4. The method according to any one of claims 1 to 3, characterized in that, The step of performing a permission check on the target access permissions based on the target IOPMP entry and obtaining the check result includes: Based on the priority number in the target IOPMP entry and the set priority threshold, the current scene type is identified, which is either a priority scene or a no-priority scene. Based on the permission check policy set for the current scenario type and the access permission provisions in the target IOPMP entry, a permission check is performed on the target access permission to obtain the check result.

5. The method according to claim 4, characterized in that, The step of identifying the current scene type based on the priority number in the target IOPMP entry and the set priority threshold includes: When there are multiple target IOPMP entries, the target priority number with the smallest value is obtained from the priority numbers contained in the multiple target IOPMP entries. The smaller the priority number in the target IOPMP entry, the higher the priority of the target IOPMP entry. If the target priority number is less than the priority threshold, the current scene type is determined to be the priority scene; If the target priority number is greater than or equal to the priority threshold, the current scene type is determined to be the no-priority scene.

6. The method according to claim 4, characterized in that, The target IOPMP entries are multiple. The permission check is performed on the target access permissions according to the permission check policy set for the current scenario type and the access permission rules in the target IOPMP entries, to obtain the check result, including: Check whether the target access permission violates the access permission rules in the reference IOPMP entry. In the priority scenario, the reference IOPMP entry is the IOPMP entry with the highest priority among the multiple target IOPMP entries. In the no-priority scenario, the reference IOPMP entry is all the target IOPMP entries. If the target access permission violates the access permission provisions in the referenced IOPMP entry, the check result is determined to be that the first accessing party does not have the target access permission to the target physical memory address; If the target access permission does not violate the access permission provisions in the referenced IOPMP entry, the check result is determined to be that the first accessing party has the target access permission to the target physical memory address.

7. The method according to claim 6, characterized in that, After checking whether the target access permissions violate the access permission provisions in the referenced IOPMP entry, the method further includes: If the target access permission violates the access permission provisions in the referenced IOPMP entry, a reporting operation is performed if multiple set conditions are met in sequence. The reporting operation includes reporting errors and / or reporting interruptions. The multiple preset conditions include: The IOPMP unit allows the reporting operation; The reference IOPMP entry allows the reporting operation; Furthermore, in the referenced IOPMP entry, at least one access permission provision violated by the target access permission allows the reporting operation.

8. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Receive an update request from an access party, the update request indicating the addition or deletion of a second access party; Configure the ready signal at the input of the IOPMP unit to a low level signal; Update information related to the second accessing party; After the information related to the second accessing party is updated, the ready signal is configured as a high-level signal.

9. An electronic device, characterized in that, include: One or more processors; A memory that stores one or more programs, which, when executed by one or more processors, cause the one or more processors to perform the following: The physical memory access method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the following: The physical memory access method according to any one of claims 1 to 8.

11. A computer program product, characterized in that, Includes a computer program, which, when executed by a processor, implements, for example: The physical memory access method according to any one of claims 1 to 8.

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