Chip operation parameter optimization method and device, electronic equipment and storage medium

Abstract

The invention discloses a chip operation parameter optimization method and device, electronic equipment and a readable storage medium, and belongs to the technical field of computers. The method comprises the following steps: for each operation scene of a plurality of tested terminals, obtaining calibrated power consumption data of a chip deployed in the tested terminals in the operation scene, and obtaining first power consumption distribution models respectively corresponding to a plurality of working frequency points of the chip; constructing a second power consumption distribution model corresponding to the operation scene according to the calibrated power consumption data; respectively calculating correlation parameters between the plurality of first power consumption distribution models and the second power consumption distribution model; determining a target first power consumption distribution model from the plurality of first power consumption distribution models according to correlation parameters of the first power consumption distribution models; and optimizing operation parameters of the chip according to the target first power consumption distribution model.

Description

Technical Field

[0001] This application belongs to the field of computer technology, specifically relating to a method, apparatus, electronic device, and readable storage medium for optimizing chip operating parameters. Background Technology

[0002] As mobile terminals continue to demand higher performance, lower power consumption, and lower temperature rise, the quality of the chip (SoC, System on a Chip) has become a key factor affecting user experience.

[0003] In the prior art, the chips deployed in mobile terminals have different frequency points. Each chip has a corresponding model file for each frequency point. The model file reflects some operating parameters of the chip at the corresponding frequency point. These parameters can be written into the chip so that the corresponding parameter set can be called according to the actual working frequency point during subsequent operation, thereby ensuring the normal and efficient operation of the chip.

[0004] However, in the increasingly complex operating environment of mobile terminals, this parameter configuration method is relatively rigid, has limited applicability, and affects chip performance. Summary of the Invention

[0005] The purpose of this application is to provide a method, apparatus, electronic device, and readable storage medium for optimizing chip operating parameters, which can solve the problems of relatively fixed parameter configuration methods and limited applicable scenarios in the prior art.

[0006] In a first aspect, embodiments of this application provide a method for optimizing chip operating parameters, the method comprising: For each operating scenario of the terminal under test, the calibration power consumption data of the chip deployed in the terminal under test under the operating scenario is obtained, and the first power distribution model corresponding to each of the multiple operating frequency points of the chip is obtained. There are multiple terminals under test. Based on the calibrated power consumption data, a second power distribution model corresponding to the operating scenario is constructed. Calculate the correlation parameters between multiple first power distribution models and second power distribution models respectively; Based on the relevance parameter, the target first power distribution model is determined from multiple first power distribution models; Based on the target first power consumption distribution model, optimize the chip's operating parameters.

[0007] Secondly, embodiments of this application provide a chip operating parameter optimization apparatus, the apparatus comprising: The acquisition module is used to acquire the calibration power consumption data of the chip deployed in the terminal under test under each operating scenario, and to acquire the first power distribution model corresponding to each of the multiple operating frequency points of the chip, wherein there are multiple terminals under test. The building module is used to construct a second power distribution model corresponding to the running scenario based on the calibrated power consumption data; The calculation module is used to calculate the correlation parameters between multiple first power distribution models and second power distribution models respectively; The decision module is used to determine the target first power distribution model from multiple first power distribution models based on the relevance parameter; The optimization module is used to optimize the chip's operating parameters based on the target first power consumption distribution model.

[0008] Thirdly, embodiments of this application provide an electronic device, including a processor and a memory, wherein the memory stores a program or instructions that can run on the processor, and when the program or instructions are executed by the processor, they implement the steps of the chip operating parameter optimization method of the first aspect.

[0009] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, and when the program or instructions are executed by a processor, they implement the steps of the chip operating parameter optimization method as described in the first or second aspect.

[0010] In this embodiment, for each operating scenario of the terminal under test, firstly, the actual power consumption of the chip in the terminal under test is quantitatively compared with multiple preset first power consumption distribution models for that operating scenario. Through mathematical correlation analysis, it can be accurately determined which first power consumption distribution model the chip's power consumption characteristics are closer to. Secondly, based on the target first power consumption distribution model, the actual power consumption of the chip in that operating scenario can be evaluated. If the actual power consumption of a certain chip is too high, the optimal operating parameters can be tailored for that chip. Finally, through precise optimization of the chip's operating parameters, the operating state of the chip in that operating scenario can be fundamentally improved, effectively reducing unnecessary excessive power consumption and heat generation, thereby improving the battery life of the terminal device and enhancing the overall quality and user reputation of the smart terminal product. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the steps of a chip operating parameter optimization method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a CMOS inverter circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of dynamic power consumption provided in an embodiment of this application; Figure 4 This is a schematic diagram illustrating the proportion of static power consumption and dynamic power consumption in total power consumption, provided in an embodiment of this application. Figure 5This is a flowchart illustrating the specific steps of a chip operating parameter optimization method provided in an embodiment of this application. Figure 6 This is a schematic diagram of a second power consumption distribution model provided in an embodiment of this application; Figure 7 This is a schematic diagram of an energy model data source provided in an embodiment of this application; Figure 8 This is a schematic diagram of a first power consumption distribution model body threshold provided in an embodiment of this application; Figure 9 This is a schematic diagram of a first power consumption distribution model corresponding to a frequency point provided in an embodiment of this application; Figure 10 This is a schematic diagram of the first power consumption distribution model corresponding to another frequency point provided in the embodiments of this application; Figure 11 This is a schematic diagram of a first power consumption distribution model provided in an embodiment of this application; Figure 12 This is a schematic diagram of a first cumulative distribution function provided in an embodiment of this application; Figure 13 This is a schematic diagram illustrating the goodness of fit between the independent variable x and the dependent variable y, provided in an embodiment of this application. Figure 14 This is a schematic diagram of goodness-of-fit calculation provided in an embodiment of this application; Figure 15 This is a logic block diagram of an implementation scheme for obtaining a target first power consumption distribution model provided in an embodiment of this application; Figure 16 This is a flowchart illustrating an implementation of obtaining a target first power consumption distribution model, as provided in an embodiment of this application. Figure 17 This is a schematic diagram illustrating the voltage difference before and after patching, provided in an embodiment of this application. Figure 18 This is a schematic diagram illustrating the power difference before and after patching, provided in an embodiment of this application. Figure 19 This is a schematic diagram illustrating the cumulative distribution of batch materials before and after improvement through patching, as provided in an embodiment of this application. Figure 20 This is a block diagram of a chip operating parameter optimization device provided in an embodiment of this application; Figure 21 This is a block diagram of an electronic device provided in an embodiment of this application; Figure 22 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0013] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] Before introducing the chip parameter optimization method, apparatus, electronic device, and readable storage medium provided in this application, the application scenarios involved in the various embodiments of this application will first be described. This application can be applied to chip operating parameter optimization apparatuses, electronic devices, etc.

[0015] As mobile terminals increasingly demand higher performance, lower power consumption, and lower temperature rise, the quality of a System-on-a-Chip (SoC) has become a key factor affecting user experience. Chip quality primarily depends on manufacturing and packaging design. Better chip quality can fully realize performance potential and achieve better power consumption and temperature rise performance; while poor quality may lead to abnormal dynamic and static power consumption, thus affecting the terminal's battery life and stability.

[0016] Currently, the industry commonly uses power consumption models based on static leakage current and the lowest operating voltage (Vmin) at various frequencies to indirectly evaluate the quality of a SoC, such as... Figure 4As shown. Typically, during the final test (FT) stage after chip packaging, relevant parameters are written to efuse (a one-time programmable memory that stores data by melting a metal fuse), and an Energy Model (EM) table is generated during device power-on / rebooting for CPU / GPU scheduling. Subsequently, a power consumption consistency distribution is generated for the batch of SoCs using a CPU scheduling algorithm for multiple scenarios (i.e., the usage ratio of each frequency point). If this distribution conforms to a normal (Gaussian) distribution, the power consumption consistency risk is considered controllable. Existing technologies mainly rely on this empirical judgment based on statistical distribution, which cannot objectively and quantitatively assess the chip's quality.

[0017] To address the aforementioned issues, this application provides a chip operating parameter optimization method, apparatus, electronic device, and readable storage medium. The chip compensation method provided in this application will be described in detail below with reference to the accompanying drawings and specific embodiments and application scenarios.

[0018] Figure 1 This is a flowchart illustrating the steps of a chip operating parameter optimization method provided in an embodiment of this application, as follows: Figure 1 As shown, the method may include the following steps.

[0019] Step 101: For each operating scenario of the terminal under test, obtain the calibration power consumption data of the chip deployed in the terminal under test under the operating scenario, and obtain the first power consumption distribution model corresponding to each of the multiple operating frequency points of the chip. There are multiple terminals under test.

[0020] In multiple test scenarios, several terminals under test were deployed in each scenario, and each terminal was equipped with the same model of chip. This chip supports multiple operating frequencies, meaning it can operate at different frequencies, such as running at 2500MHz at one time and at 3400MHz at another. These frequencies represent the chip's operating frequencies under different performance states.

[0021] Before a chip leaves the factory, manufacturers typically obtain its initial power consumption distribution model at different frequencies through testing. This initial power consumption distribution model measures the chip's energy consumption level at a specific operating frequency, providing a benchmark for subsequent power consumption evaluation and optimization of terminal devices.

[0022] For a specific operating frequency, a first power consumption distribution model is provided. This first power consumption distribution model reflects the probability distribution of the statistical power consumption of a batch of chips with the same rules. The horizontal axis represents the statistical power consumption, the vertical axis represents the number of chips, and the points on the model represent the number of chips with a statistical power consumption of a certain statistical power consumption on the horizontal axis.

[0023] In some embodiments, the running scenario is a heavy-load 3D game scenario, such as Game 1, Game 2, etc.

[0024] In other embodiments, the operating scenario is a high-pressure test scenario, and professional pressure testing software, such as pressure testing software 1, is used.

[0025] The calibrated power consumption data of the chips deployed in the tested terminal is divided into dynamic power consumption and static power consumption. For example... Figure 2 The complementary metal-oxide-semiconductor (CMOS) inverter circuit shown on the left has the source of the upper P-channel metal-oxide-semiconductor (PMOS) connected to the positive power supply (VDD), the drain connected to the output, and the gate connected to the input. The lower N-channel metal-oxide-semiconductor (NMOS) has the source connected to the negative power supply or ground, the drain connected to the output, and the gate connected to the input. The right side shows the timing diagrams for the input voltage vi, the output voltage vo, the current in flowing through the NMOS transistor, and the current ip flowing through the PMOS transistor. The dynamic power consumption of a chip consists of two parts: one part is the power consumption Pc consumed during charging and discharging of the load capacitor; the other part is the conduction power consumption P consumed by the metal-oxide-semiconductor field-effect transistor (MOS) during the short-term simultaneous conduction process of the transistor. T The calculation formula for power consumption Pc, obtained from formulas (1) and (2), is shown in formula (3). Power consumption P T The calculation formula is shown in formula (4).

[0026]

[0027] Where C L For all load capacitors at the output terminal, VDD represents the power supply voltage, vo represents the output voltage, and in i represents the current flowing through the NMOS transistor. p This represents the current flowing through the PMOS transistor, and T represents the time period.

[0028] like Figure 3 The graphical explanation of dynamic power consumption represents the threshold voltage at which the NMOS transistor turns on. The threshold voltage representing the turn-on of the PMOS transistor is given when the following relationship is satisfied:

[0029] Q1 and Q2 are both turned on simultaneously, resulting in a momentary on-current iq. CPD is the power dissipation capacitor; its specific value is usually provided by the chip manufacturer. The total dynamic power dissipation is represented by P. D express.

[0030]

[0031] Static power consumption is typically the static current under a specified power supply. Because one MOSFET in a CMOS structure is always off in the static state, the resulting leakage current is extremely small. Figure 4 As shown in the figure, the horizontal axis represents the chip's operating frequency, and the vertical axis represents the chip's power consumption. The orange and gray histograms represent static power consumption and dynamic power consumption, respectively, and the blue curve represents the proportion of static power consumption in the total power consumption. The figure shows that at high frequencies, static power consumption accounts for less than 7%, which is usually negligible. Because the static power consumption is relatively low, only the chip's dynamic power consumption is typically considered. The tested terminal is run under the same conditions, and the dynamic power consumption at each operating frequency is collected as calibration power consumption data.

[0032] The first power consumption distribution model is a standard model formed by chip manufacturers based on the measured power consumption data of the chip when the chip leaves the factory. Each operating frequency point of the chip has a corresponding first power consumption distribution model.

[0033] Step 102: Based on the calibrated power consumption data, construct a second power distribution model corresponding to the operating scenario.

[0034] In this embodiment of the application, probability distribution fitting is performed on all the calibration power consumption data of the chips deployed in the terminal under test.

[0035] Typically, the power consumption of individual chips operating at the same frequency follows or approximately follows a normal distribution (Gaussian distribution). Therefore, a normal distribution model N(μ,σ²) can be uniquely determined using a mean (μ) and a standard deviation (σ). This model is the second power consumption distribution model for that operating scenario. The second power consumption distribution model reflects the probability distribution of chip power consumption in a specific actual operating scenario, such as when the terminal is running a specific game or a specific stress test software. The horizontal axis represents the normalized power value, and the vertical axis represents the number of chips. The points on the model represent the number of chips whose normalized power value is a certain normalized power value on the horizontal axis. Subsequently, the second model can be used as a benchmark for chip power consumption in the operating scenario, and can be compared with multiple first power consumption distribution models to find the closest first power consumption distribution model.

[0036] Step 103: Calculate the correlation parameters between multiple first power distribution models and second power distribution models respectively.

[0037] In this embodiment, the similarity between the first power consumption distribution model and the second power consumption distribution model is evaluated at multiple frequency points of the chip to obtain the first power consumption distribution model that is most similar to the second power consumption distribution model. Here, the "relevance parameter" mathematically refers to a measure of the difference or similarity between two probability distributions. By quantifying the similarity between the second power consumption distribution model and the first power consumption distribution model through correlation, this quantification can be used to find the model most similar to the second power consumption distribution model from multiple first power consumption distribution models as the target first power consumption distribution model.

[0038] In some embodiments, the Kullback-Leibler divergence (KL divergence) between two power distribution models can be calculated. The KL divergence accurately quantifies the degree of difference between one distribution (the second power distribution model) and another distribution (the first power distribution model). The smaller the KL divergence value, the more similar the two distributions are.

[0039] In some embodiments, the Pearson coefficient between two power distribution models can be calculated. The Pearson correlation coefficient can be used to measure the degree of linear correlation between variables. The correlation coefficient ranges from -1 to 1. The closer the absolute value is to 1, the stronger the correlation between the two variables; the closer the absolute value is to 0, the weaker the correlation between the two variables. Generally, the correlation between variables is judged by the following value range, as shown in Table 1 below:

[0040] Table 1 Step 104: Determine the target first power distribution model from multiple first power distribution models based on the correlation parameter.

[0041] In some embodiments, multiple KL divergence values ​​are obtained in step 103, and each divergence value corresponds to the first power distribution model at a certain operating frequency. The smallest KL divergence value among these multiple KL divergence values ​​is found, and the first power distribution model corresponding to the smallest KL divergence value is the target first power distribution model.

[0042] In some embodiments, multiple Pearson coefficients are obtained in step 103, and each Pearson coefficient corresponds to a first power distribution model at an operating frequency. The largest Pearson coefficient among the multiple Pearson coefficients is found, and the first power distribution model corresponding to the largest Pearson coefficient is the target first power distribution model.

[0043] Assumptions: There are three first power distribution models a, b, and c, and a determined second power distribution model x. Calculate the KL divergence coefficients of a, b, c, and x. The KL divergence value between ax is 0.2, between bx is 0.5, and between cx is 0.7. Since the KL divergence value between ax is the smallest, it indicates that the first power distribution model a is most similar to the second power distribution model x. Therefore, the first power distribution model a is determined as the target first power distribution model.

[0044] Step 105: Optimize the chip's operating parameters based on the target first power consumption distribution model.

[0045] In some embodiments, chip operating parameters can be optimized through software patches. Based on a target first power consumption model, a software patch is generated targeting the operating system kernel or underlying firmware to optimize the chip's operating parameters. This patch can be a write operation instruction targeting a specific register of the chip's power management unit (PMIC), dynamically and subtly adjusting the voltage value sent to the CPU core. For example, if a chip's original operating voltage at a 2500MHz operating frequency is 656mV, after the patch is applied, the original voltage changes from 656mV to 562mV.

[0046] In some embodiments, the frequency-voltage correspondence table (DVFS table) loaded by the chip driver can be directly modified. Based on the target first power consumption model, the loading voltage corresponding to each frequency in the frequency-voltage correspondence table loaded by the chip driver is modified to optimize the chip operating parameters.

[0047] In summary, in this embodiment, for each operating scenario of the terminal under test, firstly, the actual power consumption of the chip in the terminal under test can be quantitatively compared with multiple preset first power consumption distribution models. Through mathematical correlation analysis, it can be accurately determined which first power consumption distribution model the chip's power consumption characteristics are closer to. Secondly, based on the target first power consumption distribution model, the actual power consumption of the chip can be evaluated. If the actual power consumption of a certain chip is too high, the optimal operating parameters can be tailored for that chip. Finally, through precise optimization of the chip's operating parameters, the chip's operating state can be fundamentally improved, effectively reducing unnecessary excessive power consumption and heat generation, thereby improving the battery life of the terminal device and enhancing the overall quality and user reputation of the smart terminal product.

[0048] Figure 5 This is a flowchart illustrating the specific steps of a chip operating parameter optimization method provided in this application embodiment. See also... Figure 5 The method may include the following steps.

[0049] Step 201: For each operating scenario of the terminal under test, obtain the calibration power consumption data of the chip deployed in the terminal under test under the operating scenario, and obtain the first power distribution model corresponding to each of the multiple operating frequency points of the chip. There are multiple terminals under test.

[0050] For details, please refer to step 101 above; it will not be repeated here.

[0051] Step 202: Based on the calibrated power consumption data, construct a second power distribution model corresponding to the operating scenario.

[0052] In this embodiment, the terminal under test can be an electronic device such as a mobile phone, smart wearable device, or tablet computer. The mobile phone under test has a mass-produced and stable software version installed. The calibrated power consumption data is obtained through the power consumption-related parameters preset in the software version.

[0053] A second power consumption distribution model is constructed based on the calibrated power consumption data of the chips deployed in all the tested mobile phones.

[0054] like Figure 6 The figure shows the actual second power consumption distribution model generated when 30,000 mobile phones are running Game 1.

[0055] For example, 30,000 mobile phones can be used as the test phones, and each phone can obtain calibration power consumption data under a certain operating scenario, resulting in a total of 30,000 calibration power consumption data. The probability distribution of the 30,000 calibration power consumption data can then be fitted.

[0056] The 30,000 calibrated power consumption data of chips of the same specification typically follow or approximately follow a normal distribution (Gaussian distribution). Therefore, a normal distribution model N(μ,σ²) can be uniquely determined using a mean (μ) and a standard deviation (σ). This model is the second power consumption distribution model in the operating scenario.

[0057] Optionally, step 202 may specifically include: Sub-step 2021: Obtain the frequency point ratio of the terminal under test in the operating scenario and the energy model (EM) of each frequency point of the chip. The frequency point ratio represents the percentage of the chip's working time at a frequency point relative to the chip's total working time, and the energy model of each frequency point represents the power consumption of the chip when working at the corresponding frequency point. Tools like Perfdog can be used to obtain the frequency distribution of the chips deployed in the tested mobile phone. The frequency distribution of each chip in a specific scenario (game scenario, stress test scenario, etc.) can be obtained and stored in the software version for later retrieval. like Figure 7 As shown, based on the pre-written chip hardware information, the EM (Electronic Module) can be generated and obtained after the phone powers on / reboots. Generally, chip manufacturers will provide public EMs in the phone's software system. Therefore, the public EMs for each frequency point of the chip deployed in the tested phone can be obtained using adb commands, serving as the EMs for each frequency point of the chip.

[0058] Sub-step 2022: Based on the frequency point ratio and the energy model of each frequency point, calculate and generate the normalized power value of the terminal under test in the operating scenario; In a specific scenario, the normalized power value can be obtained based on the frequency ratio of each frequency point and the EM that represents the power consumption of each frequency point.

[0059] For example, in a scenario where 30,000 tested mobile phones are running Game 1, the normalized power values ​​for 30,000 mobile phones in the Game 1 scenario are calculated based on the percentage of running time at 2500MHz, 3400MHz, and 1800MHz and the corresponding EM data at 2500MHz, 3400MHz, and 1800MHz.

[0060] Sub-step 2023: Generate a second power consumption distribution model based on the normalized power values ​​of multiple tested terminals.

[0061] For example, we obtain 30,000 normalized power values ​​for game 1 scenarios. These 30,000 normalized power values ​​typically follow or approximately follow a normal distribution. By fitting the probability distribution of these 30,000 normalized power values, we can obtain a second power consumption distribution model.

[0062] Optionally, sub-step 2022 may specifically include: Sub-step 20221: Calculate the product of the energy model of each frequency point of the chip and the corresponding frequency point percentage.

[0063] Sub-step 20222: Sum the products of the energy models of each frequency point of the chip and the corresponding frequency point percentages to obtain the normalized power value.

[0064] For example, in the game scenario where the tested phone is running Game 1, the runtime percentages of 2500MHz, 3400MHz, and 1800MHz are 60%, 30%, and 10%, respectively. The EM values ​​for 2500MHz, 3400MHz, and 1800MHz are 1000, 1500, and 800, respectively. Multiplying 1000 by 60%, 1500 by 30%, and 800 by 10%, and summing these three products, we obtain the normalized power value of 1130 for the tested phone running Game 1.

[0065] Step 203: Calculate the correlation parameters between multiple first power distribution models and second power distribution models respectively; For details, please refer to step 103 above; it will not be repeated here.

[0066] Step 204: Traverse the correlation parameters. When the correlation parameter encountered is greater than the preset correlation threshold, determine the first power consumption distribution model corresponding to the correlation parameter as the target first power consumption distribution model.

[0067] A relevance threshold is a pre-defined threshold value that serves as a criterion to distinguish between "sufficiently relevant" and "insufficiently relevant". This threshold is typically determined based on historical data testing, experience, or the expected level of confidence. For example, it could be set to 0.8 (assuming the relevance parameter ranges from 0 to 1), meaning that a model is considered reliable and usable only if its match to the current state exceeds 80%.

[0068] After the correlation threshold is set, the traversal process is started, and the correlation parameter is traversed in a loop. The traversed correlation parameter is compared with the preset correlation threshold. If the correlation parameter is greater than or equal to the preset correlation threshold, the model corresponding to the correlation parameter is determined as the target first power distribution model.

[0069] Typically, once the first model that meets the criteria is found, the traversal loop can be broken immediately to improve efficiency, because this means that a usable and good enough model has been found.

[0070] If the relevance parameter is less than the preset relevance threshold, the loop continues to check the next relevance parameter.

[0071] If none of the relevance parameters exceed the preset relevance threshold after iterating through all parameters, an exception handling mechanism is needed. For example, select the model with the highest relevance as the "suboptimal solution," or use a default, general power consumption model as the target primary power consumption distribution model.

[0072] For example, suppose the chip in the tested mobile phone has a first power consumption distribution model corresponding to three frequency points: Model 1: Power consumption distribution model at 2500MHz frequency, and the correlation parameter P1 of the second power consumption distribution model is 0.5.

[0073] Model 2: The power consumption distribution model at 3400MHz frequency point has a correlation parameter P2 of 0.86 with the second power consumption distribution model.

[0074] Model 3: Power consumption distribution model at 1800MHz frequency, and the correlation parameter P3 of the second power consumption distribution model is 0.1.

[0075] Current scenario: The tested phone is running game 1.

[0076] The preset relevance threshold is 0.85.

[0077] Execution process: Iterate to the relevance parameter P1. Since P1 is 0.5, and 0.5 < 0.85, skip it.

[0078] When we reach the relevance parameter P2, since P2 is 0.85 and 0.86 > 0.85, the condition is met, so we stop iterating.

[0079] Model 2 is selected as the target first power consumption distribution model.

[0080] Optionally, the correlation parameter is the Pearson correlation coefficient, and the correlation threshold is 0.85.

[0081] Pearson correlation coefficient definition:

[0082] in cov (X,Y) represents the covariance of two sets X and Y, and S represents the standard deviation of sets X and Y. and These are the means of set X and set Y, respectively.

[0083] In this embodiment of the application, the second power distribution model can be used as variable X, and the first power distribution model can be used as variable Y.

[0084] The average value of all power consumption data in the second power distribution model is obtained. The average value of all power consumption data in the first power consumption distribution model is obtained. .

[0085] The covariance of X and Y can be calculated using Formula 7.

[0086] According to Formula 8, the variance of the second power distribution model and the variance of the first power distribution model can be obtained respectively.

[0087] Then, according to Formula 6, the Pearson correlation coefficients of the second power distribution model and the first power distribution model are obtained.

[0088] Step 205: Optimize the chip's operating parameters based on the target first power consumption distribution model.

[0089] This step can be referred to as step 105 above, and will not be repeated here.

[0090] Optionally, step 205 may specifically include: Sub-step 2051: Obtain the standard deviation of the target first power consumption distribution model; The target first power consumption distribution model conforms to or approximates a normal distribution, and the standard deviation of the target first power consumption distribution model can be obtained based on the fitted normal distribution.

[0091] Alternatively, we can use all the sample data from the target first power distribution model to first calculate the mean of the samples, and then calculate the variance of the samples. The standard deviation is the arithmetic square root of the variance.

[0092] Sub-step 2052: The statistical power consumption value corresponding to the product of the standard deviation and the preset multiple in the target first power consumption distribution model is used as the physical threshold. For example, such as Figure 8 As shown, X is the mean of the target first power consumption distribution model, which is set to 550. The preset multiplier can be set to 3. Let the standard deviation of the target first power consumption distribution model be 130, then X+3 In the first power consumption distribution model, the corresponding statistical power consumption value is 940, so the physical threshold is 940.

[0093] Sub-step 2053 identifies chips whose measured power consumption in the operating scenario is greater than or equal to the physical quality threshold as chips to be optimized. For example, if a chip has a power consumption of 1000, then because 1000 > 940, the chip is identified as a chip to be optimized.

[0094] Sub-step 2054: Send the preset register value to the terminal under test where the chip to be optimized is deployed, so that the terminal under test can write the register value into the control register of the chip to be optimized. The register value is used to control the chip to be optimized to reduce the operating voltage.

[0095] Based on the formulas or mapping tables in the chip's official technical documentation and the target voltage value, calculate the specific value that needs to be written to the register.

[0096] In some embodiments, the host computer establishes a physical connection with the terminal under test via a USB-to-serial adapter, Ethernet, or a dedicated debugger. Appropriate debugging or communication software (such as a serial port assistant or a custom test script) is launched on the host computer to ensure a stable connection.

[0097] The host computer sends this preset register value to the terminal under test through the established communication link.

[0098] After receiving the preset register value, the terminal under test calls the underlying driver or directly performs memory-mapped I / O operations to write the parsed data value to the corresponding register address.

[0099] The power management unit or clock control unit inside the chip monitors the value of the control register in real time.

[0100] Once the register value changes, the hardware circuitry will respond immediately and adjust the operating voltage output to the chip core.

[0101] Optionally, after step 204, the following may also be included: Step A1: Generate a first cumulative distribution function based on the first power consumption distribution model. The first cumulative distribution function is a function of the target probability value with respect to the statistical power consumption. The target probability value is the probability that the actual power consumption of the chip is less than the statistical power consumption. The horizontal axis of the first cumulative distribution function can be the statistical power consumption, and the vertical axis of the first cumulative distribution function can be the target probability value, that is, the probability value that the actual power consumption of the chip is less than the statistical power consumption. like Figure 9 As shown, this is the first power consumption distribution model of the chip deployed in the terminal under test at a working frequency of 2500MHz.

[0102] like Figure 10 The figure shows the first power consumption distribution model of the chip deployed in the terminal under test at a working frequency of 3400MHz.

[0103] by Figure 9 Taking the 2500MHz operating frequency as an example, the power consumption distribution shows two centers, with the one on the right being the secondary center. The number of chips in the secondary center accounts for no more than 10% of the total number of chips. Figure 9For chips with power consumption exceeding 1635 MHz that exhibit abnormal characteristics, i.e., after removing the sub-center portion, the first power distribution model at a 2500MHz operating frequency point conforms to a normal distribution is obtained, such as... Figure 11 As shown.

[0104] according to Figure 11 The first power consumption distribution model corresponding to the 2500MHz operating frequency point yields the following results: Figure 12 The first cumulative distribution function is shown. The horizontal axis of the first cumulative distribution function represents the statistical power consumption, and the vertical axis represents the probability that the actual power consumption of the chip is less than the statistical power consumption.

[0105] For example, in the first cumulative distribution function corresponding to the 2500MHz operating frequency, it can be seen that the probability of the chip's actual power consumption being less than 1492 is 50%, and the probability of the chip's actual power consumption being less than 1610 is 99%.

[0106] Step A2: Select at least a portion of the chips as the first chip according to the first cumulative distribution function; Taking the first cumulative distribution function corresponding to the 2500MHz operating frequency as an example, a chip with a power consumption of 1492 kW corresponding to a 50% probability and a chip with a power consumption of 1610 kW corresponding to a 99% probability can be selected as the first chip. It should be noted that there may be multiple chips with a power consumption of 1492 kW corresponding to a 50% probability, and similarly, there may be multiple chips with a power consumption of 1610 kW corresponding to a 99% probability. All of these chips can be used as the first chip.

[0107] Step A3: Based on the power consumption data of the first chip, verify the target first power consumption distribution model and obtain the verification results.

[0108] The target first power consumption distribution model is a theoretical chip power consumption distribution model fitted by similarity judgment in step 204. It needs to be tested by the actual power consumption data of the first chip. The hypothesis testing method commonly used in statistics can be used for testing.

[0109] If the verification result is successful, proceed to step 205 in step A4.

[0110] The verification was successful, indicating that the target first power consumption distribution model can well characterize the actual power consumption distribution of a batch of chips and can be used to identify chips with excessive actual power consumption.

[0111] Step A5: If the verification result is not passed, remove the correlation parameters of the target first power consumption distribution model from multiple correlation parameters and return to step 204.

[0112] The verification failed, indicating that the target first power consumption distribution model is not sufficiently correlated with the actual power consumption distribution of the chip. In other words, there is a large deviation between the model and the actual power consumption data, and it cannot be used to identify chips with excessively high actual power consumption.

[0113] From multiple correlation parameters, the correlation parameters of the target first power consumption distribution model are extracted, and then step 304 is performed to find the target first power consumption distribution model again.

[0114] Optionally, step A3 may specifically include: Sub-step A31: Obtain the measured power consumption data of the first chip in the operating scenario; In some embodiments, the measured power consumption data of the chip deployed in the terminal under test can be obtained by capturing logs using software.

[0115] In some embodiments, the measured power consumption data of the chip deployed in the terminal under test can be obtained by using the commonly used "dummy battery" method.

[0116] Sub-step A32: Calculate the goodness-of-fit value between the measured power consumption data set of the first chip and the first cumulative distribution function; Goodness of fit (R) 2 R square, also called the determination coefficient, is the square of the correlation coefficient R (between -1 and 1, the closer to -1, the more negative the correlation, and vice versa). It is between 0 and 1. The larger the value, the better the linear regression model fits the actual data. When this value is greater than 0.8, it indicates a strong positive correlation.

[0117] R 2 definition:

[0118] Among them, dependent variable Represents actual data. Points on the regression curve (which can be obtained using the least squares method) represent the points on the regression curve. This represents the average of all actual data.

[0119] like Figure 13 As shown, the goodness of fit between the independent variable x and the dependent variable y is illustrated.

[0120] In this embodiment of the application, the set Y{ is constructed using the measured power consumption data set of the first chip. … }

[0121] As in step A2, the first chip corresponds to multiple probability values ​​on the vertical axis in the first cumulative distribution function, and these probability values ​​correspond to multiple calibration power consumption data on the horizontal axis. These multiple calibration power consumption data form a set X{ …}

[0122] in the formula and These represent the means of X and Y, respectively.

[0123] According to Formula 11, substituting the data from sets X and Y, we can obtain... The value of .

[0124] Will Substituting the value into formula 12, we can obtain... The value of .

[0125] Will and Substituting the value into formula 10, we can obtain... The value of .

[0126] Then, based on all elements of set Y and... Substituting the value into formula 9 yields the following result. .

[0127] Taking game scenario 1 as an example, and the target first distribution function of the chip at frequency 2500MHz as an example, 6 first chips are selected, and the specific values ​​are shown in Table 2 below.

[0128]

[0129] Table 2 Figure 14 The calculated goodness-of-fit values =0.8688.

[0130] In sub-step A33, if the goodness-of-fit value is greater than or equal to the preset goodness-of-fit threshold, the verification result is determined to be passed.

[0131] For example, the preset goodness-of-fit threshold is 0.8, and the calculated goodness-of-fit value is... =0.8688. Since 0.8688 > 0.8, the verification is successful, indicating that the measured power consumption data of the first chip conforms to the target first power consumption model.

[0132] Optionally, step A2 may specifically include: Sub-step A21: Select multiple probability values ​​from the first cumulative distribution function. The probability values ​​include the median of the range of probability values ​​and the probability values ​​in the range of probability values ​​that are greater than a preset probability threshold. The probability value ranges from [0, 100%].

[0133] For example, the preset probability threshold can be set to 90%.

[0134] Taking the first cumulative distribution function corresponding to the 2500MHz operating frequency as an example, you can choose a probability of 50% or 94%.

[0135] Sub-step A22: Select the curve that lies in the first cumulative distribution function and the target statistical power consumption that corresponds to the probability value; Taking the first cumulative distribution function corresponding to the 2500MHz operating frequency as an example, the target statistical power consumption corresponding to a 50% probability is 1492, and the target statistical power consumption corresponding to a 94% probability value is 1427.

[0136] Sub-step A23: Select the chip whose calibrated power consumption is equal to the target statistical power consumption as the first chip.

[0137] Taking 30,000 mobile phones under test as an example, the EM values ​​of each frequency point of the chips deployed in the 30,000 mobile phones are obtained from the 30,000 mobile phones through adb commands. The chip whose EM value is equal to the target statistical power consumption value obtained in step A22 is taken as the first chip.

[0138] Taking game scenarios as an example, Figure 15 A logic block diagram for obtaining the target first power consumption distribution model.

[0139] First, the percentage of each frequency point in the operating scenario and the energy model data of each frequency point of the chip are obtained from the terminal under test. The percentage of the frequency point represents the percentage of the chip's working time at a frequency point relative to the chip's total working time, and the energy model of each frequency point represents the power consumption of the chip when working at the corresponding frequency point. Then, based on the percentage of the frequency point and the energy model of each frequency point, the normalized power value of the terminal under test in the operating scenario is calculated and generated. Then, based on the normalized power value of the terminal under test in the operating scenario, the second power consumption distribution model is obtained. Finally, the target first power consumption distribution model can be obtained by combining the first power consumption distribution model and judging the similarity.

[0140] Figure 16 The implementation flowchart for obtaining the target first power distribution model.

[0141] Taking Game 1 as an example, a software patch (by modifying the corresponding registers to change the CPU voltage) can be applied to the abnormally high CPU voltage of the chip to appropriately reduce the voltage and improve the situation. Taking 2500MHz as an example, the actual power consumption of two poorly performing chips was measured, and the differences before and after updating the EM patch are shown in Table 3 below:

[0142] Table 3 Figure 17 The diagram shows the voltage difference before and after the patch. It can be seen that the operating voltage of the chip at different frequencies is reduced after the patch.

[0143] Figure 18The diagram illustrates the power difference before and after the patch, showing that the power consumption of the chip decreased at different frequencies after the patch.

[0144] Figure 19 By comparing the cumulative distribution of batch materials before and after patching improvements, it can be found that the number of chips with higher power consumption is significantly reduced in the improved batch.

[0145] In summary, in this embodiment, firstly, for each operating scenario of the terminal under test, the power consumption data of the chip deployed in the terminal under test under operating scenario is obtained, and the first power consumption distribution model corresponding to each of the chip's multiple operating frequency points is obtained. Secondly, based on the power consumption data, a second power consumption distribution model corresponding to the operating scenario is constructed. Then, the correlation parameters between the multiple first power consumption distribution models and the second power consumption distribution model are calculated respectively. Next, the correlation parameters are traversed, and when the traversed correlation parameters are greater than a preset correlation threshold, the first power consumption distribution model corresponding to the traversed correlation parameters is determined as the target first power consumption distribution model. Then, the measured power consumption data of the first chip can be used to verify the target first power consumption distribution model. Finally, the chip's operating parameters are optimized based on the target first power consumption distribution model. The usage ratio of each CPU frequency point varies greatly in different scenarios of mobile terminals. Through the method of this embodiment, for a specific terminal operating scenario, a chip target first power consumption distribution model that fits the operating scenario very well can be found. Using the chip target first power consumption distribution model, a chip with poor performance can be identified in a batch of chips, and the chip's power consumption can be adjusted by modifying the chip's operating parameters, thereby improving the overall user experience in terms of battery life and temperature rise.

[0146] The chip operating parameter optimization method provided in this application can be executed by a chip operating parameter optimization system or a chip operating parameter optimization device. This application uses an example of a chip operating parameter optimization device executing the chip operating parameter optimization method to illustrate the chip operating parameter optimization device provided in this application.

[0147] Figure 20 This application provides a chip operating parameter optimization device, such as... Figure 20 As shown, the chip operating parameter optimization device includes: The acquisition module 301 is used to acquire, for each operating scenario of the terminal under test, the calibration power consumption data of the chip deployed in the terminal under test under the operating scenario, and the first power distribution model corresponding to each of the multiple operating frequency points of the chip, wherein there are multiple terminals under test. The construction module 302 is used to construct a second power distribution model corresponding to the running scenario based on the calibration power consumption data; Calculation module 303 is used to calculate the correlation parameters between multiple first power distribution models and second power distribution models respectively; Decision module 304 is used to determine the target first power distribution model from multiple first power distribution models based on the relevance parameter; The optimization module 305 is used to optimize the chip's operating parameters based on the target first power consumption distribution model.

[0148] Optionally, the device may also include: The generation module is used to generate a first cumulative distribution function based on a first power consumption distribution model; the first cumulative distribution function is the probability value that the actual power consumption of the chip is less than the statistical power consumption, and is a function of the statistical power consumption. The selection module is used to select at least a portion of the chips as the first chip based on a first cumulative distribution function; The verification module is used to verify the target first power distribution model based on the power consumption data of the first chip and obtain the verification result. The first routing module is used to execute the optimization module 305 if the verification result is successful. The second routing module is used to remove the correlation parameters corresponding to the target first power consumption distribution model from multiple correlation parameters when the verification result is unsuccessful, and then return to the execution decision module 304.

[0149] Optionally, the verification module may specifically include: The first verification submodule is used to obtain the measured power consumption data of the first chip in the operating scenario. The second verification submodule is used to calculate the goodness-of-fit value between the set of measured power consumption data of the first chip and the first cumulative distribution function; The third verification submodule is used to determine the verification result as passed if the goodness-of-fit value is greater than or equal to the preset goodness-of-fit threshold.

[0150] Optionally, the selected module may specifically include: The first selection submodule is used to select multiple probability values ​​from the first cumulative distribution function. The probability values ​​include the median of a preset value range and at least one of the probability values ​​in the preset value range that are greater than a preset probability threshold. The second selection submodule is used to select the curve that is in the first cumulative distribution function and the target statistical power consumption corresponding to the probability value; The third selection submodule is used to select the chip whose calibrated power consumption is equal to the target statistical power consumption as the first chip.

[0151] Optionally, decision module 304 may specifically include: The traversal submodule is used to traverse the relevance parameters. When the traversed relevance parameter is greater than the preset relevance threshold, the traversal is exited, and the first power distribution model corresponding to the relevance parameter is determined as the target first power distribution model.

[0152] Optionally, the building module 302 may specifically include: The first construction submodule is used to obtain the proportion of each frequency point of the terminal under test in the operating scenario and the energy model of each frequency point of the chip. The frequency point proportion represents the percentage of the chip's working time at a frequency point to the total working time of the chip, and the energy model of each frequency point represents the power consumption of the chip when working at the corresponding frequency point. The second construction submodule is used to calculate and generate the normalized power value of the terminal under test in the operating scenario based on the frequency point ratio and the energy model of each frequency point. The third construction submodule is used to generate a second power consumption distribution model based on the normalized power values ​​of multiple tested terminals.

[0153] Optionally, the second build submodule may specifically include: The first building unit is used to calculate the product of the energy model of each frequency point of the chip and the corresponding frequency point percentage. The second building unit is used to sum the products of the energy models of each frequency point of the chip and the corresponding frequency point proportions to obtain the normalized power value.

[0154] Optionally, the optimization module 305 may specifically include: The first optimization submodule is used to obtain the standard deviation of the target first power consumption distribution model; The second optimization submodule is used to take the power consumption value corresponding to the product of the standard deviation and the preset multiple in the target first power consumption distribution model as the quality threshold. The third optimization submodule is used to identify chips whose measured power consumption data in the operating scenario is greater than or equal to the physical threshold as chips to be optimized. The fourth optimization submodule is used to send the preset register value to the terminal under test where the chip to be optimized is deployed, so that the terminal under test can write the register value into the control register of the chip to be optimized. The register value is used to control the chip to be optimized to reduce the operating voltage.

[0155] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0156] Optionally, such as Figure 21 As shown, this application embodiment also provides an electronic device 700, including a processor 701 and a memory 702. The memory 702 stores a program or instructions that can run on the processor 701. When the program or instructions are executed by the processor 701, they implement the various steps of the above-mentioned chip operating parameter optimization and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0157] It should be noted that the electronic devices in the embodiments of this application include the aforementioned mobile electronic devices and non-mobile electronic devices.

[0158] Figure 22 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0159] The electronic device 800 includes, but is not limited to, components such as: radio frequency unit 801, network module 802, audio output unit 803, input unit 804, sensor 805, display unit 806, user input unit 808, interface unit 808, memory 809, and processor 810.

[0160] Those skilled in the art will understand that the electronic device 800 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 810 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 12 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0161] The processor 810 is used to acquire, for each operating scenario of the terminal under test, the calibration power consumption data of the chip deployed in the terminal under test under the operating scenario, and the first power distribution model corresponding to each of the multiple operating frequency points of the chip; construct a second power distribution model corresponding to the operating scenario based on the calibration power consumption data; calculate the correlation parameters between the multiple first power distribution models and the second power distribution model respectively; determine the target first power distribution model from the multiple first power distribution models based on the correlation parameters of the first power distribution model; and optimize the operating parameters of the chip based on the target first power distribution model.

[0162] In this embodiment, firstly, for each operating scenario of the terminal under test, the actual power consumption performance of a single chip under test can be quantitatively compared with a preset standard model representing different quality levels. Through mathematical correlation analysis, it can be accurately determined which first power consumption distribution model the chip's power consumption characteristics are closer to. Secondly, based on the target first power consumption distribution model, the actual power consumption performance of the chip can be evaluated. If the actual power consumption of a chip is located at a relatively high point in the target first power consumption model, the optimal operating parameters can be tailored for that chip, avoiding the problem of some chips having excessively high power consumption under uniform parameters. Finally, through precise optimization of the chip's operating parameters, the chip's operating state can be fundamentally improved, effectively reducing unnecessary excessive power consumption and heat generation, thereby improving the battery life of the terminal device and enhancing the overall quality and user reputation of the smart terminal product.

[0163] It should be understood that, in this embodiment, the input unit 804 may include a graphics processing unit (GPU) 8041 and a microphone 8042. The GPU 8041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 806 may include a display panel 8061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 807 includes at least one of a touch panel 8071 and other input devices 8072. The touch panel 8071 is also called a touch screen. The touch panel 8071 may include two parts: a touch detection device and a touch controller. Other input devices 8072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0164] The memory 809 can be used to store software programs and various data. The memory 809 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs, or instructions required for functions (such as sound playback functions, image playback functions, etc.). Furthermore, the memory 809 may include volatile memory or non-volatile memory, or it may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (Synchlink DRAM, SLDRAM), and direct memory bus RAM (DRRAM). The memory 809 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0165] Processor 810 may include one or more processing units; optionally, processor 810 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 810.

[0166] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described chip operating parameter optimization method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0167] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0168] This application also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above-described chip operating parameter optimization method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0169] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0170] This application provides a computer program product, which is stored in a storage medium and executed by a processor to implement the various processes of chip operating parameter optimization as described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0171] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0172] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0173] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for optimizing chip operating parameters, characterized in that, The method comprises: For each running scenario of a terminal under test, obtaining calibration power consumption data of a chip deployed in the terminal under test under the running scenario, and obtaining a first power consumption distribution model corresponding to each of a plurality of working frequencies of the chip, wherein the number of the terminal under test is multiple; According to the calibration power consumption data, a second power consumption distribution model corresponding to the running scenario is constructed; The correlation parameters between the plurality of first power consumption distribution models and the second power consumption distribution model are calculated respectively; According to the correlation parameters, a target first power consumption distribution model is determined from the plurality of first power consumption distribution models; According to the target first power consumption distribution model, the running parameters of the chip are optimized.

2. The method of claim 1, wherein, After the step of determining the target first power consumption distribution model from the plurality of first power consumption distribution models according to the correlation parameters, the method further comprises: A first cumulative distribution function is generated according to the first power consumption distribution model; the first cumulative distribution function is a function of a target probability value with respect to statistical power consumption, and the target probability value is a probability value of the actual power consumption of the chip being less than the statistical power consumption; According to the first cumulative distribution function, at least part of the chips are selected as first chips from the chips; According to the power consumption data of the first chips, the target first power consumption distribution model is verified to obtain a verification result; If the verification result is passed, the step of optimizing the running parameters of the chip according to the target first power consumption distribution model is executed; If the verification result is not passed, the correlation parameter corresponding to the target first power consumption distribution model is removed from the plurality of correlation parameters, and the step of determining the target first power consumption distribution model from the plurality of first power consumption distribution models according to the correlation parameter of the first power consumption distribution model is returned.

3. The method of claim 2, wherein, The step of verifying the target first power consumption distribution model according to the power consumption data of the first chips to obtain a verification result comprises: Obtaining the measured power consumption data of the first chips under the running scenario; Calculating the goodness of fit value between the set of measured power consumption data of the first chips and the first cumulative distribution function; If the goodness of fit value is greater than or equal to a preset goodness of fit threshold, it is determined that the verification result is passed.

4. The method of claim 2, wherein, The step of selecting at least part of the first chips from the chips according to the first cumulative distribution function comprises: In the first cumulative distribution function, a plurality of probability values are selected, the probability values including at least one of the median value of the probability value range and the probability value greater than a preset probability threshold in the probability value range; Selecting a target statistical power consumption corresponding to the probability value in the curve of the first cumulative distribution function; The chip with the calibration power consumption equal to the target statistical power consumption is selected as the first chip.

5. The method of claim 1, wherein, The step of determining the target first power consumption distribution model from the plurality of first power consumption distribution models according to the correlation parameters comprises: The correlation parameter is traversed, and when the traversed correlation parameter is greater than a preset correlation threshold, the traversal is exited, and the first power consumption distribution model corresponding to the correlation parameter is determined as the target first power consumption distribution model.

6. The method of claim 1, wherein, The second power consumption distribution model corresponding to the running scenario is constructed according to the calibration power consumption data, including: obtaining the proportion of each frequency point of the measured terminal under the running scenario and the energy model of each frequency point of the chip, wherein the proportion of each frequency point represents the percentage of the working time of the chip at the frequency point in the entire working time of the chip, and the energy model of each frequency point represents the power consumption of the chip when working at the corresponding frequency point; According to the frequency point proportion and the energy model of each frequency point, the normalized power value of the measured terminal under the running scenario is calculated and generated; According to the normalized power value of the plurality of measured terminals, the second power consumption distribution model is generated.

7. The method of claim 6, wherein, According to the frequency point proportion and the energy model of each frequency point, the normalized power value of the measured terminal under the running scenario is calculated and generated, including: calculating the product of the energy model of each frequency point of the chip and the corresponding frequency point proportion; The product of the energy model of each frequency point of the chip and the corresponding frequency point proportion is summed to obtain the normalized power value.

8. The method of claim 1, wherein, According to the target first power consumption distribution model, the running parameters of the chip are optimized, including: obtaining the standard deviation of the target first power consumption distribution model; The product of the standard deviation and the preset multiple is used as the body mass threshold value in the corresponding power consumption value of the target first power consumption distribution model; The chip whose measured power consumption data under the running scenario is greater than or equal to the body mass threshold value is determined as the chip to be optimized; A preset register value is sent to a measured terminal in which the chip to be optimized is deployed, so that the measured terminal writes the register value into the control register of the chip to be optimized, and the register value is used to control the chip to be optimized to reduce the working voltage.

9. A device for optimizing chip operating parameters, characterized in that, The device includes: An acquisition module is configured to acquire calibration power consumption data of a chip deployed in a measured terminal under each running scenario of the measured terminal and acquire a plurality of first power consumption distribution models respectively corresponding to a plurality of working frequencies of the chip, wherein the number of the measured terminals is multiple; A construction module is configured to construct a second power consumption distribution model corresponding to the running scenario according to the calibration power consumption data; A calculation module is configured to calculate a correlation parameter between a plurality of first power consumption distribution models and the second power consumption distribution model, respectively; A decision module is configured to determine a target first power consumption distribution model from the plurality of first power consumption distribution models according to the correlation parameter; An optimization module is configured to optimize the running parameters of the chip according to the target first power consumption distribution model.

10. An electronic device, comprising: A processor and a memory are included, the memory stores programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement the steps of the chip running parameter optimization method according to any one of claims 1-8.

11. A readable storage medium, characterized by, The readable storage medium stores programs or instructions, which are executed by the processor to implement the steps of the chip operating parameter optimization method according to any one of claims 1-8.

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