Self-adaptive layout method, computer readable storage medium and electronic equipment
By establishing a positional relationship chain, the chip layout is automatically adjusted, solving the problem of repetitive adjustments when chip size changes and improving chip layout efficiency.
Patent Information
- Application Number
- CN202511732282.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-02-17
AI Technical Summary
When chip size changes, existing technologies require manual readjustment of the layout, which consumes a lot of manpower and time.
By establishing a positional relationship chain, the position coordinates of the starting chip are set for each group of chips. The positional relationship of the remaining chips is described using the chip size and the coordinates of the starting chip, thereby achieving automated chip planning and layout.
Quickly respond to changes in chip size and location, reduce manpower burden, and improve layout efficiency.
Smart Images
Figure CN121543539A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an adaptive layout method, a computer-readable storage medium, and an electronic device. Background Technology
[0002] Full Mask and MPW are both tape-out methods for integrated circuits (delivering the design results for manufacturing). Full Mask means "full mask", that is, all masks in the manufacturing process serve a specific design; while MPW stands for Multi Project Wafer, which means that multiple projects share a single wafer, that is, the same manufacturing process can handle the manufacturing tasks of multiple IC designs.
[0003] In actual manufacturing processes, few customers support full mask import. Most customers, especially in the early verification phase, adopt a multi-customer MPW import mode. Mainstream layout software on the market lacks sufficient automation support for MPW-type floor plans, and in practice, manual adjustment of the layout remains the primary method. If the chip size changes, a global readjustment is usually required, which is also manual and involves a significant amount of repetitive work.
[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide an adaptive layout method, a computer-readable storage medium, and an electronic device to solve the problem of needing to manually rearrange the layout when the chip size changes.
[0006] To address the aforementioned technical problems, this invention provides an adaptive layout method, comprising:
[0007] Retrieve all chips in the current layout and divide the chips into several groups;
[0008] Establish a positional relationship chain for each group of chips, including: obtaining the dimensions of all chips; selecting the starting chip in the current group and obtaining the position coordinates of the starting chip; describing the position coordinates of the remaining chips in the current group using the chip dimensions and the position coordinates of the starting chip, so as to establish the relative positional relationship between the chips;
[0009] After the position coordinates of all chips are set, automatic chip planning and layout are performed.
[0010] After modifying the size or position of any chip, the chip layout in the current layout is adjusted according to the relative positional relationships between chips in the positional relationship chain.
[0011] Preferably, the position coordinates of the remaining chips in the current group are described by the chip size and the position coordinates of the starting chip and the dicing size.
[0012] Preferably, describing the position coordinates of the remaining chips in the current group using the chip size and the position coordinates of the starting chip includes:
[0013] Sort the remaining chips in the current group;
[0014] Set the position coordinates of the remaining chips in sequence, and when setting the position coordinates of the current chip, use the position coordinates of the previous chip, the dicing size, and the chip size between the previous chip and the current chip in the horizontal and / or vertical directions to represent the position coordinates of the current chip.
[0015] Preferably, describing the position coordinates of the remaining chips in the current group using the chip size and the position coordinates of the starting chip includes:
[0016] Sort the remaining chips in the current group;
[0017] Set the position coordinates of the remaining chips in sequence, and when setting the position coordinates of the current chip, use the position coordinates of the starting chip, the dicing size, and the chip size between the current chip and the starting chip in the horizontal and / or vertical directions to represent the position coordinates of the current chip.
[0018] Preferably, the remaining chips in the current group are sorted according to their distance from the starting chip.
[0019] Preferably, the chips are divided into several groups, each group of chips has a positional relationship chain, the position coordinates of the starting chip in each positional relationship chain are obtained, and the position coordinates of the remaining starting chips are described using the position coordinates of any starting chip.
[0020] Preferably, all starting chips are rectangular, and the coordinates of the lower left corner of the starting chip are used as the position coordinates of the starting chip.
[0021] Preferably, the current layout is a layout that meets the design rules after typesetting.
[0022] A computer-readable storage medium storing computer program instructions that, when executed by a processor, cause the processor to perform the adaptive layout method as described above.
[0023] An electronic device includes a memory and a processor, the memory storing computer instructions executable on the processor, the processor executing the adaptive layout method as described above when running the computer instructions.
[0024] In the adaptive layout method provided by the present invention, by setting a position relationship chain, a relative position relationship is set between each chip and the corresponding starting chip, and a link relationship is established between chips. This can quickly respond to changes in chip size and position and automatically adjust the arrangement of related chips.
[0025] The computer-readable storage medium provided by this invention and the adaptive layout method provided by this invention belong to the same inventive concept. Therefore, the computer-readable storage medium provided by this invention has at least all the advantages of the adaptive layout method provided by this invention, which will not be repeated here.
[0026] The electronic device provided by this invention and the adaptive layout method provided by this invention belong to the same inventive concept. Therefore, the electronic device provided by this invention has at least all the advantages of the adaptive layout method provided by this invention, which will not be repeated here. Attached Figure Description
[0027] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0028] Figure 1 This is a schematic diagram of chip distribution in the existing technology landscape;
[0029] Figure 2 This is a schematic diagram of chip size adjustments in the existing technology layout;
[0030] Figure 3 This is a schematic diagram of chip distribution according to an embodiment of the present invention;
[0031] Figure 4 This is a schematic diagram of chip size adjustment according to an embodiment of the present invention;
[0032] Figure 5 This is an execution flowchart of an embodiment of the present invention. Detailed Implementation
[0033] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0034] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0035] The inventors' research revealed that most customers, especially during the early validation phase, often adopt a multi-customer, group-based onboarding model, for example... Figure 1 The layout of the several chips shown requires manual readjustment of the entire layout to adjust the chip size and position, which is time-consuming and labor-intensive. Figure 2 As shown, if the size of a chip is adjusted, then the positions of several chips in its vertical and horizontal directions need to be adjusted accordingly.
[0036] Based on this, the core idea of the present invention is to propose an adaptive layout method. By setting a positional relationship chain, a relative positional relationship is set between each chip and its corresponding starting chip, and a link relationship is established between chips. This method can quickly respond to changes in chip size and position and automatically adjust the arrangement of related chips.
[0037] For details, please refer to Figures 3-5This is a schematic diagram of an embodiment of the present invention. Figure 5 As shown, an adaptive layout method includes:
[0038] Retrieve all chips in the current layout and divide the chips into several groups;
[0039] Establish a positional relationship chain for each group of chips, including: obtaining the dimensions of all chips; selecting the starting chip in the current group and obtaining the position coordinates of the starting chip; describing the position coordinates of the remaining chips in the current group using the chip dimensions and the position coordinates of the starting chip, so as to establish the relative positional relationship between the chips;
[0040] After the position coordinates of all chips are set, automatic chip planning and layout are performed.
[0041] After modifying the size or position of any chip, the chip layout in the current layout is adjusted according to the relative positional relationships between chips in the positional relationship chain.
[0042] The relative positional relationship between chips is established by using a positional relationship chain. The chip coordinates are described by chip size and starting chip coordinates. When the position or size of a chip changes, the position of other chips can be quickly adjusted through the positional relationship chain. This allows for automated arrangement and adjustment of related chips, reducing manpower burden and improving layout speed. The method provided by this invention is applicable to main chip floor plan and also to marker placement.
[0043] First, divide the chips in the current layout into several groups and establish several positional relationship chains. Understandably, within the same layout area, one or more starting chips can be set, and one or more link relationships can be established.
[0044] It is important to note that when all chips are grouped together, a chain of positional relationships is formed that traverses all chips. When all chips are divided into multiple groups, they can be grouped according to the region where the chips are located in order to represent and calculate their position coordinates.
[0045] In one implementation, the chips are divided into several groups, each group having a positional relationship chain. The position coordinates of the starting chip in each positional relationship chain are obtained, and the position coordinates of the remaining starting chips are described using the position coordinates of any one starting chip. It is understood that multiple starting chips can be set on a single frame, establishing multiple link relationships.
[0046] Furthermore, the current layout is a layout that meets the design rules after typesetting. The current layout can be a layout that meets the design rules after preliminary typesetting and planning adjustments. After adjusting the chip size or position using the method of this invention, it is basically unnecessary to adjust other data parameters.
[0047] Secondly, a positional relationship chain is established for each group of chips. A starting chip, Chip1, is selected in the current group, and its position coordinates are determined by establishing a coordinate system in the current layout. After the other chips are arranged, that is, after the second chip, Chip2, to the nth chip, Chipn, the positional link relationship between the other chips and Chip1 is set. The positional link relationship is described by mathematical logic expression, that is, using the chip size and the coordinates of the starting chip, Chip1. The selected starting chip can be a chip at any corner of the layout.
[0048] In one implementation, all starting chips are rectangular, and the coordinates of the lower left corner of each starting chip are used as its position coordinates. For example... Figure 3 As shown, the chip in the lower left corner of the current layout is taken as the starting chip Chip1, and the coordinates of the lower left corner of the starting chip Chip1 are used as the position coordinates. The other chips are also basically rectangular, and similarly, the position coordinates of the other chips are also the coordinates of their lower left corners. Alternatively, the coordinates of the lower right, upper right, or upper left corners of the chip can be selected as the position coordinates; there are no specific restrictions here.
[0049] In one implementation, the position coordinates of the remaining chips in the current group are described by the chip size, the position coordinates of the starting chip, and the scribeline size. Scribelines, typically of fixed width, are also provided between the chips.
[0050] Set a fixed constant slit size, that is, set the width of the slit and record it as w1. Set the variable starting chip Chip1's lower left corner coordinate (x1, y1), chip size (a1, b1) and other chip sizes ((a2, b2) ... (an, bn)).
[0051] At the start of the floor plan layout, the placement of the initial chip, Chip1, is determined first. Then, the remaining chips are ordered, for example... Figure 3 As shown, the chip at the top of the starting chip Chip1 is designated as the second chip Chip2, the chip to its right is designated as the third chip Chip3, the chip at the top of the second chip Chip2 is designated as the fourth chip Chip4, and so on. Alternatively, the remaining chips in the current group can be sorted according to their distance from the starting chip.
[0052] The position coordinates of other chips can be set directly or indirectly through the starting chip Chip1. For example, the position coordinates between the chip and the starting chip Chip1 can be set directly. Alternatively, the position coordinates of the previous chip can be used to describe the position coordinates of the current chip in sequence, or the position coordinates of the adjacent chips can be used to represent the position coordinates of the current chip. There are no specific limitations here, and the method of setting position coordinates can be selected according to the current layout.
[0053] In one implementation, describing the position coordinates of the remaining chips in the current group using chip size and the position coordinates of the starting chip includes:
[0054] Sort the remaining chips in the current group;
[0055] Set the position coordinates of the remaining chips in sequence, and when setting the position coordinates of the current chip, use the position coordinates of the previous chip, the dicing size, and the chip size between the previous chip and the current chip in the horizontal and / or vertical directions to represent the position coordinates of the current chip.
[0056] For example, first set the starting chip Chip1 and the adjacent second chip Chip2, then set the position coordinates of the third chip Chip3 according to the position coordinates of the second chip Chip2; set the position coordinates of the adjacent fourth chip Chip4 according to the coordinates of the second chip Chip2, and so on until the current group of chips is set.
[0057] In another implementation, describing the position coordinates of the remaining chips in the current group using the chip size and the position coordinates of the starting chip includes:
[0058] Sort the remaining chips in the current group;
[0059] Set the position coordinates of the remaining chips in sequence, and when setting the position coordinates of the current chip, use the position coordinates of the starting chip, the dicing size, and the chip size between the current chip and the starting chip in the horizontal and / or vertical directions to represent the position coordinates of the current chip.
[0060] The position coordinates of any other chip can be directly established using the position coordinates of the starting chip Chip1, until all other chips in the current group have been set.
[0061] After setting the relative relationships of all chips, run the Auto floor plan program. If the values of one or more variables related to chip size or position change, modify the corresponding data in the corresponding entries, and then run the Auto floor plan program to obtain the adjusted layout.
[0062] For example, such as Figure 3As shown, a chip is selected with its lower left corner as the starting point (blue dot). This chip is the starting chip Chip1, with coordinates (x1, y1) and dimensions (a1, b1). The cutting width is defined as w1. The lower left corner (yellow dot) of the adjacent second chip Chip2 is defined with coordinates (x2, y2) and dimensions (a2, b2). Therefore, x2 = x1, y2 = y1 + w1 + b1. The third chip... Similarly, for IP3, define the coordinates (x4, y4) of the lower left corner (green dot) of the fourth chip Chip4. Then x4 = x1 (= x2), y4 = y1 + 2*w1 + b1 + b2 (= y2 + w1 + b2). If the size of the second chip Chip2 changes from (a2, b2) to (a21, b21), the connection relationships of the other chips (Chip4 / 5 / 6 / …) remain unchanged, and they move to the right or upward respectively following the change in the size of the second chip Chip2. Figure 4 .
[0063] Based on the same technical concept, the present invention also provides a computer-readable storage medium storing computer program instructions, which, when executed by a processor, cause the processor to perform the adaptive layout method as described above.
[0064] For example, a computer-readable storage medium may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0065] Based on the same technical concept, the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and the processor executes the adaptive layout method as described above when executing the computer instructions.
[0066] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and can control other components in an electronic device to perform desired functions.
[0067] The memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and a processor may execute the program instructions to implement the adaptive layout method of the software program of the various embodiments of this disclosure described above, and / or other desired functions.
[0068] The adaptive layout method, computer-readable storage medium, and electronic device provided by this invention use chip size and starting chip coordinates to describe chip coordinates. Other chips can directly establish a link relationship with the starting chip, or they can establish a link relationship with a chip adjacent to the starting chip Chip1. Furthermore, multiple starting chips can be set on a single chip, establishing multiple link relationships. When the chip position or size changes, the position of other chips can be quickly adjusted through the position relationship chain, automating the arrangement and adjustment of related chips, reducing the burden of manpower, and improving the layout speed. The method provided by this invention is applicable to main chip floor plan and also to marker placement.
[0069] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. An adaptive layout method, characterized in that, include: Retrieve all chips in the current layout and divide the chips into several groups; Establish a positional relationship chain for each group of chips, including: obtaining the dimensions of all chips; selecting the starting chip in the current group and obtaining the position coordinates of the starting chip; describing the position coordinates of the remaining chips in the current group using the chip dimensions and the position coordinates of the starting chip, so as to establish the relative positional relationship between the chips; After the position coordinates of all chips are set, automatic chip planning and layout are performed. After modifying the size or position of any chip, the chip layout in the current layout is adjusted according to the relative positional relationships between chips in the positional relationship chain.
2. The adaptive layout method according to claim 1, characterized in that, The position coordinates of each of the remaining chips in the current group are described by the chip size, the position coordinates of the starting chip, and the dicing size.
3. The adaptive layout method according to claim 2, characterized in that, Using the chip size and the position coordinates of the starting chip, the position coordinates of the remaining chips in the current group can be described as follows: Sort the remaining chips in the current group; Set the position coordinates of the remaining chips in sequence, and when setting the position coordinates of the current chip, use the position coordinates of the previous chip, the dicing size, and the chip size between the previous chip and the current chip in the horizontal and / or vertical directions to represent the position coordinates of the current chip.
4. The adaptive layout method according to claim 2, characterized in that, Using the chip size and the position coordinates of the starting chip, the position coordinates of the remaining chips in the current group can be described as follows: Sort the remaining chips in the current group; Set the position coordinates of the remaining chips in sequence, and when setting the position coordinates of the current chip, use the position coordinates of the starting chip, the dicing size, and the chip size between the current chip and the starting chip in the horizontal and / or vertical directions to represent the position coordinates of the current chip.
5. The adaptive layout method according to claim 3 or 4, characterized in that, The remaining chips in the current group are sorted according to their distance from the starting chip.
6. The adaptive layout method according to claim 1, characterized in that, The chips are divided into several groups, and each group of chips has a position relationship chain. The position coordinates of the starting chip in each position relationship chain are obtained, and the position coordinates of the remaining starting chips are described using the position coordinates of any starting chip.
7. The adaptive layout method according to claim 1, characterized in that, All starting chips are rectangular, and the coordinates of the bottom left corner of the starting chip are taken as the position coordinates of the starting chip.
8. The adaptive layout method according to claim 1, characterized in that, The current layout is the layout that meets the design rules after typesetting.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, cause the processor to perform the adaptive layout method as described in any one of claims 1-8.
10. An electronic device comprising a memory and a processor, wherein the memory stores computer instructions executable on the processor, characterized in that, When the processor executes the computer instructions, it performs the adaptive layout method as described in any one of claims 1-8.