Pulse width detection circuit and field programmable gate array

Abstract

The invention discloses a pulse width detection circuit and a field programmable gate array, and belongs to the technical field of integrated circuits, the circuit comprises a time delay module, a serial-to-parallel conversion module and a control module, at least one of the time delay module and the serial-to-parallel conversion module is circuit-cured; the first input end of the time delay module is used for receiving a periodic first signal, the second input end of the time delay module is connected with the output end of the control module and used for receiving the control quantity output by the control module, and the output end of the time delay module is connected with the first input end of the serial-parallel conversion module and used for outputting a second signal; the output end of the serial-parallel conversion module is connected with the first input end of the control module and used for outputting first data, and the control module is used for determining the pulse width of the first signal based on the first data corresponding to the multiple different control quantities. The circuit can be simplified, resource occupation is reduced, cost is reduced, and interference from technology, voltage, temperature and power supply noise is small.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a pulse width detection circuit and a field-programmable gate array. Background Technology

[0002] In the field of integrated circuit design and application, periodic signals are widely used to transmit data. In some application scenarios, it is necessary to detect the pulse width of periodic signals. Existing methods for pulse width detection via carry chains are costly and easily affected by process technology, voltage, temperature, and core power supply noise. Summary of the Invention

[0003] This application proposes a pulse width detection circuit and a field-programmable gate array to improve the above-mentioned defects.

[0004] In a first aspect, this application provides a pulse width detection circuit applied to a field-programmable gate array (FPGA). The circuit includes a delay module, a serial-to-parallel conversion module, and a control module. At least one of the delay module and the serial-to-parallel conversion module is circuit-fixed. A first input terminal of the delay module is used to receive a periodic first signal. A second input terminal of the delay module is connected to the output terminal of the control module and is used to receive a control quantity output by the control module. The output terminal of the delay module is connected to the first input terminal of the serial-to-parallel conversion module and is used to output a second signal, which represents a signal obtained by delaying the first signal based on the control quantity. The second input terminal of the serial-to-parallel conversion module is used to receive a first clock signal. The output terminal of the serial-to-parallel conversion module is connected to the first input terminal of the control module and is used to output first data, which represents parallel data obtained by sampling the second signal based on the first clock signal. The control module is used to determine the pulse width of the first signal based on the first data corresponding to multiple different control quantities.

[0005] Optionally, in one possible implementation, the field-programmable gate array includes multiple independent electrical regions, the delay module and the serial-to-parallel conversion module are circuit-fixed, and the delay module and the serial-to-parallel conversion module are distributed in one of the independent electrical regions.

[0006] Optionally, in one possible implementation, the delay module is an input delay unit, which is used to perform step delay on the first signal based on the control quantity.

[0007] Optionally, in one possible implementation, the serial-to-parallel conversion module is an input serial deserializer.

[0008] Optionally, in one possible implementation, the second input terminal of the control module is used to receive a second clock signal, and the third input terminal of the serial-to-parallel conversion module is used to receive the second clock signal, wherein the period of the second clock signal is an integer multiple of the period of the first clock signal; the serial-to-parallel conversion module is used to sample the second signal based on the first clock signal to obtain serial second data, and to convert the serial second data into parallel first data based on the first clock signal and the second clock signal; the control module is used to send each different control quantity to the delay module at intervals according to the period of the first signal, and the control module is also used to determine the pulse width of the first signal based on the second clock signal and the first data corresponding to each control quantity.

[0009] Optionally, in one possible implementation, the pulse width detection circuit further includes: a clock module; the first output terminal of the clock module is connected to the second input terminal of the serial-to-parallel conversion module for outputting a first clock signal, and the second output terminal of the clock module is connected to the third input terminal of the serial-to-parallel conversion module and the second input terminal of the control module for outputting a second clock signal.

[0010] Optionally, in one possible implementation, the clock module includes a phase-locked loop (PLL) and a frequency divider unit; the output of the PLL is connected to the second input of the serial-to-parallel conversion module and the input of the frequency divider unit to output the first clock signal; the output of the frequency divider unit is connected to the third input of the serial-to-parallel conversion module and the second input of the control module to output the second clock signal.

[0011] Optionally, in one possible implementation, the control module includes a splicing unit and a calculation unit; the first input terminal of the splicing unit is connected to the second output terminal of the clock module, the second input terminal of the splicing unit is connected to the output terminal of the serial-to-parallel conversion module, and the output terminal of the splicing unit is connected to the input terminal of the calculation unit, for outputting third data, the third data being obtained by sequentially splicing the first data corresponding to the control quantity based on the second clock signal; the output terminal of the calculation unit is connected to the second input terminal of the delay module, the calculation unit being used to send each different control quantity to the delay module at intervals according to the period of the first signal, the calculation unit being further used to determine the effective sampling number corresponding to each control quantity based on the third data corresponding to each control quantity, and to determine the pulse width of the first signal based on the average of the effective sampling number corresponding to all the control quantities and the period of the first clock signal, the effective sampling number representing the number of high-level samples.

[0012] Optionally, in one possible implementation, the number of control quantities is equal to the ratio of the period of the first clock signal to the step delay of the input delay.

[0013] Secondly, this application also provides a field-programmable gate array, including the pulse width detection circuit as described in the first aspect.

[0014] This application provides a pulse width detection circuit, including: a delay module, a serial-to-parallel conversion module, and a control module. At least one of the delay module and the serial-to-parallel conversion module is circuit-fixed. The first input terminal of the delay module is used to receive a periodic first signal. The second input terminal of the delay module is connected to the output terminal of the control module and is used to receive a control quantity output by the control module. The output terminal of the delay module is connected to the first input terminal of the serial-to-parallel conversion module and is used to output a second signal, which represents a signal obtained by delaying the first signal based on the control quantity. The second input terminal of the serial-to-parallel conversion module is used to receive a first clock signal. The output terminal of the serial-to-parallel conversion module is connected to the first input terminal of the control module and is used to output first data, which represents parallel data obtained by sampling the second signal based on the first clock signal. The control module is used to determine the pulse width of the first signal based on the first data corresponding to multiple different control quantities.

[0015] Compared to the current method of using carry-chain to detect the pulse width of the periodic signal, this method is costly and the detection results are easily affected by factors such as process technology and voltage. On one hand, at least one of the delay module and serial-to-parallel conversion module in this application is a fixed circuit. Fixed circuitry simplifies the circuit, reduces resource consumption, lowers costs, and is easy to implement in various applications. Furthermore, it is less affected by process technology, voltage, temperature, and power supply noise. On the other hand, the control module of this application determines the pulse width of the first signal based on first data corresponding to multiple different control quantities. By using a time-division multiplexing method to determine the pulse width of the first signal, the circuit is further simplified, resource consumption is reduced, and costs are lowered.

[0016] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A circuit block diagram of a prior art periodic signal pulse width detection circuit is shown; Figure 2 It shows Figure 1 The timing diagram corresponding to the circuit block diagram; Figure 3 A circuit block diagram of the pulse width detection circuit provided in an embodiment of this application is shown; Figure 4 A circuit block diagram of a pulse width detection circuit according to another embodiment of this application is shown; Figure 5 A circuit block diagram of a pulse width detection circuit according to another embodiment of this application is shown; Figure 6 A circuit block diagram of a pulse width detection circuit according to another embodiment of this application is shown; Figure 7 A circuit block diagram of a pulse width detection circuit according to another embodiment of this application is shown; Figure 8 The timing diagram corresponding to the pulse width detection circuit provided in the embodiment of this application is shown. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. The components of the embodiments of the present application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without inventive effort are within the scope of protection of the present application.

[0020] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] In the field of integrated circuit design and application, periodic signals are widely used to transmit data. In some application scenarios, it is necessary to detect the pulse width of periodic signals. Existing methods for pulse width detection via carry chains are costly and easily affected by process technology, voltage, temperature, and core power supply noise.

[0022] like Figure 1 As shown, it illustrates a known technique for periodic signal pulse width detection. The main modules implementing the functions in a Field-Programmable Gate Array (FPGA) include: a clock module (clk_gen), a control module (start_stop_ctl), a carry chain counter module (carry chain&counter), and a total time calculation module (time_compute).

[0023] The clock module generates the system clock sys_clk with a period of T0. Upon the rising and falling edges of the input periodic signal DIN, the start_stop_ctl module generates start and stop pulse signals, respectively. The time_compute module starts counting upon receiving the start pulse signal and stops counting upon receiving the stop pulse signal, obtaining the count value M and calculating the time interval M*T0. The carry chain&counter module, upon receiving the stop pulse signal, calculates the interval ΔT between the moment the stop pulse signal is received and the subsequent rising edge of the first sys_clk clock. M*T0 minus ΔT equals the pulse width of the periodic signal DIN. The timing diagram for detecting the pulse width of the periodic signal DIN using this scheme is shown below. Figure 2 As shown. Among them, Figure 2 The first row of values ​​represents the number of cycles of the system clock sys_clk. "start" indicates the time when the start_stop_ctl module generates the start pulse signal, and "stop" indicates the time when the start_stop_ctl module generates the stop pulse signal. The pulse width of the periodic signal DIN, T=M*T0-△T, can be determined based on the cycle T0 of the system clock sys_clk, the count value M of the time_compute module, and △T of the carrychain&counter module.

[0024] However, since the carry chain is a logic resource of the FPGA, it needs to be "enabled" and "connected" by configuring a bitstream file. This solution has the following problems.

[0025] 1. This carry chain counting module occupies a large amount of carry chain resources on the chip, resulting in high costs.

[0026] 2. The delay of this carry chain is easily affected by factors such as process, voltage, and temperature, resulting in a large deviation in the detection result of ΔT.

[0027] 3. This carry chain circuit is located in the core voltage domain, making it susceptible to interference from core power supply noise, which further introduces detection deviations.

[0028] 4. The delay of this carry chain is strongly related to the layout and requires regular positional constraints, which is difficult to implement in practical applications.

[0029] Therefore, in this application embodiment, a pulse width detection circuit and a field-programmable gate array are provided to solve or partially solve the above problems.

[0030] Please see Figure 3 The diagram shows a circuit block diagram of a pulse width detection circuit 100 provided in an embodiment of this application, which is applied to a field-programmable gate array. The circuit includes...

[0031] The delay module 110, the serial-to-parallel conversion module 120, and the control module 130 are provided, wherein at least one of the delay module 110 and the serial-to-parallel conversion module 120 is a fixed circuit.

[0032] The first input terminal of the delay module 110 is used to receive a periodic first signal. The second input terminal of the delay module 110 is connected to the output terminal of the control module 130 and is used to receive the control quantity output by the control module 130. The output terminal of the delay module 110 is connected to the first input terminal of the serial-to-parallel conversion module 120 and is used to output a second signal. The second signal represents a signal obtained by delaying the first signal based on the control quantity.

[0033] The second input terminal of the serial-to-parallel conversion module 120 is used to receive the first clock signal. The output terminal of the serial-to-parallel conversion module 120 is connected to the first input terminal of the control module 130 and is used to output the first data. The first data represents the parallel data obtained by sampling the second signal based on the first clock signal. The control module 130 is used to determine the pulse width of the first signal based on the first data corresponding to multiple different control quantities.

[0034] It should be noted that the first signal is the signal whose pulse width needs to be detected, and the control quantity represents a control signal, also known as a control word. For example, the control quantity shift_code=1, or shift_code=3, with different control signals corresponding to different control quantities. In this embodiment, the delay module 110 can delay the first signal based on the control quantity to obtain a second signal, then sample the second signal through a serial-to-parallel conversion module to obtain parallel first data. Finally, the control module determines the pulse width of the first signal based on the first data corresponding to multiple different control quantities.

[0035] Compared to the current method of using carry-chain to detect the pulse width of the periodic signal, this method is costly and the detection results are easily affected by factors such as process technology and voltage. On one hand, at least one of the delay module and serial-to-parallel conversion module in this application is a fixed circuit. Fixed circuitry simplifies the circuit, reduces resource consumption, lowers costs, and is easy to implement in various applications. Furthermore, it is less affected by process technology, voltage, temperature, and power supply noise. On the other hand, the control module of this application determines the pulse width of the first signal based on first data corresponding to multiple different control quantities. By using a time-division multiplexing method to determine the pulse width of the first signal, the circuit is further simplified, resource consumption is reduced, and costs are lowered.

[0036] In one optional embodiment, the delay module is an input delay unit, which is used to perform step delay on the first signal based on the control quantity.

[0037] It should be noted that the circuit of the input delay is fixed. The input delay (IDELAY) is the input / output (I / O) resource of the FPGA. Since the phase shift step time of the IDELAY unit is less affected by process, voltage and temperature, and the circuit is powered by an external power supply, it is less affected by power supply noise.

[0038] It's understandable that the input delay isn't "continuously adjustable," but rather jumps in stages. The width of each stage is the step delay. The step delay of the input delay is fixed, but different models from different manufacturers may have different step delays; for example, the step delay could be 10ps, 78ps, etc. The control variable is used to control the delay amount of the first signal, and the step delay of the first signal can be changed by different control variables.

[0039] For example, the step delay of the input delayer is 10ps. If the control value is 1, the input delayer delays the first signal by 10ps. If the control value is 3, the input delayer delays the first signal by 3*10ps. The first signal can be delayed based on the control value. Different phase delays can be applied to the first signal based on different control values.

[0040] In addition, the maximum delay of a certain input delay is determined by the hardware product, and the step delay is also determined by the hardware product.

[0041] In one implementation scenario, during the development phase, the number of control quantities and the specific value of each control quantity are determined based on the target detection accuracy (the accuracy required by the user), the step delay of the input delay unit, and the period of the first clock signal. Then, a configuration bitstream file is obtained through placement, routing, and synthesis. The FPGA is then configured based on the bitstream file, and the configured FPGA contains the pulse width detection circuit of this application. Each control quantity determined during the development phase is stored in a designated memory unit, and the control module can send each different control quantity to the delay module at intervals according to the period of the first clock signal.

[0042] During the development phase, the number of control quantities and the specific value of each control quantity are determined based on the target detection accuracy (the accuracy required by the user), the minimum step delay of the input delay unit, and the period T1 of the first clock signal.

[0043] For example, if the target detection accuracy is equal to the step delay A of the input delay, then the total number of control quantities N = T1 / A is determined, and the difference between any two adjacent control quantities is 1. For instance, if the step delay of the input delay is 10 ps, ​​the target detection accuracy is also 10 ps, ​​and the period of the first signal is 5 ns, then the total number of control quantities N = 5 ns / 10 ps = 500 is determined, and the difference between any two adjacent control quantities is 1. That is, 500 control quantities are determined during the development phase, and the control words corresponding to these 500 control quantities are integers from 1 to 500.

[0044] For example, if the target detection accuracy is less than the step delay A of the input delay, it means that the user's requirements cannot be met under current hardware conditions, and the best accuracy can be achieved with the step delay A. In this case, the total number of control quantities N = T1 / A is determined, and the difference between any two adjacent control quantities is 1. For instance, if the step delay of the input delay is 10 ps, ​​the target detection accuracy is 5 ps, and the period of the first signal is 5 ns, then the total number of control quantities N = 5 ns / 10 ps = 500, and the difference between any two adjacent control quantities is 1. That is, 500 control quantities are determined during the development phase, and the control words corresponding to these 500 control quantities are integers from 1 to 500.

[0045] For example, if the target detection accuracy B is greater than the step delay A of the input delay, then the total number of control quantities N = T1 / B is determined, and the difference between two adjacent control quantities is B / A. For instance, if the step delay of the input delay is 10ps, the target detection accuracy is 20ps, and the period of the first signal is 5ns, then the total number of control quantities N = 5ns / 20ps = 250 is determined, and the difference between two adjacent control quantities is 2. That is, only 250 control quantities are determined during the development phase, and the control words corresponding to these 250 control quantities are odd or even numbers between 1 and 500.

[0046] It can be seen that during the development phase, the number of control quantities and the specific value of each control quantity can be determined based on the target detection accuracy (the accuracy required by the user), the step delay of the input delay timer, and the period of the first clock signal.

[0047] In one optional embodiment, the serial-to-parallel conversion module is an input serial deserializer.

[0048] It should be noted that the circuit of the input serial / deserializer is fixed. The input serial / deserializer (ISERDES) is an FPGA I / O resource. The input serial / deserializer is less affected by process, voltage and temperature, and the circuit is powered by an external power supply, so it is less affected by power supply noise.

[0049] It is understandable that input serializers / deserializers produced by different manufacturers may differ, and the serial-to-parallel conversion ratio of the input serializer / deserializer can range from 1:1 to 1:20. The serial-to-parallel conversion ratio can be determined according to the user's needs, and then the clock signal required by the serial-to-parallel conversion module can be determined based on the serial-to-parallel conversion ratio.

[0050] In one optional embodiment, the field-programmable gate array includes multiple independent electrical regions, the delay module and the serial-to-parallel conversion module are circuit-fixed, and the delay module and the serial-to-parallel conversion module are distributed in one of the independent electrical regions.

[0051] It's important to note that the aforementioned independent electrical area is a physical section on the FPGA chip that is actually separated by power trenches and metal barriers. In Xilinx / Intel's official documentation, this corresponds to the Input / Output Bank, often simply referred to as a "Bank." Each Bank has its own dedicated power supply pin (VCCO), and different Banks' VCCO pins can be connected to different voltages (e.g., 1.2V, 1.5V, 1.8V, 2.5V, or 3.3V). The VCCO pins of different Banks do not interfere with each other; overvoltage / undervoltage faults are confined to the current Bank and will not spread to adjacent Banks.

[0052] In addition, each bank internally contains: an input / output buffer (IOB), an input delay (IDELAY), an output delay (ODELAY), an input serial / deserializer (ISERDES), an output serial / deserializer (OSERDES), a bank ultra-fast regional clock (BUFR), and a bank ultra-fast I / O clock (BUFIO). These core resources can only be accessed by the pins of the bank itself and cannot be borrowed from other banks. Therefore, each bank is an independent electrical region.

[0053] The two banks are physically separated by deep slot isolation or insulating rings to ensure that the power, ground, and signal lines of each bank can be designed independently. If the clock needs to cross banks, a global clock network or a lateral clock line must be used; otherwise, timing tools will report errors.

[0054] In this application, the delay module and the serial-to-parallel conversion module are placed in the same independent electrical area, occupying only one IO resource, which can further simplify the circuit, reduce resource consumption, and reduce costs.

[0055] In one alternative embodiment, please refer to Figure 4 The diagram shows a circuit block diagram of a pulse width detection circuit 100 provided in an embodiment of this application. The second input terminal of the control module 130 is used to receive a second clock signal, and the third input terminal of the serial-to-parallel conversion module 120 is used to receive the second clock signal. The period of the second clock signal is an integer multiple of the period of the first clock signal.

[0056] The serial-to-parallel conversion module 120 is used to sample the second signal based on the first clock signal to obtain serial second data, and to convert the serial second data into parallel first data based on the first clock signal and the second clock signal.

[0057] The control module 130 is used to send each control quantity to the delay module at periodic intervals according to the first signal. The control module 130 is also used to determine the pulse width of the first signal based on the second clock signal and the first data corresponding to each control quantity.

[0058] It should be noted that the control module can obtain the period of the first signal, and the control module can send multiple different control quantities to the delay module at intervals according to the period of the first signal.

[0059] In one alternative embodiment, please refer to Figure 5 The diagram shows a circuit block diagram of another pulse width detection circuit 100 provided in an embodiment of this application, which further includes...

[0060] Clock module 140.

[0061] The first output terminal of the clock module 140 is connected to the second input terminal of the serial-to-parallel conversion module 120 and is used to output a first clock signal. The second output terminal of the clock module 140 is connected to the third input terminal of the serial-to-parallel conversion module 120 and the second input terminal of the control module 130 respectively and is used to output a second clock signal.

[0062] In one implementation scenario, during the development phase, the frequency ratio of the first clock signal to the second clock signal is determined based on the serial-to-parallel conversion ratio required by the user and the sampling mode of the serial-to-parallel conversion module. Then, based on the frequency ratio and the frequency of the clock source, the period of the first clock signal and the period of the second clock signal are determined. After placement, routing, and synthesis, a configuration bitstream file is obtained. Then, the FPGA is configured based on the bitstream file. The configured FPGA includes the pulse width detection circuit of this application. The clock module in the pulse width detection circuit generates the first clock signal and the second clock signal.

[0063] For example, during the development phase, if the user requires a serial-to-parallel conversion ratio of 1:8, and the serial-to-parallel conversion module operates in Double Data Rate (DDR) mode (sampling two data points per cycle), then the frequency ratio of the first clock signal to the second clock signal is determined to be 4:1, and the clock source frequency is 25MHz. Therefore, the periods of the first and second clock signals can be determined based on the clock source frequency and the frequency ratio. For instance, the period of the first clock signal is 4ns, and the period of the second clock signal is 16ns.

[0064] Another example: during the development phase, if the user requires a serial-to-parallel conversion ratio of 1:8, and the serial-to-parallel conversion module operates in Single Data Rate (SDR) mode (sampling one data point per cycle), then the frequency ratio of the first clock signal to the second clock signal is determined to be 8:1, and the clock source frequency is 25MHz. The periods of the first and second clock signals can then be determined based on this frequency ratio and the clock source frequency. For example, the period of the first clock signal is 2ns, and the period of the second clock signal is 16ns.

[0065] In one alternative embodiment, please refer to Figure 6 The diagram shows a circuit block diagram of another pulse width detection circuit 100 provided in an embodiment of this application.

[0066] The clock module 140 includes a phase-locked loop 141 and a frequency divider unit 142.

[0067] The output terminal of the phase-locked loop 141 is connected to the second input terminal of the serial-to-parallel conversion module 120 and the input terminal of the frequency divider unit 142, and is used to output the first clock signal. The output terminal of the frequency divider unit 142 is connected to the third input terminal of the serial-to-parallel conversion module 120 and the second input terminal of the control module 130, and is used to output the second clock signal.

[0068] As is understandable, a phase-locked loop (PLL) is a circuit system that uses feedback control principles to achieve phase synchronization. It is widely used in clock generation, frequency synthesis, clock recovery, and jitter reduction. Its core function is to lock the phase of the output clock to the phase of the input reference clock, thereby achieving a high-precision, low-jitter clock signal output.

[0069] In one implementation scenario, during the development phase, the amplification factor G of the phase-locked loop is determined based on the clock source and the period of the obtained first clock signal. The division number of the frequency divider unit is determined based on the period of the first clock signal and the period of the second clock signal. Then, after placement, routing, and synthesis, a configuration bit stream file is obtained. The PPGA is then configured based on the bit stream file. The configured FPGA includes the pulse width detection circuit of this application. The phase-locked loop in the pulse width detection circuit generates a first clock signal based on the clock signal of the clock source, and the frequency divider unit obtains a second clock signal based on the first clock signal.

[0070] It should be noted that the output of the clock source is connected to the input of the phase-locked loop (not shown in the figure) to output the clock signal of the crystal oscillator. The frequency of the first clock signal is G times the frequency of the crystal oscillator, and the phase-locked loop can output a first clock signal with a relatively stable phase.

[0071] Understandably, a frequency divider unit is used to reduce a high-frequency clock signal FQ to FOUT = FQ / W (W ≥ 1) by an integer or fractional ratio. The frequency divider unit is a frequency divider, such as an even-number divider, an odd-number divider, or a frequency divider built into the clock management hard core.

[0072] In one example, if the frequency of the first clock signal is 200MHz and the frequency division unit is a 4-divider, then the frequency of the second clock signal is 50MHz.

[0073] In one optional embodiment, the phase-locked loop 141 is a global phase-locked loop (GPLL) used to provide a global clock for the entire FPGA system, offering high accuracy and flexibility. Its output clock signal is sent to the global clock network, reaching various parts of the chip and providing synchronous clocks for a large number of logic resources.

[0074] In one optional embodiment, the phase-locked loop 141 is a peripheral phase-locked loop (PPLL) used for clock generation of specific peripheral interfaces (such as high-speed serial interfaces). Its design focuses on low jitter and meeting the clock requirements of specific interfaces. For example, it generates clocks that meet specific protocol and rate requirements for communication interfaces, memory interfaces, etc.

[0075] In one alternative embodiment, please refer to Figure 7 The diagram shows a circuit block diagram of another pulse width detection circuit 100 provided in an embodiment of this application.

[0076] The control module 130 includes a splicing unit 131 and a calculation unit 132.

[0077] The first input terminal of the splicing unit 131 is connected to the second output terminal of the clock module 140, the second input terminal of the splicing unit 131 is connected to the output terminal of the serial-to-parallel conversion module 120, and the output terminal of the splicing unit 131 is connected to the input terminal of the calculation unit 132, for outputting third data, which is obtained by splicing the second data corresponding to the control quantity in sequence based on the second clock signal.

[0078] The output terminal of the calculation unit 132 is connected to the second input terminal of the delay module 110. The calculation unit 132 is used to send each different control quantity to the delay module 110 at intervals according to the period of the first signal. The calculation unit 132 is also used to determine the effective sampling number corresponding to each control quantity based on the third data corresponding to each control quantity, and to determine the pulse width of the first signal based on the average of the effective sampling number corresponding to all the control quantities and the period of the first clock signal. The effective sampling number represents the number of high-level samples.

[0079] As can be seen from the foregoing embodiments, a control quantity is given to the delay module, which delays the first signal based on the control quantity to obtain the second signal. Then, the serial-to-parallel conversion module samples the second signal based on the first clock signal to obtain multiple sampled values. Finally, based on the first clock signal and the second clock signal, the serial sampled values ​​are converted into parallel first data output.

[0080] It should be noted that the period of the first signal may be much longer than the period of the first clock signal. Sampling the second signal based on the first clock signal may result in a large amount of binary data. However, the bit width of the parallel data output by the serial-to-parallel conversion module is limited. Therefore, sampling a period of the first signal based on the first clock signal may require multiple serial-to-parallel conversions to obtain multiple first data points. These multiple first data points are all obtained by sampling the first signal. Therefore, it is necessary to concatenate the multiple first data points corresponding to this control quantity sequentially. The concatenated third data point is the data obtained from sampling the second signal.

[0081] Understandably, the control module transmits control signals to the delay module. The delay module delays the first signal based on the control signals to obtain the second signal. The serial-to-parallel conversion module receives the instruction from the control module and begins sampling the second signal based on the first clock signal (not shown in the diagram). This allows the control module to determine which first data corresponds to each control signal. Based on this, the control module can determine the first data corresponding to each control signal, and then determine the third data corresponding to each control signal based on the first data.

[0082] Furthermore, after determining the third data corresponding to each control quantity, the number of high-level signals in each third data is obtained as the effective sampling count. Therefore, the effective sampling count corresponding to each control quantity can be obtained. Then, the pulse width of the first signal is determined based on the average of the effective sampling counts corresponding to all control quantities and the period of the first clock signal. Specifically, the average value is multiplied by the period of the first clock signal to obtain the pulse width of the first signal.

[0083] It is known that the values ​​in the third data are high and low levels. When the rising edge of the first clock signal samples the low level of the second signal, the sampled value is "0"; when the rising edge of the first clock signal samples the high level of the second signal, the sampled value is "1". Therefore, the number of valid samples can be determined based on the number of "1"s in the third data. For example, if the third data is "0000000011111111", it means that the number of valid samples is 8. Furthermore, the number of valid samples corresponding to each control quantity can be obtained. For example, if a total of 100 control quantities are sent to the delay module, the average number of valid samples corresponding to all control quantities is 42, and the step delay of the input delay unit is 10ps, then the pulse width of the first row can be determined to be 42 * 10 = 420ps.

[0084] In one optional embodiment, the output terminal of the splicing unit is connected to the first input terminal of the computing unit, and the second input terminal of the computing unit is connected to the second output terminal of the clock module.

[0085] In one optional embodiment, the first input terminal of the splicing unit is connected to the output terminal of the frequency division unit, the second input terminal of the splicing unit is connected to the output terminal of the serial-to-parallel conversion module, and the output terminal of the splicing unit is connected to the first input terminal of the calculation unit for outputting third data. The output terminal of the calculation unit is connected to the second input terminal of the delay module, and the second input terminal of the calculation unit is connected to the output terminal of the frequency division unit.

[0086] It should be noted that the splicing unit can be a register or a shift register, etc., and the control module is a logic resource of the FPGA, that is, the FPGA is configured through a bitstream file to obtain the control module, which can realize the aforementioned functions. The calculation unit is a combinational logic circuit, and the specific circuit of the calculation unit will not be described in detail here.

[0087] Please see Figure 8 This diagram shows the timing of the valid sample values ​​corresponding to each control quantity. The first row of numbers represents the period count of the first clock signal clk. DIN is the first signal, DIN_d_1 represents the signal after delaying DIN based on the first control quantity, which is also the second signal corresponding to the first control quantity, and CNT1 represents the number of valid samples corresponding to the first control quantity. Similarly, DIN_d_N represents the signal after delaying DIN based on the Nth control quantity, which is also the second signal corresponding to the Nth control quantity, and CNTN represents the number of valid samples corresponding to the Nth control quantity. T1 represents the period of the first clock signal, and N is the total number of control quantities.

[0088] An exemplary step in determining the pulse width of the first signal is as follows: The control module sends a control quantity (i.e., the control signal shift_code) to the delay module, setting the control signal shift_code=1. The first signal (DIN) is processed by the input delay unit (IDELAY unit) to generate a second signal (DIN_d_1 signal), with a phase shift time of 1*T1 / N. This second signal is then converted from serial to parallel data by the input serial deserializer (ISERDES unit) and sent to the control module. In the control module, the multiple first data corresponding to the control signal are extended and concatenated to obtain the third data. The number of consecutive "1"s in the third data is calculated as the effective sampling number CNT1.

[0089] Similarly, setting the control signal shift_code=2, the input periodic signal DIN is processed by the IDELAY unit to generate a second signal (DIN_d_2 signal), with a phase shift time of 2*T1 / N. This second signal is then converted from serial to parallel processing by the ISERDES unit into multiple 8-bit first data bits, which are then sent to the control module. In the control module, the first data corresponding to this control signal is expanded and concatenated to obtain third data. The number of consecutive "1"s in this third data is calculated as the effective sampling number CNT2.

[0090] As mentioned earlier, by sequentially setting the control signal shift_code=3, 4, 5...N, the effective number of samples corresponding to the control signal is obtained as CNT3, CNT4, CNT5...CNTN when the phase shift times are 3*T1 / N, 4*T1 / N, 5*T1 / N...N*T1 / N.

[0091] The pulse width detection result of the input periodic signal DIN is: (CNT1*T1+CNT2*T1+CNT3*T1+CNT4*T1+CNT5*T1+……+CNTN*T1) / N =(CNT1+CNT2+CNT3+CNT4+CNT5+……+CNTN)*T1 / N That is, the pulse width detection result of the input periodic signal DIN is: the sum of the number of "1"s in the third data corresponding to each control signal, multiplied by the period T1 of the first clock signal, and then divided by the total number of control quantities N. Existing methods directly obtain the pulse width using a delay chain, which is easily affected by factors such as process technology, voltage, and power supply. The solution in this application uses time-division multiplexing of the delay module and the serial-to-parallel conversion module to obtain the pulse width. On the one hand, time-division multiplexing simplifies the circuit and reduces costs; on the other hand, at least one of the delay module and the serial-to-parallel conversion module in this application is a fixed circuit, which simplifies the circuit, reduces resource consumption, lowers costs, and is easy to implement in various applications. Furthermore, the detection accuracy of existing solutions is above 50 ps, ​​while the detection accuracy of this application is determined by the step delay of the input delay unit and can reach 10 ps. Therefore, the pulse width detection accuracy of this application is higher and the stability is better.

[0092] In one alternative embodiment, this application also provides a field-programmable gate array, including the aforementioned pulse width detection circuit.

[0093] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described device and module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0094] In the several embodiments provided in this application, the coupling between modules can be electrical, mechanical, or other forms of coupling.

[0095] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0096] In this embodiment, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0097] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, the various modules / units they contain can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A pulse width detection circuit, characterized by, The application is applied to a field programmable gate array, and the circuit comprises: a delay module, a serial-parallel conversion module and a control module, at least one of the delay module and the serial-parallel conversion module is circuit-fixed; a first input end of the delay module is used for receiving a periodic first signal, a second input end of the delay module is connected with an output end of the control module and is used for receiving a control quantity output by the control module, an output end of the delay module is connected with a first input end of the serial-parallel conversion module and is used for outputting a second signal, the second signal represents a signal obtained by delaying the first signal based on the control quantity; a second input end of the serial-parallel conversion module is used for receiving a first clock signal, an output end of the serial-parallel conversion module is connected with a first input end of the control module and is used for outputting first data, the first data represents parallel data obtained by sampling the second signal based on the first clock signal, and the control module is used for determining a pulse width of the first signal based on the first data corresponding to a plurality of different control quantities.

2. The pulse width detection circuit of claim 1, wherein, The field programmable gate array comprises a plurality of independent electrical regions, the delay module and the serial-parallel conversion module are circuit-fixed, and the delay module and the serial-parallel conversion module are distributed in one of the independent electrical regions.

3. The pulse width detection circuit of claim 1, wherein, The delay module is an input delay, and the input delay is used for performing step delay on the first signal based on the control quantity.

4. The pulse width detection circuit of claim 1, wherein, The serial-parallel conversion module is an input serial deserializer.

5. The pulse width detection circuit according to claim 3, wherein a second input end of the control module is used for receiving a second clock signal, a third input end of the serial-parallel conversion module is used for receiving the second clock signal, and a period of the second clock signal is an integer multiple of a period of the first clock signal; the serial-parallel conversion module is used for sampling the second signal based on the first clock signal to obtain serial second data and converting the serial second data into parallel first data based on the first clock signal and the second clock signal; the control module is used for sending each different control quantity to the delay module at a period interval of the first signal, and the control module is further used for determining the pulse width of the first signal based on the second clock signal and the first data corresponding to each control quantity.

6. The pulse width detection circuit of claim 5, wherein, The pulse width detection circuit further comprises: a clock module; a first output end of the clock module is connected with a second input end of the serial-parallel conversion module and is used for outputting a first clock signal, and a second output end of the clock module is connected with a third input end of the serial-parallel conversion module and a second input end of the control module respectively and is used for outputting a second clock signal.

7. The pulse width detection circuit according to claim 6, wherein the clock module comprises a phase-locked loop and a frequency division unit. An output terminal of the phase-locked loop is connected with a second input terminal of the serial-parallel conversion module and an input terminal of the frequency division unit, for outputting the first clock signal, and an output terminal of the frequency division unit is connected with a third input terminal of the serial-parallel conversion module and a second input terminal of the control module, for outputting the second clock signal. 8.The pulse width detection circuit of claim 6, wherein, The control module comprises a splicing unit and a calculation unit. A first input terminal of the splicing unit is connected with a second output terminal of the clock module, a second input terminal of the splicing unit is connected with an output terminal of the serial-parallel conversion module, and an output terminal of the splicing unit is connected with an input terminal of the calculation unit, for outputting third data, which is obtained by splicing the first data corresponding to the control quantities in sequence based on the second clock signal. An output terminal of the calculation unit is connected with a second input terminal of the delay module, the calculation unit is configured to send each different control quantity to the delay module at a period of the first signal, and the calculation unit is further configured to determine the effective sampling number corresponding to each control quantity based on the third data corresponding to each control quantity, and determine the pulse width of the first signal based on an average value of the effective sampling numbers corresponding to all the control quantities and the period of the first clock signal, the effective sampling number representing the number of sampling to high level. 9.The pulse width detection circuit of claim 3, wherein, The number of the control quantities is equal to a ratio of the period of the first clock signal to the step delay of the input delay.

10. A field programmable gate array, comprising: A pulse width detection circuit as claimed in any one of claims 1 to 9.

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