Three-electrode silicon capacitor structure, preparation method thereof and electronic equipment
By etching a trench network and stacked capacitor structure for a three-electrode silicon capacitor onto a silicon substrate, the problem of large area occupied by traditional capacitors is solved, achieving high capacitance density and circuit connection flexibility, thus promoting the miniaturization of electronic devices.
Patent Information
- Application Number
- CN202511585426.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2026-02-17
AI Technical Summary
Traditional horizontal electrode arrangement capacitors occupy a large area on the circuit board, making it difficult to meet the miniaturization requirements of electronic devices, and additional lines or solder joints need to be reserved when connecting multiple lines.
A three-electrode silicon capacitor structure is adopted, which forms a trench network on a silicon substrate to create a three-dimensional stacked capacitor structure. The structure is then mounted on a circuit board using flip-chip bonding, achieving flexibility in circuit connection and high capacitance density.
Significantly increasing capacitance density per unit area reduces the amount of wiring or solder joints required on circuit boards, promoting miniaturization and high performance of electronic devices.
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Figure CN121548053A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a three-electrode silicon capacitor structure and its fabrication method, as well as electronic devices. Background Technology
[0002] In modern integrated circuits, capacitors are key components for energy storage, decoupling, and filtering, and their performance directly affects the power consumption, speed, and stability of the entire system. As electronic devices continue to evolve towards miniaturization and higher frequencies, extremely high demands are placed on the integration density, capacitance density, and frequency characteristics of capacitors. Traditional multilayer ceramic chip capacitors, limited by package size and parasitic inductance, struggle to meet high-performance requirements in advanced packaging. Against this backdrop, silicon capacitors have emerged. Fabricated on silicon wafers using standard semiconductor processes, they possess inherent advantages such as high capacitance density, low equivalent series inductance, excellent high-frequency characteristics, and ease of three-dimensional integration with other chips, making them an ideal choice for realizing next-generation high-density, high-performance electronic systems.
[0003] Silicon capacitors typically have two electrode arrangements: vertical and horizontal. For traditional horizontally arranged capacitors, flip-chip soldering is often used to solder the capacitor to the circuit board to reduce board area. When the capacitor has multiple circuit connections, additional traces or solder joints need to be provided on the circuit board to achieve these connections. However, this increases the circuit board area, hindering the miniaturization of electronic devices. Summary of the Invention
[0004] This invention provides a three-electrode silicon capacitor structure and its fabrication method, as well as an electronic device. While increasing capacitance density, the three electrodes improve circuit connection flexibility, which is beneficial for the miniaturization of electronic devices or systems.
[0005] In a first aspect, the present invention provides a three-electrode silicon capacitor structure, comprising: A silicon substrate, wherein a trench network is formed on the front side of the silicon substrate; A stacked capacitor structure is disposed within the trench network and on the front side of the silicon substrate. The stacked capacitor structure includes at least one stacked structure composed of a bottom electrode, a dielectric layer, and a top electrode. The bottom electrode covers the bottom and side surfaces of the trench network and the front side of the silicon substrate. The dielectric layer covers the bottom electrode. The top electrode fills the trench network and covers the dielectric layer. The bottom electrode is electrically connected to the silicon substrate. The first front electrode and the second front electrode are disposed on the front side of the stacked capacitor structure and are electrically connected to the top electrode and the bottom electrode, respectively. The back electrode is disposed on the back side of the silicon substrate and is electrically connected to the silicon substrate.
[0006] According to the three-electrode silicon capacitor structure provided by the present invention, the aspect ratio of a single trench in the trench network is greater than or equal to 10:1.
[0007] According to the three-electrode silicon capacitor structure provided by the present invention, the vertical cross-sectional shape of a single trench in the trench network is circular, polygonal, conical, rectangular or spiral.
[0008] According to the present invention, a three-electrode silicon capacitor structure is provided, wherein the stacked capacitor structure comprises multiple vertically stacked layers, and the top electrode of the stacked structure is reused as the bottom electrode of the next layer of the stacked structure; The even-numbered layer electrodes are electrically connected to the first front electrode through electrode interconnect holes, and the odd-numbered layer electrodes are electrically connected to the second front electrode through electrode interconnect holes.
[0009] According to the three-electrode silicon capacitor structure provided by the present invention, the material constituting the bottom electrode includes at least one of conductive polycrystalline silicon, metal or metal nitride, and the material constituting the top electrode includes at least one of conductive polycrystalline silicon, metal or metal nitride.
[0010] According to the three-electrode silicon capacitor structure provided by the present invention, the material constituting the dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or strontium titanate.
[0011] In a second aspect, the present invention also provides a method for fabricating a three-electrode silicon capacitor structure, used to fabricate the three-electrode silicon capacitor structure as described in the first aspect, the fabrication method comprising: A silicon substrate is provided, and a trench network is formed on the front side of the silicon substrate by an etching process; A bottom electrode is formed on the front side of the silicon substrate, such that the bottom electrode covers the bottom and side surfaces of the trench network and the front side of the silicon substrate; A dielectric layer is deposited on the bottom electrode; A top electrode is formed on the dielectric layer, and the top electrode fills the trench network; Etch the top electrode to expose a portion of the bottom electrode; An insulating layer is formed on the top electrode, and the insulating layer is etched to form a first through hole exposing the bottom electrode and a second through hole exposing the top electrode; wherein the etched insulating layer covers the sidewall of the first through hole; An electrode layer is formed on the insulating layer, and the electrode layer is etched to form a first front electrode that fills the first through-hole and a second front electrode that fills the second through-hole; A back electrode is formed on the back side of the silicon substrate.
[0012] According to a method for fabricating a three-electrode silicon capacitor structure provided by the present invention, the step of forming a bottom electrode on the front side of the silicon substrate includes: The silicon substrate is doped to form heavily doped conductive regions on the surface of the trench network and the front side of the silicon substrate, thereby forming the bottom electrode.
[0013] According to a method for fabricating a three-electrode silicon capacitor structure provided by the present invention, the bottom electrode is fabricated by chemical vapor deposition, physical vapor deposition or atomic layer deposition, the top electrode is fabricated by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the dielectric layer is fabricated by chemical vapor deposition, physical vapor deposition or atomic layer deposition.
[0014] Thirdly, the present invention also provides an electronic device, including a three-electrode silicon capacitor structure as described in the first aspect, wherein the three-electrode silicon capacitor structure is mounted on the circuit board of the electronic device by flip-chip bonding; wherein the back electrode is wire-bonded to the circuit board.
[0015] In this invention, a trench network is formed by etching on the front side of a silicon substrate. With consistent dielectric material and voltage withstand capability, the originally flat two-dimensional surface is transformed into a three-dimensional structure. This means the effective area for forming the capacitor is no longer the planar projected area of the silicon substrate, but rather the sum of the surface areas of the bottom and side surfaces of all the trenches. This achieves a larger effective surface area per unit area, significantly increasing capacitance density. Furthermore, the second front electrode and the back electrode are electrically equipotential, meaning the back electrode shares potential with the front electrode through the silicon substrate. Compared to traditional horizontal electrode arrangements, the three-electrode silicon capacitor structure offers more possibilities for circuit connections, improving circuit flexibility and reducing the number of pre-installed traces or solder joints on the circuit board when multiple circuits are connected. This lays the foundation for saving circuit board wiring space, thus facilitating the miniaturization of electronic devices or systems. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 This is a three-dimensional structural diagram of a three-electrode silicon capacitor structure provided by the present invention.
[0018] Figure 2This is a cross-sectional structural diagram of a three-electrode silicon capacitor structure provided by the present invention.
[0019] Figure 3 This is a cross-sectional schematic diagram of another three-electrode silicon capacitor structure provided by the present invention.
[0020] Figure 4 This is a schematic flowchart of a method for fabricating a three-electrode silicon capacitor structure provided by the present invention.
[0021] Figures 5 to 11 This is a cross-sectional structural diagram of each step in the fabrication method of a three-electrode silicon capacitor structure. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0023] Figure 1 This is a three-dimensional structural diagram of a three-electrode silicon capacitor structure provided by the present invention. Figure 2 This is a cross-sectional structural diagram of a three-electrode silicon capacitor structure provided by the present invention. (Combined with...) Figure 1 and Figure 2 The three-electrode silicon capacitor structure includes a silicon substrate 1, a multilayer capacitor structure, a first front electrode 6, a second front electrode 7, and a back electrode 8. A trench network 2 is formed on the front side of the silicon substrate 1. The multilayer capacitor structure is disposed within the trench network 2 and on the front side of the silicon substrate 1. The multilayer capacitor structure includes at least one layer consisting of a bottom electrode 3, a dielectric layer 4, and a top electrode 5. The bottom electrode 3 covers the bottom and side surfaces of the trench network 2 and the front side of the silicon substrate 1. The dielectric layer 4 covers the bottom electrode 3. The top electrode 5 fills the trench network 2 and covers the dielectric layer 4. The bottom electrode 3 is electrically connected to the silicon substrate 1. The first front electrode 6 and the second front electrode 7 are disposed on the front side of the multilayer capacitor structure and are electrically connected to the top electrode 5 and the bottom electrode 3, respectively. The back electrode 8 is disposed on the back side of the silicon substrate 1 and is electrically connected to the silicon substrate 1.
[0024] Specifically, silicon substrate 1 refers to a substrate made of single-crystal silicon material. In this embodiment of the invention, silicon substrate 1 is a heavily doped silicon substrate for conductivity. Trench network 2 refers to multiple groove structures formed on the front side of silicon substrate 1 through an etching process. Stacked capacitor structure is a MIM (Metal-Insulator-Metal) capacitor structure. In this embodiment of the invention, it refers to a capacitor unit composed of bottom electrode 3, dielectric layer 4, and top electrode 5. Electrical connection refers to the ability of two components to conduct current.
[0025] For capacitors with traditional horizontal electrode arrangements, flip-chip soldering is typically used to solder the capacitor to the circuit board to reduce the circuit board area. When the capacitor has multiple circuit connections, additional traces or solder joints need to be provided on the circuit board to achieve these connections. However, this increases the circuit board area, hindering the miniaturization of electronic devices. To further reduce the circuit board area, this invention proposes a three-electrode silicon capacitor structure to reduce the circuit board area and thus achieve miniaturization of electronic devices.
[0026] The electrical path of a three-electrode silicon capacitor structure includes a first transmission path and a second transmission path, which are independent of each other. The first transmission path is formed by the top electrode 5 being directly electrically connected to the first front electrode 6. Figure 2 The via connecting the top electrode 5 and the first front electrode 6 is not shown. The second transmission path is formed by the second front electrode 7 being directly electrically connected to the bottom electrode 3, and the bottom electrode 3 being electrically connected to the back electrode 8 through the electrically connected silicon substrate 1. Therefore, the second front electrode 7 and the back electrode 8 are electrically at the same potential, and they are connected to the same plate of the capacitor, namely the bottom electrode 3. The first front electrode 6 is connected to the other plate of the capacitor, namely the top electrode 5.
[0027] In this embodiment of the invention, a trench network 2 is formed by etching on the front side of a silicon substrate 1. With consistent dielectric material and dielectric withstand voltage, the originally flat two-dimensional surface is transformed into a three-dimensional structure. This means the effective area for forming the capacitor is no longer the planar projected area of the silicon substrate 1, but rather the sum of the surface areas of the bottom and side surfaces of all the trenches. This achieves a larger effective surface area per unit area, significantly improving capacitance density. Furthermore, the second front electrode 7 and the back electrode 8 are electrically equipotential, meaning the back electrode 8 shares potential with the front electrode through the silicon substrate 1. Compared to traditional horizontal electrode arrangements, the three-electrode design of the three-electrode silicon capacitor structure provides more possibilities for circuit connections, improving circuit connection flexibility. This helps reduce the number of pre-reserved traces or solder joints on the circuit board when multiple lines are connected, laying the foundation for saving circuit board wiring space and thus facilitating the miniaturization of electronic devices or systems.
[0028] In some embodiments, the aspect ratio of a single trench in the trench network 2 is greater than or equal to 10:1.
[0029] Specifically, taking a cylindrical trench as an example, the depth-to-width ratio is the ratio of the depth of a single trench to the diameter of the circular cross-section. Setting the depth-to-width ratio of a single trench in the trench network 2 to be greater than or equal to 10:1, preferably 50:1 or 60:1, can further increase the sidewall area of the trench network 2 within a limited planar projected area, thereby achieving a larger effective surface area per unit area, maximizing the effective area of the capacitor, and further improving the capacitance density of the capacitor.
[0030] In some embodiments, the vertical cross-sectional shape of a single trench in the trench network 2 is rectangular or spiral.
[0031] Specifically, the vertical cross-sectional shape refers to the cross-sectional profile shape obtained by cutting a single trench with a plane perpendicular to the surface of the silicon substrate 1, corresponding to the geometric characteristics of the single trench in the depth direction. When the single trench is a columnar trench, such as... Figure 2 As shown, the vertical cross-sectional shape of a single trench is rectangular. For example, but not limited to, anisotropic etching processes, such as deep reactive ion etching, can be used to fabricate columnar trenches. The increase in surface area depends on the depth and perimeter of the individual trench. The surface area can be linearly increased by increasing the aspect ratio.
[0032] The vertical cross-section of a single spiral trench corresponds to a continuous, smooth helical curve. A single trench extends along a meandering path within the silicon substrate 1, rather than sinking in a straight line. This can be achieved by optimizing the etching process, such as modulating etching parameters. The meandering path of the spiral trench results in a trench perimeter per unit projected area that is much larger than that of a straight rectangular trench. At the same depth and area, the spiral trench provides a larger surface area due to its longer effective perimeter, overcoming the linear growth limitation of rectangular trenches and further increasing the capacitance density of the capacitor.
[0033] For example, the vertical cross-sectional shape of a single trench in the trench network 2 can also be circular, polygonal, conical, etc., with polygons including, but not limited to, pentagons and hexagons, and the tip of the cone pointing towards the silicon substrate 1. It should be noted that the foregoing embodiments only exemplify the vertical cross-sectional shape of a single trench in the trench network 2, and the embodiments of the present invention do not specifically limit the vertical cross-sectional shape of a single trench in the trench network 2.
[0034] In some embodiments, the multilayer capacitor structure includes a vertically stacked multilayer structure, wherein the top electrode 5 of the multilayer structure is reused as the bottom electrode 3 of the next layer of the multilayer structure.
[0035] Figure 3This is a cross-sectional schematic diagram of another three-electrode silicon capacitor structure provided by the present invention. Figure 2 An exemplary configuration of the multilayer capacitor structure includes a single layer consisting of a bottom electrode 3, a dielectric layer 4, and a top electrode 5. Alternatively, the multilayer capacitor structure may include vertically stacked multilayer structures, where the top electrode 5 of the multilayer structure is reused as the bottom electrode 3 of the next layer of the multilayer structure. Figure 3 An exemplary multilayer capacitor structure is shown, comprising two layers consisting of a bottom electrode, a dielectric layer, and a top electrode. Even-numbered electrode layers are electrically connected to a first front electrode 6 via electrode interconnects, and odd-numbered electrode layers are electrically connected to a second front electrode 7 via electrode interconnects.
[0036] Specifically, such as Figure 3 As shown, after completing the first layer stack structure of bottom electrode-dielectric layer-top electrode, the top electrode is used as the bottom electrode of the second layer stack structure. That is, the top electrode is reused as the bottom electrode of the next layer stack structure, and the dielectric layer and top electrode of the second layer stack structure are deposited. The first layer stack structure includes the bottom electrode layer 10, the first dielectric layer 11, and the intermediate electrode layer 12. The second layer stack structure includes the intermediate electrode layer 12, the second dielectric layer 13, and the top electrode layer 14. The electrical path of the three-electrode silicon capacitor structure also includes independent first and second transmission paths. The first transmission path is the path formed by the intermediate electrode 12 directly connected to the first front electrode 6, and the second transmission path is the path formed by the second front electrode 7 directly connected to the bottom electrode layer 10 and the top electrode layer 14. Figure 3 The via connecting the second front electrode 7 and the top electrode layer 14 is not shown in the diagram. The bottom electrode layer 10 is then electrically connected to the back electrode 8 through the electrically connected silicon substrate 1.
[0037] By setting the top and bottom electrodes of adjacent stacked structures to share the same conductive layer, and alternately connecting odd-numbered and even-numbered layer electrodes to the first front electrode 6 and the second front electrode 7 respectively, parallel connection of multilayer capacitor structures is achieved. Figure 3 Taking the illustrated double-layer structure as an example, the bottom electrode layer 10 of the odd-numbered layers is connected to the second front electrode 7, the multiplexed intermediate electrode layer 12 of the even-numbered layers is connected to the first front electrode 6, and the top electrode layer 14 of the odd-numbered layers is connected to the second front electrode 7. Figure 3 The electrode interconnect vias for connecting the top electrode layer 14 and the second front electrode 7 are not shown. Thus, two capacitor units—one consisting of the bottom electrode layer 10, the first dielectric layer 11, and the intermediate electrode layer 12, and the other consisting of the intermediate electrode layer 12, the second dielectric layer 13, and the top electrode layer 14—are connected in parallel. The total capacitance after parallel connection is the sum of the capacitances of each layer, thereby significantly increasing the total capacitance value without increasing the chip area.
[0038] Therefore, this invention utilizes a multi-layer stacked structure, overcoming the limitations of a two-dimensional plane. Without increasing the capacitor's footprint, it multiplies the total capacitance by increasing the number of vertical layers, providing an effective way to achieve ultra-high capacitance density. Electrode reuse reduces the required number of independent layers, simplifies the stacked structure, and makes the silicon capacitor structure compact. Through alternating odd and even connections, parallel connection of all capacitor units is efficiently achieved. It should be noted that the stacked capacitor structure can include three or more layers. The electrical connection relationship satisfies the following: odd-numbered layer electrodes are shorted, even-numbered layer electrodes are shorted, odd-numbered layer electrodes are electrically connected to one front electrode and one back electrode, and even-numbered layer electrodes are electrically connected to the other front electrode. Specific expansion methods can be repeated. Figure 3 The extension methods of the structure shown will not be elaborated here.
[0039] In some embodiments, the material constituting the bottom electrode 3 includes at least one of conductive polycrystalline silicon, a metal, or a metal nitride, and the material constituting the top electrode 5 includes at least one of conductive polycrystalline silicon, a metal, or a metal nitride.
[0040] Specifically, conductive polycrystalline silicon refers to polycrystalline silicon material with good conductivity after doping. Since the bottom electrode 3 is in contact with the silicon substrate 1, the silicon substrate 1 can be directly doped to form heavily doped conductive regions on the surface of the trench network 2 and the front side of the silicon substrate 1, thus constituting the bottom electrode 3. Exemplarily, the top electrode 5 can also be formed by doping the silicon dielectric layer; that is, the material constituting the top electrode 5 can also be conductive polycrystalline silicon. When the top electrode 5 or the bottom electrode 3 is made of metal, ruthenium is preferred, as it has the advantages of high dielectric constant, dielectric friendliness, and good conductivity, and low resistance, which is beneficial for improving the frequency characteristics of the capacitor. When the top electrode 5 or the bottom electrode 3 is made of nitride, tantalum nitride is preferred, as it also has the advantages of high dielectric constant, dielectric friendliness, and good conductivity, and good stability. In some embodiments, the material constituting the dielectric layer 4 includes at least one of hafnium oxide, zirconium oxide, or strontium titanate.
[0041] Specifically, high dielectric constant dielectric materials refer to insulating materials with a relative dielectric constant higher than that of silicon dioxide. In this embodiment of the invention, high dielectric constant dielectric materials such as hafnium oxide, zirconium oxide, or strontium titanate are used instead of traditional silicon dioxide or silicon nitride. Since capacitance is directly proportional to the dielectric constant of the dielectric material, high dielectric constant dielectric materials can provide a larger capacitance value with the same physical thickness, or a thicker physical layer for the same capacitance requirement, thereby significantly improving the capacitance density and voltage withstand reliability of the capacitor. Exemplarily, the material constituting dielectric layer 4 may include at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or strontium titanate; this embodiment of the invention does not specifically limit the material constituting dielectric layer 4.
[0042] This invention also provides a method for fabricating a three-electrode silicon capacitor structure. Figure 4 This is a schematic flowchart illustrating a method for fabricating a three-electrode silicon capacitor structure according to the present invention. The method for fabricating the three-electrode silicon capacitor structure can be used to fabricate the three-electrode silicon capacitor structure described in the above embodiments. Figure 4 As shown, the fabrication method of the three-electrode silicon capacitor structure includes the following steps: Step 101: Provide a silicon substrate and form a trench network on the front side of the silicon substrate through an etching process.
[0043] Specifically, Figures 5 to 11 This is a cross-sectional structural diagram of each step in the fabrication method of a three-electrode silicon capacitor structure. For example... Figure 5 As shown, multiple trenches are formed on the silicon substrate 1 by semiconductor etching process. The multiple trenches constitute the trench network 2. The semiconductor etching process can be dry etching process or wet etching process. The formation of the trench network 2 provides a physical basis for achieving high capacitance density. The depth, shape and distribution of a single trench directly determine the final performance of the capacitor.
[0044] Step 102: Form a bottom electrode on the front side of the silicon substrate, so that the bottom electrode covers the bottom and side surfaces of the trench network and the front side of the silicon substrate.
[0045] Specifically, such as Figure 6 As shown, a bottom electrode 3 is formed on the front side of a silicon substrate 1 with a trench network 2. The bottom electrode 3 covers the bottom surface, side surface and top surface of the trench outer structure. The bottom electrode 3 is a continuous and complete electrode layer, which provides the basis for the subsequent fabrication of the dielectric layer and the top electrode.
[0046] In some embodiments, forming a bottom electrode 3 on the front side of the silicon substrate 1 includes: doping the silicon substrate 1 to form heavily doped conductive regions on the surface of the trench network 2 and the front side of the silicon substrate 1 to constitute the bottom electrode 3.
[0047] Doping refers to the process of introducing impurity ions into a semiconductor material to change its conductivity type. Heavily doped conductive regions refer to low-resistance regions formed through high-concentration doping. By selectively performing high-concentration ion doping on the silicon substrate 1, the surface of the trench and the surrounding silicon substrate 1 are transformed from a semiconductor into a good conductor, thus directly utilizing the heavily doped silicon itself as the bottom electrode 3 of the capacitor. This method eliminates the need for additional conductive layer deposition, simplifying the process steps and reducing manufacturing costs. Simultaneously, the formed bottom electrode 3 is naturally integrated with the silicon substrate 1, providing excellent ohmic contact and high reliability.
[0048] In some embodiments, the bottom electrode 3 can also be prepared by chemical vapor deposition, physical vapor deposition or atomic layer deposition.
[0049] Chemical vapor deposition (CVD) refers to a process in which gaseous raw materials undergo a chemical reaction on a substrate surface and are deposited into a solid thin film. Physical vapor deposition (PVD) refers to a process in which materials are transferred from a source to a substrate surface using physical methods such as evaporation or sputtering to form a thin film. Atomic layer deposition (ALD) refers to a process in which different gaseous precursors are alternately introduced, and thin films are deposited layer by layer through self-limiting surface reactions. CVD, PVA, and ALD can all be used to fabricate bottom electrodes 3 made of materials such as conductive polycrystalline silicon, metals, or metal nitrides. ALD is preferred for fabricating bottom electrodes 3, especially suitable for covering electrode films with good conformal properties for high aspect ratio trenches, and is key to realizing high-performance three-dimensional capacitor structures.
[0050] Step 103: Deposit a dielectric layer on the bottom electrode.
[0051] Specifically, such as Figure 7 As shown, the dielectric layer 4 can be prepared by chemical vapor deposition, physical vapor deposition or atomic layer deposition. A high-quality dielectric layer 4 is the core of the normal operation of the capacitor. It determines the capacitor's withstand voltage, leakage current performance and reliability. A uniform dielectric layer 4 is the key to obtaining consistent capacitance performance.
[0052] Step 104: Form a top electrode on the dielectric layer, and fill the trench network with the top electrode.
[0053] Specifically, such as Figure 8 As shown, the top electrode 5 is fabricated using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The top electrode 5 and the bottom electrode 3 are sandwiched together with a dielectric layer 4, forming a capacitor structure. The top electrode 5 fills the trench network 2, ensuring that the dielectric layer 4 on all surfaces within the trenches is utilized, thereby maximizing the capacitance value.
[0054] Step 105: Etch the top electrode to expose part of the bottom electrode.
[0055] Specifically, such as Figure 9 As shown, the top electrode 5 is processed by semiconductor etching process to remove part of the top electrode 5 to expose the bottom electrode 3, in preparation for leading out the front electrode.
[0056] Step 106: Form an insulating layer on the top electrode and etch the insulating layer to form a first through hole exposing the bottom electrode and a second through hole exposing the top electrode; wherein the etched insulating layer covers the sidewall of the first through hole.
[0057] Specifically, such as Figure 10As shown, an insulating layer 9 is prepared using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The insulating layer 9 serves as passivation and isolation. The first via 15 and the second via provide vertical channels for connecting the front electrode to the bottom electrode 3 and the top electrode 5, respectively. The etched insulating layer 9 covers the sidewall of the first via to initially limit short circuits between the top electrode 5 and the bottom electrode 3. Furthermore, Figure 10 The second through hole is not shown in the diagram. It can be understood that the second through hole is located in a non- Figure 10 The corresponding cross-sectional position penetrates the insulating layer 9 to expose the upper surface of the top electrode.
[0058] Step 107: Form an electrode layer on the insulating layer and etch the electrode layer to form a second front electrode that fills the first through-hole and a first front electrode that fills the second through-hole.
[0059] Specifically, such as Figure 11 As shown, the second front electrode 7 is electrically connected to the bottom electrode 3 by filling the first through hole, and the first front electrode 6 is electrically connected to the top electrode 5 by filling the second through hole. This completes the fabrication and lead-out of the two front electrodes of the capacitor, realizing the function of interconnecting the capacitor with the external circuit.
[0060] Step 108: Form a back electrode on the back side of the silicon substrate.
[0061] Specifically, such as Figure 2 As shown, the third electrode of the capacitor is the back electrode 8. This back electrode 8 provides a common terminal or ground terminal through electrical connection with the silicon substrate 1 and the bottom electrode 3, and together with the two front electrodes, it forms a three-electrode structure.
[0062] This invention also provides an electronic device including the three-electrode silicon capacitor structure described in the above embodiments, thus possessing the beneficial effects described in the above embodiments, which will not be repeated here. Exemplarily, the electronic device includes, but is not limited to, a pressure sensor.
[0063] The three-electrode silicon capacitor structure is mounted on the circuit board of an electronic device using a flip-chip bonding method; wherein, the back electrode 8 is bonded to the circuit board via wire bonding. Flip-chip bonding refers to placing the front side of the three-electrode silicon capacitor structure facing down towards the circuit board and bonding it to the circuit board via wire bonding. Bonding refers to forming electrical and mechanical connections through methods such as soldering and eutectic bonding. This invention applies the three-electrode silicon capacitor structure to electronic devices. The three-electrode silicon capacitor structure is mounted using a flip-chip bonding method, with its back electrode 8 bonded to, for example, a ground pad on the circuit board via wire bonding, while the two front electrodes are connected to signal lines on the circuit board via other bumps on the circuit board. This fully utilizes the advantages of the three-electrode structure; the back electrode 8 is directly grounded, providing an excellent low-impedance grounding path for the circuit, while saving wiring space reserved on the front side of the circuit board for grounding connections, greatly promoting the miniaturization and high performance of electronic devices.
[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A three-electrode silicon capacitor structure, characterized in that, include: A silicon substrate, wherein a trench network is formed on the front side of the silicon substrate; A stacked capacitor structure is disposed within the trench network and on the front side of the silicon substrate. The stacked capacitor structure includes at least one stacked structure composed of a bottom electrode, a dielectric layer, and a top electrode. The bottom electrode covers the bottom and side surfaces of the trench network and the front side of the silicon substrate. The dielectric layer covers the bottom electrode. The top electrode fills the trench network and covers the dielectric layer. The bottom electrode is electrically connected to the silicon substrate. The first front electrode and the second front electrode are disposed on the front side of the stacked capacitor structure and are electrically connected to the top electrode and the bottom electrode, respectively. The back electrode is disposed on the back side of the silicon substrate and is electrically connected to the silicon substrate.
2. The three-electrode silicon capacitor structure according to claim 1, characterized in that, The aspect ratio of a single trench in the trench network is greater than or equal to 10:
1.
3. The three-electrode silicon capacitor structure according to claim 1, characterized in that, The vertical cross-sectional shape of a single trench in the trench network can be circular, polygonal, conical, rectangular, or spiral.
4. The three-electrode silicon capacitor structure according to claim 1, characterized in that, The stacked capacitor structure includes multiple stacked layers in a vertical direction, wherein the top electrode of the stacked structure is reused as the bottom electrode of the next stacked structure; The even-numbered layer electrodes are electrically connected to the first front electrode through electrode interconnect holes, and the odd-numbered layer electrodes are electrically connected to the second front electrode through electrode interconnect holes.
5. The three-electrode silicon capacitor structure according to any one of claims 1-4, characterized in that, The material constituting the bottom electrode includes at least one of conductive polycrystalline silicon, metal, or metal nitride, and the material constituting the top electrode includes at least one of conductive polycrystalline silicon, metal, or metal nitride.
6. The three-electrode silicon capacitor structure according to any one of claims 1-4, characterized in that, The material constituting the dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or strontium titanate.
7. A method for fabricating a three-electrode silicon capacitor structure, characterized in that, The method for fabricating a three-electrode silicon capacitor structure as described in any one of claims 1-6 includes: A silicon substrate is provided, and a trench network is formed on the front side of the silicon substrate by an etching process; A bottom electrode is formed on the front side of the silicon substrate, such that the bottom electrode covers the bottom and side surfaces of the trench network and the front side of the silicon substrate; A dielectric layer is deposited on the bottom electrode; A top electrode is formed on the dielectric layer, and the top electrode fills the trench network; Etch the top electrode to expose a portion of the bottom electrode; An insulating layer is formed on the top electrode, and the insulating layer is etched to form a first through hole exposing the bottom electrode and a second through hole exposing the top electrode; wherein the etched insulating layer covers the sidewall of the first through hole; An electrode layer is formed on the insulating layer, and the electrode layer is etched to form a first front electrode that fills the first through-hole and a second front electrode that fills the second through-hole; A back electrode is formed on the back side of the silicon substrate.
8. The method for fabricating a three-electrode silicon capacitor structure according to claim 7, characterized in that, The process of forming a bottom electrode on the front side of the silicon substrate includes: The silicon substrate is doped to form heavily doped conductive regions on the surface of the trench network and the front side of the silicon substrate, thereby forming the bottom electrode.
9. The method for fabricating a three-electrode silicon capacitor structure according to claim 7, characterized in that, The bottom electrode is prepared by chemical vapor deposition, physical vapor deposition, or atomic layer deposition; the top electrode is prepared by chemical vapor deposition, physical vapor deposition, or atomic layer deposition; and the dielectric layer is prepared by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
10. An electronic device, characterized in that, The device includes a three-electrode silicon capacitor structure as described in any one of claims 1-6, wherein the three-electrode silicon capacitor structure is mounted on the circuit board of the electronic device by flip-chip bonding; wherein the back electrode is wire-bonded to the circuit board.