Capacitor structure and forming method thereof

Abstract

The invention provides a capacitor structure and a forming method thereof. The method comprises the following steps: forming a first metal pole plate; forming a first titanium nitride layer on the first metal pole plate, wherein the thermal expansion coefficient of the first titanium nitride layer is smaller than that of the first metal pole plate; a medium lamination layer is formed on the first titanium nitride layer, all layers in the medium lamination layer are nitrogen-containing material layers, the thermal expansion coefficient of the nitrogen-containing material layers is smaller than that of the first titanium nitride layer, and the thermal expansion coefficients are increased layer by layer from a middle sub-layer of the medium lamination layer to an edge sub-layer of the medium lamination layer; forming a second titanium nitride layer on the dielectric lamination layer, wherein the thermal expansion coefficient of the second titanium nitride layer is greater than that of all layers in the dielectric lamination layer; and forming a second metal pole plate on the second titanium nitride layer, wherein the thermal expansion coefficient of the second metal pole plate is greater than that of the second titanium nitride layer. By adopting the scheme, the quality of the capacitor structure can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a capacitor structure and a forming method thereof. BACKGROUND

[0002] In the semiconductor manufacturing process, the thickness of the dielectric layer of the MIM capacitor has approached the physical limit, and has decreased to the order of several atomic layers. At this dimension, any slight thickness deviation of the dielectric layer will cause a significant fluctuation of the capacitance value. At the nanoscale dielectric layer, such fluctuation is sharply amplified, resulting in a discrete distribution of the capacitance value within the wafer and between wafers, which seriously restricts the performance consistency and manufacturing yield of precision circuits such as data converters and filters.

[0003] The MIM capacitor is stacked by metal plates and oxide / nitride dielectric layers and other materials, and the mismatch of the thermal expansion coefficients between the layers of materials constitutes an inherent reliability challenge. In subsequent thermal cycle processes such as annealing and packaging, the accumulated thermal stress will cause the dielectric layer to deform, warp, and even crack. Such microstructure damage not only causes long-term drift of the capacitance value, but also can form a conductive path, causing a sharp rise in the leakage current, which poses a serious threat to the long-term reliability of the device.

[0004] Therefore, how to provide a technical solution to improve the quality of the capacitor structure has become a technical problem to be solved. SUMMARY

[0005] Therefore, the embodiments of the present application provide a capacitor structure and a forming method thereof, which can improve the quality of the capacitor structure.

[0006] To solve the above technical problems, the embodiments of the present application provide a forming method of a capacitor structure, which comprises: forming a first metal plate; forming a first titanium nitride layer on the first metal plate, the thermal expansion coefficient of the first titanium nitride layer being less than the thermal expansion coefficient of the first metal plate; forming a dielectric stack on the first titanium nitride layer, all layers in the dielectric stack being nitrogen-containing material layers, and the thermal expansion coefficients of all layers being less than the thermal expansion coefficient of the first titanium nitride layer, wherein the thermal expansion coefficient increases layer by layer from the middle sublayer of the dielectric stack to the edge sublayer of the dielectric stack; forming a second titanium nitride layer on the dielectric stack, the thermal expansion coefficient of the second titanium nitride layer being greater than the thermal expansion coefficients of all layers in the dielectric stack; and forming a second metal plate on the second titanium nitride layer, the thermal expansion coefficient of the second metal plate being greater than the thermal expansion coefficient of the second titanium nitride layer.

[0007] Optionally, the first and second titanium nitride layers satisfy one or more of the following: the first and second titanium nitride layers are formed by a physical vapor deposition process; the process for forming the first and second titanium nitride layers uses an argon and nitrogen flow ratio in a range of 10:1 to 6:1; and the working pressure in the process for forming the first and second titanium nitride layers is 3 to 6 mTorr.

[0008] Optionally, the step of forming the dielectric stack includes: forming a first dielectric layer covering the first titanium nitride layer; forming a second dielectric layer covering the first dielectric layer; and forming a third dielectric layer covering the second dielectric layer; wherein the third dielectric layer is made of the same material as the first dielectric layer.

[0009] Optionally, the method satisfies one or more of the following: the first dielectric layer is made of silicon oxynitride or silicon carbonitride; the second dielectric layer is made of silicon oxynitride or silicon nitride; and the third dielectric layer is made of silicon oxynitride or silicon carbonitride.

[0010] Optionally, the method further includes: forming a first adhesion barrier layer covering the first metal plate; and forming a second adhesion barrier layer covering the second titanium nitride layer and in contact with the second metal plate.

[0011] Optionally, the first and second adhesion barrier layers are made of one or more of titanium, tantalum, cobalt, ruthenium, and molybdenum.

[0012] Optionally, the second metal plate is smaller than the first metal plate, and the second metal plate is parallel to the first metal plate; wherein the first metal plate further includes: an electrode region including a plug structure connected to an electrode of the capacitor structure.

[0013] Optionally, the method satisfies one or more of the following: the capacitor structure is a MIM structure; and the first metal plate is made of the same material as the second metal plate.

[0014] The embodiment of the present application also provides a capacitor structure, comprising: a first metal plate; a first titanium nitride layer located on the first metal plate, and the thermal expansion coefficient of the first titanium nitride layer is less than the thermal expansion coefficient of the first metal plate; a dielectric stack covering the first titanium nitride layer, all layers in the dielectric stack are nitrogen-containing material layers, and the thermal expansion coefficients of all layers are less than the thermal expansion coefficient of the first titanium nitride layer, wherein the thermal expansion coefficient increases layer by layer from the middle sublayer of the dielectric stack to the edge sublayer of the dielectric stack; a second titanium nitride layer covering the dielectric stack, the thermal expansion coefficient of the second titanium nitride layer is greater than the thermal expansion coefficients of all layers in the dielectric stack; and a second metal plate covering the second titanium nitride layer, the thermal expansion coefficient of the second metal plate is greater than the thermal expansion coefficient of the second titanium nitride layer.

[0015] Optionally, the dielectric stack at least comprises: a first dielectric layer covering the first titanium nitride layer; a second dielectric layer covering the first dielectric layer; and a third dielectric layer covering the second dielectric layer, wherein the material of the third dielectric layer is the same as the material of the first dielectric layer.

[0016] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages: The capacitor structure and the forming method thereof provided by the embodiment of the present application have the following advantages: the method comprises: forming a first metal plate and a second metal plate, and forming a structure of a first titanium nitride layer and a second titanium nitride layer sandwiching a dielectric stack between the first metal plate and the second metal plate, and the thermal expansion coefficient of the overall structure of the first metal plate, the second metal plate, the first titanium nitride layer, the second titanium nitride layer and the dielectric stack decreases layer by layer from the first metal plate and the second metal plate to the middle dielectric stack. The method fundamentally improves the quality of the capacitor structure by constructing a gradient stack structure with a gradually changing thermal expansion coefficient. First, the first titanium nitride layer with a medium thermal expansion coefficient is inserted between the first metal plate and the dielectric stack, and the nitrogen-containing material sublayers with the thermal expansion coefficient increasing layer by layer from the middle to the edge are designed in the dielectric stack, and then the second titanium nitride layer is used to transit to the second metal plate with a high thermal expansion coefficient, so that the concentrated stress caused by the thermal mismatch of materials in the traditional structure is dispersed to multiple interfaces, the deformation and cracking of the dielectric layer are effectively inhibited, and the integrity of the structure is ensured. At the same time, the use of the nitrogen-containing material layer and the titanium nitride transition layer enhances the interface stability and process compatibility, reduces the dielectric thickness sensitivity and defect density. Finally, the design cooperatively optimizes the precision of the capacitance value, the breakdown voltage and the leakage performance under the premise of maintaining high capacitance density, and systematically solves the inherent contradiction between the capacitance density, reliability and yield under the nanoscale node. Therefore, the capacitor structure and the forming method thereof can improve the quality of the capacitor structure. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application or the prior art description. Obviously, the following described drawings are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0018] Figure 1 is a flowchart of a method for forming a capacitor structure in an embodiment of the present application; Figures 2 to 6 is a structure diagram corresponding to part of steps in a method for forming a capacitor structure in an embodiment of the present application; Figures 7 to 8 is a structure diagram corresponding to part of steps in another method for forming a capacitor structure in an embodiment of the present application; Figure 9 is a cross-sectional view of a capacitor structure in an embodiment of the present application.

[0019] Explanation of reference signs: substrate 200, first metal plate slot 201a, first metal plate 201, first titanium nitride layer 202a, second titanium nitride layer 202b, dielectric stack 203, first dielectric layer 203a, second dielectric layer 203b, third dielectric layer 203c, second metal plate 204, plug structure 205, first electrode slot 206a, second electrode slot 207a, first electrode plate 206, second electrode plate 207; first filling medium 210, second filling medium 211, third filling medium 212, fourth filling medium 213. DETAILED DESCRIPTION

[0020] The technical solutions of the present application will be described in detail below in combination with specific embodiments and drawings. The embodiments described herein are specific specific embodiments of the present application, which are used to illustrate the concept of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. These descriptions are explanatory and exemplary, and should not be understood as limiting the embodiments of the present application and the protection scope of the present application. In addition to the embodiments described herein, those skilled in the art can also obtain other technical solutions based on the disclosure of the claims and the description of the present application, which include technical solutions that make any obvious substitutions and modifications to the embodiments described herein.

[0021] It is to be noted that the drawings in the embodiments are schematic and are used to assist in illustrating the concept of the present application and schematically represent the shape and mutual relationship of the parts. It should be understood that, in order to clearly show the structure of the components of the present application, the drawings are not drawn according to the same scale, and the same reference numerals are used to represent the same parts in the drawings.

[0022] In the semiconductor manufacturing process, the thickness of the dielectric layer of the MIM capacitor has approached the physical limit, and is reduced to the order of several atomic layers. At this dimension, any slight thickness deviation of the dielectric layer will cause a significant fluctuation of the capacitance value. At the nanoscale dielectric layer, such fluctuation is sharply amplified, resulting in a discrete distribution of the capacitance value within and between wafers, which seriously restricts the performance consistency and manufacturing yield of precision circuits such as data converters and filters.

[0023] The MIM capacitor is stacked by metal plates and oxide / nitride dielectric layers and other materials, and the mismatch of the thermal expansion coefficients between the materials of the layers constitutes an inherent reliability challenge. In subsequent thermal cycle processes such as annealing and packaging, the accumulated thermal stress will cause the dielectric layer to deform, warp and even crack. Such microstructure damage not only causes long-term drift of the capacitance value, but also can form a conductive path, causing a sharp rise in the leakage current, which seriously threatens the long-term reliability of the device.

[0024] Therefore, how to provide a technical solution to improve the quality of the capacitor structure has become a technical problem to be solved.

[0025] To solve the above technical problems, the capacitor structure and the forming method thereof provided by the embodiment of the present application, the method comprises: forming a first metal plate and a second metal plate, forming a structure of a first titanium nitride layer and a second titanium nitride layer sandwiching a dielectric stack between the first metal plate and the second metal plate, and the overall structure of the first metal plate, the second metal plate, the first titanium nitride layer, the second titanium nitride layer and the dielectric stack gradually decreases in the coefficient of thermal expansion from the first metal plate and the second metal plate to the dielectric stack in the middle. The method fundamentally improves the quality of the capacitor structure by constructing a gradient stack structure with a gradually changing coefficient of thermal expansion. First, the first titanium nitride layer with a medium coefficient of thermal expansion is inserted between the first metal plate and the dielectric stack, and the sublayer of the nitrogen-containing material with the coefficient of thermal expansion gradually increasing from the middle to the edge is designed inside the dielectric stack, and then the second titanium nitride layer is used to transit to the second metal plate with a high coefficient of thermal expansion, so that the concentrated stress caused by the thermal mismatch of the materials in the traditional structure is dispersed to multiple interfaces, the deformation and cracking of the dielectric layer are effectively inhibited, and the integrity of the structure is ensured. At the same time, the use of the nitrogen-containing material layer and the titanium nitride transition layer enhances the interface stability and process compatibility, reduces the dielectric thickness sensitivity and defect density. Finally, the design cooperatively optimizes the precision of the capacitance value, the breakdown voltage and the leakage performance under the premise of maintaining high capacitance density, and systematically solves the inherent contradiction between the capacitance density, reliability and yield under the nanoscale node. Therefore, the capacitor structure and the forming method thereof can improve the quality of the capacitor structure.

[0026] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0027] Reference Figure 1 , Figure 1 is a flowchart of a forming method of a capacitor structure in the embodiment of the present application. The method can perform the following steps S101 to S105.

[0028] In step S101, a first metal plate is formed.

[0029] In step S102, a first titanium nitride layer is formed on the first metal plate, and the coefficient of thermal expansion of the first titanium nitride layer is less than the coefficient of thermal expansion of the first metal plate.

[0030] In step S103, a dielectric stack is formed on the first titanium nitride layer, all layers in the dielectric stack are nitrogen-containing material layers, and the coefficients of thermal expansion of all layers are less than the coefficient of thermal expansion of the first titanium nitride layer, wherein the coefficient of thermal expansion gradually increases from the middle sublayer of the dielectric stack to the edge sublayer of the dielectric stack.

[0031] In step S104, a second titanium nitride layer is formed on the dielectric stack, the second titanium nitride layer having a thermal expansion coefficient greater than the thermal expansion coefficients of all layers in the dielectric stack.

[0032] In step S105, a second metal plate is formed on the second titanium nitride layer, the second metal plate having a thermal expansion coefficient greater than the thermal expansion coefficient of the second titanium nitride layer.

[0033] The above method is described below. Figures 2 to 8 The above method is described below.

[0034] Reference is made to Figures 2 to 6 , Figures 2 to 6 is a structure diagram corresponding to part of steps in a capacitor structure formation method in an embodiment of the present application.

[0035] Reference is made to Figure 2 , Figure 2 is a cross-sectional view of a semiconductor structure.

[0036] A substrate 200 is provided.

[0037] The substrate 200 is used to provide a process platform for the formation of a capacitor structure.

[0038] The substrate includes, from bottom to top, a semiconductor base, an isolation layer, a transistor gate and source / drain, an interlayer dielectric layer, and a metal interconnection layer. The metal interconnection layer includes a contact pad for electrical connection with a lower electrode of a MIM capacitor. The substrate surface has a planarization surface formed by chemical mechanical polishing (CMP) to ensure uniformity of the layers of the MIM capacitor.

[0039] In this embodiment, the substrate 200 includes a semiconductor device structure that has completed previous processes, providing an integrated technology platform for the preparation of a capacitor. The substrate 200 includes a planarized interlayer dielectric layer, metal interconnection lines, and basic elements such as silicon-based transistors, forming a surface with specific topological features and electrical characteristics, providing a reliable mechanical support substrate for the deposition of the layers of the capacitor.

[0040] In some embodiments, the substrate 200 achieves electrical connection of the lower electrode with the underlying circuit through a pre-set contact via, thereby ensuring compatibility of the capacitor with existing semiconductor processes and stability of the performance of the final device.

[0041] The substrate 200 has a first metal plate slot 201a formed thereon.

[0042] Specifically, the step of forming the first metal plate slot 201a is as follows: A photoresist is coated, covering the initial substrate, which has a smooth and flat surface.

[0043] patterning the photoresist and etching a first metal plate slot 201a on the initial substrate to obtain a substrate 200; removing the photoresist.

[0044] Referring to Figure 2 and Figure 3 a first metal plate 201 is formed in the first metal plate slot 201a.

[0045] The first metal plate slot 201a is filled with a metal material, and the metal material is planarized to form the first metal plate 201.

[0046] Specifically, a barrier layer is formed, which covers the bottom and sidewall of the first metal plate slot 201a. The barrier layer is used to block the metal in the subsequently formed first metal plate 201, preventing the metal from diffusing into the substrate 200.

[0047] A first initial metal plate is formed, which fills the first metal plate slot 201a and covers the top surface of the substrate 200.

[0048] The first initial metal plate is planarized, and the first initial metal plate on the top surface of the substrate 200 is removed to obtain the first metal plate 201.

[0049] In this embodiment, before the barrier layer is formed, the surface of the substrate 200 is cleaned using Ar ion sputtering, i.e. the bottom and sidewall of the first metal plate slot 201a are cleaned.

[0050] The material of the barrier layer is selected from one or more combinations of titanium, tantalum, titanium nitride, and tantalum nitride. The barrier layer is used to block the metal in the first metal plate 201 from diffusing into the substrate 200, improving the thermal stability and long-term working reliability of the device in the substrate 200. The barrier layer can also act as an adhesion layer, enhancing the bonding force between the first metal plate 201 and the substrate 200, preventing the first metal plate 201 from delaminating and peeling off, and ensuring the mechanical integrity of the multi-layer structure.

[0051] In this embodiment, the first metal plate 201 is formed by a physical vapor deposition (PVD) method.

[0052] The material of the first metal plate 201 is selected from one or more combinations of copper, aluminum, and copper-aluminum alloy. In this embodiment, the material of the first metal plate 201 is copper-aluminum alloy.

[0053] In one embodiment, a physical vapor deposition method is used to deposit a copper-aluminum alloy layer on the substrate 200 to form the first metal plate 201, wherein the copper-aluminum alloy contains 0.5% of copper.

[0054] In some embodiments, a physical vapor deposition method is used to form a barrier layer and a metal layer on the substrate 200, a photoresist is spin-coated on the metal layer, a photolithography technique is used to define a pattern of the first metal plate 201, and a dry etching or wet etching method is used to remove the metal material and the barrier layer material outside the pattern. Finally, the remaining photoresist is removed to complete the preparation of the first metal plate 201. The plate has a flat surface morphology, which provides a good foundation for the subsequent deposition of the first titanium nitride layer.

[0055] In some embodiments, a seed layer is sputtered on the barrier layer, then copper is electroplated, and finally planarized to form the first metal plate 201.

[0056] Continuing to refer to Figure 3 A first adhesion barrier layer (not shown in the figure) is formed, which covers the first metal plate 201.

[0057] The first adhesion barrier layer is made of one or more of titanium, tantalum, cobalt, ruthenium, and molybdenum.

[0058] The first adhesion barrier layer acts as a dense barrier layer, which can effectively inhibit the atomic interdiffusion and interface chemical reaction between the first metal plate 201 and the subsequent insulating material, thereby avoiding the degradation of electrical performance and the decline of device reliability. Moreover, through its high chemical activity, the first adhesion barrier layer forms a stable chemical bond with the subsequently formed material and a strong metal bond with the first metal plate 201, thereby greatly enhancing the adhesion and mechanical integrity of the overall thin film structure and effectively preventing interface delamination.

[0059] In this embodiment, a physical vapor deposition (PVD) method is used to form the first adhesion barrier layer.

[0060] In one embodiment, a physical vapor deposition (PVD) method is used to deposit a titanium film on the substrate 200 to form the first adhesion barrier layer.

[0061] A first initial filling medium is formed, and a trench is formed on the first initial filling medium to obtain the first filling medium 210.

[0062] The trench exposes part of the first adhesion barrier layer at the bottom.

[0063] The position of the trench directly locates the position of the subsequent second metal plate. The width of the trench is less than the width of the first metal plate 201, so that the position above the first metal plate 201 without the trench can be used for forming a plug structure connected with the electrode.

[0064] The method for forming the trench can refer to the method for forming the first metal plate groove 201a, and other methods for forming the trench can also be adopted by those skilled in the art, which will not be described here.

[0065] The material of the first filling medium 210 can be selected from the combination of one or more of the following: silicon oxide, silicon nitride, and some materials doped with other materials in silicon oxide or silicon nitride (such as silicon carbon nitride, silicon oxynitride, etc.).

[0066] The trench provides process space for the formation of the subsequent medium stack.

[0067] A first titanium nitride layer 202a is formed on the first metal plate 201, and the thermal expansion coefficient of the first titanium nitride layer 202a is less than the thermal expansion coefficient of the first metal plate 201.

[0068] In some embodiments, the first titanium nitride layer 202a covers the first adhesion barrier layer, and the first titanium nitride layer 202a and the first adhesion barrier layer cover the entire top surface of the first metal plate 201.

[0069] In this embodiment, the first titanium nitride layer 202a is located at the bottom of the trench and covers the first adhesion barrier layer at the bottom of the trench.

[0070] In this embodiment, the first titanium nitride layer 202a is formed by a physical vapor deposition (PVD) method.

[0071] The material of the first titanium nitride layer 202a can be selected from the combination of one or more of the following: titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride. In this embodiment, the material of the first titanium nitride layer 202a is titanium nitride.

[0072] In a specific embodiment, a physical vapor deposition (PVD) method is used to form the first titanium nitride layer 202a, in which titanium is used as the target material, argon gas and nitrogen gas are introduced to bombard the target material, and a titanium nitride film is deposited to form the first titanium nitride layer 202a.

[0073] Specifically, the first titanium nitride layer 202a is formed by a physical vapor deposition process, and the flow ratio of argon gas to nitrogen gas used in the process for forming the first titanium nitride layer 202a is in the range of 10:1 to 6:1. The working pressure in the process for forming the first titanium nitride layer 202a is 3-6 mTorr.

[0074] The first titanium nitride layer 202a can serve as a barrier layer to prevent the diffusion of metal in the first metal electrode 201 and can also improve the electromigration of metal in the first metal electrode 201.

[0075] Among them, the first titanium nitride layer 202a serves as an interlayer between the first metal electrode and the dielectric stack. While achieving the anti-diffusion function, the accuracy of its thermal expansion coefficient is particularly important.

[0076] The working pressure can also be called the chamber pressure of the process chamber. By setting the appropriate chamber pressure and flow rate ratio, the required coefficient of thermal expansion of the first titanium nitride layer 202a can be effectively achieved.

[0077] See also Figure 3 A dielectric stack 203 is formed on the first titanium nitride layer 202a.

[0078] The multilayer structure of the dielectric stack 203 makes it more difficult for pinholes to form during subsequent heating and cooling processes, thus blocking the pinhole penetration channel and reducing the risk of leakage current formation.

[0079] The steps for forming the dielectric stack 203 include: A first dielectric layer 203a is formed covering the first titanium nitride layer 202a; A second dielectric layer 203b is formed to cover the first dielectric layer 203a; A third dielectric layer 203c is formed covering the second dielectric layer 203b.

[0080] The material of the third dielectric layer is the same as that of the first dielectric layer.

[0081] It should be noted that the dielectric stack 203 includes at least the first dielectric layer 203a, the second dielectric layer 203b, and the third dielectric layer 203c, and may also include a fourth dielectric layer, a fifth dielectric layer, a sixth dielectric layer, etc.

[0082] The coefficient of thermal expansion of all layers in the dielectric stack 203 is less than that of the first titanium nitride layer 202a, so that the first titanium nitride layer 202a can act as a transition bridge for the coefficient of thermal expansion in the dielectric stack 203, thereby reducing interface stress and improving the quality of the capacitor structure.

[0083] In this embodiment, the coefficient of thermal expansion increases layer by layer from the middle sublayer of the dielectric stack 203 to the edge sublayer of the dielectric stack 203. The edge sublayer is either the dielectric layer close to the first metal electrode 201 or the dielectric layer close to the second metal electrode formed subsequently.

[0084] In this embodiment, all layers in the dielectric stack 203 are nitrogen-containing material layers.

[0085] Specifically, the first dielectric layer 203a is made of silicon oxynitride or silicon carbonitride. The second dielectric layer 203b is made of silicon oxynitride or silicon nitride. The third dielectric layer 203c is made of silicon oxynitride or silicon carbonitride. In this embodiment, the first dielectric layer 203a is made of silicon oxynitride, the second dielectric layer 203b is made of silicon nitride, and the third dielectric layer 203c is made of silicon oxynitride.

[0086] The coefficient of thermal expansion of aluminum is 23 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of titanium nitride is 9.35 × 10⁻⁶. -6 At / ℃, the coefficient of thermal expansion of silicon nitride is approximately 3×10⁻⁶. -6 / ℃. The typical coefficient of thermal expansion for silicon oxynitride ranges from 0.5 to 2.5 × 10⁻⁶. -6 / ℃, its coefficient of thermal expansion is between that of silicon dioxide (0.5 × 10⁻⁶). -6 / ℃) and silicon nitride (2.8 ~ 3.2×10 -6 The coefficient of thermal expansion in silicon oxynitride (SNO) is between 2.5 and 4.5 × 10⁻⁶ °C. The higher the oxygen content, the lower the coefficient of thermal expansion; the higher the nitrogen content, the higher the coefficient of thermal expansion. Typical coefficients of thermal expansion for silicon carbonitride range from 2.5 to 4.5 × 10⁻⁶ °C. -6 Its coefficient of thermal expansion is typically between that of silicon nitride (2.8 ~ 3.2 × 10⁻⁶ °C). -6 / ℃) and silicon carbide (4.0 ~ 4.5×10 -6 The coefficient of thermal expansion is between 0.5°C and 0.6°C. The higher the carbon content of silicon carbonitride, the higher its coefficient of thermal expansion. By using the multilayer structure of the dielectric stack 203 and the metal layer, a gradual transition of the coefficient of thermal expansion is achieved from the metal layer to the dielectric layer, which can significantly alleviate the thermal stress during the cooling process of high temperature and suppress the warping or cracking of the dielectric layer.

[0087] In this embodiment, the dielectric stack 203 is formed by plasma-enhanced chemical vapor deposition.

[0088] See also Figure 3 A second titanium nitride layer 202b is formed on the dielectric stack 203.

[0089] The coefficient of thermal expansion of the second titanium nitride layer 202b is greater than that of all layers in the dielectric stack 203.

[0090] The second titanium nitride layer 202b covers the dielectric stack 203.

[0091] In this embodiment, the second titanium nitride layer 202b is formed using physical vapor deposition (PVD).

[0092] The material of the second titanium nitride layer 202b can be selected from one or more of the following: titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride. In this embodiment, the material of the second titanium nitride layer 202b is titanium nitride.

[0093] In one specific embodiment, a physical vapor deposition (PVD) method is used, with titanium as the target material, and argon and nitrogen gases are introduced to bombard the target material to deposit a titanium nitride film, forming the second titanium nitride layer 202b.

[0094] Specifically, the second titanium nitride layer 202b is formed using a physical vapor deposition process, wherein the argon to nitrogen flow ratio used in the process of forming the second titanium nitride layer 202b is in the range of 10:1 to 6:1. The working pressure in the process of forming the second titanium nitride layer 202b is 3 to 6 mTorr.

[0095] The second titanium nitride layer 202b can serve as a barrier layer to prevent the diffusion of metal in the subsequently formed second metal electrode plate, and can also improve the electromigration of metal in the second metal electrode plate.

[0096] Among them, the second titanium nitride layer 202b, as the interlayer between the second metal electrode and the dielectric stack, is particularly important in terms of the accuracy of its thermal expansion coefficient while achieving the anti-diffusion function.

[0097] The working pressure can also be called the chamber pressure of the process chamber. By setting the appropriate chamber pressure and flow ratio, the required coefficient of thermal expansion of the second titanium nitride layer 202b can be effectively achieved.

[0098] See Figure 4 A second initial filling medium is formed, which covers the second titanium nitride layer 202b and the first filling medium 210.

[0099] A second metal electrode groove is formed on the second initial filling medium to obtain the second filling medium 211.

[0100] The second titanium nitride layer 202b is exposed at the bottom of the second metal electrode groove.

[0101] In some embodiments, the dielectric stack 203 is exposed at the bottom of the second metal plate groove.

[0102] The method for forming the second metal electrode groove can refer to the method for forming the first metal electrode groove 201a. Those skilled in the art can also use other methods for forming grooves, which will not be elaborated here.

[0103] The material of the second filling medium 211 may be selected from one or more of the following: silicon oxide, silicon nitride, and some materials that dope silicon oxide or silicon nitride with other materials (such as silicon carbide, silicon oxynitride, etc.).

[0104] The second metal electrode groove provides process space for the subsequent formation of the second metal electrode 204.

[0105] A second adhesive barrier layer (not shown) is formed, which covers the second titanium nitride layer 202b.

[0106] The second adhesive barrier layer comes into contact with the subsequently formed second metal electrode 204.

[0107] The material of the second adhesive barrier layer is selected from one or more combinations of titanium, tantalum, cobalt, ruthenium, and molybdenum.

[0108] The second adhesive barrier layer, as a dense barrier layer, effectively suppresses atomic interdiffusion and interfacial chemical reactions between the second metal electrode 204 and the dielectric stack 203, preventing degradation of electrical performance and decrease in device reliability. Furthermore, its high chemical activity allows it to form stable chemical bonds with the dielectric stack 203 or the second titanium nitride layer 202b, and also forms strong metallic bonds with the second metal electrode 204, thereby greatly enhancing the adhesion and mechanical integrity of the overall thin film structure and effectively preventing interfacial delamination.

[0109] The method for forming the second adhesive barrier layer can refer to the method for forming the first adhesive barrier layer described above. Other methods can also be used by those skilled in the art, which will not be elaborated here.

[0110] See also Figure 4 A second metal electrode 204 is formed on the second titanium nitride layer 202b.

[0111] The coefficient of thermal expansion of the second metal electrode 204 is greater than that of the second titanium nitride layer 202b.

[0112] The formation process of the second metal electrode 204 can refer to the formation process of the first metal electrode 201 described above. Other formation methods can also be used by those skilled in the art, which will not be elaborated here.

[0113] In this embodiment, the second metal electrode 204 is formed using physical vapor deposition (PVD).

[0114] The material of the second metal electrode 204 is selected from one or more of the following: copper, aluminum, and copper-aluminum alloy. In this embodiment, the material of the second metal electrode 204 is a copper-aluminum alloy.

[0115] In one specific embodiment, a physical vapor deposition method is used, with a copper-aluminum alloy as the target material, and Ar ions are used to bombard the target material to deposit a copper-aluminum metal layer to form the second metal electrode 204, wherein the copper content in the copper-aluminum alloy is 0.5%.

[0116] In this embodiment, the capacitor structure is a MIM structure, and the material of the first metal plate 201 is the same as that of the second metal plate 204.

[0117] In this embodiment, the size of the second metal electrode 204 is smaller than the size of the first metal electrode 201, and the second metal electrode 204 is parallel to the first metal electrode 201. This allows the first metal electrode 201 to be connected to the electrode through a through hole or plug formed in a region offset from the second metal electrode 204.

[0118] The size of the second metal electrode 204 can be greater than or equal to the size of the dielectric stack 203. In this embodiment, the size of the second metal electrode 204 is larger than the size of the dielectric stack 203. This design effectively compensates for photolithography alignment deviations and etching process fluctuations, ensuring that the second metal electrode 204 completely covers the dielectric stack 203, reducing the risk of dielectric exposure, electrode short circuits, or high leakage current due to insufficient edge coverage. It also helps to mitigate the electric field concentration effect at the edge of the dielectric layer, thereby improving the breakdown voltage and enhancing the long-term operational stability of the capacitor. Furthermore, the larger electrode area provides redundant alignment areas for the connection of the upper electrodes, ensuring the reliability of ohmic contacts, ultimately improving overall manufacturing yield and optimizing the performance of the capacitor.

[0119] The first titanium nitride layer 202a and the second titanium nitride layer 202b are formed between the first metal electrode 201 and the second metal electrode 204, enclosing the dielectric stack 203. This multi-layer structure makes it more difficult for pinholes, which are easily formed during subsequent heating and cooling processes, to form continuously, thus blocking the pinhole penetration path and reducing the risk of leakage current formation. This structure effectively disperses and absorbs the concentrated high stress generated at a single interface due to material thermal mismatch in traditional single-layer dielectrics, transforming it into multiple low-stress steps between multiple interfaces. This design avoids the rapid accumulation of stress at a vulnerable interface, thereby significantly suppressing warping, deformation, and even cracking of the dielectric film due to huge thermal stress, ensuring the structural integrity and density of the dielectric layer. This is beneficial for improving capacitor performance, enhancing the long-term stability of the capacitance value, and effectively blocking leakage current paths caused by stress-induced defects and microcracks, thereby comprehensively improving the reliability and lifespan of the device under thermal cycling conditions.

[0120] The coefficient of thermal expansion of the overall structure of the first metal electrode 201, the second metal electrode 204, the first titanium nitride layer 202a, the second titanium nitride layer 202b, and the dielectric stack 203 decreases layer by layer from the first metal electrode 201 and the second metal electrode 204 toward the middle dielectric stack 203, and the coefficient of thermal expansion of the dielectric stack 203 also decreases layer by layer from the edge dielectric layer to the middle dielectric layer. This method constructs a gradient stack structure with a progressively changing coefficient of thermal expansion. When the temperature changes, the metal electrodes (201 / 204) with high coefficients of thermal expansion attempt to undergo large dimensional changes. However, by designing the dielectric stack 203 as a gradient structure with a coefficient of thermal expansion that decreases layer by layer from its edge to its center, a buffer region with a continuous transition in coefficient of thermal expansion is formed between the metal electrodes and the dielectric stack, as well as between each dielectric sublayer. This design allows the shear stress caused by thermal mismatch to be dispersed across multiple interfaces and absorbed and released step by step, avoiding the severe concentration of stress at a specific interface (especially the metal / dielectric interface). This reduces the local stress peak to below the material's fracture strength, which helps to solve the cracking problem caused by thermal stress concentration in the dielectric layer.

[0121] Therefore, the capacitor structure and its formation method can improve the quality of the capacitor structure.

[0122] See also Figure 5 and Figure 6 This forms the third filling medium 212 and the fourth filling medium 213.

[0123] The method for forming the third filling medium 212 and the fourth filling medium 213 can refer to the method for forming the first filling medium 210 described above, and will not be repeated here.

[0124] The first metal plate 201 further includes an electrode region, which includes a plug structure 205 connected to the electrode of the capacitor structure.

[0125] The third filling medium 212 has a through hole 205a (reference) Figure 7 The through hole 205a is used to subsequently form the plug structure 205.

[0126] The fourth filling medium 213 has a first electrode groove 206a and a second electrode groove 207a (see reference). Figure 7 The first electrode groove 206a and the second electrode groove 207a are used to subsequently form the first electrode plate 206 and the second electrode plate 207.

[0127] The specific steps are as follows: A third filling medium 212 with a through hole 205a is formed; The plug structure 205 is formed; A fourth filling medium 213 with a first electrode groove 206a and a second electrode groove 207a is formed; The first electrode plate 206 and the second electrode plate 207 are formed.

[0128] The material of the plug structure 205 may be selected from one or more of the following: copper, aluminum, tungsten, gold, silver, tantalum, titanium nitride, titanium, aluminum-copper alloy, copper alloy, and composite adhesion / barrier layer structure composed of titanium / titanium nitride or tantalum / tantalum nitride.

[0129] The first electrode plate 206 and the second electrode plate 207 are made of the same material.

[0130] The first electrode plate 206 and the second electrode plate 207 are respectively connected to the second metal electrode plate 204 and the first metal electrode plate 201 through a plurality of plug structures 205. The arrangement of the plurality of plug structures 205 can improve the fault tolerance of the connection between the electrode plate and the metal electrode plate of the capacitor and reduce the resistance between the electrode plate and the metal electrode plate of the capacitor.

[0131] The materials of the first electrode plate 206 and the second electrode plate 207 can be selected from one or more of the following combinations: aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, platinum, gold, polycrystalline silicon, tungsten silicide, molybdenum, nickel, silver, aluminum-copper alloy, copper-aluminum alloy, and composite stacked structures composed of titanium / titanium nitride or tantalum / tantalum nitride.

[0132] In this embodiment, the materials of the first electrode plate 206 and the second electrode plate 207 are different from the material of the plug structure 205.

[0133] In some embodiments, the first electrode plate 206 and the second electrode plate 207 are made of the same material as the plug structure 205. The first electrode plate 206 and the second electrode plate 207 may be formed in the same step as the plug structure 205.

[0134] See also Figures 7 to 8 The specific steps are as follows: A third filling medium 212 is formed, the third filling medium 212 having a through hole 205a, a first electrode groove 206a, and a second electrode groove 207a; Form a barrier layer; A seed layer is formed and electroplated to form a plug structure 205 and a first electrode plate 206 and a second electrode plate 207.

[0135] The first electrode plate 206, the second electrode plate 207 and the plug structure 205 are formed in the same step, and the first electrode plate 206, the second electrode plate 207 and the plug structure 205 are made of the same material.

[0136] It should be noted that the materials of the first filling medium 210, the second filling medium 211, the third filling medium 212, and the fourth filling medium 213 may be the same, different, or partially the same and partially different.

[0137] The materials of the first filling medium 210, the second filling medium 211, the third filling medium 212, and the fourth filling medium 213 can be selected from one or more of the following combinations: silicon nitride, silicon oxide, undoped silicon glass, phosphosilicate glass, borosilicate glass, carbon-doped silicon nitride, silicon oxynitride, porous silicon dioxide, silsesquioxane hydrogenation, polyimide, amorphous fluorinated carbon, silicon dioxide-TiO2 composite material, and Si-COH series organosilicones. In this embodiment, the materials of the first filling medium 210, the second filling medium 211, the third filling medium 212, and the fourth filling medium 213 are composed of silicon oxide, silicon nitride, or doped materials of silicon oxide and silicon nitride. The first filling medium 210, the second filling medium 211, the third filling medium 212, and the fourth filling medium 213 provide robust mechanical support, reliable electrical isolation, critical surface planarization, effective stress buffering, and final environmental passivation, collectively laying a solid foundation for ensuring the performance consistency, process feasibility, and long-term operating life of the MIM capacitor.

[0138] To address the aforementioned technical problems, this application also provides a capacitor structure.

[0139] See Figure 9 , Figure 9 This is a cross-sectional schematic diagram of a capacitor structure in an embodiment of the present invention.

[0140] The capacitor structure includes: a first metal plate 201.

[0141] The material of the first metal electrode 201 is selected from one or more of the following: copper, aluminum, and copper-aluminum alloy. In this embodiment, the material of the first metal electrode 201 is copper-aluminum alloy.

[0142] A first titanium nitride layer 202a is located on the first metal electrode 201, and the coefficient of thermal expansion of the first titanium nitride layer 202a is less than the coefficient of thermal expansion of the first metal electrode 201.

[0143] The material of the first titanium nitride layer 202a can be selected from one or more of the following: titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride. In this embodiment, the material of the first titanium nitride layer 202a is titanium nitride.

[0144] In this embodiment, a first adhesive barrier layer (not shown) is provided between the first titanium nitride layer 202a and the first metal electrode 201, and the first adhesive barrier layer covers the first metal electrode 201.

[0145] The material of the first adhesive barrier layer is selected from one or more combinations of titanium, tantalum, cobalt, ruthenium, and molybdenum.

[0146] As a dense barrier layer, the first adhesive barrier layer effectively suppresses atomic interdiffusion and interfacial chemical reactions between the first metal electrode 201 and the subsequent insulating material, preventing degradation of electrical performance and decrease in device reliability. Furthermore, its high chemical activity allows it to form stable chemical bonds with the subsequently formed materials, while simultaneously forming strong metallic bonds with the first metal electrode 201, thereby greatly enhancing the adhesion and mechanical integrity of the overall thin film structure and effectively preventing interfacial delamination.

[0147] The capacitor structure also includes a dielectric stack 203.

[0148] The dielectric stack 203 covers the first titanium nitride layer 202a. All layers in the dielectric stack 203 are nitrogen-containing material layers, and their coefficients of thermal expansion are all less than those of the first titanium nitride layer 202a. The coefficients of thermal expansion increase layer by layer from the middle sub-layer to the edge sub-layer of the dielectric stack 203.

[0149] The dielectric stack 203 includes at least a first dielectric layer 203a, a second dielectric layer 203b, and a third dielectric layer 203c. The first dielectric layer 203a covers the first titanium nitride layer 202a, the second dielectric layer 203b covers the first dielectric layer 203a, and the third dielectric layer 203c covers the second dielectric layer. The material of the third dielectric layer 203c is the same as that of the first dielectric layer 203a.

[0150] It should be noted that the dielectric stack 203 includes at least the first dielectric layer 203a, the second dielectric layer 203b, and the third dielectric layer 203c, and may also include a fourth dielectric layer, a fifth dielectric layer, a sixth dielectric layer, etc.

[0151] The coefficient of thermal expansion of all layers in the dielectric stack 203 is less than that of the first titanium nitride layer 202a, so that the first titanium nitride layer 202a can act as a transition bridge for the coefficient of thermal expansion in the dielectric stack 203, thereby reducing interface stress and improving the quality of the capacitor structure.

[0152] The first dielectric layer 203a is made of silicon oxynitride or silicon carbonitride. The second dielectric layer 203b is made of silicon oxynitride or silicon nitride. The third dielectric layer 203c is made of silicon oxynitride or silicon carbonitride. In this embodiment, the first dielectric layer 203a is made of silicon oxynitride, the second dielectric layer 203b is made of silicon nitride, and the third dielectric layer 203c is made of silicon oxynitride.

[0153] The coefficient of thermal expansion of aluminum is 23 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of titanium nitride is 9.35 × 10⁻⁶. -6 At / ℃, the coefficient of thermal expansion of silicon nitride is approximately 3×10⁻⁶. -6 / ℃. The typical coefficient of thermal expansion for silicon oxynitride ranges from 0.5 to 2.5 × 10⁻⁶. -6 / ℃, its coefficient of thermal expansion is between that of silicon dioxide (0.5 × 10⁻⁶). -6 / ℃) and silicon nitride (2.8 ~ 3.2×10 -6 The coefficient of thermal expansion in silicon oxynitride (SNO) is between 2.5 and 4.5 × 10⁻⁶ °C. The higher the oxygen content, the lower the coefficient of thermal expansion; the higher the nitrogen content, the higher the coefficient of thermal expansion. Typical coefficients of thermal expansion for silicon carbonitride range from 2.5 to 4.5 × 10⁻⁶ °C. -6 Its coefficient of thermal expansion is typically between that of silicon nitride (2.8 ~ 3.2 × 10⁻⁶ °C). -6 / ℃) and silicon carbide (4.0 ~ 4.5×10 -6 The coefficient of thermal expansion is between 0.5°C and 0.6°C. The higher the carbon content of silicon carbonitride, the higher its coefficient of thermal expansion. By using the multilayer structure of the dielectric stack 203 and the metal layer, a gradual transition of the coefficient of thermal expansion is achieved from the metal layer to the dielectric layer, which can significantly alleviate the thermal stress during the cooling process of high temperature and suppress the warping or cracking of the dielectric layer.

[0154] A second titanium nitride layer 202b covers the dielectric stack 203, and the coefficient of thermal expansion of the second titanium nitride layer 202b is greater than the coefficient of thermal expansion of all layers in the dielectric stack 203.

[0155] The material and function of the second titanium nitride layer 202b can be referred to the material and function of the first titanium nitride layer 202a, and will not be repeated here.

[0156] The second metal electrode 204 covers the second titanium nitride layer 202b, and the coefficient of thermal expansion of the second metal electrode 204 is greater than the coefficient of thermal expansion of the second titanium nitride layer 202b.

[0157] The material and function of the second metal electrode 204 can be referred to the material and function of the first metal electrode 201, and will not be repeated here.

[0158] The second metal electrode 204 is smaller than the first metal electrode 201, and the second metal electrode 204 is parallel to the first metal electrode 201. The area where the first metal electrode 201 and the second metal electrode 204 are offset is the electrode area, and the electrode area has a plug structure 205 connected to the electrode.

[0159] The capacitor structure described above comprises a first titanium nitride layer 202a and a second titanium nitride layer 202b sandwiching a dielectric stack 203 between the first metal plate 201 and the second metal plate 204. Furthermore, the coefficient of thermal expansion of the overall structure of the first metal plate 201, the second metal plate 204, the first titanium nitride layer 202a, the second titanium nitride layer 202b, and the dielectric stack 203 decreases progressively from the first metal plate 201 and the second metal plate 204 towards the intermediate dielectric stack 203. This structure, by creating a gradient stack structure with a progressively changing coefficient of thermal expansion, fundamentally improves the quality of the capacitor structure.

[0160] A first titanium nitride layer 202a with a moderate coefficient of thermal expansion is inserted between the first metal electrode 201 and the dielectric stack 203. A nitrogen-containing material sublayer with a coefficient of thermal expansion that gradually increases from the middle to the edge is designed inside the dielectric stack 203. Then, the second titanium nitride layer 202b is used to transition to the second metal electrode 204 with a high coefficient of thermal expansion. This disperses the concentrated stress caused by material thermal mismatch in the traditional structure to multiple interfaces, effectively suppressing the deformation and cracking of the dielectric layer and ensuring the integrity of the structure.

[0161] The use of a nitrogen-containing material layer and a titanium nitride transition layer in the dielectric stack 203 enhances interface stability and process compatibility, while reducing dielectric thickness sensitivity and defect density. This design, while maintaining high capacitance density, synergistically optimizes capacitance accuracy, breakdown voltage, and leakage performance, systematically resolving the inherent contradiction between density, reliability, and yield in capacitors at nanoscale nodes. Therefore, this capacitor structure improves the overall quality of the capacitor structure.

[0162] This invention also provides a semiconductor device comprising the capacitor structure described in any of the preceding embodiments.

[0163] The semiconductor devices include logic chips and memory chips.

[0164] It should be understood that in the embodiments of this application, the logic chip can be a central processing unit (CPU), which can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0165] It should also be understood that the memory chip in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be ROM, Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), or flash memory. The volatile memory can be Random Access Memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate Synchronous DRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0166] This invention also provides an electronic device, including any of the semiconductor devices described above.

[0167] The semiconductor device can be built into or externally connected to the electronic device, which includes, but is not limited to, mobile phones, computers, tablets, servers, cloud platforms, etc.

[0168] It is understood that the above description of capacitor structure and formation method, semiconductor device, and electronic device has multiple embodiments. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed in this invention.

[0169] It should be understood that "multiple" in the embodiments of this application refers to two or more.

[0170] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0171] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.

[0172] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a capacitor structure, characterized in that, include: Form the first metal electrode plate; A first titanium nitride layer is formed on the first metal electrode, and the coefficient of thermal expansion of the first titanium nitride layer is smaller than the coefficient of thermal expansion of the first metal electrode. A dielectric stack is formed on the first titanium nitride layer, wherein all layers in the dielectric stack are nitrogen-containing material layers and their coefficients of thermal expansion are all less than those of the first titanium nitride layer. The coefficients of thermal expansion increase layer by layer from the middle sub-layer to the edge sub-layer of the dielectric stack. A second titanium nitride layer is formed on the dielectric stack, and the coefficient of thermal expansion of the second titanium nitride layer is greater than the coefficient of thermal expansion of all layers in the dielectric stack. A second metal electrode is formed on the second titanium nitride layer, and the coefficient of thermal expansion of the second metal electrode is greater than that of the second titanium nitride layer.

2. The method according to claim 1, characterized in that, The first titanium nitride layer and the second titanium nitride layer satisfy one or more of the following: The first titanium nitride layer and the second titanium nitride layer are formed using a physical vapor deposition process. The argon to nitrogen flow ratio used in the process of forming the first titanium nitride layer and the second titanium nitride layer is in the range of 10:1 to 6:1; The working pressure in the process of forming the first titanium nitride layer and the second titanium nitride layer is 3 ~ 6 mTorr.

3. The method according to claim 1, characterized in that, The step of forming the dielectric stack includes: forming a first dielectric layer covering the first titanium nitride layer; A second dielectric layer is formed covering the first dielectric layer; A third dielectric layer is formed covering the second dielectric layer; The material of the third dielectric layer is the same as that of the first dielectric layer.

4. The method according to claim 3, characterized in that, Meet one or more of the following: The first dielectric layer is made of silicon oxynitride or silicon carbonitride; The material of the second dielectric layer is silicon oxynitride or silicon nitride; The material of the third dielectric layer is silicon oxynitride or silicon carbonitride.

5. The method according to claim 1, characterized in that, Also includes: A first adhesive barrier layer is formed, which covers the first metal electrode plate; A second adhesive barrier layer is formed, which covers the second titanium nitride layer and is in contact with the second metal electrode.

6. The method according to claim 5, characterized in that, The materials of the first adhesive barrier layer and the second adhesive barrier layer are selected from one or more combinations of titanium, tantalum, cobalt, ruthenium, and molybdenum.

7. The method according to claim 1, characterized in that, The second metal electrode is smaller than the first metal electrode, and the second metal electrode is parallel to the first metal electrode. The first metal electrode plate further includes an electrode region, wherein the electrode region comprises: A plug structure is connected to the electrodes of the capacitor structure.

8. The method according to claim 1, characterized in that, Meet one or more of the following: The capacitor structure is a MIM structure; The first metal electrode plate is made of the same material as the second metal electrode plate.

9. A capacitor structure, characterized in that, include: First metal electrode plate; A first titanium nitride layer is located on the first metal electrode plate, and the coefficient of thermal expansion of the first titanium nitride layer is less than the coefficient of thermal expansion of the first metal electrode plate. A dielectric stack covers the first titanium nitride layer. All layers in the dielectric stack are nitrogen-containing material layers, and their coefficients of thermal expansion are all less than those of the first titanium nitride layer. The coefficients of thermal expansion increase layer by layer from the middle sub-layer to the edge sub-layer of the dielectric stack. A second titanium nitride layer covers the dielectric stack, and the coefficient of thermal expansion of the second titanium nitride layer is greater than the coefficient of thermal expansion of all layers in the dielectric stack. A second metal electrode plate covers the second titanium nitride layer, and the coefficient of thermal expansion of the second metal electrode plate is greater than that of the second titanium nitride layer.

10. The capacitor structure according to claim 9, characterized in that, The dielectric stack includes at least: a first dielectric layer covering the first titanium nitride layer; A second dielectric layer covers the first dielectric layer; A third dielectric layer covers the second dielectric layer; The material of the third dielectric layer is the same as that of the first dielectric layer.

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