Lateral insulated gate bipolar transistor and manufacturing method thereof

Abstract

The invention relates to a lateral insulated gate bipolar transistor and a manufacturing method thereof. The lateral insulated gate bipolar transistor comprises a substrate, an epitaxial layer, a base region, a channel substrate contact, a source region, a buried oxide groove, a drain region, a gate oxide layer, a grid electrode, a source electrode and a drain electrode, wherein the epitaxial layer is located on the substrate; the base region, the buried oxide type groove and the drain region all extend into the epitaxial layer from the surface of the epitaxial layer, and the buried oxide type groove is located between the base region and the drain region; the channel substrate contact and the source region extend into the epitaxial layer from the surface of the base region, the channel substrate contact is adjacent to the source region, and a channel is formed in the base region on one side of the source region; the gate oxide layer covers a part of the surface of the source region, the channel and a part of the surface of the epitaxial layer, and the gate is located on the gate oxide layer; the source electrode covers a part of the contact surface of the channel substrate and a part of the surface of the source region; the drain electrode is located on the drain region. According to the lateral insulated gate bipolar transistor, collaborative optimization of voltage resistance, reliability and overall performance is realized.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor devices, specifically relating to a lateral insulated gate bipolar transistor and its fabrication method. Background Technology

[0002] Power devices, as core components of electrical energy processing and conversion, perform critical functions such as voltage transformation, current conversion, frequency conversion, and power amplification. They play an indispensable role in equipment such as switching power supplies, motor drive and speed control systems, and UPS (uninterruptible power supplies). These devices all require a stable power supply to the load, making power semiconductor devices essential in circuit design. After development stages such as silicon controlled rectifiers (SCRs), thyristors (GTRs), and field-effect transistors (MOSFETs), power semiconductor technology has entered the era of lateral insulated-gate bipolar transistors (L-IGBTs), which offer higher integration and superior performance.

[0003] L-IGBTs ingeniously combine the low conduction losses of turn-off thyristors (GTRs) with the low drive power characteristics of field-effect transistors (MOSFETs), achieving the dual advantages of low drive power and low saturation voltage. Their applications are extremely broad, covering not only converter systems with DC voltages of 600V and above, such as AC motor control, frequency converter design, high-efficiency switching power supplies, intelligent lighting solutions, and traction drive systems, but also occupying an important position in national strategic emerging industries, including power electronic conversion in rail transit, smart grid construction, and advanced electric drive systems in the aerospace field, demonstrating strong technological adaptability and market potential.

[0004] However, traditional silicon-based L-IGBTs have concentrated electric field regions, resulting in poor blocking voltage capability. Furthermore, due to the low performance of devices with intrinsic critical electric fields of silicon materials, traditional silicon-based L-IGBT devices cannot achieve synergistic optimization of withstand voltage, reliability, and overall performance. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a lateral insulated gate bipolar transistor and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a lateral insulated gate bipolar transistor, comprising: a substrate, an epitaxial layer, a base region, a channel substrate contact, a source region, a buried oxide trench, a drain region, a gate oxide layer, a gate electrode, a source electrode, and a drain electrode, wherein, The epitaxial layer is located on the substrate; The base region, the buried oxide trench, and the drain region all extend from the surface of the epitaxial layer to the interior of the epitaxial layer, and the buried oxide trench is located between the base region and the drain region, and the depth of the buried oxide trench is less than the depth of the base region; Both the channel substrate contact and the source region extend from the surface of the base region into the interior of the epitaxial layer, and the channel substrate contact and the source region are adjacent to each other, with a channel formed in the base region on one side of the source region; The gate oxide layer covers a portion of the surface of the source region, the channel, and a portion of the surface of the epitaxial layer; the gate electrode is located on the gate oxide layer; the source electrode covers a portion of the surface of the channel substrate contact and a portion of the surface of the source region; the drain electrode is located on the drain region. The substrate, the base region, the channel substrate contact, and the drain region all have a first doping type; the epitaxial layer and the source region both have a second doping type.

[0006] In one embodiment of the present invention, the epitaxial layer includes a wide bandgap material epitaxial layer and a silicon epitaxial layer, wherein, The wide bandgap material epitaxial layer is located on the substrate, and the silicon epitaxial layer is located on the wide bandgap material epitaxial layer; both the wide bandgap material epitaxial layer and the silicon epitaxial layer have a second doping concentration; The base region, the buried oxide trench, and the drain region all extend from the surface of the silicon epitaxial layer into the wide bandgap material epitaxial layer. The channel substrate contact and the source region are located in the base region and extend from the surface of the silicon epitaxial layer into the wide bandgap material epitaxial layer. A PN junction is formed between the base region and the wide bandgap material epitaxial layer, and the channel is located in the silicon epitaxial layer.

[0007] In one embodiment of the present invention, the thickness of the wide bandgap material epitaxial layer is greater than the thickness of the silicon epitaxial layer.

[0008] In one embodiment of the present invention, the thickness of the silicon epitaxial layer is 0.5 μm to 1 μm, and the thickness of the wide bandgap material epitaxial layer is 2 μm to 3 μm. The doping concentration of the wide-bandgap material epitaxial layer and the silicon epitaxial layer is 3 × 10⁻⁶. 15 cm -3 ~9×10 15 cm -3 .

[0009] In one embodiment of the present invention, the base region extends into the wide bandgap material epitaxial layer to a depth of 2 μm to 4 μm; The depth to which the channel substrate contact, the source region, and the drain region extend into the wide bandgap material epitaxial layer is 0.5 μm to 1 μm.

[0010] In one embodiment of the present invention, the substrate material includes a wide bandgap material; The substrate has a doping concentration of 1×10⁻⁶. 13cm -3 ~1×10 15 cm -3 .

[0011] In one embodiment of the present invention, the wide bandgap material includes one or more of silicon carbide, gallium nitride, diamond, and gallium oxide.

[0012] In one embodiment of the present invention, the width of the buried oxygen trench is 1μm to 3μm and the depth is 1μm to 3μm; The distance from the first boundary of the buried oxide trench to the base region is 1 μm to 2 μm, the distance from the second boundary to the drain region is 1 μm to 2 μm, and the distance from the bottom to the substrate is 0.5 μm to 2 μm.

[0013] Another embodiment of the present invention provides a method for fabricating a lateral insulated gate bipolar transistor, comprising the steps of: Provide substrate; An epitaxial layer is prepared on the substrate; The epitaxial layer is partially etched using partial etching technology to form trenches, and silicon dioxide is filled into the trenches using local oxidation technology to form buried oxide trenches. Ion implantation technology is used to form a base region in the epitaxial layer; wherein the depth of the buried oxide trench is less than the depth of the base region; A gate oxide layer is formed on a portion of the surface of the source region, the trench, and a portion of the surface of the epitaxial layer, and a gate is formed on the gate oxide layer; Ion implantation is performed in the base region to form adjacent channel substrate contacts and source regions, and a channel is formed between the boundary between the source region and the base region using a double diffusion technique; ion implantation is performed in the epitaxial layer to form a drain region, wherein the buried oxide trench is located between the base region and the drain region; A passivation layer is deposited on the device surface, and the passivation layer on the surface of the channel substrate contact portion and the surface of the source region portion is etched to form a source region contact hole, and the passivation layer on the drain region is etched to form a drain region contact hole; then metal is deposited on the device surface to form a source electrode in the source region contact hole and a drain electrode in the drain region contact hole; The substrate, the base region, the channel substrate contact, and the drain region all have a first doping type; the epitaxial layer and the source region both have a second doping type.

[0014] In one embodiment of the present invention, the preparation of an epitaxial layer on the substrate includes: An epitaxial layer of wide-bandgap material is epitaxially grown on the substrate; A silicon epitaxial layer is prepared on the wide bandgap material epitaxial layer, wherein both the wide bandgap material epitaxial layer and the silicon epitaxial layer have a second doping type.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The lateral insulated gate bipolar transistor of the present invention achieves the folding of the drift region in the longitudinal direction by setting an epitaxial layer on the substrate and forming buried oxide trenches in the epitaxial layer. By utilizing the breakdown point transfer mechanism, the electric field concentration region in the traditional device is effectively transferred to the interior of the epitaxial layer, which effectively optimizes the electric field distribution, significantly improves the blocking voltage capability of the device, and the device can withstand higher breakdown voltage. It breaks through the bottleneck of the voltage withstand performance of the traditional device and achieves synergistic optimization of voltage withstand performance, reliability and overall performance. 2. In the lateral insulated gate bipolar transistor of the present invention, the epitaxial layer is composed of a wide bandgap material epitaxial layer and a silicon epitaxial layer, constructing a silicon-wide bandgap material composite drift region structure. The wide bandgap material epitaxial layer has high critical breakdown electric field characteristics. Based on the longitudinal folding of the drift region by the buried oxide trench, the electric field concentration region in the traditional device can be transferred to the interior of the wide bandgap material through the breakdown point transfer mechanism, forming an elevated electric field peak distribution, realizing the uniform reconstruction of the electric field distribution, effectively breaking through the physical bottleneck of the voltage withstand performance of single silicon material, and significantly improving the blocking voltage capability of the device. At the same time, the channel substrate contact, source region and drain region are formed in the silicon epitaxial layer, and the source and drain electrodes are fabricated on the channel substrate contact, source region and drain region. The metal electrode is in direct contact with the silicon epitaxial layer. While maintaining compatibility with traditional CMOS processes, it not only effectively avoids the technical problem of excessively high contact resistance at the wide bandgap material-metal interface, but also retains the excellent thermal conductivity characteristics of the wide bandgap material, significantly improving the heat dissipation performance of the device. Attached Figure Description

[0016] Figure 1 A schematic diagram of a lateral insulated gate bipolar transistor provided in an embodiment of the present invention; Figure 2 This is a schematic flowchart illustrating a method for fabricating a lateral insulated gate bipolar transistor according to an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Example 1 Please see Figure 1 , Figure 1 This is a schematic diagram of a lateral insulated gate bipolar transistor provided in an embodiment of the present invention.

[0019] The lateral insulated gate bipolar transistor of this embodiment includes: a substrate 1, an epitaxial layer 2, a base region 3, a channel substrate contact 4, a source region 5, a buried oxide trench 6, a drain region 7, a gate oxide layer 8, a gate 9, a source 10, and a drain 11.

[0020] Epitaxial layer 2 is located on substrate 1; base region 3, buried oxide trench 6 and drain region 7 all extend from the surface of epitaxial layer 2 to the interior, and buried oxide trench 6 is located between base region 3 and drain region 7, the depth of buried oxide trench 6 is less than the depth of base region 3; channel substrate contact 4 and source region 5 are both formed in base region 3, and channel substrate contact 4 and source region 5 are adjacent, and a channel is formed in base region 3 on one side of source region 5; gate oxide layer 8 covers part of the surface of source region 5, channel and part of the surface of epitaxial layer 2, and gate 9 is located on gate oxide layer 8; source 10 covers part of the surface of channel substrate contact 4 and part of the surface of source region 5; drain 11 is located on drain region 7; substrate 1, base region 3, channel substrate contact 4 and drain region 7 all have a first doping type; epitaxial layer 2 and source region 5 both have a second doping type.

[0021] Specifically, the base region 3 can extend from the surface of the epitaxial layer 2 to the bottom of the epitaxial layer 2, or it can extend into the interior of the epitaxial layer 2. The region in the epitaxial layer 2 where no base region is formed is the drift region, and the depth of the drift region is the same as the depth of the base region 3. The buried oxide trench 6 extends from the surface of the epitaxial layer 2 to the interior of the epitaxial layer 2, and the buried oxide trench 6 is located within the drift region, meaning the depth of the buried oxide trench 6 is less than the depth of the base region 3. The channel substrate contact 4 and the source region 5 are formed in the base region 3 and are adjacent to each other. The source region 5 is located between the channel substrate contact 4 and the drain region 7. A channel is formed in the base region 3 on one side of the source region 5, meaning that relative to the source region 5, the channel substrate contact 4 is located on the side away from the channel. The drain region 7 is located on the side of the buried oxide trench 6 away from the base region 3.

[0022] Specifically, the first doping type is P-type, and the second doping type is N-type. That is, substrate 1, base region 3, channel substrate contact 4, and drain region 7 are all P-type doped, while epitaxial layer 2 and source region 5 are both N-type doped. In other words, if the substrate is P-type, then base region 3 is a P-type base region, channel substrate contact 4 is a P+ channel substrate contact, drain region 7 is a P+ drain region, epitaxial layer 2 is an N-type epitaxial layer, and source region 5 is an N+ source region. Alternatively, the first doping type is N-type, and the second doping type is P-type. That is, substrate 1, base region 3, channel substrate contact 4, and drain region 7 are all N-type doped, while epitaxial layer 2 and source region 5 are both P-type doped. In other words, if the substrate is N-type, then base region 3 is an N-type base region, channel substrate contact 4 is an N+ channel substrate contact, drain region 7 is an N+ drain region, epitaxial layer 2 is a P-type epitaxial layer, and source region 5 is a P+ source region.

[0023] This embodiment of the lateral insulated gate bipolar transistor (IGBT) achieves longitudinal folding of the drift region by forming an epitaxial layer on the substrate and a buried oxide trench within the epitaxial layer. Utilizing a breakdown point transfer mechanism, the electric field concentration region in traditional devices is effectively transferred to the interior of the epitaxial layer, effectively optimizing the electric field distribution and significantly improving the device's blocking voltage capability. The device can withstand higher breakdown voltages, breaking through the bottleneck of traditional devices in terms of withstand voltage performance and achieving synergistic optimization of withstand voltage, reliability, and overall performance. In one specific embodiment, the substrate 1 is made of a wide bandgap material; the doping concentration of the substrate 1 is 1×10⁻⁶. 13 cm -3 ~1×10 15 cm -3 .

[0024] Specifically, wide bandgap materials include one or more of silicon carbide, gallium nitride, diamond, and gallium oxide.

[0025] In one specific embodiment, the epitaxial layer 2 includes a wide bandgap material epitaxial layer 21 and a silicon epitaxial layer 22, wherein the wide bandgap material epitaxial layer 21 is located on the substrate 1, and the silicon epitaxial layer 22 is located on the wide bandgap material epitaxial layer 21; both the wide bandgap material epitaxial layer 21 and the silicon epitaxial layer 22 have a second doping concentration; the base region 3, the buried oxide trench 6, and the drain region 7 all extend from the surface of the silicon epitaxial layer 22 into the wide bandgap material epitaxial layer 21; the channel substrate contact 4 and the source region 5 are located in the base region 3 and extend from the surface of the silicon epitaxial layer 22 into the wide bandgap material epitaxial layer 21; a PN junction is formed between the base region 3 and the wide bandgap material epitaxial layer 21, and the channel is formed in the silicon epitaxial layer 22.

[0026] Specifically, the base region 3 is formed in one end region of the wide bandgap material epitaxial layer 21 and the silicon epitaxial layer 22, and the base region 3 extends into the wide bandgap material epitaxial layer 21. That is, the PN junction formed by the base region 3 and the wide bandgap material epitaxial layer 21 is located in the wide bandgap material epitaxial layer 21, and the channel is located in the silicon epitaxial layer 22.

[0027] The buried oxide trench 6 is formed in the middle region between the wide bandgap material epitaxial layer 21 and the silicon epitaxial layer 22. The bottom boundary of the buried oxide trench 6 extends into the wide bandgap material epitaxial layer 21 and is not adjacent to the substrate 1. The left boundary of the buried oxide trench 6 is not adjacent to the base region 3, and the right boundary of the buried oxide trench 6 is not adjacent to the drain region 7.

[0028] The thickness of the wide bandgap material epitaxial layer 21 is greater than the thickness of the silicon epitaxial layer 22. Specifically, the thickness of the silicon epitaxial layer 22 is 0.5 μm to 1 μm, and the thickness of the wide bandgap material epitaxial layer 21 is 2 μm to 3 μm. The doping concentration of the wide bandgap material epitaxial layer 21 and the silicon epitaxial layer 22 is determined by the breakdown voltage requirements of the device; specifically, the doping concentration of the wide bandgap material epitaxial layer 21 and the silicon epitaxial layer 22 is 3 × 10⁻⁶.15 cm -3 ~9×10 15 cm -3 The wide bandgap material in the wide bandgap material epitaxial layer 21 includes one or more of silicon carbide, gallium nitride, diamond, and gallium oxide.

[0029] Furthermore, the base region 3 extends into the wide bandgap material epitaxial layer 21 to a depth of 2 μm to 4 μm. The channel substrate contact 4, source region 5, and drain region 7 extend into the wide bandgap material epitaxial layer 21 to a depth of 0.5 μm to 1 μm.

[0030] In one specific embodiment, the width of the buried oxygen trench 6 W T The depth of the buried oxide trench 6 is less than the drift region length of the device. D T It is less than the sum of the thicknesses of the wide-bandgap material epitaxial layer 21 and the silicon epitaxial layer 22. Specifically, the width of the buried oxide trench 6 is... W T The depth is 1μm to 3μm. D T The size ranges from 1μm to 3μm.

[0031] Furthermore, the distance from the first boundary of the buried oxide trench 6 to the base region 3 is 1 μm to 2 μm, the distance from the second boundary to the drain region 7 is 1 μm to 2 μm, and the distance from the bottom to the substrate 1 is 0.5 μm to 2 μm.

[0032] In one specific embodiment, gate 9 is a polysilicon gate, source 10 is a metallized source, and drain 11 is a metallized drain.

[0033] In the lateral insulated gate bipolar transistor of the present invention, the epitaxial layer is composed of a wide bandgap material epitaxial layer and a silicon epitaxial layer, constructing a silicon-wide bandgap material composite drift region structure. The wide bandgap material epitaxial layer has high critical breakdown electric field characteristics. Based on the longitudinal folding of the drift region by the buried oxide trench, the electric field concentration region in the traditional device can be transferred to the interior of the wide bandgap material through the breakdown point transfer mechanism, forming an elevated electric field peak distribution. This achieves uniform reconstruction of the electric field distribution, effectively breaking through the physical bottleneck of the voltage withstand performance of single silicon material and significantly improving the device's blocking voltage capability. At the same time, the channel substrate contact, source region, and drain region are formed in the silicon epitaxial layer, and the source and drain electrodes are fabricated on the channel substrate contact, source region, and drain region. The metal electrode is in direct contact with the silicon epitaxial layer. While maintaining compatibility with traditional CMOS processes, this not only effectively avoids the technical problem of excessively high contact resistance at the wide bandgap material-metal interface, but also retains the excellent thermal conductivity characteristics of the wide bandgap material, significantly improving the device's heat dissipation performance.

[0034] The lateral insulated gate bipolar transistor of this embodiment successfully breaks through the performance bottleneck of traditional silicon-based L-IGBTs, which are limited by the intrinsic critical breakdown electric field of silicon material (~0.3 MV / cm). While maintaining the advantage of manufacturing cost, it achieves synergistic optimization of device withstand voltage characteristics, reliability and overall performance.

[0035] Example 2 Based on Embodiment 1, this embodiment provides a fabrication scheme for a lateral insulated gate bipolar transistor. Please refer to [link to embodiment 1]. Figure 2 , Figure 2 This is a schematic flowchart of a method for fabricating a lateral insulated gate bipolar transistor according to an embodiment of the present invention. The method includes the following steps: S1, Provide substrate 1.

[0036] Specifically, the substrate 1 is made of a wide bandgap material, which includes one or more of silicon carbide, gallium nitride, diamond, and gallium oxide; the doping concentration of substrate 1 is 1×10⁻⁶. 13 cm -3 ~1×10 15 cm -3 .

[0037] S2. Fabricate epitaxial layer 2 on substrate 1. This includes the following steps: S21, an epitaxial layer 21 of wide bandgap material is epitaxially grown on substrate 1.

[0038] Specifically, a homogeneous wide-bandgap material epitaxial layer 21 is formed on substrate 1 using vapor phase epitaxy (VPE) or bonding technology.

[0039] S22. A silicon epitaxial layer 22 is prepared on a wide bandgap material epitaxial layer 21.

[0040] Specifically, a silicon epitaxial layer 22 is formed on a wide bandgap material epitaxial layer 21 using heteroepitaxial growth technology or bonding technology.

[0041] Specifically, the material of the wide bandgap epitaxial layer 21 includes one or more of silicon carbide, gallium nitride, diamond, and gallium oxide. Both the wide bandgap epitaxial layer 21 and the silicon epitaxial layer 22 have a second doping type, which is opposite to the doping type of the substrate 1.

[0042] S3. Partial etching technology is used to partially etch the epitaxial layer 2 to form trenches, and local oxidation technology is used to fill the trenches with silicon dioxide to form buried oxide trenches 6. Specifically, firstly, partial etching technology is used to partially etch the wide bandgap material epitaxial layer 21 and the silicon epitaxial layer 22, and the etched trenches extend into the wide bandgap material epitaxial layer 21; then, local oxidation technology is used to fill the trenches with silicon dioxide to form buried oxide trenches 6.

[0043] S4. Ion implantation is performed in the epitaxial layer 2 to form the base region 3.

[0044] Specifically, a base region 3 is formed on the left side of the upper part of the silicon epitaxial layer 22 using ion implantation technology. The depth of the base region 3 needs to be greater than the depth of the buried oxide trench 6.

[0045] S5. A gate oxide layer 8 is prepared on a portion of the surface of the source region 5, the trench, and a portion of the surface of the epitaxial layer 2, and a gate 9 is prepared on the gate oxide layer 8. Specifically, the gate oxide layer 8 can be made of silicon dioxide.

[0046] S6. Ion implantation is performed in the base region 3 to form adjacent channel substrate contacts 4 and source region 5. A channel is formed between the boundary of source region 5 and base region 3 using a double diffusion technique. Ion implantation is performed in the epitaxial layer 2 to form drain region 7, wherein buried oxide trench 6 is located between base region 3 and drain region 7.

[0047] Specifically, a base region 3 is formed on the left side of the upper part of the silicon epitaxial layer 22 using ion implantation technology. The depth of the base region 3 must be greater than the depth of the buried oxide trench 6. Then, a channel substrate contact 4, a source region 5, and a drain region 7 are formed using ion implantation technology, and a corresponding channel is formed using double diffusion technology. This ensures that the longitudinal boundaries of the source region 5 and the channel substrate contact 4 extend into the wide bandgap material epitaxial layer 21. At the same time, it ensures that the longitudinal boundary of the base region 3 extends into the wide bandgap material epitaxial layer 21. That is, the PN junction formed by the base region 3 and the wide bandgap material epitaxial layer 21 is located within the wide bandgap material epitaxial layer 21, and the channel is still located in the silicon epitaxial layer 22. In addition, it ensures that the longitudinal boundary of the drain region 7 extends into the silicon epitaxial layer 22.

[0048] S7. Deposit a passivation layer on the device surface, and etch the passivation layer on the surface of the channel substrate contact 4 and the surface of the source region 5 to form a source region contact hole, and etch the passivation layer on the drain region 7 to form a drain region contact hole; then deposit metal on the device surface to form a source electrode 10 in the source region contact hole and a drain electrode 11 in the drain region contact hole.

[0049] Taking the wide bandgap material as silicon carbide (SiC), substrate 1 as a P-type SiC wafer, wide bandgap epitaxial layer 21 as an N-type SiC epitaxial layer, silicon epitaxial layer 22 as an N-type Si epitaxial layer, base region 3 as a P-type base region, channel substrate contact 4 as a P+ channel substrate contact, source region 5 as an N+ source region, and drain region 7 as a P+ drain region as an example, the fabrication method of the lateral insulated gate bipolar transistor in this embodiment includes the following steps: S1, Provide substrate 1.

[0050] A doping concentration of 1×10⁻⁶ was selected. 14 cm -3 P-type SiC wafers are used as substrates.

[0051] S2, Prepare epitaxial layer 2.

[0052] S21. An N-type SiC epitaxial layer is homoepitaxially grown on a P-type SiC wafer using vapor phase epitaxy (VPE) with a doping concentration of 3.3 × 10⁻⁶. 15 cm -3 .

[0053] S22. First, the bonding surfaces of P-type SiC wafers and N-type Si wafers are cleaned using RCA standard cleaning to remove organic contaminants and metal ions; ammonium hydroxide solution is sprayed for cleaning to improve surface hydrophilicity; ultrasonic cleaning is used to remove tiny particles, and the surface is spun dry to ensure it is dry.

[0054] Then, preliminary bonding of P-type SiC wafers and N-type Si wafers was performed at low temperature; and annealing was carried out in a nitrogen atmosphere at 300°C for 24 hours to enhance the stability of the bonding interface.

[0055] Finally, chemical mechanical polishing (CMP) is used to remove part of the Si layer to form an N-type Si epitaxial layer, preparing for the formation of the source region.

[0056] S3. Oxide-buried trenches are formed using partial etching and localized oxidation techniques.

[0057] First, a layer of photoresist is coated on the surface of the N-type Si epitaxial layer. Then, windows are created in the trench structure region through the exposure and development steps of the photolithography process. Subsequently, wet etching or plasma etching is used to etch the trench, forming a trench with a depth and width of 2 μm, extending into the N-type SiC epitaxial layer. The trench is then filled with SiO2 dielectric using chemical vapor deposition (CVD) to form buried oxide trench 6, where TEOS is used as the raw material for the SiO2 film. This filling process ensures complete trench filling, thereby improving the stability and insulation performance of the trench structure and providing a reliable foundation for the smooth progress of subsequent processes.

[0058] S4. The base region 3 is formed using ion implantation technology.

[0059] Before ion implantation, a crucial pretreatment step is to grow a thin oxide layer on the Si wafer surface. This layer primarily serves as a buffer for the subsequent ion implantation process, preventing potential damage to the Si substrate, including lattice structure disruption and non-uniform impurity distribution. First, the P-well (i.e., the P-type base region) area is defined using photolithography. Then, boron ions are implanted. Following implantation, annealing is performed. The main purpose of annealing is to repair lattice damage caused during ion implantation, activate the implanted boron ions to become effective charge carriers, and ensure their uniform distribution throughout the P-well region. The final concentration achieved is 5 × 10⁻⁶. 17 cm-3 And a P-well with a junction depth of 3 μm.

[0060] S5. Prepare the gate oxide layer 8 and the gate electrode 9.

[0061] First, a very thin oxide film is grown using dry oxygen oxidation technology, ensuring good adhesion between the oxide layer and the silicon substrate and the initial oxide layer quality. Then, a thicker oxide layer is rapidly generated using wet oxygen oxidation, significantly improving fabrication efficiency. However, the wet oxygen oxide layer may be relatively porous; therefore, dry oxygen oxidation is performed again to form a dense and high-quality top oxide film. This dry-wet-dry oxygen composite oxidation method ensures the overall performance and stability of the gate oxide layer.

[0062] After completing the gate oxide layer, the planar gate is then fabricated. First, a gate oxide layer with a thickness of 0.05 μm is formed using dry oxidation technology; then, polysilicon is deposited on the gate oxide layer using low-pressure chemical vapor deposition (LPCVD) technology to form a uniform and high-quality polysilicon gate.

[0063] S6, impurity doping in the active region.

[0064] First, the source region is precisely defined on the surface of the N-type Si epitaxial layer using photolithography. Then, phosphorus ions are implanted into the selected region using an N+ ion implantation process to obtain a doping concentration of 1×10⁻⁶. 20 cm -3 The N+ source region is formed; then, boron ions are implanted, and the implanted boron ions are activated by a high-temperature annealing process, while the damage in the lattice is repaired, forming a stable P+ channel substrate contact and P+ drain region, and the channel is formed by double diffusion technology.

[0065] S7. Formation of device electrodes.

[0066] Metal vias are etched in the contact area of ​​the device using etching technology. Aluminum metal is deposited into these vias using deposition technology. Then, through steps such as resist coating, photolithography, development, aluminum etching, and resist removal, aluminum electrodes with reliable electrical connection and excellent conductivity are formed as source 10 and drain 11.

[0067] Furthermore, simulations of the device fabricated in this embodiment were performed. Senterus TCAD simulations show that the device in this embodiment exhibits improved performance compared to traditional silicon-based L-IGBTs. With the same drift region length and doping concentration in both devices, the breakdown voltage of the device in this embodiment is 2-3 times higher than that of traditional silicon-based L-IGBTs. For example, in an L-IGBT with a drift region length of 4 μm, the device in this embodiment, employing both silicon carbide and silicon epitaxial layers and featuring buried oxide trenches, has a breakdown voltage 160% higher than that of traditional silicon-based L-IGBTs.

[0068] Furthermore, Senterus TCAD simulations were performed on a device using gallium nitride epitaxial layers and silicon epitaxial layers with buried oxide trenches. When the drift region length of the L-IGBT is 4μm, the breakdown voltage of the device in this embodiment is 160% higher than that of the traditional silicon-based L-IGBT.

[0069] This embodiment uses a wide bandgap material as the substrate. A wide bandgap epitaxial layer and a silicon epitaxial layer are sequentially grown on the substrate surface using heteroepitaxial technology or bonding technology, constructing a composite drift region structure. Subsequently, through photolithography and dry etching processes, a buried oxide trench structure is formed at the interface between the silicon epitaxial layer and the wide bandgap epitaxial layer, penetrating the silicon layer and partially extending into the wide bandgap epitaxial layer. This design, through the longitudinal folding of the drift region by the buried oxide trench, combined with the high critical breakdown electric field characteristics of the wide bandgap material, utilizes the electric field shielding and breakdown point transfer mechanism to transfer the high electric field concentration effect in traditional silicon-based devices to the gallium nitride region, achieving a uniform reconstruction of the electric field distribution and effectively overcoming the physical bottleneck of single silicon material in terms of voltage withstand performance. Simultaneously, the excellent thermal conductivity of the wide bandgap material significantly improves the device's heat dissipation capability. Combined with the optimized control of the current path by the buried oxide trench, the reliability of the device under high-temperature operating conditions is improved by more than 30%, providing a novel technical solution for high-frequency, high-voltage power electronics applications.

[0070] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A lateral insulated gate bipolar transistor, characterized in that, include: Substrate (1), epitaxial layer (2), base region (3), channel substrate contact (4), source region (5), buried oxide trench (6), drain region (7), gate oxide layer (8), gate (9), source (10), and drain (11), wherein, The epitaxial layer (2) is located on the substrate (1); The base region (3), the buried oxide trench (6) and the drain region (7) all extend from the surface of the epitaxial layer (2) to the interior of the epitaxial layer (2), and the buried oxide trench (6) is located between the base region (3) and the drain region (7), and the depth of the buried oxide trench (6) is less than the depth of the base region (3); The channel substrate contact (4) and the source region (5) both extend from the surface of the base region (3) into the interior of the epitaxial layer (2), and the channel substrate contact (4) and the source region (5) are adjacent to each other, with a channel formed in the base region (3) on one side of the source region (5); The gate oxide layer (8) covers a portion of the surface of the source region (5), the channel, and a portion of the surface of the epitaxial layer (2); the gate electrode (9) is located on the gate oxide layer (8); the source electrode (10) covers a portion of the surface of the channel substrate contact (4) and a portion of the surface of the source region (5); the drain electrode (11) is located on the drain region (7); The substrate (1), the base region (3), the channel substrate contact (4), and the drain region (7) all have a first doping type; the epitaxial layer (2) and the source region (5) both have a second doping type.

2. The lateral insulated gate bipolar transistor according to claim 1, characterized in that, The epitaxial layer (2) includes a wide bandgap material epitaxial layer (21) and a silicon epitaxial layer (22), wherein, The wide bandgap material epitaxial layer (21) is located on the substrate (1), and the silicon epitaxial layer (22) is located on the wide bandgap material epitaxial layer (21); both the wide bandgap material epitaxial layer (21) and the silicon epitaxial layer (22) have a second doping concentration; The base region (3), the buried oxide trench (6), and the drain region (7) all extend from the surface of the silicon epitaxial layer (22) into the wide bandgap material epitaxial layer (21). The channel substrate contact (4) and the source region (5) are located in the base region (3) and extend from the surface of the silicon epitaxial layer (22) into the wide bandgap material epitaxial layer (21). A PN junction is formed between the base region (3) and the wide bandgap material epitaxial layer (21), and the channel is located in the silicon epitaxial layer (22).

3. The lateral insulated gate bipolar transistor according to claim 2, characterized in that, The thickness of the wide bandgap material epitaxial layer (21) is greater than the thickness of the silicon epitaxial layer (22).

4. The lateral insulated gate bipolar transistor according to claim 2, characterized in that, The thickness of the silicon epitaxial layer (22) is 0.5 μm to 1 μm, and the thickness of the wide bandgap material epitaxial layer (21) is 2 μm to 3 μm; The doping concentration of the wide bandgap material epitaxial layer (21) and the silicon epitaxial layer (22) is 3 × 10⁻⁶. 15 cm -3 ~9×10 15 cm -3 .

5. The lateral insulated gate bipolar transistor according to claim 2, characterized in that, The base region (3) extends into the wide bandgap material epitaxial layer (21) to a depth of 2 μm to 4 μm; The depth to which the channel substrate contact (4), the source region (5), and the drain region (7) extend into the wide bandgap material epitaxial layer (21) is 0.5 μm to 1 μm.

6. The lateral insulated gate bipolar transistor according to claim 1, characterized in that, The substrate (1) is made of a wide bandgap material; The doping concentration of the substrate (1) is 1×10⁻⁶. 13 cm -3 ~1×10 15 cm -3 .

7. The lateral insulated gate bipolar transistor according to any one of claims 2-6, characterized in that, The wide bandgap material includes one or more of silicon carbide, gallium nitride, diamond, and gallium oxide.

8. The lateral insulated gate bipolar transistor according to claim 1, characterized in that, The width of the buried oxygen type trench (6) is 1μm to 3μm and the depth is 1μm to 3μm; The distance from the first boundary of the buried oxide trench (6) to the base region (3) is 1 μm to 2 μm, the distance from the second boundary to the drain region (7) is 1 μm to 2 μm, and the distance from the bottom to the substrate (1) is 0.5 μm to 2 μm.

9. A method for fabricating a lateral insulated gate bipolar transistor, characterized in that, Including the following steps: Provide substrate (1); An epitaxial layer (2) is prepared on the substrate (1); The epitaxial layer (2) is partially etched using partial etching technology to form trenches, and silicon dioxide is filled into the trenches using local oxidation technology to form buried oxide trenches (6). Ion implantation technology is used to implant ions into the epitaxial layer (2) to form a base region (3); wherein the depth of the buried oxide trench (6) is less than the depth of the base region (3); A gate oxide layer (8) is prepared on a portion of the surface of the source region (5), the trench, and the epitaxial layer (2), and a gate (9) is prepared on the gate oxide layer (8); Ion implantation is performed in the base region (3) to form adjacent channel substrate contacts (4) and source regions (5), and a channel is formed between the source region (5) and the base region (3) using a double diffusion technique; ion implantation is performed in the epitaxial layer (2) to form a drain region (7), wherein the buried oxide trench (6) is located between the base region (3) and the drain region (7); A passivation layer is deposited on the device surface, and the passivation layer on the surface of the channel substrate contact (4) and the surface of the source region (5) is etched to form a source region contact hole, and the passivation layer on the drain region (7) is etched to form a drain region contact hole; then metal is deposited on the device surface to form a source electrode (10) in the source region contact hole and a drain electrode (11) in the drain region contact hole; The substrate (1), the base region (3), the channel substrate contact (4) and the drain region (7) all have a first doping type; the epitaxial layer (2) and the source region (5) all have a second doping type.

10. The lateral insulated gate bipolar transistor according to claim 9, characterized in that, The preparation of the epitaxial layer (2) on the substrate (1) includes: A wide-bandgap material epitaxial layer (21) is epitaxially grown on the substrate (1); A silicon epitaxial layer (22) is prepared on the wide bandgap material epitaxial layer (21), wherein both the wide bandgap material epitaxial layer (21) and the silicon epitaxial layer (22) have a second doping type.

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