Transistor structure preparation method, device, equipment and medium
By controlling the relationship between the gate oxide thickness and the emitter width, the β value of the BJT can be precisely adjusted, solving the problem of inefficient adjustment of the β value in the prior art and achieving a more stable and reliable circuit design.
Patent Information
- Application Number
- CN202511493052.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-17
- Publication Date
- 2026-02-17
AI Technical Summary
Existing technologies make it difficult to efficiently adjust the current amplification factor β in a fabricated bipolar junction transistor (BJT), leading to the need to introduce negative feedback to define the closed-loop gain in circuit designs that aim for stability, reliability, and accuracy.
By controlling the gate oxide layer thickness and combining it with a linear fitting algorithm, the correlation between the gate oxide layer thickness and the transistor current amplification factor β and emitter width is established, thereby precisely controlling the β value of the fabricated transistor.
This enables precise control of transistor electrical performance parameters during fabrication, simplifies process steps, reduces costs, and improves the controllability of β values and the stability of circuit design.
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Figure CN121548058A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method, apparatus, equipment and medium for fabricating a transistor structure. Background Technology
[0002] For a fabricated bipolar junction transistor (BJT), its current amplification factor β is primarily determined by the device's physical structure (such as base region width and doping concentration), and is an inherent property that is difficult to significantly change after manufacturing. Therefore, engineers typically alter the β value of the BJT during fabrication by adjusting the position, size, or doping concentration of the ion implantation region.
[0003] For discrete BJTs, their effective beta value can generally be affected within a certain range by changing their static operating point (mainly Ic). However, in circuit design that pursues stability, reliability, and accuracy, engineers almost always introduce negative feedback to define a closed-loop gain that is independent of the transistor's own beta, thereby achieving effective "adjustment" and control of the amplification factor.
[0004] How to provide a simpler and more efficient method for adjusting the β value of BJT preparation is one of the technical problems that researchers urgently need to solve. Summary of the Invention
[0005] Therefore, it is necessary to provide a method, apparatus, equipment, and dielectric for fabricating transistor structures to address the problems mentioned in the background art. This method can at least precisely control the β value of the fabricated transistor by controlling the thickness of the gate oxide layer according to the process node parameters, thereby accurately controlling the electrical performance parameters of the fabricated transistor.
[0006] To achieve the above and other objectives, one aspect of this disclosure provides a method for fabricating a transistor structure, comprising:
[0007] The process node parameters of the transistor structure and the corresponding gate oxide thickness adjustment model are obtained. The gate oxide thickness adjustment model includes the correlation between the gate oxide thickness and the transistor current amplification factor β, and the correlation between the gate oxide thickness and the emitter width. Based on the target β value of the transistor structure and the correlation between the gate oxide thickness and the transistor current amplification factor β, the target gate oxide thickness of the transistor structure is determined. Based on the target gate oxide thickness and the correlation between the gate oxide thickness and the emitter width, the target emitter width value of the transistor structure is determined. Before fabricating the source / drain regions of the transistor structure, the semiconductor equipment is controlled to fabricate the gate oxide layer of the transistor structure according to the target gate oxide thickness. The semiconductor equipment is controlled to fabricate the emitter region of the transistor structure according to the target emitter width value.
[0008] The transistor structure fabrication method in the above embodiments first establishes a gate oxide thickness adjustment model for transistor structures at different process nodes. This gate oxide thickness adjustment model includes the correlation between the gate oxide thickness and the transistor current amplification factor β value corresponding to different process node parameters, as well as the correlation between the gate oxide thickness and the emitter width. This allows for obtaining the correlation between the gate oxide thickness and the transistor current amplification factor β value, and the correlation between the gate oxide thickness and the emitter width, after acquiring the process node parameters of the transistor structure. Then, based on the target β value of the transistor structure and the correlation between the gate oxide thickness and the transistor current amplification factor β value, the target gate oxide thickness of the transistor structure is determined. Based on the target gate oxide thickness and the correlation between the gate oxide thickness and the emitter width, the target emitter width value of the transistor structure is determined. Before fabricating the source / drain regions of the transistor structure, the semiconductor equipment is controlled to fabricate the gate oxide layer of the transistor structure based on the target gate oxide thickness. Finally, the semiconductor equipment is controlled to fabricate the emitter region of the transistor structure based on the target emitter width value. At least it can achieve precise control of the β value of the fabricated transistor by controlling the gate oxide layer thickness according to the process node parameters, so as to precisely control the electrical performance parameters of the fabricated transistor.
[0009] In some embodiments, the relationship between gate oxide thickness and transistor current amplification factor β includes: the transistor current amplification factor β decreases as the gate oxide thickness increases.
[0010] In some embodiments, the relationship between the gate oxide thickness T and the transistor current amplification factor β includes:
[0011] β = K1•T + B1;
[0012] In the above formula, -0.02 <K1<-0.0013;B1> 0.
[0013] In some embodiments, the relationship between gate oxide thickness and emitter width includes:
[0014] The emitter width decreases as the gate oxide thickness increases.
[0015] In some embodiments, the relationship between the gate oxide thickness T and the emitter width W includes:
[0016] W = K2•T + B2;
[0017] In the above formula, -0.001 <K2<-0.0003;B2> 0.
[0018] In some embodiments, the thickness of the gate oxide layer ranges from 15 angstroms to 45 angstroms.
[0019] In some embodiments, the range of β includes 1.1-1.7.
[0020] In some embodiments, a transistor structure fabrication apparatus is provided, including a gate oxide thickness adjustment model acquisition module, a target gate oxide thickness determination module, a target emitter width value determination module, and a machine control module. The gate oxide thickness adjustment model acquisition module is used to acquire the process node parameters of the transistor structure and the corresponding gate oxide thickness adjustment model. The gate oxide thickness adjustment model includes the correlation between the gate oxide thickness and the transistor current amplification factor β, and the correlation between the gate oxide thickness and the emitter width. The target gate oxide thickness determination module is used to determine the target gate oxide thickness of the transistor structure based on the target β value of the transistor structure and the correlation between the gate oxide thickness and the transistor current amplification factor β. The target emitter width value determination module is used to determine the target emitter width value of the transistor structure based on the target gate oxide thickness and the correlation between the gate oxide thickness and the emitter width. The machine control module is used to control the semiconductor machine to fabricate the gate oxide layer of the transistor structure according to the target gate oxide thickness before fabricating the source / drain region of the transistor structure. The machine control module is also used to control the semiconductor machine to fabricate the emitter region of the transistor structure according to the target emitter width value.
[0021] In some embodiments, the relationship between gate oxide thickness and transistor current amplification factor β includes:
[0022] The transistor current amplification factor β decreases as the gate oxide thickness increases.
[0023] In some embodiments, the relationship between gate oxide thickness and emitter width includes:
[0024] The emitter width decreases as the gate oxide thickness increases.
[0025] In some embodiments, a transistor structure fabrication apparatus is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of any transistor structure fabrication method in the embodiments of this application.
[0026] In some embodiments, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of any transistor structure fabrication method in the embodiments of this application.
[0027] In some embodiments, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the transistor structure fabrication methods described above.
[0028] The transistor structure fabrication method, apparatus, device, and medium in this disclosure have the following unexpected beneficial effects:
[0029] After obtaining the process node parameters of the transistor structure, the system can determine the correlation between the gate oxide thickness and the transistor current amplification factor β, as well as the correlation between the gate oxide thickness and the emitter width. Then, based on the target β value of the transistor structure and the correlation between the gate oxide thickness and the transistor current amplification factor β, the target gate oxide thickness of the transistor structure is determined. Based on the target gate oxide thickness and the correlation between the gate oxide thickness and the emitter width, the target emitter width of the transistor structure is determined. Before fabricating the source / drain regions of the transistor structure, the semiconductor equipment is controlled to fabricate the gate oxide layer based on the target gate oxide thickness. The semiconductor equipment is then controlled to fabricate the emitter region of the transistor structure based on the target emitter width. This achieves at least the ability to precisely control the β value of the fabricated transistor by specifically controlling the gate oxide thickness according to the process node parameters, thereby precisely controlling the electrical performance parameters of the fabricated transistor. Attached Figure Description
[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic flowchart of a transistor structure fabrication method provided in one embodiment of this application;
[0032] Figure 2 This is a schematic diagram illustrating the relationship between the gate oxide layer thickness and the transistor current amplification factor β in one embodiment of this application;
[0033] Figure 3 This is a schematic diagram illustrating the relationship between the gate oxide layer thickness and the emitter width in one embodiment of this application;
[0034] Figure 4 This is a schematic diagram comparing the gate oxide thickness and current amplification factor β of a transistor fabricated under one embodiment of this application with that fabricated under basic conditions.
[0035] Figure 5 This is a schematic cross-sectional view of a BJT transistor provided in one embodiment of this application.
[0036] Figure 6 This is a schematic diagram of a transistor structure fabrication apparatus provided in one embodiment of this application.
[0037] Explanation of reference numerals in the attached figures:
[0038] e. Emitter; b. Base region; c. Collector; 1000. Transistor structure fabrication device; 101. Gate oxide thickness adjustment model acquisition module; 102. Target gate oxide thickness determination module; 103. Target emitter width value determination module; 104. Machine control module. Detailed Implementation
[0039] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0043] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0044] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.
[0045] Depending on the doping type of the intermediate semiconductor layer, BJTs are mainly divided into NPN transistors and PNP transistors. The current amplification factor β of a single BJT is uncontrollable and highly variable. Engineers typically achieve stable and controllable amplification through the following methods:
[0046] 1) Component screening and matching
[0047] In applications requiring precise β values, transistors with specific β values are selected directly from a batch of transistors, or matched pairs of transistors are used (as in differential amplifiers).
[0048] 2) Use negative feedback
[0049] Instead of relying on the unstable β of the BJT itself, a stable and accurate closed-loop gain is constructed through an external resistor network.
[0050] 3) Use Darlington Pair tubing.
[0051] Connecting two BJTs together, the total β_total value is approximately the product of β1 and β2 of the two different transistors. This can achieve extremely high current amplification, but at the cost of higher saturation voltage drop and slower switching speed.
[0052] Based on this, the present disclosure aims to provide a method, apparatus, device and medium for fabricating a transistor structure, which can at least precisely control the β value of the fabricated transistor by controlling the thickness of the gate oxide layer according to the process node parameters, so as to precisely control the electrical performance parameters of the fabricated transistor.
[0053] In some embodiments, please refer to Figure 1 A method for fabricating a transistor structure is provided, comprising:
[0054] Step S12: Obtain the process node parameters of the transistor structure and the corresponding gate oxide thickness adjustment model. The gate oxide thickness adjustment model includes the relationship between the gate oxide thickness and the transistor current amplification factor β, as well as the relationship between the gate oxide thickness and the emitter width.
[0055] Step S14: Determine the target gate oxide thickness of the transistor structure based on the target β value of the transistor structure and the correlation between the gate oxide thickness and the transistor current amplification factor β value;
[0056] Step S15: Determine the target emitter width value of the transistor structure based on the target gate oxide thickness and the relationship between the gate oxide thickness and the emitter width;
[0057] Step S16: Before fabricating the source / drain region of the transistor structure, the gate oxide layer of the transistor structure is fabricated using a semiconductor apparatus according to the target gate oxide layer thickness.
[0058] Step S18: Control the semiconductor equipment to fabricate the emitter region of the transistor structure according to the target emitter width value.
[0059] For example, firstly, a gate oxide thickness adjustment model for transistor structures at different process nodes is established. This model includes the correlation between the gate oxide thickness and the transistor current amplification factor β value corresponding to different process node parameters, as well as the correlation between the gate oxide thickness and the emitter width. This allows for obtaining the correlation between the gate oxide thickness and the transistor current amplification factor β value, and the correlation between the gate oxide thickness and the emitter width, after acquiring the process node parameters of the transistor structure. Then, based on the target β value of the transistor structure and the correlation between the gate oxide thickness and the transistor current amplification factor β value, the target gate oxide thickness of the transistor structure is determined. Based on the target gate oxide thickness and the correlation between the gate oxide thickness and the emitter width, the target emitter width value of the transistor structure is determined. Before fabricating the source / drain regions of the transistor structure, the semiconductor equipment is controlled to fabricate the gate oxide layer of the transistor structure based on the target gate oxide thickness. The semiconductor equipment is controlled to fabricate the emitter region of the transistor structure based on the target emitter width value. This at least achieves precise control of the β value of the fabricated transistor by specifically controlling the gate oxide thickness according to the process node parameters, thereby precisely controlling the electrical performance parameters of the fabricated transistor.
[0060] During the research and fabrication of BJT transistors, the applicant discovered that as the gate oxide layer thickness increases, the ion implantation depth decreases after gate oxide layer formation, leading to a reduction in the base region width and a decrease in the current amplification factor β. After further compiling extensive data on gate oxide layer thickness, corresponding emitter width, and β values, the applicant used a fitting algorithm to find that both the transistor current amplification factor β and the emitter width decrease with increasing gate oxide layer thickness.
[0061] For example, after obtaining the gate oxide thickness data, corresponding emitter width data, and β value data of a PNP type BJT transistor with a process node of 65nm, a gate oxide thickness adjustment model is established using a linear fitting algorithm.
[0062] For example, since the transistor current amplification factor β decreases with increasing gate oxide thickness, the following mathematical relationship can be obtained by fitting the relationship between gate oxide thickness and transistor current amplification factor β using a linear fitting algorithm:
[0063] β = K1•T + B1;
[0064] In the above formula, -0.02 <K1<-0.0013;B1> 0.
[0065] For example, please refer to Figure 2After obtaining the gate oxide thickness data, corresponding emitter width data, and β value data of a 65nm PNP BJT transistor, a linear fitting algorithm is used to fit the relationship between the gate oxide thickness and the transistor current amplification factor β, resulting in the following mathematical formula:
[0066] β = -0.0075•T + 1.8296;
[0067] The above formula, obtained with a coefficient of determination (R²) of 0.9999, indicates that the experimental data and the fitting function have a good agreement.
[0068] For example, after obtaining the gate oxide thickness data, corresponding emitter width data, and β value data of a PNP type BJT transistor with a process node of 65nm, a linear fitting algorithm is used to fit the correlation between the gate oxide thickness T and the emitter width W, including:
[0069] W = K2•T + B2;
[0070] In the above formula, -0.001 <K2<-0.0003;B2> 0.
[0071] For example, please refer to Figure 3 The relationship between the gate oxide thickness T and the emitter width W was fitted using a linear fitting algorithm, including:
[0072] W = -0.0006•T + 0.133;
[0073] The above formula, obtained with a coefficient of determination (R²) of 0.945, indicates that the experimental data and the fitting function have a good agreement.
[0074] Furthermore, in studying the gate oxide thickness data, corresponding emitter width data, and β value data of PNP-type BJT transistors at a process node of 65nm, to obtain the correlation between gate oxide thickness and transistor current amplification factor β, and the correlation between gate oxide thickness and emitter width, the applicant discovered that the gate oxide thickness range includes 15 angstroms to 45 angstroms. For example, the gate oxide thickness can be 15 angstroms, 25 angstroms, 35 angstroms, or 45 angstroms. This avoids excessively thick gate oxide layers, which would result in an excessively small β value; and also avoids excessively thin gate oxide layers, which would increase the risk of inducing gate leakage current channels.
[0075] Furthermore, in studying the gate oxide thickness data, corresponding emitter width data, and β value data of PNP-type BJT transistors with a process node of 65nm, to obtain the correlation between gate oxide thickness and transistor current amplification factor β, and the correlation between gate oxide thickness and emitter width, the applicant found that the range of β includes 1.1-1.7. Since the gate oxide thickness not only affects the transistor current amplification factor β, but also the emitter width W, and consequently the base region width, in order to ensure excellent overall performance parameters of the fabricated BJT transistors, the range of current amplification factor β was determined to be 1.1-1.7, for example, β of 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, or 1.7, to ensure the overall electrical performance and yield of the fabricated BJT transistors.
[0076] The applicant measured a 65nm BJT transistor under conventional process conditions. With a gate oxide thickness of 91 Å, the current amplification factor β was 1.1. These conditions included adjusting the position, size, or doping concentration of the ion implantation region to change the β value of the BJT. Using the method described in this application, the correlation between the gate oxide thickness and the transistor's current amplification factor β, as well as the correlation between the gate oxide thickness and the emitter width, was obtained. With a target gate oxide thickness of 91 Å - 60 Å = 31 Å, the current amplification factor β was determined to be 1.5. Therefore, this application effectively reduces the gate oxide thickness without decreasing the current amplification factor β, and avoids the additional steps of changing the position, size, or doping concentration of the ion implantation region, effectively reducing the complexity and cost of the fabrication process. Furthermore, the β value of the fabricated transistor can be precisely controlled by adjusting the gate oxide thickness according to process node parameters, thereby precisely controlling the electrical performance parameters of the fabricated transistor.
[0077] In some embodiments, the provided transistor structure is as follows: Figure 5 As shown, the P-substrate can be made of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, the substrate can include, for example, Si / SiGe, Si / SiC, etc. Therefore, the type of substrate should not limit the scope of this disclosure.
[0078] Please continue to refer to this. Figure 5An N-type doped region is formed in a P-type substrate, and a P-type doped region is located within the N-type doped region. The emitter e covers part of the top surface of the P-type doped region, the base region b covers part of the top surface of the N-type doped region, and the collector c is located on the surface of the P-type substrate away from the P-type doped region.
[0079] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Furthermore, Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0080] In some embodiments, please refer to Figure 6 A transistor structure fabrication apparatus 1000 is provided, including a gate oxide thickness adjustment model acquisition module 101, a target gate oxide thickness determination module 102, a target emitter width determination module 103, and a machine control module 104. The gate oxide thickness adjustment model acquisition module 101 is used to acquire the process node parameters of the transistor structure and the corresponding gate oxide thickness adjustment model. The gate oxide thickness adjustment model includes the correlation between the gate oxide thickness and the transistor current amplification factor β, and the correlation between the gate oxide thickness and the emitter width. The target gate oxide thickness determination module 102 is used to determine the target gate oxide thickness based on the transistor structure... The target gate oxide thickness of the transistor structure is determined by the correlation between the target β value and the gate oxide thickness and the transistor current amplification factor β value. The target emitter width determination module 103 is used to determine the target emitter width value of the transistor structure based on the target gate oxide thickness and the correlation between the gate oxide thickness and the emitter width. The machine tool control module 104 is used to control the semiconductor machine to fabricate the gate oxide layer of the transistor structure according to the target gate oxide thickness before fabricating the source / drain region of the transistor structure. The machine tool control module 104 is also used to control the semiconductor machine to fabricate the emitter region of the transistor structure according to the target emitter width value.
[0081] In some embodiments, the relationship between gate oxide thickness and transistor current amplification factor β includes:
[0082] The transistor current amplification factor β decreases as the gate oxide thickness increases.
[0083] In some embodiments, the relationship between gate oxide thickness and emitter width includes:
[0084] The emitter width decreases as the gate oxide thickness increases.
[0085] For example, after obtaining the gate oxide thickness data, corresponding emitter width data, and β value data of a PNP type BJT transistor with a process node of 65nm, a gate oxide thickness adjustment model is established using a linear fitting algorithm.
[0086] For example, since the transistor current amplification factor β decreases with increasing gate oxide thickness, the following mathematical relationship can be obtained by fitting the relationship between gate oxide thickness and transistor current amplification factor β using a linear fitting algorithm:
[0087] β = K1•T + B1;
[0088] In the above formula, -0.02 <K1<-0.0013;B1> 0.
[0089] For example, please refer to Figure 2 After obtaining the gate oxide thickness data, corresponding emitter width data, and β value data of a 65nm PNP BJT transistor, a linear fitting algorithm is used to fit the relationship between the gate oxide thickness and the transistor current amplification factor β, resulting in the following mathematical formula:
[0090] β = -0.0075•T + 1.8296;
[0091] The above formula, obtained with a coefficient of determination (R²) of 0.9999, indicates that the experimental data and the fitting function have a good agreement.
[0092] For example, after obtaining the gate oxide thickness data, corresponding emitter width data, and β value data of a PNP type BJT transistor with a process node of 65nm, a linear fitting algorithm is used to fit the correlation between the gate oxide thickness T and the emitter width W, including:
[0093] W = K2•T + B2;
[0094] In the above formula, -0.001 <K2<-0.0003;B2> 0.
[0095] For example, please refer to Figure 3 The relationship between the gate oxide thickness T and the emitter width W was fitted using a linear fitting algorithm, including:
[0096] W = -0.0006•T + 0.133;
[0097] The above formula, obtained with a coefficient of determination (R²) of 0.945, indicates that the experimental data and the fitting function have a good agreement.
[0098] Furthermore, in studying the gate oxide thickness data, corresponding emitter width data, and β value data of PNP-type BJT transistors at a process node of 65nm, to obtain the correlation between gate oxide thickness and transistor current amplification factor β, and the correlation between gate oxide thickness and emitter width, the applicant discovered that the gate oxide thickness range includes 15 angstroms to 45 angstroms, for example, the gate oxide thickness can be 15 angstroms, 25 angstroms, 35 angstroms, or 45 angstroms. This avoids excessively thick gate oxide layers, which would result in an excessively small β value; and also avoids excessively thin gate oxide layers, which would increase the risk of inducing gate leakage current channels.
[0099] Furthermore, in studying the gate oxide thickness data, corresponding emitter width data, and β value data of PNP-type BJT transistors with a process node of 65nm, to obtain the correlation between gate oxide thickness and transistor current amplification factor β, and the correlation between gate oxide thickness and emitter width, the applicant found that the range of β includes 1.1-1.7. Since the gate oxide thickness not only affects the transistor current amplification factor β, but also the emitter width W, and consequently the base region width, in order to ensure excellent overall performance parameters of the fabricated BJT transistors, the range of current amplification factor β was determined to be 1.1-1.7, for example, β of 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, or 1.7, to ensure the overall electrical performance and yield of the fabricated BJT transistors.
[0100] In some embodiments, a transistor structure fabrication apparatus is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of any transistor structure fabrication method in the embodiments of this application.
[0101] In some embodiments, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of any transistor structure fabrication method in the embodiments of this application.
[0102] In some embodiments, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the transistor structure fabrication methods described above.
[0103] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include non-volatile, volatile, or combinations thereof. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), or graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application can include relational databases, non-relational databases, or combinations thereof. Non-relational databases can include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, or quantum computing-based data processing logic devices, etc., and are not limited to these.
[0104] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.
[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0107] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.
Claims
1. A method of fabricating a transistor structure, comprising: The method comprises: acquiring process node parameters of the transistor structure and a corresponding gate oxide layer thickness adjustment model, the gate oxide layer thickness adjustment model comprising a correlation between gate oxide layer thickness and transistor current amplification multiple β value, and a correlation between gate oxide layer thickness and emitter width; determining a target gate oxide layer thickness of the transistor structure according to a target β value of the transistor structure and the correlation between gate oxide layer thickness and transistor current amplification multiple β value; determining a target emitter width value of the transistor structure according to the target gate oxide layer thickness and the correlation between gate oxide layer thickness and emitter width; controlling a semiconductor machine to prepare a gate oxide layer of the transistor structure according to the target gate oxide layer thickness before preparing a source region / drain region of the transistor structure; controlling a semiconductor machine to prepare an emitter region of the transistor structure according to the target emitter width value.
2. The method of claim 1, wherein the step of forming the gate electrode is performed after the step of forming the source and drain regions. The correlation between the gate oxide layer thickness and the transistor current amplification multiple β value comprises: The transistor current amplification multiple β value decreases with the increase of the gate oxide layer thickness.
3. The method of claim 1, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first gate electrode and a second gate electrode, and forming a gate insulating layer between the first gate electrode and the second gate electrode. The correlation between the gate oxide layer thickness T and the transistor current amplification multiple β value comprises: β=K1•T+B1; In the above formula, -0.02 4. The method of claim 1, wherein The correlation between the gate oxide layer thickness and the emitter width comprises: The emitter width decreases with the increase of the gate oxide layer thickness.
5. The method for fabricating a transistor structure according to claim 1, characterized in that, The correlation between the gate oxide layer thickness T and the emitter width W comprises: W=K2•T+B2; In the above formula, -0.001 6. The method of claim 1-5, wherein The method further comprises at least one of the following features: The thickness range of the gate oxide layer comprises: 15 angstroms-45 angstroms; The range of β comprises: 1.1-1.
7.
7. A transistor structure fabrication apparatus, characterized in that, The method comprises: a gate oxide layer thickness adjustment model acquisition module, configured to acquire process node parameters of the transistor structure and a corresponding gate oxide layer thickness adjustment model, the gate oxide layer thickness adjustment model comprising a correlation between gate oxide layer thickness and transistor current amplification multiple β value, and a correlation between gate oxide layer thickness and emitter width; a target gate oxide layer thickness determination module, configured to determine a target gate oxide layer thickness of the transistor structure according to a target β value of the transistor structure and the correlation between gate oxide layer thickness and transistor current amplification multiple β value; a target emitter width value determination module, configured to determine a target emitter width value of the transistor structure according to the target gate oxide layer thickness and the correlation between gate oxide layer thickness and emitter width; a machine control module, configured to control a semiconductor machine to prepare a gate oxide layer of the transistor structure according to the target gate oxide layer thickness before preparing a source region / drain region of the transistor structure; and further configured to control a semiconductor machine to prepare an emitter region of the transistor structure according to the target emitter width value. The correlation between the gate oxide layer thickness and the transistor current amplification multiple β value comprises:
8. The transistor structure fabrication apparatus of claim 7, wherein The transistor current amplification multiple β value decreases with the increase of the gate oxide layer thickness; and / or The correlation between the gate oxide layer thickness and the emitter width comprises: The emitter width decreases as the gate oxide layer thickness increases.
9. A transistor structure manufacturing apparatus comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor, when executing the computer program, realizes the steps of the method in any one of claims 1 to 6.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, realizes the steps of the method in any one of claims 1 to 6.