Field effect transistor

Abstract

A field effect transistor suppresses recovery current in a field effect transistor having a deep layer. In the field effect transistor, when a semiconductor substrate is viewed from above, a plurality of contact layers are disposed at intervals in a specific direction parallel to a plurality of trenches in each inter-trench region, and when the semiconductor substrate is viewed from above, a plurality of deep layers are disposed at intervals in the specific direction in each inter-trench region. In each inter-trench region, the spacer portion of the contact layer is disposed on the upper portion of the corresponding deep layer. In each inter-trench region, each of the deep spacers is disposed at a lower portion of the corresponding contact layer.

Description

Technical Field

[0001] (Cross-reference to related applications) This application is a related application to Japanese Patent Application No. 2023-124922, filed on July 31, 2023, and claims priority based on that Japanese patent application, incorporating all the contents described in that Japanese patent application as part of this specification.

[0002] The technology disclosed in this specification relates to field-effect transistors. Background Technology

[0003] The field-effect transistor disclosed in Japanese Patent Application Publication No. 2001-267570 has a trench-type gate electrode. Furthermore, this field-effect transistor has a p-type deep layer (also called a lower electric field shielding region of the base region) extending downwards from the p-type body layer (also called the base region). The deep layer extends to a position lower than the lower end of the trench. A p-type contact layer connecting the body layer and the source electrode is provided on the upper part of the deep layer. The contact layer is provided to stabilize the potential of the body layer. The deep layer is provided to mitigate the electric field strength of the gate insulating film within the trench. Summary of the Invention

[0004] If the potential of the source electrode increases, a forward voltage is applied to the pn junction at the interface between the body layer and the drift layer. Therefore, the diode formed by this pn structure conducts, and holes flow from the body layer into the drift layer. Then, if the potential of the source electrode decreases, holes in the drift layer flow to the source electrode via the deep layer, body layer, and contact layer. The current generated by these holes flowing to the source electrode is called the recovery current. A surge voltage is generated in the field-effect transistor by the flow of the recovery current. High recovery currents are easily generated in the field-effect transistor disclosed in Japanese Patent Application Publication No. 2001-267570. This specification proposes a technique for suppressing recovery currents in field-effect transistors with deep layers.

[0005] The field-effect transistor disclosed in this specification includes: a semiconductor substrate made of a compound semiconductor and having multiple trenches on its upper surface; multiple gate electrodes disposed in corresponding trenches and insulated from the semiconductor substrate by a gate insulating film; and source electrodes connected to the upper surface of the semiconductor substrate. The semiconductor substrate has multiple n-type source layers, multiple p-type contact layers, a p-type body layer, an n-type drift layer, and multiple p-type deep layers. Each semiconductor region located between the multiple trenches in the semiconductor substrate is a trench-interval region. Each source layer is disposed in a corresponding trench-interval region, connected to the source electrode, and connected to the corresponding gate insulating film. Each contact layer is disposed in a corresponding trench-interval region, connected to the source electrode. Multiple contact layers are disposed in each trench-interval region. When viewed from above, in each trench-interval region, the multiple contact layers are spaced apart in a specific direction parallel to the multiple trenches. The body layer has a lower p-type impurity concentration than each contact layer, is distributed across multiple inter-trench regions, is disposed below each source layer and each contact layer, and is in contact with the gate insulating film. The drift layer is distributed across the lower portion of the multiple inter-trench regions, is in contact with the body layer from the bottom in each inter-trench region, and is in contact with the gate insulating film. Each deep layer extends from the body layer to a position lower than the bottom end of each trench. When viewing the semiconductor substrate from above, in each inter-trench region, the multiple deep layers are arranged with spacers in a specific direction. In each inter-trench region, the spacers of the contact layers are respectively disposed above the corresponding deep layer. In each inter-trench region, the spacers of the deep layers are respectively disposed below the corresponding contact layer.

[0006] In this field-effect transistor, the spacers in the contact layer are positioned above the deep layer, and the spacers in the deep layer are positioned below the contact layer. This reduces the area where the contact layer and the deep layer overlap in the vertical direction. Consequently, the resistance of the path from the drift layer through the deep layer, the body layer, and the contact layer to the source electrode (i.e., the path for recovery current flow) is high. Therefore, according to this field-effect transistor, recovery current can be suppressed. Attached Figure Description

[0007] Figure 1 This is a three-dimensional view showing the xz and yz sections of the switching element.

[0008] Figure 2 This is an XZ cross-sectional view of the switching element, excluding the deep locations.

[0009] Figure 3 It is an xz cross-sectional view of the switching element in a deep location.

[0010] Figure 4 This is a yz cross-sectional view of the switching element at a location excluding the groove.

[0011] Figure 5This is a top view of the upper surface of a semiconductor substrate.

[0012] Figure 6 It is a graph showing the distribution of impurity concentration in the contact region, body region, and source region.

[0013] Figure 7 It is a graph showing the drain current and drain voltage during the recovery operation.

[0014] Figure 8 It is a graph showing the relationship between depth D and surge voltage.

[0015] Figure 9 The switching element of the first variation is AND Figure 5 The corresponding top view.

[0016] Figure 10 It is a graph showing the relationship between the width W and the rate of decrease of the surge voltage.

[0017] Figure 11 The switching element of the second variation is AND Figure 5 The corresponding top view.

[0018] Figure 12 The switching element of the third variation is... Figure 5 The corresponding top view.

[0019] Figure 13 The switching element of the fourth variation is AND Figure 5 The corresponding top view.

[0020] Figure 14 The switching element of the fifth variation is AND Figure 5 The corresponding top view. Detailed Implementation

[0021] In one embodiment disclosed in this specification, the deep layers may intersect with the trenches when the semiconductor substrate is viewed from above.

[0022] This configuration can further mitigate the electric field strength of the gate insulating film.

[0023] In one embodiment disclosed in this specification, the contact layers and the deep layers do not overlap when the semiconductor substrate is viewed from above. In this case, the width of the spacing portion of the contact layers can be wider than the width of the deep layers, and the width of the spacing portion of the deep layers can be wider than the width of the contact layers.

[0024] Based on this configuration, recovery current can be suppressed more effectively.

[0025] In one embodiment disclosed in this specification, the deeper spacer portion in each of the trench regions may have a first spacer portion that overlaps with the contact layer when the semiconductor substrate is viewed from above, and a second spacer portion that does not overlap with the contact layer when the semiconductor substrate is viewed from above.

[0026] In one embodiment disclosed in this specification, the lower end of each contact layer may be located at the same position as the lower end of each source layer or at a position above the lower end of each source layer in the thickness direction of the semiconductor substrate.

[0027] Based on this configuration, the depletion of the contact layer can be suppressed, thus enabling more effective suppression of recovery current.

[0028] Figure 1 The MOSFET 10 (metal-oxide-semiconductor field-effect transistor) of the illustrated embodiment has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 will be referred to as the z-direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 (or orthogonal to the z-direction) will be referred to as the x-direction, and a direction orthogonal to both the x-direction and the z-direction will be referred to as the y-direction. The semiconductor substrate 12 is made of silicon carbide (SiC). Alternatively, the semiconductor substrate 12 may also be made of other compound semiconductors such as gallium nitride or gallium oxide. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Figure 5 As shown, a plurality of trenches 14 extend elongatedly along the y-direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x-direction. Furthermore, hereinafter, each semiconductor region within the area enclosed by the trenches 14 will be referred to as the inter-trench region 50.

[0029] like Figures 1-3 As shown, the inner surfaces (i.e., the side surfaces and bottom surfaces) of each trench 14 are covered by a gate insulating film 16. A gate electrode 18 is disposed within each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 through the gate insulating film 16. The upper surface of each gate electrode 18 is covered by an interlayer insulating film 20. A source electrode 22 is disposed on the upper part of the semiconductor substrate 12. The source electrode 22 is covered by each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 through the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at locations where the interlayer insulating film 20 is not present. A drain electrode 24 is disposed on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire area of ​​the lower surface 12b of the semiconductor substrate 12.

[0030] The semiconductor substrate 12 has multiple source layers 30, multiple contact layers 32, a body layer 34, multiple deep layers 36, multiple trench layers 35, a drift layer 38, and a drain layer 40.

[0031] Each contact layer 32 is a p-type layer with a high concentration of p-type impurities. For example... Figure 1 , Figure 2 , Figure 4 , Figure 5 As shown, each contact layer 32 is disposed within the trench region 50. Each contact layer 32 is disposed over a region including the upper surface 12a of the semiconductor substrate 12. Multiple contact layers 32 are provided in each trench region 50. Each contact layer 32 is disposed at a position not in contact with the trench 14. In each trench region 50, multiple contact layers 32 are arranged at intervals along the y-direction (i.e., the direction parallel to the trench 14 on the upper surface 12a). Hereinafter, the region between the contact layers 32 in the y-direction will be referred to as the spacer portion 33. Each contact layer 32 makes ohmic contact with the source electrode 22.

[0032] Each source layer 30 is an n-type layer with a high concentration of n-type impurities. For example... Figures 1-5 As shown, each source layer 30 is disposed within the trench region 50. Each source layer 30 is disposed within the area including the upper surface 12a of the semiconductor substrate 12, but without the contact layer 32. That is, each source layer 30 is disposed within the region adjacent to the trench 14 and the spacer portion 33. The source layer 30 is in contact with the side surface of the contact layer 32. Each source layer 30 is in ohmic contact with the source electrode 22. The uppermost part of each source layer 30 on the side surface of the trench 14 is in contact with the gate insulating film 16. Each source layer 30 is opposed to the gate electrode 18 through the gate insulating film 16.

[0033] Body layer 34 is a p-type layer with a lower p-type impurity concentration than contact layer 32. For example... Figures 1-3 As shown, the body layer 34 is distributed across multiple trench regions 50. The body layer 34 is disposed below the multiple source layers 30 and multiple contact layers 32. The body layer 34 is in contact with the multiple source layers 30 and multiple contact layers 32 from below. The body layer 34 is in contact with the gate insulating film 16 on the side of the trench 14 located below the source layers 30. The body layer 34 is opposed to the gate electrode 18 through the gate insulating film 16.

[0034] like Figure 1 , Figure 4 As shown, each deep layer 36 is a p-type layer protruding downwards from the lower surface of the body layer 34. Each deep layer 36 extends from the lower surface of the body layer 34 to a position lower than the lower end of each trench 14. Figure 5As shown, when viewing the semiconductor substrate 12 from above, each deep layer 36 extends relatively long in the x-direction and intersects the trench 14 at an angle of approximately 90 degrees. That is, each deep layer 36 is distributed across multiple inter-trench regions 50. When viewing the semiconductor substrate 12 from above, the multiple deep layers 36 are arranged at intervals in the y-direction. Hereinafter, the region between the deep layers 36 in the y-direction will be referred to as the spacer portion 37. Figure 3 As shown, each deep layer 36 is in contact with the gate insulating film 16 on the side of the trench 14 located below the body layer 34. Each deep layer 36 is opposite to the gate electrode 18 through the gate insulating film 16.

[0035] like Figures 1-3 As shown, each trench lower layer 35 is a p-type layer disposed at the bottom of the corresponding trench 14. Each trench lower layer 35 extends relatively long along the length direction (i.e., the y-direction) of the corresponding trench 14 and intersects with each deep layer 36. Each trench lower layer 35 is in contact with the gate insulating film 16 on the bottom surface of the corresponding trench 14.

[0036] The drift layer 38 is an n-type layer with a lower n-type impurity concentration than the source layer 30. The drift layer 38 is distributed across the lower portion of multiple inter-trench regions 50. The drift layer 38 is in contact with multiple deep layers 36 and multiple trench underlayers 35 from below. The drift layer 38 is distributed within each spacer 37 between the multiple deep layers 36. Within each spacer 37, the drift layer 38 is in contact with the sides of the multiple deep layers 36 and the sides of the multiple trench underlayers 35. The drift layer 38 extends through each spacer 37 into each inter-trench region 50. Within each inter-trench region 50, the drift layer 38 is in contact with the body layer 34 from below. Within each inter-trench region 50, the drift layer 38 is in contact with the gate insulating film 16. That is, the drift layer 38 is in contact with the gate insulating film 16 on the side of the trench 14 located below the body layer 34.

[0037] The drain layer 40 is an n-type layer with a higher n-type impurity concentration than the drift layer 38. The drain layer 40 is connected to the drift layer 38 from the bottom. The drain layer 40 is disposed over the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0038] Figure 5 This diagram illustrates the positional relationship between the contact layer 32 and the depth layer 36 when viewed from above on the semiconductor substrate 12. In each trench region 50, the spacer portions 33 of the contact layer 32 are disposed above the corresponding depth layer 36. Furthermore, in each trench region 50, the spacer portions 37 of the depth layer 36 are disposed below the corresponding contact layer 32. Each contact layer 32 is positioned so as not to overlap with the depth layer 36 when viewed from above on the semiconductor substrate 12.

[0039] like Figure 2As shown, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30. Figure 6 This indicates the impurity concentration distribution in the z-direction within the source layer 30, contact layer 32, and body layer 34. The lower end 30a of the source layer 30 is defined as the position where the n-type impurity concentration and p-type impurity concentration are the same. In the body layer 34 (i.e., the p-type region lower than the source layer 30), the p-type impurity concentration is distributed in a normal distribution with a peak value P1. In this specification, the contact layer 32 is defined as a p-type layer with a p-type impurity concentration higher than the peak value P1. Therefore, the lower end 32a of the contact layer 32 is defined as the position with the same p-type impurity concentration as the peak value P1. Figure 6 As shown, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30.

[0040] Next, the operation of MOSFET 10 will be explained. If a potential above the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16. The source layer 30 and the drift layer 38 are connected through the channel. When the potential of the drain electrode 24 is higher than the potential of the source electrode 22, electrons flow from the source layer 30 through the channel and the drift layer 38 to the drain layer 40. That is, MOSFET 10 is turned on. If the potential of each gate electrode 18 is reduced to a value below the gate threshold, the channel disappears, and the flow of electrons stops. That is, MOSFET 10 is turned off. When MOSFET 10 is turned off, a depletion layer extends from the body layer 34 to the drift layer 38. Additionally, the depletion layer also extends from the deep layer 36 and the lower trench layer 35 to the drift layer 38. Through the depletion layer extending from the deep layer 36 and the lower trench layer 35, depletion is promoted in the semiconductor region surrounding the lower end of the trench 14. Therefore, the concentration of the electric field to the gate insulating film 16 is suppressed.

[0041] Furthermore, there is a case where a higher potential is applied to the source electrode 22 than to the drain electrode 24. If a higher potential is applied to the source electrode 22 than to the drain electrode 24, the diode formed by the pn structure at the interface between the p-type layer (i.e., the p-type layer composed of the body layer 34, the lower trench layer 35, and the deep layer 36) and the drift layer 38 conducts. That is, holes flow from the p-type layer to the drift layer 38, and electrons flow from the drift layer 38 to the p-type layer. Subsequently, if the applied voltage to the MOSFET 10 changes, causing the potential of the source electrode 22 to become lower than the potential of the drain electrode 24, a recovery operation occurs in the diode. Figure 7 This represents the changes in drain-source voltage Vds and drain current Ids during the recovery operation. During recovery, the depletion layer progresses from the pn junction at the interface between the p-type layer and drift layer 38 into the drift layer, and holes within drift layer 38 are discharged to the source electrode 22 via the p-type layer. Thus, as... Figure 7As shown, the recovery current IR flows. As a result, a surge voltage Vak is generated between the source electrode 22 and the drain electrode 24. In this embodiment, since the deep layer 36 protrudes towards the drift layer 38, holes easily flow from the drift layer 38 into the deep layer 36 during the recovery operation. Therefore, as... Figure 4 As indicated by arrow 100, holes are discharged from the drift layer 38 through the deep layer 36, the body layer 34, and the contact layer 32 to the source electrode 22. In this embodiment, the contact layer 32 is absent above the deep layer 36; therefore, holes passing through the deep layer 36 move laterally within the body layer 34 and then flow towards the contact layer 32. Consequently, the resistance of the hole flow path is high. Therefore, the recovery current IR is suppressed, and the surge voltage Vak is suppressed.

[0042] Furthermore, during the recovery operation, the depletion layer extends from the pn junction into the p-type layer. Holes discharged from the depleted p-type layer to the source electrode 22 also constitute the recovery current. Within the body layer 34, the depletion layer extends upward from the pn junction. If the depletion layer reaches the lower end 30a of the source layer 30, the upward extension of the depletion layer stops. In this embodiment, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30, thus preventing the extension of the depletion layer into the contact layer 32. Therefore, the situation where a high concentration of holes within the contact layer 32 is discharged to the source electrode 22 as a recovery current is prevented. Consequently, the recovery current is further suppressed, and the surge voltage is further suppressed. Figure 8 This indicates the relationship between the depth D of contact layer 32 and the surge voltage Vak. Figure 8 In this context, depth D refers to the relative position of the lower end 32a of the contact layer 32 with respect to the lower end 30a of the source layer 30 in the z-direction. A positive depth D means that the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30. For example... Figure 8 As shown, the greater the depth D (i.e., the more the lower end 32a of the contact layer 32 is located on the upper side), the more the surge voltage Vak is suppressed.

[0043] As explained above, the MOSFET 10 according to the embodiment can suppress recovery current.

[0044] Furthermore, in the above embodiment, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30. However, in the thickness direction of the semiconductor substrate 12, the lower end 32a of the contact layer 32 may also exist at the same position as the lower end 30a of the source layer 30. That is, the depth D may also be zero. Figure 8 As shown, even when the depth D is zero, the surge voltage Vak is suppressed compared to when the depth D is negative.

[0045] Furthermore, in the above embodiment, there is no contact layer 32 above the deep layer 36. However, as... Figure 9 As shown, a portion 32x of the contact layer 32 may also be disposed on the upper part of the depth layer 36. That is, when the semiconductor substrate 12 is viewed from above, a portion 32x of the contact layer 32 may overlap with the depth layer 36. Figure 10 The width W of the overlapping portion of contact layer 32 and deep layer 36 (refer to) Figure 9 The relationship between the width W and the rate of reduction of surge voltage Vak. A negative width W means that contact layer 32 and deep layer 36 do not overlap. Additionally, in Figure 10 In the text, the width Wd refers to the width of the depth 36 in the y-direction (see reference). Figure 9 W=1 / 2Wd means that there is no interval 33. For example... Figure 10 As shown, even when the width W is positive, the surge voltage Vak decreases as the width W decreases from 1 / 2Wd. Thus, even if a portion 32x of the contact layer 32 overlaps with the deep layer 36, the resistance of the recovery current path can be increased by arranging the spacing portion 33 on the upper part of the deep layer 36, thereby suppressing the recovery current.

[0046] Furthermore, in the above embodiment, a contact layer 32 is provided in each spacer 37 of the depth 36. However, as... Figure 11 As shown, in the inter-groove region 50, the contact layer 32 may be less than the spacer portion 37. That is, in Figure 11 In this configuration, the spacer portion 37 has a first spacer portion 37a that overlaps with the contact layer 32 when the semiconductor substrate 12 is viewed from above, and a second spacer portion 37b that does not overlap with the contact layer 32 when the semiconductor substrate 12 is viewed from above. Alternatively, in this case, the contact layer 32 can be evenly distributed.

[0047] Furthermore, in the above embodiment, a source layer 30 is provided in the surface portion near the upper surface 12a, covering the entire area where the contact layer 32 is not present. However, the distribution range of the source layer 30 can be narrower. Figure 12 , Figure 13 This indicates that the distribution range of source layer 30 is greater than that of source layer 30. Figure 5 A narrow example. In Figure 12 , 13 In the diagram, the area R marked with a diagonal line represents a region on the upper surface 12a where neither the contact layer 32 nor the source layer 30 is disposed. Within region R, on the upper surface 12a, the body layer 34 is connected to the source electrode 22. Figure 12 In this configuration, the source layer 30 is only located within the region adjacent to the trench 14. Figure 13 In the process, a body layer 34 (i.e., region R) is provided in the region adjacent to the end of the contact layer 32 in the x direction, and a source layer 30 is provided in other regions.

[0048] Furthermore, in the above embodiment, when the semiconductor substrate 12 is viewed from above, each depth layer 36 extends relatively long in the x-direction. However, as... Figure 14 As shown, when viewed from above, the semiconductor substrate 12 shows that each depth layer 36 can also be dispersed in the x-direction. Figure 14 In this configuration, deep layers 36 are dispersed in the x-direction, such that they exist in the inter-trench region 50. Within each inter-trench region 50, the deep layers 36 are spaced apart in the y-direction. Figure 14 In its composition, it can also suppress recovery current.

[0049] The following describes the structure of the technology disclosed in this specification.

[0050] (Component 1) A field-effect transistor, characterized in that it has: A semiconductor substrate, which is made of compound semiconductor, has multiple trenches on its upper surface. Multiple gate electrodes are respectively disposed in corresponding trenches and insulated from the semiconductor substrate by a gate insulating film; and The source electrode is in contact with the upper surface of the semiconductor substrate. The semiconductor substrate has multiple n-type source layers, multiple p-type contact layers, a p-type body layer, an n-type drift layer, and multiple p-type deep layers. The semiconductor regions located between the plurality of trenches in the semiconductor substrate are inter-trench regions. Each of the aforementioned source layers is disposed in the corresponding trench region, connected to the source electrode, and connected to the corresponding gate insulating film. Each of the contact layers is disposed in the corresponding trench region and is connected to the source electrode. Multiple contact layers are provided in the area between each of the trenches. When viewed from above, in each of the trench regions, the plurality of contact layers are arranged with spacing portions in a specific direction parallel to the plurality of trenches. The body layer has a lower p-type impurity concentration than each of the contact layers, is distributed across the multiple trench regions, is disposed below each of the source layers and each of the contact layers, and is in contact with the gate insulating film. The drift layer is distributed across the lower region of the plurality of inter-trench regions, and in each inter-trench region it is connected from below to the body layer and to the gate insulating film. Each of the deeper layers extends from the body layer to a position lower than the lower end of each of the trenches. When viewed from above, in each of the trench regions, a plurality of deep layers are arranged with spacing between them in a specific direction. In each of the trench regions, the spaced portions of the contact layer are respectively disposed on the upper part of the corresponding deeper layer. In each of the trench regions, the deep spacer portion is respectively disposed on the lower part of the corresponding contact layer.

[0051] (Component 2) According to the field-effect transistor of configuration 1, when the semiconductor substrate is viewed from above, each of the deep layers intersects with each of the trenches.

[0052] (Component 3) According to the field-effect transistor of configuration 1 or 2, when the semiconductor substrate is viewed from above, each of the contact layers does not overlap with each of the deep layers.

[0053] (Component 4) According to any one of the field-effect transistors 1 to 3, in each of the trench regions, the deep spacer portion has a first spacer portion that overlaps with the contact layer when the semiconductor substrate is viewed from above, and a second spacer portion that does not overlap with the contact layer when the semiconductor substrate is viewed from above.

[0054] (Component 5) According to any one of the field-effect transistors 1 to 4, in the thickness direction of the semiconductor substrate, the lower end of each of the contact layers is located at the same position as the lower end of each of the source layers or at a position above the lower end of each of the source layers.

[0055] The embodiments have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes technologies obtained by various modifications and alterations to the specific examples described above. The technical elements illustrated in this specification or drawings exert their technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. Furthermore, the technology illustrated in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A field effect transistor, characterized by Having: a semiconductor substrate (12) composed of a compound semiconductor, a plurality of trenches (14) being provided on an upper surface of the semiconductor substrate; a plurality of gate electrodes (18) respectively arranged in corresponding ones of the trenches, insulated from the semiconductor substrate by a gate insulating film; and a source electrode (22) in contact with the upper surface of the semiconductor substrate, the semiconductor substrate having a plurality of n-type source layers (30), a plurality of p-type contact layers (32), a p-type body layer (34), an n-type drift layer (38), and a plurality of p-type deep layers (36), each of the semiconductor regions of the semiconductor substrate located between the plurality of trenches is an inter-trench region (50), each of the source layers is arranged in a corresponding one of the inter-trench regions, in contact with the source electrode and with the corresponding gate insulating film, each of the contact layers is arranged in a corresponding one of the inter-trench regions, in contact with the source electrode, a plurality of the contact layers are provided in each of the inter-trench regions, when the semiconductor substrate is viewed from above, in each of the inter-trench regions, the plurality of contact layers are arranged apart by a spacing portion (33) in a certain direction parallel to the plurality of trenches, the body layer has a lower p-type impurity concentration than each of the contact layers, is distributed across the plurality of inter-trench regions, is arranged below each of the source layers and each of the contact layers, and is in contact with the gate insulating film, the drift layer is distributed across a region of lower portions of the plurality of inter-trench regions, is in contact with the body layer from a lower side within each of the inter-trench regions, and is in contact with the gate insulating film, each of the deep layers extends from the body layer to a position lower than a lower end of each of the trenches, when the semiconductor substrate is viewed from above, in each of the inter-trench regions, the plurality of deep layers are arranged apart by a spacing portion (37) in the certain direction, in each of the inter-trench regions, the spacing portions of the contact layers are respectively arranged in upper portions of corresponding ones of the deep layers, in each of the inter-trench regions, the spacing portions of the deep layers are respectively arranged in lower portions of corresponding ones of the contact layers.

2. The field effect transistor according to claim 1, wherein when the semiconductor substrate is viewed from above, each of the deep layers intersects each of the trenches.

3. The field effect transistor according to claim 1 or 2, wherein when the semiconductor substrate is viewed from above, each of the contact layers does not overlap each of the deep layers.

4. The field effect transistor according to claim 1 or 2, wherein in each of the inter-trench regions, the spacing portions of the deep layers have a first spacing portion (37a) that overlaps the contact layer when the semiconductor substrate is viewed from above, and a second spacing portion (37b) that does not overlap the contact layer when the semiconductor substrate is viewed from above.

5. The field effect transistor according to claim 1 or 2, wherein in a thickness direction of the semiconductor substrate, a lower end (32a) of each of the contact layers is located at a same position as a lower end (30a) of each of the source layers or a position higher than the lower end (30a) of each of the source layers. ​

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