Method and system for testing transmission delay time between signals

Abstract

The invention relates to the technical field of semiconductor testing, and particularly provides a method and a system for testing transmission delay time between signals. The test method comprises the following steps: respectively inputting two input signals with the same period into two input channels, and outputting output signals corresponding to the input channels through two output channels; in a set scanning window, signal levels of the two output channels are acquired step by step according to a set scanning step length; based on a comparison result of each signal level and a set voltage threshold value, obtaining edge moments when rising edges of the two output signals pass through the set voltage threshold value; and calculating the difference value of the two edge moments to obtain the transmission delay time between the two output signals. According to the method and the system for testing the transmission delay time between the signals, provided by the invention, the hardware cost of signal time parameter testing can be reduced, and the accuracy of a testing result can be met without complicated high-precision synchronous circuit design.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a method and system for testing the transmission delay time between signals. Background Technology

[0002] In the field of semiconductor testing, accurately measuring signal timing parameters, such as rise time, fall time, edge-to-edge time intervals, and propagation delay, is crucial for verifying chip performance. As semiconductor devices evolve towards higher frequencies and higher integration, the accuracy requirements for timing parameter testing have increased significantly.

[0003] Currently, the mainstream time measurement solution in the industry adopts a synchronous test architecture using dual counters. This technology achieves synchronous triggering based on a high-precision clock signal within the system. Taking the time interval of the test signal edges as an example, the test process involves recording the count values ​​at the start and end edges of the tested signal, and then calculating the difference to obtain the target time interval. However, achieving high-precision time measurement with this solution places extremely high demands on hardware performance: taking a measurement resolution of 0.078ns (i.e., minimum step size) as an example, the corresponding equivalent counting accuracy needs to reach 12.8GHz. To achieve this accuracy, the hardware system not only needs to use high-speed, high-precision electronic components and complex and optimized circuit design, but also requires special designs such as high-precision impedance matching and electromagnetic interference shielding for the signal transmission path. This leads to a significant increase in the hardware cost of the time measurement unit, becoming one of the important factors restricting the improvement of the cost-effectiveness of ATE (Automatic Test Equipment).

[0004] There is currently no effective solution to the problem of high hardware cost and complexity in measuring the time parameters of signals in related technologies. Summary of the Invention

[0005] The present invention provides a method and system for testing the transmission delay time between signals, which at least solves the problems of high hardware cost and high complexity required for testing signal time parameters in related technologies.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] The first aspect of the present invention provides a method for testing the transmission delay time between signals, comprising the following steps: inputting two input signals with the same period to two input channels respectively, and outputting output signals corresponding to the input channels through two output channels; within a set scanning window, progressively acquiring the signal levels of the two output channels with a set scanning step size; wherein the set scanning window covers the rising edge time of the two input signals; based on the comparison result of each signal level with a set voltage threshold, obtaining the edge time when the rising edge of the two output signals crosses the set voltage threshold; wherein the edge time is determined based on the time when the comparison result changes; calculating the difference between the two edge times to obtain the transmission delay time between the two output signals.

[0008] Preferably, the method involves inputting two input signals with the same period to two input channels and outputting corresponding output signals to the input channels through two output channels, comprising the following steps: simultaneously inputting two input signals with the same period to the two input channels to be tested through a signal generation module in an automatic testing device; wherein, both input signals are periodic square wave signals; and outputting corresponding output signals through two output channels; wherein, each output channel is connected to the corresponding input channel.

[0009] Preferably, before acquiring the signal levels of the two output channels step by step with a set scan step size, the method further includes the following steps: determining the start time and window length of the scan window based on the rising edge time, rising edge time, and period of the two input signals; wherein the start time is less than the rising edge time of the input signals, and the window length is greater than the rising edge time; and determining the scan step size based on the minimum sequential resolution of the pin electronics module in the automatic test equipment.

[0010] Preferably, within a set scanning window, the signal levels of the two output channels are gradually acquired at a set scanning step size, including the following steps: within the set scanning window, the pin output module in the automatic test device scans the two output signals gradually at the start of the scanning window, using the smallest sequential resolution of the pin electronic module as the set scanning step size; and at each scan, the signal levels of the two output signals are acquired.

[0011] Preferably, the method for obtaining the rising edge time of the two output signals crossing the set voltage threshold based on the comparison results of each signal level with the set voltage threshold includes the following steps: comparing each signal level with the set voltage threshold respectively and recording the comparison results; wherein the voltage amplitudes of the two input signals are the same, and the set voltage threshold is less than the voltage amplitudes of the two input signals; sorting the comparison results in ascending order according to the sampling time; and obtaining the rising edge time of the corresponding output signal crossing the set voltage threshold based on the first time when the comparison result changes.

[0012] Preferably, comparing each of the signal levels with a set voltage threshold and recording the comparison results includes the following steps: comparing each of the signal levels with a set voltage threshold; when the signal level is less than the set voltage threshold, recording the comparison result as a first result; when the signal level is greater than the set voltage threshold, recording the comparison result as a second result; until the comparison results of all sampling times are recorded, all comparison results corresponding to the two output channels are obtained.

[0013] Preferably, obtaining the rising edge time of the output signal crossing the set voltage threshold based on the first moment when the comparison result changes includes the following steps: constructing a target step size range based on the two sampling moments before and after the comparison result changes; wherein the target step size range covers the two sampling moments; repeatedly acquiring the signal levels of the two output signals at each sampling moment within the target step size range, and recording the comparison results of each signal level with the set voltage threshold; taking the sampling moment with the smallest difference between the probability of the second result occurring and 50% in the comparison results as the corresponding moment when the output signal crosses the set voltage threshold.

[0014] Preferably, within the target step size range, repeatedly acquiring the signal levels of the two output signals at various sampling times includes the following steps: In each of N consecutive cycles, repeatedly acquiring the signal levels of the two output signals at various sampling times within the target step size range; where N is a natural number and N≥10; arranging the signal levels corresponding to each output signal according to time sequence to obtain two sets of signal level sequences corresponding to the two output signals.

[0015] Another aspect of the present invention provides a system for measuring the transmission delay time between signals, comprising: a signal acquisition module, configured to acquire signal levels of two output channels stepwise within a set scanning window at a set scanning step size; wherein the two output channels are respectively connected to corresponding input channels; the two input channels are respectively input with two input signals of the same period; the set scanning window covers the rise time of the two input signals; a level comparison module, connected to the signal acquisition module, configured to compare the magnitude of each signal level with a set voltage threshold to obtain a comparison result; wherein the comparison result is used to determine the edge time when the rise time of the two output signals corresponding to the two output channels crosses the set voltage threshold; and a calculation module, connected to the level comparison module, configured to calculate the difference between the two edge times to obtain the transmission delay time between the two output signals.

[0016] In another aspect, the present invention provides an electronic device comprising: an automatic testing device, the automatic testing device comprising: a processor, and a memory storing a program, characterized in that the program comprises instructions, which, when executed by the processor, cause the processor to perform a test method based on the aforementioned inter-signal transmission delay time.

[0017] Compared with the prior art, the above-described technical solution of the present invention has the following advantages:

[0018] This invention provides a method and system for testing the transmission delay time between signals. By scanning a window, the signal levels of two output signals are acquired at various sampling times. Then, based on level comparison, the edge times at which the two output signals cross the set voltage threshold are determined by comparing each signal level with the threshold. Finally, the transmission delay time of the two output signals is obtained by calculating the time difference between the two edge times. Since the input signals of the two output channels have the same period, the difference in input delay can be canceled out when calculating the transmission delay time. Therefore, the testing method provided by this invention does not require high-precision synchronization of the two input signals, does not require high-precision electronic components, and does not require the design of complex circuits. Furthermore, the signal acquisition and level comparison process can be implemented using a module with signal acquisition and level comparison functions built into an automated test equipment (ATE), such as a Pin Electronics (PE) module. Therefore, the method and system for testing the transmission delay time between signals provided by this invention can reduce the requirements for dedicated hardware modules and high-precision synchronous testing, thereby significantly reducing hardware costs and complexity, and solving the problems of high hardware costs and high complexity required for signal time parameter testing in related technologies. Attached Figure Description

[0019] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other embodiments based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a method for testing the transmission delay time between signals, according to an embodiment of the present invention.

[0021] Figure 2 This is a comparison diagram of the timing of multi-channel signals in an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of the structure of a signal transmission delay test system according to an embodiment of the present invention.

[0023] Figure 4 This is a schematic diagram of the structure of the electronic device created by this invention. Detailed Implementation

[0024] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0025] In the early stages of semiconductor device testing technology development, automated test equipment (ATE) did not integrate dedicated time measurement units. Testing of device time parameters (such as signal delay, pulse width, and edge interval) was generally achieved using external, independent measuring instruments. While this met the basic time measurement needs of early semiconductor devices, it had significant limitations: Firstly, external instruments required additional signal cables to connect to the ATE system and the device under test, easily introducing signal transmission delays, interference noise, and other problems, leading to increased measurement errors. Secondly, the coordinated control of external instruments and the ATE relied on complex external synchronization mechanisms, which not only reduced testing efficiency but also increased system integration difficulty and maintenance costs, making it difficult to adapt to the high-efficiency testing requirements of large-scale mass production scenarios.

[0026] The mainstream time parameter measurement scheme in related technologies adopts a synchronous test architecture with dual counters. Synchronous triggering is achieved based on a high-precision clock signal within the system. During testing, for the time parameter to be measured, such as the time interval between one signal edge and another, the two counters are first synchronously started via a common trigger signal. When the start edge of the measured signal is detected (corresponding to the start signal), the first counter stops counting and latches its current count value, recording the time information of the start edge. When the stop edge of the measured signal is detected (corresponding to the stop signal), the second counter stops counting and latches its current count value, recording the time information of the stop edge. After the test, the time interval between the start and stop edges can be obtained by performing a difference calculation on the latched count values ​​of the two counters, thus achieving the measurement of the target time parameter.

[0027] However, this technology places extremely high demands on hardware performance. It requires not only high-speed, high-precision electronic components and complex and optimized circuit design, but also special designs such as high-precision impedance matching and electromagnetic interference shielding for signal transmission paths. This leads to a significant increase in the hardware cost of the time measurement unit, becoming one of the important factors restricting the improvement of the cost-effectiveness of ATE equipment.

[0028] The high cost of hardware not only limits the widespread application of time measurement units, especially for some small and medium-sized semiconductor companies that are more sensitive to costs, making it difficult for them to afford high-precision time measurement modules; but it also hinders the overall innovation and development of the semiconductor testing industry towards low cost and high efficiency.

[0029] like Figure 1 As shown, in order to reduce the cost and complexity of testing the transmission delay time between signals, the embodiments of the present invention provide a method for testing the transmission delay time between signals, including the following steps S1 to S4.

[0030] Step S1: Input two input signals with the same period to the two input channels respectively, and output the corresponding output signals to the input channels through the two output channels.

[0031] Step S2: Within the set scan window, the signal levels of the two output channels are gradually acquired at a set scan step size; wherein, the set scan window covers the rise time of the two input signals.

[0032] Step S3: Based on the comparison results of each signal level and the set voltage threshold, obtain the edge time when the rising edge of the two output signals crosses the set voltage threshold; wherein, the edge time is determined based on the time when the comparison result changes.

[0033] Step S4: Calculate the difference between the two edge times to obtain the transmission delay time between the two output signals.

[0034] Furthermore, both input and output channels are physical transmission links for signals, which can be cables, PCB lines, or connectors with independent pins.

[0035] In this embodiment of the invention, the two input channels are independent and identical, meeting the requirements for signal delay testing. Each input channel is connected to a corresponding output channel, and the two output channels also have identical specifications. Output signals corresponding to the input channels are output through the two output channels respectively.

[0036] The two input channels can be represented as Input Pin1 and Input Pin2, respectively, and the two output channels can be represented as Output Pin1 and Output Pin2, respectively. The two input signals can be represented as the first input signal and the second input signal. The two output signals can be represented as the first output signal and the second output signal.

[0037] The input signal is a periodic signal, which can be a square wave, pulse signal, triangular wave, sawtooth wave, or sine wave, etc., with a distinct rising edge and stable crossing over. The input signal can be generated by devices such as function generators, dedicated signal transmission modules, or standard signal source instruments.

[0038] In this embodiment of the invention, the two input signals have the same period, which eliminates phase difference interference between the two input signals. As long as the periods of the two input signals are exactly the same, this deviation will repeat in each period and will eventually be eliminated in the "delay difference calculation" at the output, thus offsetting the difference in input delay. Therefore, the test method provided by this embodiment of the invention does not require high-precision synchronization of the two input signals, nor does it require high-precision electronic components or complex circuit design.

[0039] The scanning window is a preset time interval used to accurately acquire the signal levels of the two output channels. This invention, by setting the scanning window to cover the rise time of the two input signals, can acquire the signal levels of the entire rise phase of the two input channels, thereby capturing the edge moments of the rise of the two input channels, resulting in more accurate test results and higher test precision.

[0040] like Figure 2 As shown, in this embodiment of the invention, both input signals are ideal square waves, with the rising edge of the first input signal triggering at 2ns and the rising edge of the second input signal triggering at 4ns, both with a period of 12ns. The scanning window can be set as follows: , , or wait.

[0041] Figure 2 In the code, LE (Latency Edge) = 2ns indicates that the trigger time of the rising edge of input channel 1 is delayed by 2ns compared to the start time of the scan window. Similarly, LE = 4ns indicates that the trigger time of the rising edge of input channel 2 is delayed by 4ns compared to the start time of the scan window. Period = 12ns indicates that the period is 12ns.

[0042] The scan step size, which is the time interval between two adjacent signal level acquisitions within a set scan window, determines the temporal resolution of signal acquisition. The smaller the scan step size, the more densely the acquisition time points, and the more finely the signal details are captured; conversely, the larger the scan step size, the coarser the signal.

[0043] In order to improve scanning accuracy and testing accuracy, the scanning step size is set to be higher than the rate of change of the rising edge in the embodiments of the present invention. The preferred range for the scanning step size is within a certain range. between.

[0044] In the embodiments of the present invention, step S2 can be executed by the pin electronic module built into the ATE. This solution does not require additional high-precision electronic components, which can greatly reduce hardware costs and eliminate the need to design complex circuits to meet high-precision synchronization requirements.

[0045] Furthermore, step S2 in the embodiments of this invention can also be implemented using a microcontroller (MCU). Specifically, the scanning window and scanning step size are set through MCU software programming, and the level signal acquisition of the output channel can be achieved through the MCU's built-in analog-to-digital converter (ADC). This method is low-cost and has a simple circuit, meeting the requirements of low cost and low complexity.

[0046] A voltage threshold is set as a standard for determining the rising edge time of an input signal. In this invention, the signal level is compared to the set voltage threshold, and the comparison result is categorized into two cases: the signal level is below the set voltage threshold, and the signal level is above the set voltage threshold. The rising edge time can be determined by the moment when the comparison result changes.

[0047] The comparison result changes abruptly, that is, the rising edge signal level changes from below the set voltage threshold to above the set voltage threshold. The edge moment is the instant when the rising edge signal level crosses the set voltage threshold.

[0048] The voltage threshold is generally set to be less than the voltage amplitude of the input signal, and can preferably be 30% to 70% of the voltage amplitude.

[0049] Step S3 in the embodiments of the present invention can be executed by a device / module with a level comparison function, such as a level comparator or a pin electronic module built into the ATE. By comparing each acquired signal level with a set voltage threshold, each comparison result can be obtained.

[0050] Furthermore, since the input signals have the same period, the trigger time difference between input channel 1 and input channel 2 is fixed. The difference between the two edge times is actually the sum of the delay time of the two output channels and the trigger time difference between input channel 1 and input channel 2. Since the trigger time difference between input channel 1 and input channel 2 is fixed, it can be measured. Therefore, the transmission delay time between the two output channels can be calculated by calculating the difference between the two edge times.

[0051] Furthermore, the difference in trigger times between input channel 1 and input channel 2 can be measured through calibration or zeroing. A common method is to connect the two input channels using an ideal reference system with no delay difference (or a system with known minimal delay) before the formal test begins. In this case, the difference between the measured two edge times is approximately equal to the relative transmission delay time between input channel 1 and input channel 2, since theoretically the difference in trigger times between input channel 1 and input channel 2 is approximately zero. This value is stored as a calibration value for subsequent tests.

[0052] This invention provides a method for testing the transmission delay time between signals. By scanning a window, the signal levels of two output signals are acquired at various sampling times. Then, based on level comparison, the edge times at which the two output signals cross the set voltage threshold are determined by comparing each signal level with that threshold. Finally, the transmission delay time of the two output signals is obtained by calculating the time difference between the two edge times. Since the input signals of the two output channels have the same period, the difference in input delay can be canceled out when calculating the transmission delay time. Therefore, the testing method provided by this invention does not require high-precision synchronization of the two input signals, does not require high-precision electronic components, and does not require the design of complex circuits.

[0053] Furthermore, the signal acquisition and level comparison processes can be implemented using modules with signal acquisition and level comparison functions built into automated test equipment (ATE), such as pin electronics modules. Therefore, the signal transmission delay testing method provided by this invention reduces the requirements for dedicated hardware modules and high-precision synchronous testing, thereby significantly reducing hardware costs and complexity. This solves the problem of high hardware costs and complexity required for signal timing parameter testing in related technologies.

[0054] Further, step S1 in the embodiment of the present invention includes the following steps: simultaneously inputting two input signals with the same period to the two input channels to be tested through the signal generation module in the automatic testing equipment; wherein, both input signals are periodic square wave signals; and outputting corresponding output signals through two output channels; wherein, each output channel is connected to the corresponding input channel.

[0055] The testing method in the embodiments of the present invention can simultaneously input two input signals with the same period to two input channels through the signal generation module executed by the automatic test equipment (ATE), thereby making the trigger time difference between input channel 1 and input channel 2 as close to zero as possible, making the testing process simpler, eliminating additional calibration steps, and ensuring that highly consistent results can be obtained for each measurement under the same test conditions.

[0056] Furthermore, before acquiring the signal levels of the two output channels step by step with a set scan step size in step S2, the method of this invention preferably includes the following steps: determining the start time and window length of the scan window based on the rising edge time, rising edge time and period of the two input signals; wherein the start time is less than the rising edge time of the input signal and the window length is greater than the rising edge time; and determining the scan step size based on the smallest sequential resolution of the pin electronic module in the automatic test equipment.

[0057] Specifically, in order to ensure that the set scanning window covers the rising edge time of the two input signals, the preferred embodiment of the present invention sets the starting time of the scanning window to be less than the rising edge time of the input signal and the window length to be greater than the rising edge time. This ensures effective coverage of the rising edge time of the input signal, eliminates measurement failures caused by improper window settings, and greatly improves the stability and repeatability of the test.

[0058] Furthermore, in the embodiments of this invention, the signal level acquisition process is preferably performed by the pin electronics module built into the ATE device. In this case, the scan step size is the smallest sequential resolution of the pin electronics module, preferably 0.078125 ns. By setting the scan step size based on the smallest sequential resolution of the ATE, the highest accuracy measurement within the achievable range is achieved, while avoiding unnecessary time waste.

[0059] Furthermore, step S2 preferably includes the following steps: within the set scanning window, the pin output module in the automatic test device scans the two output signals step by step at the beginning of the scanning window with the smallest sequential resolution of the pin electronic module as the set scanning step size; and during each scan, the signal level of the two output signals is acquired.

[0060] The embodiments of this invention fully utilize the hardware limits of the automatic testing equipment to sample the signal edges at the highest time density achievable by the system. This ensures that the instantaneous moments when the two output signals cross the threshold voltage can be accurately captured, providing high-resolution and highly reliable raw data for subsequent calculation of transmission delay time, and ultimately achieving high-precision delay measurement at the sub-nanosecond level.

[0061] Furthermore, step S3 in the embodiments of the present invention preferably includes steps S31 to S33.

[0062] Step S31: Compare each signal level with a set voltage threshold and record the comparison results; wherein, the voltage amplitudes of the two input signals are the same, and the set voltage threshold is less than the voltage amplitudes of the two input signals.

[0063] Step S32: Sort the comparison results in ascending order of sampling time.

[0064] Step S33: Based on the first moment when the comparison result changes, obtain the moment when the rising edge of the corresponding output signal crosses the set voltage threshold.

[0065] The present invention compares the acquired signal level with a preset voltage threshold lower than the signal amplitude, sorts the comparison results by time, and finally accurately locks the edge crossing point by identifying the moment of the "first jump" in the comparison result sequence. This effectively eliminates the risk of misjudging the edge moment caused by the signal lingering near the threshold multiple times due to noise, ringing, or non-ideal characteristics (such as back channels), thereby ensuring the uniqueness, stability, and accuracy of the edge moment extraction results and providing a solid and reliable benchmark for subsequent calculation of transmission delay time.

[0066] Furthermore, if the signal level is lower than the set voltage threshold, the comparison result is recorded as "0"; if the signal level is higher than the set voltage threshold, the comparison result is recorded as "1". By sorting the comparison results from smallest to largest according to the sampling time, a comparison table of signal level comparison results for each channel at each acquisition time can be obtained as shown in Table 1.

[0067] Table 1. Comparison of signal levels for each output channel during each acquisition.

[0068]

[0069] As shown in Table 1, the comparison result of output channel 1 changes at step 26, and the comparison result of output channel 2 changes at step 52.

[0070] In the embodiments of this invention, both signal level acquisition and level comparison can be performed by the PE module. The PE module stores the comparison results of each acquisition in real time into a local cache (such as a FIFO memory). After the entire scanning window is completed, the results are transmitted in batches to the main control unit of the ATE, and the edge timing is analyzed by the main control unit of the ATE.

[0071] Furthermore, step S31 preferably includes the following steps: comparing each signal level with a set voltage threshold; when the signal level is less than the set voltage threshold, recording the comparison result as the first result; when the signal level is greater than the set voltage threshold, recording the comparison result as the second result; until the comparison results of all sampling times are recorded, all comparison results corresponding to the two output channels are obtained.

[0072] The first comparison result and the second comparison result can be "0 / 1", "L / H", etc.

[0073] In step S33, the timing when the rising edges of the two output signals cross the set voltage threshold can be determined by a binary search method.

[0074] Furthermore, with the trigger time of the rising edge of the first input signal being 2ns and the trigger time of the rising edge of the second input signal being 4ns, both with a period of 12ns, the preferred scanning window is... Taking a scan step size of 0.078125 ns as an example, a total of 64 scans were performed within the set scan window. The moment T1 when the output channel 1 crosses the reference threshold can be determined in 6 searches using the binary search method. Similarly, the moment T2 when the output channel 2 crosses the reference threshold can be determined in 6 searches, thus further improving computational efficiency.

[0075] Furthermore, due to circuit noise and signal jitter, a single sampling may not accurately capture the precise moment when the edge crosses the threshold. To further improve the accuracy of signal edge detection, a probabilistic statistical method can be used to repeatedly verify the edge triggering moment. Theoretically, the percentage of "1" states in the rising edge trigger signal should monotonically increase with the sampling step size (and monotonically decrease with the falling edge). Therefore, step S33 can preferably include the following steps:

[0076] Step S331: Based on the two sampling times before and after the comparison result jumps, construct the target step size range; wherein, the target step size range covers the two sampling times.

[0077] Step S332: Within the target step size range, repeatedly acquire the signal levels of the two output signals at each sampling time, and record the comparison results of each signal level with the set voltage threshold.

[0078] Step S333: Take the sampling moment when the difference between the probability of the second result appearing and 50% is the smallest among the comparison results, and take it as the edge moment when the corresponding output signal crosses the set voltage threshold.

[0079] In step S331 of this invention, the approximate range of edge times, i.e., the target step size range, is first obtained based on the results of the first round of scanning, in order to narrow the resampling interval. In this embodiment of the invention, the target step size range preferably covers the two sampling times before and after the jump in the comparison result, and the target step size range is preferably greater than two scanning steps to effectively cover the rising edge times.

[0080] Next, in step S332, a second sampling process is performed. By repeatedly acquiring the signal levels of the two output signals at each sampling time within the target step size range, random noise on the signal can be effectively filtered out, preventing misjudgment of edge time due to uncertainty of single sampling, and improving the noise resistance and robustness of the test.

[0081] In step S333, the sampling time with the smallest difference between the probability of the second result appearing and 50% in the comparison results is the sampling time that is closest to the ideal "statistical center point" or "50% probability point" among all available sampling times. By using the aforementioned sampling time as the edge time, this invention can most accurately represent the true, average transition center time of the signal affected by noise, thereby improving the noise immunity and accuracy of the test.

[0082] Steps S331 to S333 provided in the embodiments of this invention upgrade a simple first transition detection into a high-precision, high-reliability measurement process. By performing local focusing and multiple statistical sampling in the suspected edge region, the two major problems of limited accuracy and unstable results are solved simultaneously. Ultimately, it can stably output an edge time value with a time resolution far exceeding the single sampling capability of ATE and is immune to noise, thereby pushing the measurement accuracy of the entire transmission delay time to the limit.

[0083] Furthermore, step S332 of the present invention preferably includes the following steps: in each of N consecutive cycles, the signal levels of the two output signals at each sampling time within the target step size range are repeatedly collected; wherein, N is a natural number and N≥10; the signal levels corresponding to each output signal are arranged in time sequence to obtain two sets of signal level sequences corresponding to the two output signals.

[0085] Since the input signal is a periodic square wave, the waveform characteristics of each cycle, such as the rising edge time, have strict repeatability on the time axis. Based on this characteristic, this invention employs a timing-based scanning sampling method to measure the delay between two channels. For each channel, within multiple consecutive cycles, the sampling point is moved cycle by cycle with a fixed scanning step size for single-point sampling. By arranging the obtained sampling sequence in chronological order, the signal waveform within a set scanning window of one cycle can be equivalently reconstructed. By comparing the positions of the rising edges in the reconstructed waveforms of the two channels, the precise delay time can be calculated.

[0086] Furthermore, in the embodiments of the present invention, by continuously sampling in each of N cycles and setting the continuous sampling cycle to be greater than or equal to 10, sufficient sample data can be provided, thereby improving the reliability and accuracy of edge moments, and thus achieving high-precision, high-repeatability measurements at the subsampling step level in real, noisy environments.

[0087] Further, refer to Table 1 for the signal level comparison results of each output channel during each acquisition. Edge time of output channel 1: 26 * 0.078125 ns = 2.03125 ns. Edge time of output channel 2: 52 * 0.078125 ns = 4.0625 ns. In step S4, the calculated transmission delay time between output channel 1 and output channel 2 is: 4.0625 - 2.03125 = 2.03125 ns.

[0088] Therefore, the method for testing the transmission delay time between signals provided by this invention has the following beneficial effects:

[0089] (1) Extremely high hardware cost performance: It makes full use of the existing high-precision timing generation and comparison capabilities of the PE module of the ATE machine, without the need to add any additional dedicated time measurement hardware.

[0090] (2) High precision and high accuracy: It directly inherits the inherent timing accuracy of the PE module (e.g., 78.125ps), and its performance is comparable to that of a dedicated time measurement module. When measuring a certain moment (e.g., when the edge crosses the reference threshold), the midpoint interpolation algorithm can be used to make the final measurement accuracy better than the minimum step size set in the timing.

[0091] (3) Strong portability and flexibility: This method is a software-defined measurement scheme. Its core logic lies in the writing of the test program. Therefore, it can be easily ported to any test platform that supports PE modules with similar accuracy. It has strong versatility and is not limited by specific chip processes or hardware.

[0092] (4) High-throughput testing: This method can achieve fast scanning and calculation through binary search, which can meet the requirements of efficiency and reliability in large-scale production testing.

[0093] like Figure 3 As shown, an embodiment of the present invention also provides a measurement system for inter-signal transmission delay time, applied to a method for testing inter-signal transmission delay time. Preferably, the measurement system for inter-signal transmission delay time includes: a signal acquisition module, a level comparison module, and a calculation module.

[0094] The signal acquisition module is used to gradually acquire the signal levels of two output channels within a set scanning window and with a set scanning step size. The two output channels are connected to their corresponding input channels. The two input channels are each input with two input signals of the same period. The set scanning window covers the rise time of the two input signals.

[0095] The level comparison module, connected to the signal acquisition module, is used to compare the levels of each signal with the set voltage threshold to obtain the comparison result. The comparison result is used to determine the time when the rising edge of the two output signals corresponding to the two output channels crosses the edge of the set voltage threshold.

[0096] The calculation module, connected to the level comparison module, is used to calculate the difference between the two edge times to obtain the transmission delay time between the two output signals.

[0097] This invention provides a system for testing the transmission delay time between signals. A signal acquisition module scans within a set window to acquire the signal levels of two output signals at various sampling times. A level comparison module then compares each signal level with a set voltage threshold to determine the edge times when the two output signals cross the threshold. Finally, a calculation module calculates the time difference between the two edge times to obtain the transmission delay time of the two output signals.

[0098] Since the input signals of the two output channels have the same period, the difference in input delay can be canceled out when calculating the transmission delay time. Therefore, the test method provided by the embodiments of the present invention does not require high-precision synchronization of the two input signals, does not require high-precision electronic components, and does not require the design of complex circuits.

[0099] Furthermore, the signal acquisition and level comparison processes can be implemented using modules with signal acquisition and level comparison functions built into automated test equipment (ATE), such as Pin Electronics (PE) modules. Therefore, the signal transmission delay testing method and system provided by this invention can reduce the requirements for dedicated hardware modules and high-precision synchronous testing, thereby significantly reducing hardware costs and complexity. This solves the problem of high hardware costs and complexity required for signal timing parameter testing in related technologies.

[0100] An embodiment of the present invention also provides a non-transitory machine-readable medium storing a computer program, wherein the computer program, when executed by a computer's processor, is used to enable the computer to perform a method for testing the inter-signal transmission delay time of an embodiment of the present invention.

[0101] An embodiment of the present invention also provides a computer program product, including a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform a method for testing the inter-signal transmission delay time according to an embodiment of the present invention.

[0102] An embodiment of the present invention also provides an electronic device, which includes an ATE (Automatic Test Equipment) device. The ATE device includes at least one processor and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor, which, when executed by the at least one processor, causes the electronic device to perform a test method for inter-signal transmission delay time according to an embodiment of the present invention.

[0103] Furthermore, the automated testing equipment of the present invention can be applied to the semiconductor industry, consumer electronics industry, automotive electronics industry, and aerospace field, and is preferably applied to the semiconductor industry.

[0104] refer to Figure 4 This is a structural block diagram of an electronic device for a server or client, representing an embodiment of the present invention, and is an example of a hardware device that can be applied to various aspects of the present invention. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0105] like Figure 4 As shown, the electronic device includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. The RAM 603 may also store various programs and data required for the operation of the electronic device. The computing unit 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0106] Multiple components in the electronic device are connected to I / O interface 605, including: input unit 606, output unit 607, storage unit 608, and communication unit 609. Input unit 606 can be any type of device capable of inputting information into the electronic device. Input unit 606 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of the electronic device. Output unit 607 can be any type of device capable of presenting information and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 608 may include, but is not limited to, disks and optical discs. Communication unit 609 allows the electronic device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, and / or wireless communication transceivers, such as Bluetooth devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0107] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, CPUs, graphics processing units (GPUs), various special-purpose artificial intelligence (AI) computing units, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above. For example, in some embodiments, the method embodiments of the present invention can be implemented as computer programs tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed on an electronic device via ROM 602 and / or communication unit 609. In some embodiments, the computing unit 601 can be configured to perform the methods described above by any other suitable means (e.g., by means of firmware).

[0108] Computer programs for implementing the methods of embodiments of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0109] In the context of embodiments of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable signal medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, or infrared systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0110] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of this invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more".

[0111] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this invention are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0112] The steps described in the method embodiments provided by the present invention can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of protection of the present invention is not limited in this respect.

[0113] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0114] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A method for testing the transmission delay time between signals, characterized in that, Includes the following steps: Two input signals with the same period are input to two input channels respectively, and output signals corresponding to the input channels are output through two output channels; Within a set scan window, the signal levels of the two output channels are acquired step by step at a set scan step size; wherein, the set scan window covers the rise time of the two input signals; Based on the comparison results of each of the signal levels and the set voltage threshold, the edge times when the rising edges of the two output signals cross the set voltage threshold are obtained; wherein, the edge times are determined based on the time when the comparison results change. The difference between the two edge times is calculated to obtain the transmission delay time between the two output signals.

2. The method for testing the inter-signal transmission delay time according to claim 1, characterized in that, The method involves inputting two input signals with the same period into two input channels, and outputting output signals corresponding to the input channels through two output channels, including the following steps: The automatic testing equipment uses a signal generation module to simultaneously input two input signals with the same period to the two input channels under test; wherein both input signals are periodic square wave signals. The corresponding output signals are output through two output channels respectively; wherein each output channel is connected to the corresponding input channel.

3. The method for testing the inter-signal transmission delay time according to claim 1, characterized in that, Before acquiring the signal levels of the two output channels step by step at a set scan step size, the method further includes the following steps: Based on the rising edge time, rising edge time, and period of the two input signals, the start time and window length of the scanning window are determined; wherein the start time is less than the rising edge time of the input signals, and the window length is greater than the rising edge time. The scan step size is determined based on the smallest sequential resolution of the pin electronics module in the automated test equipment.

4. The method for testing the inter-signal transmission delay time according to claim 3, characterized in that, Within the set scan window, the signal levels of the two output channels are acquired step-by-step at a set scan step size, including the following steps: Within the set scanning window, the pin output module in the automatic test device scans the two output signals step by step at the start of the scanning window, using the smallest sequential resolution of the pin electronic module as the set scanning step size. During each scan, the signal levels of the two output signals are acquired.

5. The method for testing the inter-signal transmission delay time according to claim 1, characterized in that, Based on the comparison results between each of the signal levels and the set voltage threshold, the timing of the rising edge of the two output signals crossing the edge of the set voltage threshold is obtained, including the following steps: Each of the signal levels is compared with a set voltage threshold, and the comparison results are recorded; wherein, the voltage amplitudes of the two input signals are the same, and the set voltage threshold is less than the voltage amplitudes of the two input signals; The comparison results are sorted from smallest to largest according to the sampling time. Based on the first moment when the comparison result changes, the moment when the rising edge of the corresponding output signal crosses the edge of the set voltage threshold is obtained.

6. The method for testing the inter-signal transmission delay time according to claim 5, characterized in that, Each of the signal levels is compared with a set voltage threshold, and the comparison results are recorded, including the following steps: Each of the signal levels is compared with a set voltage threshold. When the signal level is less than the set voltage threshold, the comparison result is recorded as the first result; When the signal level is greater than the set voltage threshold, the comparison result is recorded as the second result; The comparison results for all sampling times are recorded until all comparison results for the two corresponding output channels are obtained.

7. The method for testing the inter-signal transmission delay time according to claim 6, characterized in that, Based on the first moment when the comparison result changes, the moment when the rising edge of the corresponding output signal crosses the set voltage threshold is obtained, including the following steps: Based on the two sampling times before and after the jump in the comparison result, a target step size range is constructed; wherein, the target step size range covers the two sampling times; Within the target step size range, the signal levels of the two output signals are repeatedly acquired at each sampling time, and the comparison results of each signal level with the set voltage threshold are recorded; The sampling moment with the smallest difference between the probability of the second result occurring and 50% in the comparison results is taken as the corresponding moment when the output signal crosses the set voltage threshold.

8. The method for testing the inter-signal transmission delay time according to claim 7, characterized in that, Within the target step size range, the signal levels of the two output signals are repeatedly acquired at various sampling times, including the following steps: Within each of N consecutive cycles, the signal levels of the two output signals at various sampling times within the target step size range are repeatedly acquired; where N is a natural number and N≥10; Arrange the signal levels corresponding to each output signal according to the timing sequence to obtain two sets of signal level sequences corresponding to the two output signals.

9. A system for measuring the transmission delay time between signals, characterized in that, include: The signal acquisition module is used to gradually acquire the signal levels of two output channels within a set scanning window and with a set scanning step size; wherein the two output channels are respectively connected to corresponding input channels; the two input channels are respectively input with two input signals with the same period; the set scanning window covers the rise time of the two input signals; A level comparison module, connected to the signal acquisition module, is used to compare the levels of each signal with a set voltage threshold to obtain a comparison result; wherein, the comparison result is used to determine the time when the rising edge of the two output signals corresponding to the two output channels crosses the edge of the set voltage threshold. The calculation module, connected to the level comparison module, is used to calculate the difference between the two edge times to obtain the transmission delay time between the two output signals.

10. An electronic device, the electronic device comprising: An automatic testing device, comprising: a processor and a memory storing a program, characterized in that the program includes instructions that, when executed by the processor, cause the processor to perform a test method for inter-signal transmission delay time according to any one of claims 1 to 8.

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