A semiconductor device and a manufacturing method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-01-23
- Publication Date
- 2026-06-02
Smart Images
Figure CN121559811B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its manufacturing method. Background Technology
[0002] In the manufacturing process of semiconductor devices, the mask layer is an important process structure for local processing of wafers. It can block part of the wafer surface and expose the part that needs to be processed, so as to realize local processing of the wafer (such as local etching, local doping, etc.).
[0003] A photomask layer is typically formed using a photoresist layer and a photomask. In the photoresist exposure process, the photomask is positioned upstream of the exposure light path, ensuring that the exposed area of the photoresist receiving the exposure beam aligns with the light-transmitting area of the photomask. This achieves pattern transfer between the photomask and the photoresist layer, thus forming the photomask layer. Specifically, when a positive photoresist is used, the pattern of the photomask layer matches that of the photomask; when a negative photoresist is used, the pattern of the photomask layer is opposite to that of the photomask.
[0004] Given that wafer local processing is related to the actual structure of the fabricated semiconductor device, adjusting the device structure often requires redesigning and manufacturing a photomask, resulting in significant production costs and hindering the adjustment and testing of the semiconductor device. Therefore, how to form a mask layer more flexibly is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] In view of this, embodiments of this application provide a semiconductor device and manufacturing method, which replaces at least part of the function of the photomask in the development stage by forming a surface carbon layer on the surface of the photoresist layer, thereby enabling adjustment of the mask layer.
[0006] In a first aspect, this application provides a method for manufacturing a semiconductor device. The method includes forming a mask layer based on a surface carbon layer and performing partial wafer processing based on the mask layer. The method of forming a mask layer based on a surface carbon layer includes: forming a photoresist layer on the surface of a substrate; performing surface carbonization on the photoresist layer to form a surface carbon layer, wherein the surface carbon layer is used to block an exposure beam from entering the photoresist below the surface carbon layer; performing an exposure process on the photoresist layer to expose and modify the photoresist layer located within the exposure range that is not covered by the surface carbon layer; and performing a development process on the modified photoresist layer to form a mask layer.
[0007] In a second aspect, this application provides a semiconductor device, which includes a first wafer and a second wafer, and a bonding structure pair is disposed between the first wafer and the second wafer; the bonding structure pair is formed based on the manufacturing method of the first aspect, and a surface carbon layer of a mask layer is formed based on the wafer edge region of the wafer, so that the bonding structure pair avoids the wafer edge regions of the first wafer and the second wafer during formation; the first wafer and the second wafer are bonded to each other through the bonding structure pair.
[0008] Based on the semiconductor device and manufacturing method provided in this application, a corresponding surface carbon layer can be formed on the photoresist surface to address the adjustment requirements of the mask layer during local wafer processing. Based on this surface carbon layer, during the photoresist exposure process, the surface carbon layer blocks the exposure beam from entering the underlying photoresist, allowing the photoresist within the exposure range that is not covered by the surface carbon layer to be exposed and modified. Therefore, during the mask layer formation process, the pattern formed differs from the actual corresponding photomask, thus meeting the adjustment requirements of the semiconductor device and reducing the modification cost of the photomask. Furthermore, considering that the surface carbon layer and the photomask have similar actual functions in the exposure process, the surface carbon layer can also completely replace the photomask during mask layer formation, realizing a maskless photoresist exposure process and increasing the freedom of mask layer formation. Attached Figure Description
[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 This is a schematic diagram of the photoresist exposure and development process provided by the related technology of this application.
[0011] Figure 2 This is a schematic diagram of the photoresist exposure and development process based on a surface carbon layer provided in some embodiments of this application.
[0012] Figure 3 This is an exemplary flowchart of a mask layer formation process based on a surface carbon layer provided in some embodiments of this application.
[0013] Figure 4 This is an exemplary flowchart of the surface carbon layer formation process provided in some embodiments of this application.
[0014] Figure 5 This is an exemplary flowchart of a mask layer formation process based on a surface carbon layer and a photolithographic mask, provided in some embodiments of this application.
[0015] Figure 6 This is a schematic diagram of the structure of a semiconductor device having at least two wafers and a bonding structure provided by the related technology of this application.
[0016] Figure 7 This is an exemplary flowchart of the semiconductor device fabrication process provided in some embodiments of this application.
[0017] Figure 8 This is an exemplary flowchart of the process for forming a wafer bonding structure that avoids the wafer edge region, as provided by the related technologies of this application.
[0018] Among them, 110 is the substrate; 120 is the photoresist layer; 121 is the exposed area; 122 is the unexposed area; 123 is the surface carbon layer; 130 is the photomask; 131 is the light-transmitting area; 132 is the light-shielding area; 140 is the exposure light source; 600 is the semiconductor device; 610 is the first wafer; 620 is the second wafer; 630 is the bonding structure; 631 is the first bonding groove; 632 is the second bonding groove; 633 is the bonding medium; and 640 is the wafer edge area. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0020] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0021] In this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.
[0022] Application Overview:
[0023] Photoresist is a photosensitive mixed colloidal liquid. Based on its photosensitive properties, photoresist can be used as a mask layer in semiconductor devices to achieve localized wafer processing. Specifically, a mask layer is formed by the exposure and development process of photoresist. This mask layer covers part of the wafer surface and exposes part of the wafer. That is, part of the wafer is covered by the mask layer, and part of the wafer is exposed relative to the mask layer.
[0024] In semiconductor fabrication processes, localized wafer processing can be achieved using mask layers. For example, when a wafer surface is placed in an etching environment, the mask layer covering the wafer surface blocks the etching process. As a result, the morphology of the wafer surface covered by the mask layer remains unchanged, while the morphology of the wafer surface not covered by the mask layer is altered by etching (e.g., forming grooves, vias, etc.). Furthermore, surface doping processes can also be performed using mask layers to form semiconductor source and drain structures.
[0025] As mentioned above, the process of transferring photoresist to the mask layer depends on a photomask. A photomask typically includes a light-transmitting area and a light-shielding area. For example, a photomask can consist of a transparent substrate (quartz or glass) and an opaque light-shielding layer (usually a chromium film), with the light-shielding layer forming the shielding area.
[0026] In the photoresist exposure and development process, light shines through the light-transmitting area onto the substrate coated with photoresist, triggering a photochemical reaction (i.e., localized photomodification of the photoresist) to achieve pattern transfer. The pattern transfer process generally includes steps such as coating, pre-baking, alignment and exposure, post-baking, and development.
[0027] Specifically, coating refers to uniformly spin-coating photoresist onto the surface of a silicon wafer to form a thin layer. Pre-bake removes the solvent used during coating, enhancing the adhesion between the photoresist and the substrate (such as a wafer). Alignment and exposure involve irradiating a photomask (printed with circuit patterns) with light of a specific wavelength, causing a photochemical reaction in the exposed areas of the photoresist. Post-exposure baking intensifies the chemical changes in the exposed areas, improving pattern accuracy. Development is used to remove portions of the photoresist layer.
[0028] In the aforementioned process, the photoresist can be modified during exposure, thus manifesting as the corresponding image during subsequent development. The photoresist can include both positive and negative types. With positive photoresist, the solubility of the photoresist in the exposed areas increases during exposure (generally by forming photoacids internally), and it is dissolved and removed during subsequent development. With negative photoresist, the photoresist in the exposed areas is solidified during exposure and retained during subsequent development, while the photoresist in the unexposed areas is dissolved and removed during development.
[0029] To further illustrate this point, this application also provides a schematic diagram of the photoresist exposure and development process. Figure 1 ).
[0030] like Figure 1 As shown, photoresist can be formed on the surface of substrate 110 based on the aforementioned coating and pre-baking processes to form photoresist layer 120. Substrate 110 refers to a wafer undergoing partial wafer processing, a portion of a wafer, or the bonding result of multiple wafers. The surface of substrate 110 can refer to the side of the wafer undergoing partial wafer processing; for example, in a doping process, the surface of substrate 110 can be the side of the wafer where the source and drain electrodes are formed.
[0031] In the alignment exposure process, the photomask 130 can be aligned with the photoresist layer and positioned upstream of the photoresist layer 120 along the exposure optical path. As mentioned above, the photomask 130 includes a light-transmitting region 131 and a light-shielding region 132. The light-transmitting region 131 is a light-transmitting substrate without a light-shielding layer, and the light-shielding region 132 is a light-transmitting substrate covered with a light-shielding layer.
[0032] Based on the light-transmitting region 131 and light-shielding region 132 of the aforementioned photomask 130, an exposed region 121 and an unexposed region 122 can be formed in the photoresist layer 120. The exposed region 121 refers to the portion of the photoresist layer 120 that is not blocked by the photomask 130 in the exposure optical path and corresponds to the light-transmitting region 131; the unexposed region 122 refers to the portion of the photoresist layer 120 that is blocked by the photomask 130 in the exposure optical path and corresponds to the light-shielding region 132.
[0033] In the exposure process, the exposure beam emitted by the exposure light source 140 propagates onto the photoresist layer 120. Specifically, the exposure beam directed toward the exposure area 121 propagates onto the photoresist layer 120 without obstruction, causing the photoresist layer 120 on the surface of the exposure area 121 to change; while the exposure beam directed toward the unexposed area 122 is blocked by the photomask 130, so that the properties of the photoresist layer 120 in the unexposed area 122 remain unchanged.
[0034] Taking positive photoresist as an example, most advanced positive photoresists rely on photoacid-driven chemical amplification reactions to achieve patterning. Specifically, in photoresist layer 120, photoacid-generating agents (such as sulfonium salts and iodonium salts) decompose after absorbing photons, releasing strongly acidic molecules (such as sulfonic acid H₂). + ).
[0035] Based on the aforementioned modified photoresist layer 120, in the subsequent post-baking process, the photoacid in the photoresist layer 120 of the exposed area 121 diffuses into the resin molecular chain during the post-baking stage, catalyzing the removal of protecting groups (such as tert-butyloxycarbonyl t-BOC). Then, in the subsequent development process, the resin after the protecting groups are removed dissolves in an alkaline developer (such as 2.38% TMAH), causing the photoresist layer corresponding to the exposed area 121 to be removed, forming the same pattern as the photomask 130.
[0036] In addition, positive photoresists can also be traditional DNQ-phenolic resin positive photoresists, where the photoresist layer in the exposed area 121 is removed based on carboxylic acid denaturation. Negative photoresists are processed similarly to the aforementioned methods, primarily relying on photo-crosslinking or photopolymerization for denaturation, thereby preserving the photoresist in the exposed area.
[0037] Based on the foregoing Figure 1 The photoresist patterning process shown illustrates that the patterning of the photoresist itself depends on the structure of the photomask. Adjustments to semiconductor devices often require the fabrication of a new photomask (i.e., redistribution of the mask's light-shielding layer), a process that incurs significant production costs. This is especially true when test results are unsatisfactory, often necessitating multiple tests.
[0038] Based on the aforementioned masking logic of the photoresist layer itself, this application creatively discovers that a light-shielding structure similar to the photoresist mask can be formed on the side of the photoresist layer facing the exposure light source (i.e., the surface of the photoresist layer), thereby achieving protection of the photoresist layer below this area and forming an unexposed area outside the photoresist mask.
[0039] Furthermore, this application discovers that when high-energy particles (such as laser photons or ion beam particles) bombard the surface of the photoresist layer, the photoresist on the surface undergoes pyrolysis to form a carbon layer. Based on the black light-absorbing structural characteristics of the carbon layer itself, it can play a similar role to a photomask, blocking the exposure beam from reaching the underlying photoresist layer.
[0040] Therefore, by forming a surface carbon layer, the patterning of the photoresist can be further adjusted based on the existing photomask, thereby temporarily adjusting the etching of the semiconductor structure itself without the need to fabricate a new photomask. In special scenarios, etching can even be performed directly based on the surface carbon layer without using a photomask, thus achieving maskless exposure processes.
[0041] To further illustrate the aforementioned improvements to the photoresist exposure process, this application also provides a schematic diagram of a photoresist exposure and development process based on a surface carbon layer. Figure 2 ).
[0042] Figure 2 The exposure and development process shown is the same as described above. Figure 1 Similar, the main difference is Figure 2 A surface carbon layer 123 is formed on a portion of the surface of the exposure area 121 of the photoresist layer 120 shown. When the exposure beam shines on the surface carbon layer 123, the surface carbon layer 123 will block the exposure beam, preventing the photoresist beneath the surface carbon layer 123 from being modified.
[0043] Therefore, based on the aforementioned surface carbon layer 123, an equivalent unexposed area can be formed in the exposure area 121, thereby preventing the photoresist covered by the surface carbon layer 123 from being modified by exposure, thus adjusting the patterning result of the photoresist layer 120 and affecting the subsequent etching of the substrate 110. For example, if the aforementioned photoresist layer 120 is configured as a positive photoresist, the photoresist in the aforementioned avoidance area will not be removed, protecting the underlying substrate 110 from being etched in subsequent processes. It should be noted that, to avoid confusion caused by the surface carbon layer, the area reachable by the exposure beam determined by the light source and the mask will be referred to as the exposure range in the following discussion.
[0044] Therefore, based on the surface carbon layer, in the photoresist exposure process, the surface carbon layer blocks the exposure beam from entering the underlying photoresist, allowing the photoresist within the exposure range that is not covered by the surface carbon layer to be exposed and modified. Consequently, during the formation of the mask layer, the pattern formed differs from its actual corresponding photomask, thus meeting the adjustment requirements of semiconductor devices and reducing the modification cost of the photomask. Furthermore, considering that the surface carbon layer and the photomask play similar roles in the exposure process, the surface carbon layer can completely replace the photomask during mask layer formation, enabling maskless photoresist exposure and increasing the freedom of mask layer formation.
[0045] Based on the aforementioned development and exposure process, the following will combine... Figure 3 ~ Figure 8 The manufacturing method of the semiconductor device provided in this application is described in detail.
[0046] Exemplary mask layer formation method:
[0047] Based on the aforementioned photoresist etching process using the surface carbon layer, at least one of the aforementioned mask layer formation processes based on the surface carbon layer can be performed during the fabrication of semiconductor devices, thereby enabling local wafer processing processes (such as local etching and local doping) based on the mask layer to complete the fabrication of semiconductor devices.
[0048] To further illustrate the mask layer formation process based on a surface carbon layer, this application also provides an exemplary flowchart of the mask layer formation process based on a surface carbon layer ( Figure 3 ).
[0049] like Figure 3 As shown, process P300 may include the following steps:
[0050] S310, A photoresist layer is formed on the surface of the substrate.
[0051] S320. Surface carbonization is performed on the photoresist layer to form a surface carbon layer.
[0052] S330. Perform an exposure process on the photoresist layer to expose and modify the photoresist in the photoresist layer that is within the exposure range and is not covered by a surface carbon layer.
[0053] S340. The modified photoresist layer is developed to form a mask layer.
[0054] In the aforementioned S310, the substrate can refer to the object that needs to undergo partial wafer processing, which can be a complete wafer or a processed wafer (such as a diced wafer or a bonded wafer). The substrate can generally include a substrate that houses semiconductor structures (such as a silicon substrate and a doped substrate grown on it) and semiconductor structures formed on the substrate (such as PN junctions, metal interconnect layers, etc.).
[0055] In the aforementioned S310, the formation process of the photoresist layer can be referred to the relevant description in the above-mentioned coating and pre-baking processes, and will not be repeated here. In addition, this application does not limit the specific type of photoresist layer used, and those skilled in the art can adapt the photoresist development and exposure process based on the surface carbon layer provided in this application according to actual needs.
[0056] In the aforementioned S320, the surface carbon layer can refer to the thin layer structure formed after the surface of the photoresist layer is carbonized. In the subsequent exposure process, the surface carbon layer is used to block the exposure beam from entering the photoresist below the surface carbon layer, so as to prevent the photoresist layer below from being modified.
[0057] The surface carbon layer can be achieved through a carbonization process on the surface of the photoresist layer away from the substrate. Specifically, considering that the photoresist itself is composed of materials such as polymers and organic solvents, and contains a large number of carbon (C), hydrogen (H), and oxygen (O) elements, its composition can be equivalently characterized as C x H y O z This component carbonizes when heated, i.e., C. x H y O z→C+H2O, in which water molecules are lost in a gaseous state, and the remaining carbon elements remain in solid form on the surface of the photoresist layer, thus forming a surface carbon layer.
[0058] In some embodiments, considering that the surface carbon layer has a certain pattern, it is difficult to form it globally in one go. Its formation process is often achieved by moving the carbonization interface. Here, the carbonization interface can refer to the local area on the photoresist surface where surface carbonization is performed. For example, the carbonization interface can refer to the contact interface between the external heat source and the photoresist surface.
[0059] In some embodiments, considering that the surface carbon layer serves to block the exposure beam from entering the underlying photoresist layer, the surface carbon layer needs to be dense enough to block all exposure beams in the corresponding area. To improve the density of the surface carbon layer, the aforementioned surface carbonization of the photoresist layer can be achieved using high-energy rays.
[0060] High-energy radiation refers to radiation processes involving high energy, which can be any process involved in the fabrication of semiconductor devices other than mask layer formation. For example, high-energy radiation can include high-energy ion beams and plasma beams involved in processes such as ion implantation and electron beam lithography, as well as traditional lasers and microwaves.
[0061] Surface carbonization based on high-energy rays is a non-contact method for forming surface carbon layers. The carbonized interface generated by high-energy rays often appears as a "spot" formed by focusing high-energy rays on the photoresist surface. This spot provides sufficient energy to carbonize or dehydrogenate the photoresist, thereby achieving the aforementioned surface carbon layer. Considering the control precision of this spot, laser rays and microwave rays are preferred.
[0062] Furthermore, considering that some semiconductor device fabrication methods involve high-energy radiation processes (such as doping processes) and that high-energy radiation is similar to exposure beams, the density of the surface carbon layer can be further guaranteed when forming the surface carbon layer using high-energy radiation.
[0063] Specifically, when using high-energy rays to form a surface carbon layer, the high-energy rays form a spot on the photoresist surface. This spot causes carbonization of the photoresist surface, gradually forming a surface carbon layer. Considering that high-energy rays are similar to the exposure beam (i.e., the exposure beam is also a type of high-energy ray) and can both be blocked by the surface carbon layer, the high-energy rays are gradually blocked by the forming surface carbon layer until its formation is complete. After the surface carbon layer is formed, high-energy rays cannot penetrate it to carbonize the photoresist, thus ensuring a stable thickness. Given this characteristic of the surface carbon layer, when performing an exposure process based on it, the exposure beam cannot penetrate the surface carbon layer to reach the underlying photoresist. Therefore, the surface carbon layer formed by high-energy rays ensures that the exposure beam cannot pass through it.
[0064] In some embodiments, the extent of the surface carbon layer formation can be determined based on the actual fabrication process of the mask layer (e.g., whether a photolithographic mask is used) and the actual structure of the semiconductor device (e.g., the difference between the structure of the semiconductor device and the photolithographic mask). See details... Figure 4 , Figure 5 The relevant descriptions will not be repeated here.
[0065] In the aforementioned S330, the exposure process can refer to irradiating the surface of the photoresist layer with an exposure beam, thereby modifying the irradiated photoresist layer. The area of the photoresist layer away from the substrate that is irradiated by the exposure beam can be denoted as the exposure range.
[0066] Based on the aforementioned surface carbon layer, when the photoresist layer covered by the surface carbon layer is within the exposure range, the exposure beam will preferentially reach the surface carbon layer and be blocked by it. This prevents the underlying photoresist layer from contacting the exposure beam and maintains its original properties, thus protecting the photoresist layer within the exposure range through the surface carbon layer. Meanwhile, photoresist without a surface carbon layer but within the exposure range will undergo exposure modification. The specific exposure modification depends on the type of photoresist itself, as described above.
[0067] In some embodiments, the exposure range of the aforementioned exposure process can cover the entire photoresist surface, in which case the exposure process of the photoresist does not involve the photomask. The aforementioned exposure range can also correspond to the light-transmitting area of the photomask, thereby performing the exposure process based on the photomask and the surface carbon layer.
[0068] In the aforementioned S340, based on the photoresist layer after the aforementioned exposure treatment, a corresponding development treatment can be performed to remove a portion of the photoresist layer. The amount of photoresist removed during the development treatment depends on the type of photoresist layer; positive photoresist removes the modified portion, while negative photoresist removes the unmodified portion.
[0069] After the aforementioned development process, a portion of the photoresist layer can be removed, exposing a portion of the substrate surface. This developed photoresist layer can be referred to as a mask layer. Based on this mask layer, the exposed portion of the substrate surface can be processed, thus achieving localized wafer processing. For example, etching or surface doping of the exposed portion can be performed using the mask layer. In other words, after completing P300, "localized wafer processing based on the mask layer" can be executed.
[0070] Taking etching as an example, during the etching process, the portion of the substrate surface covered by the photoresist layer can prevent the underlying substrate from being exposed to the etching environment, thus maintaining its original shape. The portion of the substrate surface not covered by the photoresist layer will be exposed to the etching environment (such as direct contact with the etching reagent or direct exposure to the etching rays), and will be etched to form common semiconductor structures such as grooves and vias.
[0071] After completing the local processing, the aforementioned photoresist layer can be removed to allow for subsequent processing. The removal of the photoresist layer can be performed using conventional photoresist removal processes. For example, in a surface doping process based on a mask layer, the high-energy ion beam used for doping may also cause carbonization of the mask layer surface; in such cases, the mask layer removal method of this application can be performed based on the mask layer removal process under these circumstances.
[0072] In some embodiments, considering the influence of the surface carbon layer on the photoresist removal process, a wet cleaning process can be used to remove the photoresist. The wet cleaning process can remove the photoresist beneath the surface carbon layer, allowing the surface carbon layer to separate from the photoresist and be removed. In some embodiments, the photoresist layer can also be completely carbonized, thereby removing the carbonized photoresist layer based on the carbonization layer removal method. The contact interface between the carbonized photoresist layer and the substrate surface is generally more porous, making it easier to peel off the fully carbonized photoresist layer.
[0073] It should be noted that the aforementioned P300 mainly involves the coating, developing, and exposure processes in the mask layer formation process. Other processes, such as pre-baking and post-baking, can be implemented adaptively based on actual needs and will not be elaborated here.
[0074] To address the need for mask layer adjustments during local wafer processing, the aforementioned mask layer formation process P300 can form a corresponding surface carbon layer on the photoresist surface. Based on this surface carbon layer, during the photoresist exposure process, the surface carbon layer blocks the exposure beam from entering the underlying photoresist, allowing the photoresist within the exposure range that is not covered by the surface carbon layer to be exposed and modified.
[0075] Therefore, the pattern formed during the mask layer formation process differs from the actual corresponding photomask, thus meeting the adjustment requirements of semiconductor devices and reducing the modification cost of the photomask. Furthermore, considering that the surface carbon layer and the photomask play similar roles in the exposure process, the surface carbon layer can completely replace the photomask during mask layer formation, enabling maskless photoresist exposure and increasing the freedom of mask layer formation.
[0076] To further illustrate the aforementioned process of forming a surface carbon layer, this application also provides an exemplary flowchart of the surface carbon layer formation process ( Figure 4 ).
[0077] like Figure 4 As shown, process P400 may include the following steps:
[0078] S410. Determine the formation range of the surface carbon layer.
[0079] S420. High-energy rays are used to irradiate a portion of the photoresist layer corresponding to the formation range, causing the portion of the photoresist layer corresponding to the formation range to carbonize into a surface carbon layer.
[0080] In the aforementioned S410, the formation range can refer to the actual range of the surface carbon layer on the side of the photoresist layer away from the substrate. That is, before forming the surface carbon layer, the formation range of the surface carbon layer can be determined based on the actual needs of the semiconductor device.
[0081] In some embodiments, the extent of the surface carbon layer formation can be determined based on adjustments to the semiconductor device relative to its original design. For example, when it is desired to increase the size of a trench within the semiconductor device, a negative photoresist can be used to form a surface carbon layer over the increased area of the trench. This surface carbon layer prevents the negative photoresist from being modified and thus washed away during development, exposing more substrate surface and forming a larger trench. As another example, when it is desired that the semiconductor device not be etched in a certain area (such as the wafer edge), a positive photoresist can be used to form a surface carbon layer at the wafer edge. This surface carbon layer prevents the positive photoresist from being modified, and the photoresist at the wafer edge is retained during subsequent development to avoid etching in that area.
[0082] In some embodiments, considering that the mechanism of action of the surface carbon layer provided in this application is similar to that of a photomask, the surface carbon layer can be directly used to replace the photomask for forming the mask layer. In this case, the formation range can be directly determined based on the design of the semiconductor device. That is, the target area can be determined based on the type of photoresist in the photoresist layer, and the target area can be used as the formation range of the surface carbon layer. Specifically, when the photoresist layer is positive, the target area is determined based on the area of the substrate where wafer localization is not performed; when the photoresist layer is negative, the target area is determined based on the area of the substrate where wafer localization is performed.
[0083] Based on the aforementioned determined and formed surface carbon layer, direct exposure can be performed in subsequent development processes without the need for a photomask. That is, the photoresist layer can be placed within the exposure range, and the surface carbon layer blocks the exposure beam within the exposure range, allowing the photoresist without the surface carbon layer to be exposed and modified.
[0084] In some embodiments, the determination of the aforementioned forming range can also be combined with the photomask used, as detailed in [reference needed]. Figure 5 The details and related descriptions will not be elaborated here.
[0085] As mentioned above, when performing S420, it can be based on the light spot formed by high-energy rays. That is, when high-energy rays perform surface carbonization, they will focus and form a "light spot" on the side of the photoresist layer away from the substrate or within a certain depth. This "light spot" can carbonize the photoresist layer at the corresponding location, thereby forming a surface carbon layer. In order to form a surface carbon layer within the aforementioned formation range, the "light spot" can be moved along a certain trajectory to form the surface carbon layer.
[0086] Considering the aforementioned high-precision requirements for focusing and moving the light spot, the high-energy rays can be configured as highly controllable high-energy rays such as laser rays or microwave rays. Experiments have shown that the laser rays have a wavelength range of 450 nm to 550 nm, a pulse width of 5 ns to 20 ns, and an energy density of 0.05 J / cm². 2 ~ 0.5J / cm 2 The spot diameter is 10μm ~ 100μm and the repetition frequency is 1kHz ~ 10kHz, which can meet the requirements for the formation of the surface carbon layer in this application.
[0087] Based on the aforementioned laser beam, the aforementioned S420 may include the following sub-steps:
[0088] S421. Focus the laser beam into the formation range so that the photoresist at the laser beam spot is carbonized.
[0089] S422. Based on the formation range, the laser spot is moved so that the movement trajectory of the laser spot covers the formation range to form a surface carbon layer.
[0090] Furthermore, during the execution of S421, the carbonization execution parameters of the light spot can be determined based on the blocking effect of the aforementioned surface carbon layer on high-energy rays. That is, the carbonization time at which the surface carbon layer can block high-energy rays (i.e., the aforementioned laser rays) after it is fully formed (e.g., the surface carbon layer no longer thickens within a certain period of time) can be determined as the time parameter for the formation of the surface carbon layer.
[0091] In the aforementioned S422, the laser spot can be moved based on the carbonization time of the aforementioned surface carbon layer, so that the movement trajectory of the laser spot covers the formation area, thereby forming the surface carbon layer. Furthermore, to increase the formation rate, the aforementioned laser beam can also form multiple spots, forming the surface carbon layer in parallel.
[0092] Therefore, based on the aforementioned surface carbon layer formation process, a suitable surface carbon layer can be formed within a pre-configured formation range. Simultaneously, considering the similar properties of high-energy rays and exposure beams, the surface carbon layer gradually blocks high-energy rays during formation, preventing them from passing through the formed surface carbon layer, thereby ensuring that the exposure beam also cannot pass through it.
[0093] To further illustrate the mask layer formation process based on a photolithographic mask, this application also provides an exemplary flowchart of the mask layer formation process based on a surface carbon layer and a photolithographic mask. Figure 5 ).
[0094] like Figure 5 As shown, process P500 may include the following steps:
[0095] S510. Determine the target area based on the photoresist type of the photoresist layer.
[0096] S520. Determine the exposure range of the photomask corresponding to the photoresist layer.
[0097] S530, the formation range is determined based on the exposure range and the target area.
[0098] S540. High-energy rays are used to irradiate a portion of the surface of the photoresist layer corresponding to the formation range, causing the portion of the photoresist layer corresponding to the formation range to carbonize into a surface carbon layer.
[0099] S550: Align the photomask with the photoresist layer so that part of the photoresist layer is exposed through the mask layer into the exposure range.
[0100] S560. The photoresist layer is exposed using a photomask, so that the photoresist in the photoresist layer that is within the exposure range and is not covered by a surface carbon layer is exposed and modified.
[0101] In the aforementioned S510, the target area can refer to the area where a surface carbon layer needs to be formed theoretically, and can be specifically determined based on the actual needs of the semiconductor device. Specifically, when the photoresist layer is a positive photoresist, the target area is determined based on the area of the substrate where wafer local processing is not performed; when the photoresist layer is a negative photoresist, the target area is determined based on the area of the substrate where wafer local processing is performed.
[0102] In some embodiments, the target region can be directly configured as the aforementioned region based on the aforementioned mapping relationship. That is, for positive photoresist, the target region can be directly configured as the region in the substrate where wafer local processing is not performed. For negative photoresist, the target region can be directly configured as the region in the substrate where wafer local processing is performed.
[0103] In some embodiments, the target region may also be determined based on adjustments to the semiconductor device relative to its original design. For example, for positive photoresist, the target region may be configured as an area that originally required local processing but does not require local processing after adjustment (such as the wafer edge region in subsequent embodiments).
[0104] In the aforementioned S520, the exposure range can be determined based on the light transmittance of the photomask. In some embodiments, the photomask can be configured as a photomask used before semiconductor device adjustment. In some embodiments, when the photomask used before semiconductor device adjustment cannot meet the etching requirements (e.g., for positive photoresist, the target area needs to have an increased etching range), the closest photomask can be determined based on the actual needs of the semiconductor device (i.e., the area in the substrate where wafer local processing is performed / not performed).
[0105] In the aforementioned S530, considering that the target area can refer to the area where a surface carbon layer needs to be formed theoretically, and that this application uses a photomask, which may block part of the target area, it is not necessary to form a surface carbon layer in all target areas. That is, in the aforementioned S530, the formation range can be determined based on the portion of the target area not blocked by the photomask, so that the light-blocking area of the photomask and the formation range cover the target area.
[0106] In some embodiments, the aforementioned forming range may be further expanded (e.g., by 5%) at its boundary with the portion of the target area not covered by the photomask, so that there is no gap at the boundary between the forming range and the photomask, ensuring that the exposure beam cannot enter the photoresist in the target area.
[0107] In some embodiments, the aforementioned formation range can also be determined by replanning the portion of the target area not obscured by the photomask. For example, for discrete regions, a regular region can be defined to form the surface carbon layer.
[0108] The aforementioned S540 can be found in the relevant descriptions in P300 and P400. In actual implementation, the movement path and control of the light spot can be achieved using a path planning algorithm for a self-moving device, which will not be elaborated here.
[0109] The aforementioned S550 involves the alignment process of the photoresist layer, that is, the photomask and the photoresist need to be aligned before exposure. It should be noted that the aforementioned alignment process can also be adjusted based on the surface carbon layer so that the light-shielding area and the formation range of the aligned photomask cover the target area.
[0110] The aforementioned S560 involves exposure processing, and this processing, as well as the subsequent baking and developing processes, can be found in the foregoing content and will not be repeated here.
[0111] Therefore, based on the aforementioned process, this application can adjust the mask layer formed on the photolithographic mask to meet the requirements of semiconductor devices. Furthermore, when determining the formation range of the surface carbon layer based on the photolithographic mask, the formation range can be optimized based on the occlusion of the photolithographic mask itself, thereby reducing the time and process difficulty in the preparation of the surface carbon layer.
[0112] Exemplary semiconductor devices and methods for manufacturing the same:
[0113] This application discovers that during bonding, the bonding structure at the wafer edge may fail to bond or form bubble defects. However, based on the aforementioned mask layer formation process, a surface carbon layer can be formed at the wafer edge, allowing the wafer bonding structure to be formed outside the wafer edge, thereby avoiding bubble defects in the wafer bonding structure caused by the wafer edge region.
[0114] The wafer bonding involved in the aforementioned situation (mainly involving hybrid bonding) is a three-dimensional wafer integration technology that enables vertical stacking and interconnection of wafers. It is primarily used in stacked image sensors (CIS), 3D NAND memory, high-performance processors, and MEMS (microelectromechanical systems).
[0115] Taking a back-illuminated image sensor as an example, a pixel array wafer and a logic processing wafer can be bonded using wafer bonding technology. Specifically, the pixel array wafer can include a pixel layer (generally including pixel photosensitive units, such as photodiodes, color filters, etc.) and a metal interconnect layer. The logic processing wafer can include a logic circuit layer (such as an integrated ADC, signal processor, control circuit, etc., used to realize photoelectric signal conversion and processing) and a metal interconnect layer. Bonding grooves can be formed on the surfaces of the pixel array wafer and the logic processing wafer near the metal interconnect layer. The interconnection of the metal interconnect layers in the two wafers is achieved through the alignment of the bonding grooves and the bonding medium, thereby realizing the driving of the pixel layer by the logic circuit layer.
[0116] To further illustrate the cause of bubble defects appearing at the wafer edge in the aforementioned wafer bonding technology, this application provides a schematic diagram of a semiconductor device having at least two wafers and their bonding structure. Figure 6 ).
[0117] like Figure 6 As shown, the semiconductor device 600 may include a first wafer 610 and a second wafer 620 bonded together. The first wafer 610 and the second wafer 620 may represent two wafers bonded together, such as the aforementioned pixel array wafer serving as the aforementioned first wafer 610, and the aforementioned logic processing wafer serving as the aforementioned second wafer 620.
[0118] To achieve bonding between the first wafer 610 and the second wafer 620, multiple bonding structures 630 are formed at the contact interface between the first wafer 610 and the second wafer 620. The bonding structures 630 are formed by aligning bonding grooves and interconnecting bonding media within the bonding grooves. Specifically, the bonding structure 630 may include a first bonding groove 631 formed on the surface of the first wafer 610 facing the second wafer 620, a second bonding groove 632 formed on the surface of the second wafer 620 facing the first wafer 610, and bonding media 633 filling the first bonding groove 631 and the second bonding groove 632.
[0119] During bonding, the first bonding groove 631 and the second bonding groove 632 can be filled with bonding media (generally metallic media). Then, the first bonding groove 631 and the second bonding groove 632 are aligned and the two wafers are bonded together in a vacuum or inert gas (such as N2) environment. The bonding of the two wafers is promoted by plasma treatment and hydrogen bonding, and atomic diffusion at the interface of the metallic media is promoted by heat curing (heating temperature 300-400℃), so that the bonding media in the first bonding groove 631 and the second bonding groove 632 are fused and interconnected at the interface, thereby forming a bonding structure 630.
[0120] During the aforementioned bonding process, the interface between the first bonding trench 631 and the second bonding trench 632 often needs to be in close contact to expel air, which places requirements on the flatness of the wafer surface. Specifically, before bonding, the surfaces of the first wafer 610 and the second wafer 620 to be bonded need to be mirror-polished and thoroughly cleaned to remove particles, organic matter, and metallic impurities, so that the surfaces of the first wafer 610 and the second wafer 620 to be bonded have a flat appearance, thereby expelling gases from the environment at the interface between the first bonding trench 631 and the second bonding trench 632.
[0121] However, the wafer edge region 640 often requires an edge washing process before bonding. If a bonding trench is formed within the edge washing process area, the edge washing process will cause the bonding medium filled in the bonding trench to be consumed by the edge washing process reaction, thereby causing at least part of the medium to be lost from the surface of the bonding medium filled in the bonding trench, making its morphology unable to completely match the bonding medium on the other side. As a result, in subsequent bonding steps, the bonding trench in the area covered by the edge washing process is difficult to bond, and even if it is bonded, it may form a void structure due to the loss of medium.
[0122] Considering that the bonding trenches of the bonding structure 630 are often formed through wafer etching based on a mask layer, based on the aforementioned mask layer formation method, a mask layer can be formed based on the wafer edge region 640 during the wafer etching process, preventing the bonding structure 630 from forming in the wafer edge region 640. This avoidance measure can mitigate bubble defects that occur when the bonding structure 630 forms in the wafer edge region 640, thereby improving the performance of the semiconductor device.
[0123] In summary, during wafer bonding in related technologies, bubble defects may exist in the bonding structure 630 at the wafer edge region 640 due to the need for an edge washing process. This situation can be seen in [reference needed]. Figure 6 The bonding structure 630 is located within the left-hand wafer edge region 640. For cases where the bonding structure is not placed in the wafer edge region 640, please refer to [reference needed]. Figure 6 The right edge region of the wafer, 640. Additionally, the normal bonding structure 630 can be seen in [reference needed]. Figure 6 The bonding structure in the middle is 630.
[0124] To further illustrate the process of avoiding bonding structures in the wafer edge region, this application also provides an exemplary flowchart of a semiconductor device manufacturing method (…). Figure 7 ).
[0125] like Figure 7 As shown, process P700 may include the following steps:
[0126] S710 provides a first wafer and a second wafer that need to be bonded.
[0127] S720. For the target wafer in the first wafer and the second wafer, perform at least one mask layer formation based on the surface carbon layer and a local wafer processing based on the mask layer based on the wafer edge region of the target wafer to form a bonding structure.
[0128] S730, based on a bonding structure, bonds the first wafer and the second wafer.
[0129] In the aforementioned S710, the first wafer and the second wafer can refer to wafers that have undergone other processing steps prior to bonding and have not yet formed bonding trenches. In actual fabrication, wafers are often processed individually based on their type. That is, the first wafer can be processed in a separate batch, and the second wafer can also be processed in a separate batch. Then, a set of wafers processed by both is selected for bonding.
[0130] In the aforementioned S720, the target wafer can refer to the wafer in which the bonding trench is formed. It can be a designation for one of the first wafer and the second wafer, reflecting the processing method of each wafer when forming the bonding trench.
[0131] "Mask layer formation based on surface carbon layer" can refer to the mask layer formation process described in the aforementioned P300 and related descriptions. Considering the actual requirements when forming bonding trenches, the "surface of the substrate" involved in this process can be configured as the side of the target wafer to be bonded. Since the "mask layer" is generally formed based on positive photoresist, the "surface carbon layer" should be formed in the edge region of the wafer. Therefore, forming the surface carbon layer in the edge region of the wafer (i.e., the aforementioned wafer edge region) ensures that the photoresist in this area is not modified. Combined with positive photoresist, the mask layer can cover the wafer edge region, thus preventing subsequent local wafer processing based on the mask layer from being performed in the wafer edge region.
[0132] Considering that bonding structures often manifest as bonding trenches within each wafer, "wafer local processing based on the mask layer" can be configured as a trench etching process on the wafer. That is, wafer local processing includes wafer etching. Based on the aforementioned surface carbon layer, the wafer etching process will not etch the wafer edge region, causing the bonding structure to form outside the wafer edge region. Therefore, the bonding structure will not form in the wafer edge region, thus preventing bubble defects caused by edge washing processes in the wafer edge region.
[0133] In the foregoing description, considering the anomalous formation of bonding structures in the wafer edge region, the wafer edge region can refer to the edge region of the wafer after the edge-washing process. Actual testing has shown that the wafer edge region can be configured as an area extending 1mm to 3mm inward from the outer edge of the target wafer.
[0134] The formation of a surface carbon layer based on the wafer edge region and the formation of a mask layer based on the surface carbon layer ensure that the bonding trench is formed outside the wafer edge region. Subsequent bonding steps (i.e., S730) can be performed based on the bonding trench formed outside the wafer edge region to form a bonding structure between the first wafer and the second wafer.
[0135] Furthermore, in the actual fabrication process of the bonding structure, considering the communication requirements between wafers, the bonding structure can further include vias and trenches. The vias can extend from the surface of the target wafer to the internal circuitry of the target wafer (e.g., ...). Figure 6 Medium-depth bonding trenches allow channel bonding trenches on different wafers to bond together, forming conductive channels that connect the internal circuitry of the two wafers, thus enabling communication between them. Surface bonding trenches can be formed only on the surface of the target wafer (e.g., Figure 6 Surface bonding grooves (with moderate to shallow depth) are not used for data communication. They are primarily used to increase the bonding strength between two wafers.
[0136] Based on the aforementioned channel bonding trenches and surface bonding trenches, the bonding structure formation process for the target wafer can be repeated twice to form the aforementioned two types of bonding trenches. To further describe this process, this application also provides an exemplary flowchart of the wafer bonding structure formation process (…). Figure 8 ).
[0137] like Figure 8 As shown, process P800 may include the following steps:
[0138] S810. Determine the target size of the wafer edge region of the target wafer based on the size of the first wafer and the size of the second wafer.
[0139] S820 performs mask layer formation based on surface carbon layer and wafer local processing based on mask layer to form channel bonding trenches.
[0140] S830 performs mask layer formation based on surface carbon layer and wafer local processing based on mask layer to form surface bonding trenches.
[0141] S840. Fill the channel bonding groove and the surface bonding groove with bonding medium.
[0142] S850 performs an edge-washing process on the wafer edge area.
[0143] S860, Align the first wafer and the second wafer and perform bonding process.
[0144] In the aforementioned S810, the target size of the wafer edge region of the target wafer can be determined based on the foregoing description. For example, the target size of the wafer edge region of the target wafer can be 3 mm.
[0145] In practice, the first and second wafers used for bonding often have the same dimensions; therefore, the delineation of the wafer edge regions is generally the same. Furthermore, considering that the wafer edge regions are curved, direct contact may be undesirable. Before bonding (i.e., after S840 and before S860), one side of the wafer can be trimmed before bonding. In this case, the two wafers will exhibit a certain difference in size. That is, as... Figure 6 As shown, this is the case where the first wafer is smaller than the second wafer.
[0146] In some embodiments, wafer bonding can also be performed based on wafers of different sizes (e.g., edge trimming was performed before performing P800 or wafers of different specifications were used). In this case, the bonding trenches (i.e., the light-transmitting areas in the photomask) that may be covered by the wafer edge region of the smaller wafer may be different from those of the wafer edge region of the larger wafer. Therefore, when performing S810, the surface carbon layer formation area of the larger wafer can be adjusted based on the smaller wafer (i.e., the size of the wafer edge region of the larger wafer can be adjusted).
[0147] Specifically, when the wafer sizes of the first wafer and the second wafer are different, the target size of the edge region of the target wafer can be determined based on the specific object it refers to. If the target wafer refers to the smaller of the first and second wafers (denoted as the first target wafer), the target size of the edge region of the target wafer can be configured as the actual edge size (i.e., the actual edge region for which the edge washing process is performed, specifically 1mm to 3mm as mentioned above). If the target wafer refers to the larger of the first and second wafers (denoted as the second target wafer), the target size of the edge region of the target wafer can be configured as the sum of the difference between the actual edge size and the wafer edge size.
[0148] That is, when executing the aforementioned S810, in response to the fact that the wafer sizes of the first wafer and the second wafer are different and the target wafer is the first target wafer, the target size of the wafer edge region of the target wafer can be configured as the actual edge size. Alternatively, in response to the fact that the wafer sizes of the first wafer and the second wafer are different and the target wafer is the second target wafer, the target size of the wafer edge region of the target wafer can be configured as the sum of the difference between the actual edge size and the wafer edge size, wherein the wafer size of the second target wafer is larger than that of the first target wafer.
[0149] Assumption Figure 6 The two wafers shown had a size difference before bonding; here, we take... Figure 6 Taking the wafer edge region 640 on the right as an example, the determination of the size of the wafer edge region will be explained. Figure 6 If the wafer size of the first wafer 610 is smaller than that of the second wafer 620 (it should be noted that the first wafer 610 and the second wafer 620 refer to two wafers that need to be bonded, and the first wafer 610 often refers to the wafer above it, and there is no substantial requirement for its size), then after the two are aligned, a wafer edge size difference d0 is formed in the wafer edge region 640.
[0150] Based on the foregoing description, the first wafer 610 is the first target wafer, and the second wafer 620 is the second target wafer. The size of the wafer edge region of the first wafer 610 can be the actual edge size d1 (for example, it can be 3mm), and the size of the wafer edge region of the second wafer 620 can be the sum of the actual edge size d1 and the difference between the wafer edge size d0 (i.e., d2 = d1 + d0).
[0151] This ensures that the bonding grooves of the first wafer and the second wafer match each other during bonding, avoiding the situation where a larger wafer forms bonding grooves in the edge area of a smaller wafer due to size differences.
[0152] The aforementioned S820 and S830 can be considered as local processing procedures for two wafers with different etching depths. Their actual fabrication logic is similar, mainly differing in etching depth. For details, please refer to... Figure 6 The bonding structure 630 in the intermediate region, wherein the deeper bonding structure 630 can be formed based on the channel bonding groove, and the shallower bonding structure 630 can be formed based on the surface bonding groove.
[0153] The etching depth of a channel bonding trench within its corresponding wafer can be h1, and the etching depth of a surface bonding trench within its corresponding wafer can be h2. The etching depth h1 of the channel bonding trench is generally determined based on the distance between the bonding surface of the wafer and the metal interconnect layer, so that the channel bonding trench can extend from the surface of the target wafer to the internal circuitry of the target wafer. This allows the bonding structure formed by the interlocking of channel bonding trenches to become a conductive channel connecting the internal circuitry of the two wafers. The etching depth h2 of the surface bonding trench is generally determined based on the thickness of the wafer surface (generally less than this thickness) to avoid affecting other structures within the wafer during its formation.
[0154] After determining the aforementioned etching depth, a mask layer can be formed based on the corresponding photomask and the surface carbon layer of the wafer edge region. Then, based on the corresponding etching depth, corresponding bonding trenches can be formed to achieve S820 and S830. In actual fabrication, the channel bonding trenches are often fabricated first. After fabricating one bonding trench, the mask layer needs to be removed and regenerated. Methods for removing the mask layer can be found in the foregoing content and related technologies.
[0155] In the aforementioned S840, the bonding medium is often a metallic medium (such as copper), and its filling can be performed based on a metal-filling process. The surfaces of the bonding media in the two bonding grooves to be bonded need to be aligned so that subsequent processes can heat-bond the bonding media of two different wafers.
[0156] In the aforementioned S850, following the metal-filled bonding medium formation process, if an edge-washing process is not performed, the metal-filling process may cause copper contamination on the wafer surface. Therefore, an edge-washing process can be performed after the aforementioned bonding medium filling is completed. The edge-washing process can be performed adaptively based on the possible residues at the edges. The edge-washing process here is mainly a metal residue edge-washing process. Considering that the aforementioned process involves photoresist etching and subsequent bonding processing, this step may also include a photoresist residue edge-washing process and a pre-bonding edge-washing process.
[0157] Based on the aforementioned settings, when performing the edge-washing process of S850, the bonding structure will not be located within the influence range of the edge-washing process, thereby ensuring the integrity and consistency of the bonding medium morphology within the bonding groove.
[0158] In the aforementioned S860, after processing the two wafers, the two wafers can be aligned and then bonded. For the specific bonding process of the two wafers, please refer to relevant techniques in the art, which will not be elaborated here.
[0159] Therefore, a suitable bonding trench can be formed based on the aforementioned P800, thereby achieving bonding between the first wafer and the second wafer. Furthermore, in addition to the aforementioned semiconductor device manufacturing method, this application also protects semiconductor devices produced based on this manufacturing method. For example, semiconductor devices generated based on the manufacturing methods shown in P700 or P800 are also within the scope of protection of this application. Furthermore, semiconductor devices based on the mask layer formation methods shown in P300 to P500 mentioned above in the semiconductor fabrication process are also within the scope of protection of this application.
[0160] Unexpected technical effects:
[0161] In summary, the semiconductor device and manufacturing method provided in this application have the following unexpected effects:
[0162] ① To address the need for mask layer adjustments during local wafer processing, this application allows the formation of a corresponding surface carbon layer on the photoresist surface. Based on this surface carbon layer, during the photoresist exposure process, the surface carbon layer blocks the exposure beam from entering the underlying photoresist, allowing the photoresist within the exposure range that is not covered by the surface carbon layer to be exposed and modified. Therefore, during the mask layer formation process, the pattern formed differs from its actual corresponding photomask, thus meeting the adjustment requirements of semiconductor devices and reducing the modification cost of the photomask.
[0163] ② Considering that the surface carbon layer and the photomask play similar roles in the exposure process, the surface carbon layer can completely replace the photomask during the formation of the mask layer, realizing the maskless exposure process of photoresist and increasing the degree of freedom in mask layer formation.
[0164] ③ The surface carbon layer can be formed using high-energy rays. When using high-energy rays to form the surface carbon layer, the high-energy rays form a spot on the photoresist surface. This spot causes the photoresist surface to carbonize, gradually forming the surface carbon layer. Considering that high-energy rays are similar to the exposure beam (i.e., the exposure beam is actually a type of high-energy ray), both can be blocked by the surface carbon layer. During the formation of the surface carbon layer, the high-energy rays are gradually blocked by the forming surface carbon layer until its formation is complete. After the surface carbon layer is formed, high-energy rays cannot penetrate it to carbonize the photoresist, thus giving the surface carbon layer a stable thickness. Considering the role of the surface carbon layer, when performing the exposure process based on it, the exposure beam cannot penetrate the surface carbon layer to irradiate the underlying photoresist. Therefore, the surface carbon layer formed by high-energy rays ensures that the exposure beam cannot penetrate it.
[0165] ④ In this application, the surface carbon layer of the photoresist does not completely penetrate the photoresist layer; instead, there is a certain amount of photoresist between the surface carbon layer and the wafer surface. Therefore, when removing the mask layer, a wet cleaning process can be used to remove the cured photoresist layer. At this time, the photoresist remaining between the wafer surface and the surface carbon layer is removed by the wet cleaning process, while the surface carbon layer is simultaneously stripped away.
[0166] ⑤ This application has discovered that bonding structures at wafer edges often suffer from bonding failures or bubble defects. This application can form a surface carbon layer at the wafer edge based on the aforementioned mask layer formation process, so that the wafer bonding structure is formed outside the wafer edge, thereby avoiding bubble defects in the wafer bonding structure caused by the edge washing process in the wafer edge region.
[0167] The embodiments disclosed above are merely illustrative of this application. The embodiments do not exhaustively describe all details, nor do they limit the application to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to better understand and utilize this application. This application is limited only by the claims and their full scope and equivalents.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes forming a mask layer based on a surface carbon layer and performing partial wafer processing based on the mask layer, wherein forming the mask layer based on the surface carbon layer includes: A photoresist layer is formed on the surface of the substrate; Determine the formation range of the surface carbon layer; A portion of the photoresist layer corresponding to the formation range is irradiated with high-energy rays to carbonize the portion of the photoresist layer corresponding to the formation range into a surface carbon layer, wherein the surface carbon layer is used to block the exposure beam from entering the photoresist below the surface carbon layer; The photoresist layer is exposed to modify the photoresist layer that is within the exposure range and is not covered by the surface carbon layer. The modified photoresist layer is subjected to a development process to form the mask layer.
2. The manufacturing method according to claim 1, characterized in that, The high-energy rays are configured as laser rays, and the step of irradiating a portion of the photoresist layer corresponding to the formation range with high-energy rays to carbonize the portion of the photoresist layer corresponding to the formation range into the surface carbon layer includes: The laser beam is focused onto the formation area, causing the photoresist at the laser beam spot to be carbonized; The laser spot is moved based on the formation range, so that the movement trajectory of the laser spot covers the formation range to form the surface carbon layer; The laser beam has a wavelength range of 450 nm to 550 nm, a pulse width of 5 ns to 20 ns, and an energy density of 0.05 J / cm². 2 ~0.5J / cm 2 The spot diameter is 10μm~100μm, and the repetition frequency is 1kHz-10kHz.
3. The manufacturing method according to claim 1, characterized in that, Determining the formation range of the surface carbon layer includes: The target region is determined based on the photoresist type of the photoresist layer. When the photoresist layer is positive, the target region is determined based on the region of the substrate where the wafer local processing is not performed. When the photoresist layer is negative, the target region is determined based on the region of the substrate where the wafer local processing is performed. Determine the exposure range of the photomask corresponding to the photoresist layer; The formation range is determined based on the exposure range and the target area, wherein the light-blocking area of the photomask and the formation range cover the target area; The exposure process performed on the photoresist layer to modify the photoresist within the exposure range that is not covered by the surface carbon layer includes: Align the photomask with the photoresist layer so that a portion of the photoresist layer is exposed through the photomask within the exposure area; The photoresist layer is exposed using the photomask so that the photoresist in the photoresist layer that is within the exposure range and is not covered by the surface carbon layer is exposed and modified.
4. The manufacturing method according to claim 1, characterized in that, Determining the formation range of the surface carbon layer includes: The target area is determined based on the photoresist type of the photoresist layer, and the target area is used as the formation range of the surface carbon layer. The exposure process performed on the photoresist layer to modify the photoresist within the exposure range that is not covered by the surface carbon layer includes: The photoresist layer is placed within the exposure range, and the exposure beam within the exposure range is blocked by the surface carbon layer, so that the photoresist not covered by the surface carbon layer is exposed and modified.
5. The manufacturing method according to claim 1, characterized in that, The semiconductor device includes a first wafer and a second wafer bonded together, and the manufacturing method includes: For a target wafer in the first wafer and the second wafer, at least one mask layer formation based on a surface carbon layer and a wafer local processing based on the mask layer are performed on the wafer edge region of the target wafer to form a bonding structure, wherein the surface of the substrate is configured as one side of the target wafer for bonding, the mask layer is formed based on positive photoresist, the surface carbon layer is formed in the wafer edge region, the wafer local processing includes a wafer etching process, and the bonding structure is formed outside the wafer edge region; The first wafer and the second wafer are bonded based on the bonding structure.
6. The manufacturing method according to claim 5, characterized in that, The bonding structure includes channel bonding trenches and surface bonding trenches. The wafer edge region based on the target wafer undergoes at least one mask layer formation based on a surface carbon layer and a local wafer processing based on the mask layer to form the bonding structure, including: The formation of the mask layer based on the surface carbon layer and the local wafer processing based on the mask layer are performed on the wafer edge region to form the channel bonding trench, wherein the channel bonding trench extends from the surface of the target wafer to the internal circuit of the target wafer, and the channel bonding trenches of different wafers are bonded to each other to form a conductive channel connecting the internal circuits of the two wafers. The formation of the mask layer based on the surface carbon layer and the local wafer processing based on the mask layer are performed on the wafer edge region to form the surface bonding trench, wherein the surface bonding trench is formed on the surface of the target wafer.
7. The manufacturing method according to claim 5, characterized in that, Before bonding the bonding structure, the edge region of the target wafer is subjected to an edge washing process.
8. The manufacturing method according to claim 5, characterized in that, The manufacturing method further includes: The target size of the edge region of the target wafer is determined based on the wafer size of the first wafer and the wafer size of the second wafer; Wherein, in response to the fact that the wafer sizes of the first wafer and the second wafer are different and the target wafer is the first target wafer, the target size of the wafer edge region of the target wafer is configured as the actual edge size; In response to the fact that the first wafer and the second wafer have different wafer sizes and the target wafer is the second target wafer, the target size of the wafer edge region of the target wafer is configured as the sum of the difference between the actual edge size and the wafer edge size, wherein the wafer size of the second target wafer is larger than that of the first target wafer.
9. A semiconductor device, characterized in that, The semiconductor device includes a first wafer and a second wafer, and a pair of bonding structures are disposed between the first wafer and the second wafer. The bonding structure is formed by the manufacturing method according to any one of claims 1 to 8 and forms a mask layer on the wafer edge region of the wafer, so that the bonding structure avoids the wafer edge regions of the first wafer and the second wafer during formation. The first wafer and the second wafer are bonded to each other through the bonding structure.