Instruction scheduling method and apparatus, storage medium, and electronic device

Abstract

The application discloses an instruction scheduling method and device, a storage medium and an electronic device. The instruction scheduling method comprises the following steps: obtaining a current instruction to be transmitted, and extracting at least one read-write address information from the current instruction; mapping the read-write address information into a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in the memory; obtaining a historical region bitmap of a historical instruction; performing a logical AND operation on the historical region bitmap and the current region bitmap, and judging whether the current instruction and the historical instruction have relevance according to the result; pausing the transmission of the current instruction when the current instruction and the historical instruction have relevance; and transmitting the current instruction when the current instruction and the historical instruction do not have relevance. The application can improve the efficiency of instruction scheduling.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of neural network, in particular to an instruction scheduling method and device, a storage medium and an electronic device. BACKGROUND

[0002] With the rapid development of artificial intelligence computing, neural processing unit (NPU) has become the core hardware for accelerating deep learning tasks. In order to improve the computing throughput, the current NPU generally adopts instruction-level parallelism technologies such as multi-issue and out-of-order execution. However, the correlation between instructions will restrict the improvement of parallelism: if the subsequent instruction needs to read the data that has not been written by the previous instruction, or write the data that has not been read by the previous instruction, it must be executed in order, otherwise it will cause calculation errors. Therefore, efficiently and accurately determining the correlation between instructions is a key prerequisite for implementing high-performance instruction scheduling.

[0003] Currently, the mainstream scheme for processing instruction correlation in neural network processors mainly relies on software and hardware cooperation. One is a software and hardware interrupt interaction scheme: the hardware triggers an interrupt after executing each instruction, notifying the software (compiler or driver) to analyze the correlation and schedule the next instruction. The other is a compiler static scheduling scheme: in the neural network compilation phase, the compiler uses a static analysis algorithm to pre-calculate the execution order and correlation of all instructions in the entire computation graph, and embeds these dependency information as metadata in the instruction stream. The hardware parses this metadata to determine the instruction issue order when executing.

[0004] However, the software and hardware interrupt interaction scheme introduces significant communication and scheduling delay. The hardware needs to wait for the software response after executing each instruction, resulting in frequent idle of the hardware computing unit and reduced utilization. The compiler static scheduling scheme, although reducing the runtime interrupt, greatly increases the design and optimization complexity of the compiler, and tightly couples the hardware execution logic with the static data generated at compile time, increasing the difficulty of software development and maintenance. Therefore, in order to implement the correlation determination between instructions, the current mainstream schemes all need to pay high software and hardware cooperation overhead or unacceptable hardware implementation cost, resulting in inefficient implementation of instruction scheduling. SUMMARY

[0005] Embodiments of the present application provide an instruction scheduling method, device, storage medium and electronic device, which can improve the efficiency of instruction scheduling.

[0006] In a first aspect, the embodiments of the present application provide an instruction scheduling method, comprising:

[0007] obtaining a current instruction to be issued, and extracting at least one read-write address information from the current instruction;

[0008] mapping the read-write address information into a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in the memory;

[0009] obtaining a history region bitmap of a history instruction;

[0010] performing a logical AND operation on the history region bitmap and the current region bitmap, and determining whether the current instruction and the history instruction have relevance according to a result;

[0011] when the current instruction and the history instruction have relevance, pausing transmission of the current instruction;

[0012] when the current instruction and the history instruction have no relevance, transmitting the current instruction.

[0013] In the instruction scheduling method provided in the embodiments of the present application, the mapping of the read-write address information into a corresponding current region bitmap comprises:

[0014] extracting a start address and a feature parameter of the read-write address information;

[0015] calculating an end address corresponding to the read-write address information according to the start address and the feature parameter, to determine a continuous address range;

[0016] determining a current region bitmap according to the continuous address range.

[0017] In the instruction scheduling method provided in the embodiments of the present application, the determining of the current region bitmap according to the continuous address range comprises:

[0018] determining a target region block covered by the continuous address range according to a size of the preset region block;

[0019] initializing a binary region bitmap, and setting a bit position corresponding to the target region block in the binary region bitmap to a first value, to generate the current region bitmap.

[0020] In the instruction scheduling method provided in the embodiments of the present application, when the current instruction contains a plurality of read-write address information, the initializing of the binary region bitmap and the setting of the bit position corresponding to the target region block in the binary region bitmap to the first value, to generate the current region bitmap, comprises:

[0021] initializing a plurality of binary region bitmaps, wherein the number of the binary region bitmaps is the same as the number of the read-write address information;

[0022] Setting a bit position corresponding to the target region block as a first value in each of the binary region bitmaps, to obtain a plurality of original bitmaps;

[0023] Performing a bitwise OR operation on the plurality of original bitmaps to generate a current region bitmap.

[0024] In the instruction scheduling method provided in the embodiments of the present application, the target region block covered by the continuous address range is determined according to the size of the preset region block, including:

[0025] Calculating the start block number of the continuous address range according to the size of the preset region block and the start address;

[0026] Calculating the end block number of the continuous address range according to the size of the preset region block and the end address;

[0027] Determining all region blocks from the start block number to the end block number as the target region block covered by the continuous address range.

[0028] In the instruction scheduling method provided in the embodiments of the present application, the history region bitmap includes a history write bitmap and a history read-write combined bitmap, and the current region bitmap includes a current read bitmap and a current write bitmap;

[0029] The logical AND operation of the history region bitmap and the current region bitmap is performed, and whether the current instruction and the history instruction have relevance is determined according to the result, including:

[0030] Performing a bitwise AND operation on the current read bitmap and the history write bitmap to obtain a first operation result;

[0031] Performing a bitwise AND operation on the current write bitmap and the history read-write combined bitmap to obtain a second operation result;

[0032] Determining whether the current instruction and the history instruction have relevance according to the first operation result and the second operation result.

[0033] In the instruction scheduling method provided in the embodiments of the present application, determining whether the current instruction and the history instruction have relevance according to the first operation result and the second operation result, including:

[0034] If the first operation result and the second operation result are both zero, it is determined that the current instruction and the history instruction do not have relevance;

[0035] If the first operation result and / or the second operation result is not zero, it is determined that the current instruction and the history instruction have relevance.

[0036] In a second aspect, an embodiment of the present application provides an instruction scheduling apparatus, comprising:

[0037] An instruction obtaining unit is configured to obtain a current instruction to be transmitted, and extract at least one read-write address information from the current instruction;

[0038] An information mapping unit is configured to map the read-write address information into a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in a memory;

[0039] A bitmap obtaining unit is configured to obtain a historical region bitmap of a historical instruction;

[0040] A logical operation unit is configured to perform a logical AND operation on the historical region bitmap and the current region bitmap, and determine whether the current instruction and the historical instruction have a correlation according to a result;

[0041] An instruction scheduling unit is configured to suspend transmission of the current instruction when the current instruction and the historical instruction have a correlation, and transmit the current instruction when the current instruction and the historical instruction do not have a correlation.

[0042] In a third aspect, the present application provides a storage medium, which stores a plurality of instructions, and the instructions are adapted to be loaded by a processor to execute the instruction scheduling method of any one of the above aspects.

[0043] In a fourth aspect, the present application provides an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the instruction scheduling method of any one of the above aspects when executing the computer program.

[0044] In summary, the instruction scheduling method provided by the embodiments of the present application comprises obtaining a current instruction to be transmitted, and extracting at least one read-write address information from the current instruction; mapping the read-write address information into a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in a memory; obtaining a historical region bitmap of a historical instruction; performing a logical AND operation on the historical region bitmap and the current region bitmap, and determining whether the current instruction and the historical instruction have a correlation according to a result; suspending transmission of the current instruction when the current instruction and the historical instruction have a correlation; and transmitting the current instruction when the current instruction and the historical instruction do not have a correlation. The embodiments of the present application can improve the efficiency of instruction scheduling. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can be obtained from these drawings without any creative effort.

[0046] Figure 1 is a schematic diagram of an application scenario of the instruction scheduling method provided by the embodiments of the present application.

[0047] Figure 2 is a schematic diagram of a flow of the instruction scheduling method provided by the embodiments of the present application.

[0048] Figure 3 is a schematic diagram of the structure of the instruction scheduling apparatus provided by the embodiments of the present application.

[0049] Figure 4 is a schematic diagram of the structure of the electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0050] The exemplary embodiments will be described in detail herein with reference to the drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0051] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements does not only include those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element. In addition, components, features, elements with the same name in different embodiments of the present application can have the same meaning or different meanings, and the specific meaning thereof should be determined in combination with the explanation thereof in the specific embodiment or further in combination with the context in the specific embodiment.

[0052] It should be understood that the specific embodiments described herein are merely used to explain the present application, and are not used to limit the present application.

[0053] In the following description, suffixes such as "module", "part", or "unit" used for an element are merely intended for facilitating the description of the present application, and are by no means specific thereto. Therefore, "module", "part", or "unit" can be mixedly used.

[0054] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are merely for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", and the like are only for the purpose of description and cannot be understood as indicating or implying relative importance.

[0055] Currently, the mainstream scheme for processing instruction correlation in a neural network processor mainly relies on software and hardware cooperation. One is a software and hardware interrupt interaction scheme: the hardware triggers an interrupt after executing each instruction, notifying the software (compiler or driver) to perform correlation analysis and schedule the next instruction. The other is a compiler static scheduling scheme: in the neural network compilation phase, the compiler calculates the execution order and correlation of all instructions in the entire computation graph in advance through static analysis algorithm, and embeds these dependency information as metadata in the instruction stream. The hardware parses this metadata to determine the instruction emission order when executing.

[0056] However, the software and hardware interrupt interaction scheme introduces significant communication and scheduling delay. The hardware needs to wait for the software response after executing each instruction, resulting in frequent idle of the hardware computing unit and reduced utilization. The compiler static scheduling scheme, although reducing the run-time interrupt, greatly increases the design and optimization complexity of the compiler, and tightly couples the hardware execution logic with the static data generated at the compilation time, increasing the difficulty of software development and maintenance. Therefore, in order to realize the correlation determination between instructions, the current mainstream schemes all need to pay high software and hardware cooperation overhead or unacceptable hardware implementation cost, resulting in inefficient implementation of instruction scheduling.

[0057] The embodiment of the application fundamentally avoids the multi-stage high-bit-width comparator logic which linearly grows with the judgment window and the number of operands in the traditional scheme by converting the complex high-bit-width address range comparison into a simple logical AND / OR operation on a fixed-length binary region bitmap. The hardware implementation of this method is extremely simple, only requiring basic logic units such as AND gates and OR gates, replacing the multi-stage high-bit-width comparator with huge area and power consumption, significantly reducing the complexity and area overhead of hardware design. At the same time, the logic path is short and regular, the critical path delay is small, and the timing is easy to converge, supporting a larger correlation judgment window and a higher clock frequency, so that the instruction-level parallel potential can be more fully tapped in the neural network processor supporting multiple emission and out-of-order execution, improving hardware utilization and overall performance.

[0058] Based on this, the embodiment of the application provides an instruction scheduling method and device, a storage medium and an electronic device. Specifically, the instruction scheduling device can be integrated in an electronic device, which can be a server or a terminal device. The terminal device can include a mobile phone, a wearable smart device, a tablet computer, a notebook computer, a personal computer (PC), and other computers and auxiliary devices. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0059] For example, as shown in Figure 1 The electronic device can obtain a current instruction to be emitted, and extract at least one read-write address information from the current instruction. The read-write address information is mapped to a corresponding current region bitmap, where the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in the memory. A history region bitmap of a history instruction is obtained. The history region bitmap and the current region bitmap are logically ANDed, and the result is used to determine whether the current instruction and the history instruction have correlation. When the current instruction and the history instruction have correlation, the current instruction is paused. When the current instruction and the history instruction do not have correlation, the current instruction is emitted.

[0060] The technical solutions shown in the application will be described in detail below through specific embodiments. It should be noted that the order of the following embodiments is not limited to the priority order of the embodiments.

[0061] Please refer to Figure 2 , Figure 2 is a flowchart of the instruction scheduling method provided by the embodiment of the application. The specific process of the instruction scheduling method can be as follows:

[0062] 101, obtain a current instruction to be emitted, and extract at least one read-write address information from the current instruction.

[0063] Specifically, a to-be-transmitted instruction can be selected from an instruction queue (e.g., a Reorder Buffer, ROB) or an instruction cache, and determined as a "current instruction". The instruction in the neural network processor is generally in an indefinite-length format, and its encoding includes an operation type, execution parameters, and access information of one or more operands (usually a Tensor). By decoding the current instruction, read-write address information corresponding to each operand can be extracted.

[0064] The read-write address information is a structured data unit. The read-write address information can include an access type, a start address, and feature parameters (such as a Tensor shape, a stride, and an element size).

[0065] The access type can indicate whether the operation is a read (Load) operation or a write (Store) operation. The start address is the start address (Start Address) of the operand (such as a Tensor) in the memory. The feature parameters can be used to determine the continuous address range occupied by the operand in the memory. In some embodiments, for a four-dimensional Tensor with a shape of (N, C, H, W), the feature parameters can include the dimensions (N, C, H, W) and the strides of the dimensions (Stride). Based on the start address and the feature parameters, the complete address distribution range of the Tensor in the memory can be calculated.

[0066] 102. mapping the read-write address information to a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit of the current region bitmap corresponds to a preset region block in the memory.

[0067] In this embodiment, a linear and continuous address range is abstracted into a fixed-length binary bitmap, so that a complex high-bit-width address comparison is converted into a subsequent extremely low-cost logical operation. That is, the current region bitmap is a binary number, and the total number of bits M is related to the preset memory management granularity (i.e., the size of the Region). Each bit (Bit) in the current region bitmap uniquely corresponds to a "preset region block" (hereinafter referred to as Region) in the memory. The Region is a fixed-size block obtained by equally dividing the memory, for example, each Region has a size of 4 KB or 64 KB. If a bit is set to "1" (i.e., a first value), it indicates that the current instruction accesses at least one address in the entire Region corresponding to the bit; if it is "0" (i.e., a second value), it indicates that it does not access any address in the Region.

[0068] In some embodiments, the step of "mapping the read-write address information to a corresponding current region bitmap" can include the following steps:

[0069] 1021、extract the start address and characteristic parameters of the read-write address information.

[0070] By parsing the read-write address, the start address and characteristic parameters thereof can be obtained.

[0071] 1022、calculate the end address corresponding to the read-write address information according to the start address and characteristic parameters, so as to determine the continuous address range.

[0072] For each extracted read-write address information, the corresponding end address (End Address) can be calculated according to the start address and characteristic parameters thereof, so as to determine the continuous address range occupied by the operand.

[0073] Firstly, the physical layout of the operand (usually a tensor) in the memory can be determined. The start address is the lowest memory address of the continuous address range. The characteristic parameters accurately describe the range and manner of the operand extending from the start address in the memory, which mainly includes dimension and layout information. By locating the address of the last element of the operand in the memory, the end address can be obtained.

[0074] According to the continuity of the memory layout, the calculation method of the end address can include the following two kinds:

[0075] The first kind is for the operand stored continuously in the memory (such as no padding, no interval, and close arrangement). The characteristic parameters usually include the dimension size and the byte size of each data element. The calculation of the end address can be directly based on the total data amount contained in the operand. First, multiply the dimension sizes to obtain the total number of elements contained in the operand. Then, multiply the total number of elements by the byte size of each element to obtain the total number of bytes occupied by the operand. Finally, add the total number of bytes to the start address and subtract one address unit (usually 1 byte) to obtain the end address. The principle is that the start address plus the total number of bytes points to an address after the last element, so 1 needs to be subtracted to obtain the actual address of the last element.

[0076] The second kind is for the operand stored non-continuously in the memory (such as with a step, padding, or specific data layout). The characteristic parameters need to additionally include the step information of each dimension in the memory (usually in bytes). At this time, the logical index of the last element in the operand (i.e., the maximum index value of each dimension) needs to be located. Then, the byte offset of the element relative to the start address is calculated: multiply the index value of each dimension by its corresponding step, and add the product results of all dimensions. The offset is the distance of the first byte of the last element relative to the start address. Finally, add the start address, offset, and element byte size, and subtract one address unit to obtain the accurate end address.

[0077] After obtaining the end address by any of the above methods, the start address and the end address jointly define a closed interval [start address, end address]. This interval explicitly defines the complete, continuous linear physical address range occupied by the operand.

[0078] 1023、According to the continuous address range, determine the current region bitmap.

[0079] First, according to the size of the preset region block, the target region block covered by the continuous address range can be determined.

[0080] In some embodiments, according to the size of the preset Region, the start address and the end address can be mapped to the corresponding Region number respectively. Specifically, the Region number (start block number) where the start address is located and the Region number (end block number) where the end address is located can be calculated by integer division operation (usually right shift operation). All regions from the start block number to the end block number are determined as the target region block covered by the read-write address information.

[0081] That is, the step of "determining the target region block covered by the continuous address range according to the size of the preset region block" can include: calculating the start block number of the continuous address range according to the size of the preset region block and the start address; calculating the end block number of the continuous address range according to the size of the preset region block and the end address; determining all region blocks from the start block number to the end block number as the target region block covered by the continuous address range.

[0082] Then, initialize the binary region bitmap, and set the bit position corresponding to the target region block to the first value in the binary region bitmap to generate the current region bitmap.

[0083] For each read-write address information, a binary number of M bits (all bits are 0 by default) can be initialized. The bitmap generation circuit can set the corresponding bit position to "1" according to the determined target region block, thereby generating an original bitmap representing the access range of a single operand. It can be understood that since a current instruction can include one or more read-write address information. Therefore, when the current instruction includes one read-write address information, the original bitmap is the current region bitmap.

[0084] When the current instruction includes multiple read-write address information, bitwise OR operation needs to be performed on several original bitmaps to generate the current region bitmap.

[0085] That is, when the current instruction contains multiple read-write address information, the step of "initializing a binary region bitmap and setting the bit position corresponding to the target region block in the binary region bitmap to the first value to generate a current region bitmap" can include: initializing a plurality of binary region bitmaps, the number of binary region bitmaps being the same as the number of read-write address information; setting the bit position corresponding to the target region block in each binary region bitmap to the first value respectively to obtain a plurality of original bitmaps; and performing a bitwise OR operation on the plurality of original bitmaps to generate a current region bitmap.

[0086] Specifically, a bitwise OR (OR) operation can be performed on the original bitmaps corresponding to all read operations in the current instruction to generate a current read bitmap. A bitwise OR operation can be performed on the original bitmaps corresponding to all write operations in the current instruction to generate a current write bitmap. The current read bitmap and the current write bitmap can jointly constitute a current region bitmap representing the complete memory access pattern of the current instruction.

[0087] 103. Obtain a history region bitmap of the history instruction.

[0088] The history instruction refers to an instruction that is located before the current instruction in program order and has not been executed. The executed instruction does not need to participate in the correlation judgment. In order to judge the correlation between the current instruction and all history instructions, a history region bitmap reflecting the cumulative view of the memory access state of the history instruction needs to be dynamically maintained.

[0089] In a specific hardware implementation, in order to accurately judge different types of data dependencies such as "write after read" (RAW), "read after write" (WAR), and "write after write" (WAW), the history region bitmap is embodied as two independent bitmaps maintained respectively: a history write bitmap and a history read-write combined bitmap. The history region bitmap is also constructed based on the granularity of a preset region block (Region), and its essence is a cumulative binary bitmap used to aggregate all memory regions declared to be accessed (including read and write) by the history instruction. Specifically:

[0090] ①History write bitmap: the history write bitmap can be accumulated by performing a bitwise OR (OR) operation on the history write bitmaps of all history instructions. It identifies the set of Regions that all history instructions plan to write. If any subsequent instruction reads data in these Regions, there is a "write after read" data dependency.

[0091] ②History Read-Write Bitmap: This history read-write bitmap is accumulated by performing a bitwise OR operation on the history read bitmap and the history write bitmap of each of all history instructions (to obtain the total access bitmap of a single instruction), and then performing a bitwise OR operation on the total access bitmap of all instructions. The history read-write bitmap identifies the set of Regions accessed (whether read or written) by all history instructions. If any subsequent instruction writes to these Regions, there can be a "read-before-write" or "write-before-write" data dependency.

[0092] In the implementation process, a dedicated history state register can be provided to store the two history bitmaps (i.e., the history write bitmap and the history read-write bitmap). It should be noted that the update mechanism of the history bitmap is independent of whether the current instruction is suspended from being issued due to the dependency. When a new instruction completes step 102, the bitmap information of the instruction is updated in real time into the history write bitmap and the history read-write bitmap through hardware logic circuit (mainly an OR gate network), regardless of whether the instruction is suspended from being issued due to the dependency check. This real-time update mechanism ensures that the history bitmap always contains the latest access state of all instructions that have entered the scheduling process but have not been completed.

[0093] To support the multi-issue and out-of-order execution capability of the NPU, multiple parallel issue queues and dependency judgment logics can be designed on the hardware. These parallel judgment logics share the same real-time updated history region bitmap (i.e., the history write bitmap and the history read-write bitmap). In each clock cycle, each issue queue independently queries the shared and latest history bitmap when judging whether the head instruction of the queue can be issued. Since the history bitmap is updated through a simple bitwise OR operation, the state of the history bitmap can be synchronized and refreshed in each clock cycle, thereby ensuring that the dependency judgment reference (i.e., the history bitmap) "seen" by all instructions to be issued is consistent and up-to-date in the same cycle.

[0094] This design enables the dependency judgment window to dynamically and continuously slide forward, with extremely low update overhead, which is the key to realizing large-window, low-latency dynamic scheduling, and is particularly suitable for neural network processors that require high instruction-level parallelism. Obtaining the history region bitmap is to read the latest history region bitmap from the history state register, which is used for comparison with the current region bitmap of the current instruction.

[0095] 104. performing a logical AND operation on the history region bitmap and the current region bitmap, and judging whether there is a dependency between the current instruction and the history instruction according to the result.

[0096] The history region bitmap includes a history write bitmap and a history read-write bitmap, and the current region bitmap includes a current read bitmap and a current write bitmap.

[0097] The embodiment can complete the correlation decision through a bitwise AND operation, thereby reducing hardware overhead. The rules of the correlation decision are based on the fundamental principle of data dependency:

[0098] 1) The read operation of the current instruction cannot occur before the write operation of the historical instruction (Read After Write, RAW);

[0099] 2) The write operation of the current instruction cannot occur before the read operation or the write operation of the historical instruction (Write After Read, WAR; Write After Write, WAW).

[0100] Specifically, the current read bitmap can be subjected to a bitwise AND operation with the historical write bitmap to obtain a first operation result; the current write bitmap can be subjected to a bitwise AND operation with the historical read-write combined bitmap to obtain a second operation result; and then the first operation result and the second operation result are used to determine whether the current instruction and the historical instruction have correlation.

[0101] It can be understood that when the first operation result is nonzero (that is, at least one bit is 1), it indicates that the data to be read by the current instruction is located in a Region that is about to be written by a historical instruction, and there is a true correlation of "write first and then read". When the second operation result is nonzero, it indicates that the region to be written by the current instruction overlaps with the Region that has been read or written by the historical instruction, that is, there is a true correlation of "read first and then write" (WAR) or "write first and then write" (WAW).

[0102] Therefore, if the first operation result and the second operation result are both zero, it is determined that the current instruction and the historical instruction do not have correlation; if the first operation result and / or the second operation result is nonzero, it is determined that the current instruction and the historical instruction have correlation.

[0103] It can be understood that the decision process only involves simple bit logic operations, and the path delay is extremely short, which is the key to realizing large-window and low-overhead dynamic scheduling.

[0104] 105、In the case where the current instruction and the historical instruction have correlation, the current instruction is suspended from being emitted; and in the case where the current instruction and the historical instruction do not have correlation, the current instruction is emitted.

[0105] Specifically, in a neural network processor supporting multiple emissions, there are usually multiple parallel scheduling queues. If there is correlation, the current instruction is suspended from being emitted, and is retained in the scheduling queue where the current instruction is located. The scheduler can continue to attempt to determine other instructions in the queue. If there is no correlation, the current instruction is immediately emitted and sent to a subsequent execution unit.

[0106] It should be noted that the plurality of scheduling queues are independent of each other, but share the same historical region bitmap (i.e. the historical write bitmap and the historical read-write combined bitmap). Each scheduling queue can independently query the shared historical bitmap according to the current region bitmap of the head instruction to be transmitted in each clock cycle to make a correlation judgment. When the instruction in a queue is determined to be irrelevant, the instruction can be transmitted from the queue.

[0107] Meanwhile, the historical region bitmap must be updated. That is, the current write bitmap of the current instruction is logically ORed with the historical write bitmap to update the historical write bitmap, and the current region bitmap of the current instruction is logically ORed with the historical region bitmap to update the historical region bitmap. In this way, the instructions in all subsequent scheduling queues will be compared with the updated unified historical bitmap when making a judgment in the next cycle, thereby ensuring the consistency of the global correlation problem judgment.

[0108] In some embodiments, in order to accurately reflect the access state of the historical instructions by the historical region bitmap, the bitmap information corresponding to the executed instructions needs to be retired and cleaned. The hardware maintains a completion flag for the bitmap information of each instruction. When the execution unit returns an instruction completion signal, the corresponding completion flag is set. When updating the historical bitmap (the historical write bitmap and the historical read-write combined bitmap), the hardware logic ignores the bitmap information corresponding to the instructions whose completion flags have been set, i.e. the completed bitmap is no longer involved in the logical OR operation. This retirement mechanism can be completed in the same clock cycle of updating the historical bitmap, ensuring that the historical bitmap is always accurate, thereby not affecting the correct transmission of subsequent instructions. According to the specific design, the system can support the retirement of the bitmap information of multiple completed instructions at the same time in a single cycle to maintain the efficiency and effectiveness of the correlation judgment window.

[0109] To sum up, the instruction scheduling method provided in the embodiments of the present application comprises: obtaining a current instruction to be transmitted, and extracting at least one read-write address information from the current instruction; mapping the read-write address information into a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in the memory; obtaining a historical region bitmap of a historical instruction; performing a logical AND operation on the historical region bitmap and the current region bitmap, and judging whether the current instruction and the historical instruction have relevance according to a result; when the current instruction and the historical instruction have relevance, pausing transmission of the current instruction; and when the current instruction and the historical instruction have no relevance, transmitting the current instruction. The embodiments of the present application convert complex high-bit-width address comparison into simple logical operation on a fixed-length binary bitmap, only basic logic units such as AND gates and OR gates are required, instead of a multi-stage high-bit-width comparator with huge area and power consumption, greatly reducing hardware overhead and design complexity. Moreover, the logical operation path is short and regular, the critical path delay is small, the timing is easy to converge, and higher clock frequency and larger relevance judgment window (i.e. more historical instructions can be considered at the same time) are supported. What is particularly key is that the present scheme perfectly adapts to a multi-transmission and out-of-order execution architecture: multiple parallel scheduling queues can share and quickly synchronize the same historical bitmap maintained through simple bit operation, and efficient and unified relevance judgment can be performed on all instructions to be transmitted in each clock cycle. This lightweight dynamic judgment mechanism based on bitmap has very significant advantages in reducing hardware complexity and area and optimizing timing path compared with the traditional scheme that requires a large number of address calculations and comparisons. In addition, the instruction scheduling method provided in the embodiments of the present application is completely judged by hardware, and the compiler does not need to perform complex static relevance analysis and embed metadata, thereby reducing software complexity and system coupling degree, and improving ease of use and debuggability. That is, the embodiments of the present application can improve the efficiency of instruction scheduling.

[0110] To better implement the instruction scheduling method provided in the embodiments of the present application, the embodiments of the present application further provide an instruction scheduling device. The meanings of the terms are the same as those in the above-mentioned instruction scheduling method, and the specific implementation details can be referred to the description in the method embodiment.

[0111] Please refer to Figure 3 , Figure 3 is a structural schematic diagram of the instruction scheduling device provided in the embodiments of the present application. The instruction scheduling device can comprise an instruction obtaining unit 201, an information mapping unit 202, a bitmap obtaining unit 203, a logical operation unit 204 and an instruction scheduling unit 205. Wherein,

[0112] The instruction obtaining unit 201 is configured to obtain a current instruction to be transmitted, and extract at least one read-write address information from the current instruction;

[0113] The information mapping unit 202 is configured to map the read-write address information into a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in the memory.

[0114] The bitmap obtaining unit 203 is configured to obtain a historical region bitmap of a historical instruction.

[0115] The logical operation unit 204 is configured to perform a logical AND operation on the historical region bitmap and the current region bitmap, and determine whether the current instruction and the historical instruction have a correlation according to a result.

[0116] The instruction scheduling unit 205 is configured to suspend transmitting the current instruction when the current instruction and the historical instruction have a correlation, and transmit the current instruction when the current instruction and the historical instruction do not have a correlation.

[0117] The specific implementation of each unit can refer to the above-mentioned embodiments of the instruction scheduling method, and will not be repeated here.

[0118] In summary, the instruction scheduling apparatus provided by the embodiments of the present application can obtain a current instruction to be transmitted by the instruction obtaining unit 201, and extract at least one read-write address information from the current instruction. The information mapping unit 202 maps the read-write address information into a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in the memory. The bitmap obtaining unit 203 obtains a historical region bitmap of a historical instruction. The logical operation unit 204 performs a logical AND operation on the historical region bitmap and the current region bitmap, and determines whether the current instruction and the historical instruction have a correlation according to a result. The instruction scheduling unit 205 suspends transmitting the current instruction when the current instruction and the historical instruction have a correlation, and transmits the current instruction when the current instruction and the historical instruction do not have a correlation. The embodiments of the present application can improve the efficiency of instruction scheduling.

[0119] The embodiments of the present application also provide an electronic device, which can integrate the instruction scheduling apparatus of the embodiments of the present application, as shown in FIG. Figure 4 The electronic device related to the embodiments of the present application is shown in FIG.

[0120] The electronic device can include a processor 301 with one or more processing cores and a memory 302 with one or more computer readable storage media, and the like. Those skilled in the art can understand that the structure of the electronic device shown in FIG. Figure 4 The electronic device structure shown in FIG. does not constitute a limitation on the electronic device, and can include more or fewer components than shown, or combine certain components, or different component arrangements. Among them:

[0121] The processor 301 is the control center of the electronic device, connects each part of the entire electronic device by various interfaces and lines, executes various functions of the electronic device and processes data by running or executing software programs and / or the present application stored in the memory 302, and calling data stored in the memory 302, thereby overall monitoring the electronic device. Optionally, the processor 301 can include one or more processing cores; preferably, the processor 301 can integrate an application processor and a modem processor, wherein the application processor mainly processes operation storage media, user interfaces and application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 301.

[0122] The memory 302 can be used to store software programs and the present application, and the processor 301 executes various function applications and data processing by running the software programs stored in the memory 302 and the present application. The memory 302 can mainly include a program storage area and a data storage area, wherein the program storage area can store application programs required by at least one function, etc.; the data storage area can store data created according to the use of the electronic device, etc. In addition, the memory 302 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state memory device. Accordingly, the memory 302 can also include a memory controller to provide access for the processor 301 to the memory 302.

[0123] Although not shown, the electronic device can also include a display unit, an input unit, a power supply, etc., which will not be described here. In particular, in the present embodiment, the processor 301 in the electronic device will load the executable file corresponding to the process of one or more application programs into the memory 302 according to the following instructions, and run the application programs stored in the memory 302 by the processor 301, thereby realizing various functions, as follows:

[0124] Obtain a current instruction to be transmitted, and extract at least one read-write address information from the current instruction;

[0125] Map the read-write address information to a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in the memory;

[0126] Obtain a history region bitmap of a history instruction;

[0127] Perform a logical AND operation on the history region bitmap and the current region bitmap, and determine whether the current instruction and the history instruction have relevance according to the result;

[0128] suspend transmitting the current instruction when the current instruction has the correlation with the history instruction;

[0129] transmit the current instruction when the current instruction has no correlation with the history instruction.

[0130] Those skilled in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by instructions, or by related hardware controlled by the instructions, which can be stored in a computer readable storage medium and loaded and executed by a processor.

[0131] To this end, an embodiment of the present application provides a storage medium, which stores a plurality of instructions capable of being loaded by a processor to execute steps in any of the methods provided by the embodiments of the present application. For example, the instructions can execute the following steps:

[0132] obtain a current instruction to be transmitted, and extract at least one read-write address information from the current instruction;

[0133] map the read-write address information to a corresponding current region bitmap, wherein the current region bitmap is a binary number, and each bit in the current region bitmap corresponds to a preset region block in the memory;

[0134] obtain a history region bitmap of a history instruction;

[0135] perform a logical AND operation on the history region bitmap and the current region bitmap, and determine whether the current instruction has the correlation with the history instruction according to a result;

[0136] suspend transmitting the current instruction when the current instruction has the correlation with the history instruction;

[0137] transmit the current instruction when the current instruction has no correlation with the history instruction.

[0138] The specific implementation of each operation can refer to the foregoing embodiments, which will not be described here.

[0139] The storage medium can include a read only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0140] Since the instructions stored in the storage medium can execute steps in any of the methods provided by the embodiments of the present application, the beneficial effects that can be achieved by any of the methods provided by the embodiments of the present application can be achieved, which will be described in detail in the foregoing embodiments, and will not be described here.

[0141] The instruction scheduling method and device, the storage medium and the electronic device provided by the present application are described in detail above, the principle and implementation manner of the present application are described by applying specific examples in the present article, and the above example is only used to help understand the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed, and the above description should not be understood as the limitation of the present application.

Claims

1. A method of instruction scheduling, characterized by, The method comprises the following steps: acquiring a current instruction to be transmitted, and extracting at least one read-write address information from the current instruction; mapping the read-write address information into a corresponding current region bitmap, wherein the current region bitmap is a binary number, each bit in the current region bitmap uniquely corresponds to a preset region block in the memory in a one-to-one manner, the preset region block is a fixed-size continuous region obtained by equally dividing the memory, the value of each bit is used to represent whether the corresponding preset region block is accessed by the current instruction, and the current region bitmap comprises a current read bitmap and a current write bitmap; acquiring a history region bitmap of a history instruction, wherein the history region bitmap comprises a history write bitmap and a history read-write combined bitmap; performing a bitwise AND operation on the current read bitmap and the history write bitmap to obtain a first operation result; performing a bitwise AND operation on the current write bitmap and the history read-write combined bitmap to obtain a second operation result; judging whether the current instruction and the history instruction have relevance according to the first operation result and the second operation result; suspending the transmission of the current instruction when the current instruction and the history instruction have relevance; and transmitting the current instruction when the current instruction and the history instruction do not have relevance.

2. The instruction scheduling method of claim 1, wherein, The step of mapping the read-write address information into a corresponding current region bitmap comprises the following steps: extracting a starting address and a feature parameter of the read-write address information; calculating an ending address corresponding to the read-write address information according to the starting address and the feature parameter to determine a continuous address range; determining a current region bitmap according to the continuous address range.

3. The instruction scheduling method of claim 2, wherein, The step of determining a target region block covered by the continuous address range according to the size of the preset region block comprises the following steps: initializing a binary region bitmap, and setting a bit position corresponding to the target region block in the binary region bitmap to a first value to generate a current region bitmap. When the current instruction comprises a plurality of read-write address information, the step of initializing a binary region bitmap and setting a bit position corresponding to the target region block in the binary region bitmap to a first value to generate a current region bitmap comprises the following steps:

4. The instruction scheduling method of claim 3, wherein, initializing a plurality of binary region bitmaps, wherein the number of the binary region bitmaps is the same as the number of the read-write address information; setting a bit position corresponding to the target region block in each binary region bitmap to a first value to obtain a plurality of original bitmaps; performing a bitwise OR operation on the plurality of original bitmaps to generate a current region bitmap. The step of determining a target region block covered by the continuous address range according to the size of the preset region block comprises the following steps:

5. The instruction scheduling method of claim 3, wherein, calculating a starting block number of the continuous address range according to the size of the preset region block and the starting address; calculating an ending block number of the continuous address range according to the size of the preset region block and the ending address; determining all region blocks from the starting block number to the ending block number as the target region block covered by the continuous address range. ​ 6. The method of claim 1, wherein, The determining whether the current instruction and the historical instruction have relevance comprises: If the first operation result and the second operation result are both zero, it is determined that the current instruction and the historical instruction do not have relevance. If the first operation result and / or the second operation result is not zero, it is determined that the current instruction and the historical instruction have relevance.

7. An instruction scheduling apparatus, characterized by comprising: The method comprises: An instruction obtaining unit is configured to obtain a current instruction to be transmitted, and extract at least one read-write address information from the current instruction; An information mapping unit is configured to map the read-write address information into a corresponding current region bitmap, wherein the current region bitmap is a binary number, each bit in the current region bitmap uniquely corresponds to a preset region block in the memory in a one-to-one manner, the preset region block is a fixed-size continuous region obtained by equally dividing the memory, and the value of each bit is used to represent whether the corresponding preset region block is accessed by the current instruction, the current region bitmap comprises a current read bitmap and a current write bitmap; A bitmap obtaining unit is configured to obtain a historical region bitmap of a historical instruction, the historical region bitmap comprises a historical write bitmap and a historical read-write combined bitmap; A logical operation unit is configured to perform a bitwise AND operation on the current read bitmap and the historical write bitmap to obtain a first operation result; perform a bitwise AND operation on the current write bitmap and the historical read-write combined bitmap to obtain a second operation result; determine whether the current instruction and the historical instruction have relevance according to the first operation result and the second operation result; An instruction scheduling unit is configured to pause transmission of the current instruction when the current instruction and the historical instruction have relevance, and transmit the current instruction when the current instruction and the historical instruction do not have relevance.

8. A storage medium, characterized by The storage medium stores a plurality of instructions, and the instructions are adapted to be loaded by the processor to execute the instruction scheduling method of any one of claims 1-6.

9. An electronic device, comprising: The computer program is stored in the memory and executable on the processor, and when the processor executes the computer program, the instruction scheduling method of any one of claims 1-6 is implemented.

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