9t-sram based dual bitline in-memory computing cell, circuit, chip

Abstract

The application discloses a 9T-SRAM-based dual-bit-line in-memory computing unit, circuit and chip, and relates to the technical field of SRAM circuit design. The 9T storage unit is designed for the highest 16 rows of multiplication and accumulation calculation of 2bit activation values and 1bit weights, two inverters are introduced to generate opposite control signals S and S' based on a single bit line; S and 2bit activation values are subjected to AND operation through corresponding AND gates, and S' and 2bit activation values are subjected to AND operation through corresponding AND gates, so as to control the input of 2bit activation values into the 9T storage unit to perform corresponding bit line discharge, thereby increasing the bit lines that can participate in discharge from only one bit line BL to two bit lines BL and BLB, and significantly improving the linearity; and S and S' also control the connection of the corresponding bit line to the 5-bit analog-to-digital converter through the output control part for low 5-bit quantization, and the state of S directly obtains the highest bit quantization value, so that the area and power consumption can be reduced by half.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of static random access memory (SRAM) circuit design, and more particularly, to: 1. a dual bit line in-memory computing unit based on 9T-SRAM; 2. a computing circuit constructed based on the dual bit line in-memory computing unit; 3. an in-memory computing chip based on the layout of the dual bit line in-memory computing unit or the dual bit line in-memory computing circuit. BACKGROUND

[0002] There are mainly two implementation ways for SRAM in-memory computing, namely digital way (i.e. digital CIM) and analog way (i.e. analog CIM).

[0003] Generally speaking, digital CIM has the advantages of high computing accuracy and strong anti-interference ability, but the multi-cycle operation limits the throughput, and the large-area hardware overhead reduces the density. Analog CIM uses the characteristics of analog computing and simple logic structure, and has a significant advantage in throughput and area density, but when multiple rows are opened in parallel, it not only leads to poor linearity, but also severely limits the discharge margin, and the quantization accuracy also deteriorates. Moreover, analog CIM needs to use an analog-to-digital converter (i.e. ADC) to quantize and read out the multiply-accumulate result, but a multi-bit analog-to-digital converter will bring large power consumption and area overhead.

[0004] Specifically, the following in-memory computing scenarios exist: up to 16 rows of multiply-accumulate computation are required, in which each row performs a multiplication computation of 2-bit active value and 1-bit weight. Then, the multiply-accumulate value of 16 rows in full parallel is up to 48, which not only needs a 6-bit analog-to-digital converter to output full precision, resulting in large power consumption and area overhead, but also if the multiply-accumulate result is always reflected on a single bit line, the discharge curve will gradually slow down, resulting in poor linearity and severely affecting the quantization accuracy. SUMMARY

[0005] Therefore, it is necessary to provide a dual bit line in-memory computing unit, circuit and chip based on 9T-SRAM to solve the problems of large power consumption and area overhead and poor quantization accuracy in the above in-memory computing specific scenarios.

[0006] The present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a dual bit line in-memory computing unit based on 9T-SRAM, comprising: 1 column of 16 9T storage units, 2 inverters INV1~INV2, 16 AND gates AND1[0]~AND1

[15] , 16 AND gates AND2[0]~AND2

[15] , and 1 output control unit OUT_Con.

[0008] Sixteen 9T memory cells share the same bit line BL and the same bit line BLB. The (k+1)th 9T memory cell includes: a 6T storage unit 6T-SRAM[k] and a 3T computing unit 3T-Cal[k]; the 6T-SRAM[k] is equipped with storage nodes Q[k] and QB[k], which are used to store 1 bit weight W[k]; the 3T-Cal[k] is equipped with two discharge paths, which are switched according to W[k], input signal RWL[k], and input signal RWLB[k]; k∈[0,15].

[0009] The input of INV1 is connected to BL, and the output is used to output the control signal S to characterize the 6th bit quantization result OUT. <5> The input terminal of INV2 is connected to S, and the output terminal is used to output the inverted signal S'. The flip voltage of INV1 is set to the bit line voltage corresponding to the multiplied cumulative value MAC=24.

[0010] AND1[k] has one input connected to S', another input connected to the 2-bit activation value INPUT[k], and an output used to output RWL[k].

[0011] AND2[k] has one input terminal connected to S, another input terminal connected to INPUT[k], and an output terminal used to output RWLB[k].

[0012] OUT_Con is used to: connect BL, BLB to the 5-bit analog-to-digital converter (ADC) to obtain the lower 5-bit quantization result OUT<4:0>; OUT_Con is controlled by S and S'; when S is 0 and S' is 1, BL is connected to the 5-bit ADC; when S is 1 and S' is 0, BLB is connected to the 5-bit ADC.

[0013] The implementation of this dual-bit in-memory computing unit based on 9T-SRAM is carried out according to the method or process of an embodiment of the present disclosure.

[0014] In a second aspect, the present invention discloses a dual-bit in-memory computing circuit based on 9T-SRAM, comprising: a plurality of dual-bit in-memory computing units based on 9T-SRAM as disclosed in the first aspect, which are arranged in columns.

[0015] The implementation of this dual-bit in-memory computing circuit based on 9T-SRAM is carried out according to the method or process of an embodiment of the present disclosure.

[0016] Thirdly, the present invention discloses a dual-bit in-memory computing chip based on 9T-SRAM, which adopts the circuit layout of the dual-bit in-memory computing unit based on 9T-SRAM disclosed in the first aspect, or the circuit layout of the dual-bit in-memory computing circuit based on 9T-SRAM disclosed in the second aspect.

[0017] The implementation of this dual-bit in-memory computing chip based on 9T-SRAM is carried out according to the method or process of embodiments of the present disclosure.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] This invention designs a 9T memory cell for the highest 16 rows of multiply-accumulate calculations using 2-bit activation values ​​and 1-bit weights. Two inverters are introduced to generate opposite control signals S and S' based on a single bit line. S and the 2-bit activation value are ANDed with corresponding AND gates, and S' and the 2-bit activation value are ANDed with corresponding AND gates to control the input of the 2-bit activation value to the 9T memory cell for corresponding bit line discharge. This increases the number of bit lines that can participate in the discharge from only bit line BL to two bit lines BL and BLB, reusing the discharge interval with the best linearity to significantly improve linearity. Furthermore, S and S' are used to control the corresponding bit lines to connect to a 5-bit analog-to-digital converter for low-5-bit quantization through the output control unit. The state of S directly obtains the highest-order quantized value, which can save one bit of analog-to-digital quantization and reduce the area and power consumption by half. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 The circuit diagram of the dual-bit in-memory computing unit based on 9T-SRAM provided in Embodiment 1 of the present invention;

[0022] Figure 2 for Figure 1 Circuit diagram of the 6T-SRAM[k] memory section;

[0023] Figure 3 for Figure 1 Circuit diagram of the output control unit OUT_Con;

[0024] Figure 4 This is a timing diagram of the signal used for multiply-accumulate calculation provided in Embodiment 1 of the present invention;

[0025] Figure 5 The discharge experiment curve provided in Embodiment 1 of the present invention;

[0026] Figure 6 This is a discharge difference curve provided in Embodiment 1 of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] Example 1

[0031] This embodiment 1 provides a dual-bit in-memory computing unit based on 9T-SRAM, which aims to achieve multiplication and accumulation calculation of up to 16 rows, and multiplication calculation of 2-bit activation value and 1-bit weight for each row.

[0032] First, it should be noted that since the 2-bit activation value has four possibilities: 00, 01, 10, and 11, and the 1-bit weight has two possibilities: 1 and 0, then when performing parallel computation on a maximum of 16 lines, the multiply-accumulate value (MAC) has a maximum of 48 possible results, i.e., MAC∈[1,48].

[0033] Experiments revealed that when discharging a single bit line, the discharge linearity is best from MAC 1 to 24. However, the discharge process from 24 to 48 gradually slows down, leading to a decrease in linearity. Therefore, based on these experimental results, this dual-bit-line in-memory computing unit based on 9T-SRAM chooses to increase the number of bit lines that can participate in the discharge by switching bit line discharges, thereby reusing the discharge interval with the best linearity to significantly improve linearity and save one bit of modulus quantization.

[0034] See Figure 1The dual-bit in-memory computing unit based on 9T-SRAM can be divided into the following functional areas: 1 storage and computing unit SRAM_Cal, 1 control signal generation unit Control, 1 input control unit IN_Con, and 1 output control unit OUT_Con.

[0035] The following will introduce them one by one:

[0036] 1. SRAM_Cal is used to: read and store 16 1-bit weights, and combine them with 2-bit activation values ​​to perform multiplication calculations in single-row calculations and multiply-accumulate calculations in parallel calculations.

[0037] See Figure 1 SRAM_Cal includes: 1 column of 16 9T memory cells, which share the same bit line BL and the same bit line BLB.

[0038] The structure of each 9T memory cell is the same. Taking the (k+1)th 9T memory cell as an example, it includes: a 6T storage section (6T-SRAM[k]) and a 3T computation section (3T-Cal[k]); k∈[0,15].

[0039] First refer to Figure 2 6T-SRAM[k] is a conventional 6T memory cell, which includes: 2 PMOS transistors P1[k]~P2[k] and 4 NMOS transistors N1[k]~N4[k].

[0040] Specifically, P1[k] and N1[k] form one inverter, and P2[k] and N2[k] form another inverter. The two inverters are cross-coupled to form memory nodes Q[k] and QB[k]. QB[k] is connected to bit line BL through N3, and Q[k] is connected to bit line BLB through N4[k]. The gates of N3[k] and N4[k] are connected to word line WL[k]. The sources of P1[k] and P2[k] are connected to power supply VDD. The sources of N1[k] and N2[k] are connected to GND.

[0041] In other words, the 6T-SRAM[k] is configured with storage nodes Q[k] and QB[k] to store 1 bit weight W[k]. Specifically, if Q[k]=1 and QB[k]=0, then W[k]=1; if Q[k]=0 and QB[k]=1, then W[k]=0.

[0042] When WL[k]=1, the 6T-SRAM[k] performs reads and writes of W[k]; when WL[k]=0, the 6T-SRAM[k] holds W[k]. For specific read / write and hold operations, refer to the operation of a regular 6T memory cell; these details will not be elaborated here.

[0043] See again Figure 13T-Cal[k] includes: 3 NMOS transistors N5[k]~N7[k].

[0044] Specifically, the gate of N7[k] is connected to Q[k], and the drain is connected to the source of N5[k] and the source of N6[k]. The source is grounded to GND. The gate of N5[k] is connected to the input signal RWL[k], and the drain is connected to BL. The gate of N6[k] is connected to the input signal RWLB[k], and the drain is connected to BLB.

[0045] N7[k] and N5[k] constitute the discharge path of BL to GND; N7[k] and N6[k] constitute the discharge path of BLB to GND.

[0046] When RWL[k]=1 and W[k]=1, N7[k] and N5[k] are both turned on, thus enabling BL to discharge to GND; when RWLB[k]=1 and W[k]=1, N6[k] and N5[k] are both turned on, thus enabling BLB to discharge to GND.

[0047] In other words, 3T-Cal[k] has two discharge paths, which are switched according to W[k], RWL[k], and RWLB[k], so that the corresponding bit line is discharged for the corresponding duration to represent the multiplication result of 2-bit activation value and 1-bit weight.

[0048] 2. Control is used to generate two opposite control signals S and S' based on the voltage of BL.

[0049] See Figure 1 The control includes two inverters, INV1 and INV2.

[0050] Specifically, the input terminal of INV1 is connected to BL, and its output terminal is used to output the control signal S. The input terminal of INV2 is connected to S, and its output terminal is used to output the inverted signal S'.

[0051] It is important to note that since subsequent bit line discharge switching will be involved, the flip voltage of INV1 should be set to the bit line voltage corresponding to the accumulated value MAC=24. This ensures that the bit line discharge is always within the range with the best linearity.

[0052] 3. IN_Con is used to: control the 2-bit activation value input storage and calculation unit according to S and S', and realize bit line discharge switching to ensure that the discharge is in the range with the best linearity, and save one bit of modulus quantization.

[0053] See Figure 1 IN_Con includes: 16 AND gates AND1[0]~AND1

[15] and 16 AND gates AND2[0]~AND2

[15] .

[0054] Specifically, AND1[k] has one input connected to S', another input connected to the 2-bit activation value INPUT[k], and its output is used to output RWL[k]. AND2[k] has one input connected to S, another input connected to INPUT[k], and its output is used to output RWLB[k].

[0055] In other words, RWL[k] and RWLB[k] serve as the two inputs of 3T-Cal[k]. When only S is 1, INPUT[k] will be directly used as the input of RWLB[k]; when only S is 1, INPUT[k] will be directly used as the input of RWL[k]. Thus, by controlling the levels of RWL[k] and RWLB[k] through an AND operation, bit line discharge switching is achieved.

[0056] It should be noted that since multiplication is characterized based on bit line discharge, it is recommended to use pulse width encoding for INPUT[k] to form the input signal, so as to control the on-time of N5[k] or N6[k].

[0057] Specifically, when INPUT[k] is 00, it is a low-level signal without pulses;

[0058] When INPUT[k] is 0 or 1, it is a pulse signal with a pulse width of t;

[0059] When INPUT[k] is 10, it is a pulse signal with a pulse width of 2t;

[0060] When INPUT[k] is 11, it is a pulse signal with a pulse width of 3t.

[0061] Where t represents the pulse width unit duration.

[0062] 4. OUT_Con is used to connect BL, BLB to the 5-bit analog-to-digital converter 5bit_ADC to obtain the lower 5-bit quantization result OUT<4:0>.

[0063] OUT_Con switches the connected object according to S and S' to perform the corresponding low 5-bit quantization. OUT_Con is controlled by S and S'; when S is 0 and S' is 1, BL is connected to the 5-bit ADC; when S is 1 and S' is 0, BLB is connected to the 5-bit ADC.

[0064] See Figure 3 OUT_Con can be designed using transmission gates, which include two transmission gates, Gate1 and Gate2. Gate1's control terminal is connected to S', its inverse control terminal is connected to S, its input is connected to BL, and its output is connected to the 5-bit ADC. Gate2's control terminal is connected to S, its inverse control terminal is connected to S', its input is connected to BLB, and its output is connected to the 5-bit ADC.

[0065] Specifically, Gate1 includes: one PMOS transistor PM1 and one NMOS transistor NM1; the gate of PM1 serves as the inverted control terminal; the gate of NM1 serves as the control terminal; the source of PM1 is connected to the drain of NM1 and serves as the input terminal; the drain of PM1 is connected to the source of NM1 and serves as the output terminal.

[0066] Gate2 includes: two PMOS transistors PM2 and two NMOS transistors NM2; the gate of PM2 serves as the inverse control terminal; the gate of NM2 serves as the control terminal; the source of PM2 is connected to the drain of NM2 and serves as the input terminal; the drain of PM2 is connected to the source of NM2 and serves as the output terminal.

[0067] Of course, OUT_Con can also use a selector or other switch design, as long as the above-mentioned turn-on and turn-off logic is satisfied.

[0068] In summary, the computation and quantization process of the dual-bit in-memory computing unit based on the above structure is as follows:

[0069] BL and BLB are initially pre-charged to VDD, S is initialized to 0, and S' is initialized to 1;

[0070] Based on actual needs, several 9T memory cells are selected for calculation. The corresponding 2-bit activation value is input through pulse width encoding and ANDed with S and S' respectively before being input from the 3T calculation unit, so that BL discharges first. For ease of understanding, take the (k+1)th 9T memory cell participating in the multiplication calculation as an example: INPUT[k] is ANDed with S and S' respectively; since S' is 1 at this time, RWLB[k]=0, RWL[k]=INPUT[k]; then N6[k] is turned off, N5[k] is turned on (when INPUT[k] is 01, 10, 11); N7[k] is turned on (when W[k]=1), BL discharges first, and BLB does not discharge.

[0071] Several 9T memory cells involved in the calculation cause BL to discharge to GND, and the voltage of BL continuously decreases. Since BL starts discharging from VDD, the discharge process is in the region with the best linearity.

[0072] If the multiply-accumulate value MAC does not reach 24, the entire multiply-accumulate result is reflected in BL, indicating that the 6th bit quantization result is OUT. <5> =0 (because the 6th bit of the binary number corresponding to MAC [1,24] must be 0), at this time INV1 does not toggle (because the BL voltage is lower than the INV1 toggle voltage), S remains 0, S' remains 1, the 5-bit ADC turns on BL and quantizes the voltage of BL to obtain the lower 5-bit quantization result OUT<4:0>. Therefore, OUT <5> =0, OUT<4:0> form a 6-bit quantization result OUT<5:0>. It can be seen that in this case, S and OUT... <5> The values ​​should remain consistent.

[0073] When MAC exceeds 24, if discharge continues on BL, it will enter a region with poor linearity. In this case, INV1 flips (because the BL voltage reaches the flip voltage of INV1), S switches to 1, and S' switches to 0, causing BL to stop discharging and BLB to start discharging immediately. For ease of understanding, let's take the (k+1)th 9T memory cell participating in the multiplication calculation as an example: Since S' switches to 0, RWLB[k] = INPUT[k] and RWL[k] = 0; then N6[k] is turned on and N5[k] is turned off (when INPUT[k] is 0, 10, or 11); N7[k] is turned on (when W[k] = 1), BL stops discharging, and BLB to start discharging immediately.

[0074] Several 9T memory cells involved in the calculation cause the BLB to discharge to GND, and the voltage of the BLB continuously decreases. Similarly, since the BLB also starts discharging from VDD, the discharge process is also in the region with the best linearity. Since both BL and BLB have discharged, it means that the 6th bit of the binary number corresponding to MAC must be 1, that is, the quantization result of the 6th bit is OUT. <5> =1. When S is switched to 1 and S' is switched to 0, the 5-bit ADC is activated by the BLB, and the voltage of the BLB is quantized to obtain the lower 5-bit quantization result OUT<4:0>. Therefore, OUT... <5> =1, OUT<4:0> form a 6-bit quantized result OUT<5:0>. It can be seen that in this case, S and OUT... <5> The value remains unchanged.

[0075] In other words, the 6th quantization result OUT is directly represented by S. <5> Since the 6th bit does not need to be quantized, this dual-bit in-memory computing unit based on 9T-SRAM only requires a 5-bit ADC to complete the quantization, reducing the area and power consumption by half.

[0076] In addition, see Figure 4 This embodiment 1 provides a signal timing diagram for multiply-accumulate calculation, which gives a specific example of 16-line fully parallel calculation.

[0077] To quantify the performance of the dual-bit line-of-memory computing unit based on 9T-SRAM, this embodiment 1 also underwent experimental simulation, comparing the traditional single-line discharge with the aforementioned dual-bit line discharge design. The results are shown in [reference needed]. Figure 5 , Figure 6 .

[0078] See Figure 5 This demonstrates the difference in discharge curves between single-line discharge and two-line discharge. (By...) Figure 4 It can be seen that when using unit line discharge (i.e., continuous BL discharge): in the initial stage of discharge, the linearity k is 14.72 (i.e., the ratio of the voltage difference of BL from 805.77mV to 732.16mV to the corresponding time) and remains stable; however, as the discharge continues, the discharge curve gradually slows down (i.e., deviates from the linearity). Figure 4 (The slope reference line in the diagram); towards the end of the discharge, the linearity k drops to 8.22 (i.e., the ratio of the voltage difference of BL from 233.60mV to 192.50mV to the corresponding time), meaning the linearity deteriorates. However, when using dual-line discharge: BL discharges first and remains within the range with the best linearity; when BL stops discharging, BLB immediately begins discharging and reuses the range with the best linearity.

[0079] See Figure 6 The integral nonlinear processing of the potential line voltage aims to demonstrate the difference in discharge values ​​between single-line discharge and double-line discharge. Figure 6 It can be seen that when using single-line discharge (i.e., BL continuously discharges), the integral nonlinearity also shows an increasing trend with the increase of MAC, reaching a maximum value of 9.76 LSB; while when using dual-line discharge, the maximum value of the integral nonlinearity of BL is only 1.64 LSB - 8.12 LSB less than 9.76 LSB, a reduction of 83.2%, and the maximum value of the integral nonlinearity of BLB is only 1.16 LSB - 8.60 LSB less than 9.76 LSB, a reduction of 88.11%. This also shows that the dual-line in-memory computing unit based on 9T-SRAM significantly improves linearity.

[0080] Example 2

[0081] Considering the array application of SRAM, this embodiment 2 provides a dual-bit in-memory computing circuit based on 9T-SRAM, which includes: a plurality of dual-bit in-memory computing units based on 9T-SRAM as disclosed in embodiment 1, which are arranged in columns. Among them, 9T memory cells in the same row share the same word line WL - specifically, 9T memory cells in the (k+1)th row share WL[k].

[0082] Of course, these dual-line in-memory computing units based on 9T-SRAM can also share the same 5-bit ADC. However, in order to ensure that the 5-bit ADC can be properly quantized, additional selectors or switches need to be set for the dual-line in-memory computing units and the 5-bit ADC to control that only the multiplication and accumulation results of a single column are input to the 5-bit ADC.

[0083] Example 3

[0084] This embodiment 3 also discloses a dual-bit in-memory computing chip based on 9T-SRAM, which adopts the circuit layout of the dual-bit in-memory computing unit based on 9T-SRAM disclosed in embodiment 1, or the circuit layout of the single-channel dual-bit in-memory computing based on 9T-SRAM disclosed in embodiment 1. The chip-packaged approach facilitates the promotion and application of the aforementioned circuit.

[0085] Of course, the above-mentioned dual-bit in-memory computing unit and circuit based on 9T-SRAM can also be designed as a module—if designed as a module, the corresponding pins can be designed as terminals.

[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A dual-bit in-memory computing unit based on 9T-SRAM, characterized in that, It includes: One column contains 16 9T memory cells, which share the same bit line BL and the same bit line BLB; The (k+1)th 9T memory cell includes: a 6T storage unit (6T-SRAM[k]) and a 3T computing unit (3T-Cal[k]); the 6T-SRAM[k] is equipped with storage nodes Q[k] and QB[k], which are used to store 1 bit weight W[k]; the 3T-Cal[k] is equipped with two discharge paths, which are switched according to W[k], input signal RWL[k], and input signal RWLB[k]; k∈[0,15]; Two inverters, INV1 and INV2; the input of INV1 is connected to BL, and its output is used to output the control signal S to represent the 6th bit quantization result OUT. <5> The input of INV2 is connected to S, and the output is used to output the inverted signal S'. The flip voltage of INV1 is set to the bit line voltage corresponding to the multiplied cumulative value MAC=24. 16 AND gates AND1[0]~AND1[15]; one input of AND1[k] is connected to S', the other input is connected to the 2-bit activation value INPUT[k], and the output is used to output RWL[k]; 16 AND gates AND2[0]~AND2[15]; one input of AND2[k] is connected to S, the other input is connected to INPUT[k], and the output is used to output RWLB[k]; and One output control unit OUT_Con is used to: connect BL, BLB to the 5-bit analog-to-digital converter (ADC) to obtain the lower 5-bit quantization result OUT<4:0>; OUT_Con is controlled by S and S'; when S is 0 and S' is 1, BL is connected to the 5-bit ADC; when S is 1 and S' is 0, BLB is connected to the 5-bit ADC.

2. The dual-bit in-memory computing unit based on 9T-SRAM according to claim 1, characterized in that, When INPUT[k] is 00, it is a low-level signal without pulses; When INPUT[k] is 0 or 1, it is a pulse signal with a pulse width of t; When INPUT[k] is 10, it is a pulse signal with a pulse width of 2t; When INPUT[k] is 11, it is a pulse signal with a pulse width of 3t; Where t represents the pulse width unit duration.

3. The dual-bit in-memory computing unit based on 9T-SRAM according to claim 1, characterized in that, The 6T-SRAM[k] includes: 2 PMOS transistors P1[k]~P2[k] and 4 NMOS transistors N1[k]~N4[k]; P1[k] and N1[k] form one inverter, and P2[k] and N2[k] form another inverter. The two inverters are cross-coupled to form memory nodes Q[k] and QB[k]. QB[k] is connected to bit line BL through N3, and Q[k] is connected to bit line BLB through N4[k]. The gates of N3[k] and N4[k] are connected to word line WL[k]. The sources of P1[k] and P2[k] are connected to power supply VDD. The sources of N1[k] and N2[k] are connected to GND.

4. The dual-bit in-memory computing unit based on 9T-SRAM according to claim 3, characterized in that, When WL[k]=1, 6T-SRAM[k] performs read and write operations on W[k]; when WL[k]=0, 6T-SRAM[k] holds W[k].

5. The dual-bit in-memory computing unit based on 9T-SRAM according to claim 1, characterized in that, 3T-Cal[k] includes: 3 NMOS transistors N5[k]~N7[k]; The gate of N7[k] is connected to Q[k], and the drain is connected to the source of N5[k] and the source of N6[k]. The source is grounded to GND. The gate of N5[k] is connected to the input signal RWL[k], and the drain is connected to BL. The gate of N6[k] is connected to the input signal RWLB[k], and the drain is connected to BLB. N7[k] and N5[k] constitute the discharge path of BL to GND; N7[k] and N6[k] constitute the discharge path of BLB to GND.

6. The dual-bit in-memory computing unit based on 9T-SRAM according to claim 1, characterized in that, OUT_Con includes: two transmission gates, Gate1 and Gate2; The C control terminal of Gate1 is connected to S', the C inverse control terminal is connected to S, the input terminal is connected to BL, and the output terminal is connected to the 5-bit ADC; the C control terminal of Gate2 is connected to S, the C inverse control terminal is connected to S', the input terminal is connected to BLB, and the output terminal is connected to the 5-bit ADC.

7. The dual-bit in-memory computing unit based on 9T-SRAM according to claim 6, characterized in that, Gate1 includes: One PMOS transistor PM1 and one NMOS transistor NM1; the gate of PM1 is used as the inverted collector control terminal; the gate of NM1 is used as the collector control terminal; the source of PM1 and the drain of NM1 are connected together and used as the input terminal; the drain of PM1 and the source of NM1 are connected together and used as the output terminal. Gate2 includes: two PMOS transistors PM2 and two NMOS transistors NM2; the gate of PM2 serves as the inverse control terminal; the gate of NM2 serves as the control terminal; the source of PM2 is connected to the drain of NM2 and serves as the input terminal; the drain of PM2 is connected to the source of NM2 and serves as the output terminal.

8. The dual-bit in-memory computing unit based on 9T-SRAM according to claim 1, characterized in that, When performing the calculation, S is initially set to 0, and BL discharges first; If MAC does not reach 24, S remains 0, the multiplication and accumulation results are all reflected in BL, and the 6th bit quantization result is OUT. <5> =0, the 5-bit ADC quantizes the voltage of BL to obtain the lower 5-bit quantization result OUT<4:0>, OUT <5> =0 and OUT<4:0> together form a 6-bit quantization result OUT<5:0>; When MAC exceeds 24, S switches to 1, BL stops discharging, BLB then starts discharging, and the 6th bit quantization result is OUT. <5> =1, the 5-bit ADC quantizes the voltage of the BLB to obtain the lower 5-bit quantization result OUT<4:0>; OUT <5> =1, OUT<4:0> form a 6-bit quantization result OUT<5:0>.

9. A dual-bit in-memory computing circuit based on 9T-SRAM, characterized in that, It includes: Several dual-bit in-memory computing units based on 9T-SRAM as described in any one of claims 1-8 are arranged in columns.

10. A dual-bit in-memory computing chip based on 9T-SRAM, characterized in that, The circuit layout of the dual-bit in-memory computing unit based on 9T-SRAM as described in any one of claims 1-8, or the circuit layout of the dual-bit in-memory computing circuit based on 9T-SRAM as described in claim 9, is adopted.

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