Methods, systems, and equipment for solving polysilicon flatness in digital layout design

Abstract

This invention discloses a method, system, and device for solving polysilicon flatness in digital layout design, relating to the field of integrated circuit design technology. The method includes: after placing circuit devices in the initial layout design stage and before routing, performing a density check of the circuit device area, and partitioning the layout based on the cluster density and type of the circuit devices; calling an adjustment module from a database to adjust the polysilicon flatness in the layout, wherein the adjustment module includes: a density improvement module, a closure module, and a polysilicon filling module; connecting signal lines and power supplies to the adjusted layout, adding virtual metal to meet the metal layer density requirements, and obtaining a layout design to be verified; and performing design rule verification on the layout design to be verified. This invention solves the problem of polysilicon density uniformity, making the manufacturing environment more favorable during chemical mechanical polishing and improving the yield rate during chip mass production.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and specifically to a method, system, and device for solving polysilicon flatness in digital layout design. Background Technology

[0002] During the chip design process, refer to Figure 1 The traditional approach involves completing the layout design, then verifying the density of each area in the design drawing using design rules to ensure it meets requirements. Based on the verification results, areas that do not meet the requirements are added or modified. Once the layout design is revised, the design rules verification is performed again. This process of modification and verification needs to be repeated until the design rules verification is error-free.

[0003] With the continuous development of integrated circuits, people have increasingly higher requirements for chip performance, leading to greater circuit complexity. Simultaneously, following Moore's Law, integrated circuit manufacturing technology is developing at a rate of doubling integration density every two years, resulting in increasingly smaller feature sizes for circuit devices. This necessitates a greater number of metal interconnects that can pass through the same area, causing the minimum linewidth and minimum spacing of these interconnects to continuously shrink. To avoid reducing yield, the flatness of the manufacturing layer should not only focus on the back-end of line (BEOL) manufacturing; the front-end of line (FEOL) also deserves attention and has a greater impact. This is because the front-end is the "foundation" of the back-end; unevenness in the front-end manufacturing will not stop there, but will propagate upwards like dominoes, affecting the entire three-dimensional structure of the chip. Summary of the Invention

[0004] This invention addresses the issue of unevenness in FEOL manufacturing affecting the three-dimensional structure of the entire chip. It provides a method, system, and equipment for solving the problem of polysilicon flatness in digital layout design, achieving uniform polysilicon density, creating a more favorable manufacturing environment during chemical mechanical polishing, and improving the yield rate during chip mass production.

[0005] The present invention is achieved through the following technical solution.

[0006] In a first aspect, a method for solving polysilicon flatness in digital model layout design is provided, the method comprising:

[0007] After placing circuit devices in the early stages of layout design and before routing, a circuit device area density check is performed, and the layout is partitioned based on the cluster density and type of the circuit devices.

[0008] The adjustment module in the database is invoked to adjust the flatness of the polysilicon in the layout. The adjustment module includes: a density improvement module, a closure module, and a polysilicon filling module.

[0009] Connect signal lines and power supplies to the adjusted layout, add virtual metals to meet the metal layer density requirements, and obtain the layout design to be verified.

[0010] The design rules of the layout design to be verified are verified.

[0011] In some embodiments, after placing circuit devices in the early stages of layout design and before routing, a circuit device area density check is performed, and the layout is partitioned based on the cluster density and type of the circuit devices, including:

[0012] The density of the circuit device clusters in the layout after the circuit devices are placed is checked to ensure that the polysilicon density of all circuit device clusters is within the industry density requirement range.

[0013] Extract the type and density of each circuit device cluster to obtain density differentiation and type differentiation. The density differentiation includes: high-density area, low-density area, and blank area. The type differentiation includes: N-type transistor, P-type transistor, resistor, and capacitor.

[0014] In some embodiments, the density improvement module is an isolation ring space disposed between the cluster of circuit devices and the blank area to adjust the density around the cluster of circuit devices.

[0015] In some embodiments, the density improvement module includes a first-direction density improvement module and a second-direction density improvement module, wherein the first direction is perpendicular to the second direction, the first-direction density improvement module is used to configure the density in the first direction, and the second-direction density improvement module is used to configure the density in the second direction.

[0016] The configuration of the first directional density or the second directional density includes:

[0017] Determine 55%, the midpoint of the industry density requirement range, as a benchmark;

[0018] The density of the improved density module is set as: m = (M-55) / 2 + 55, where M represents the polysilicon integration density and 55 is determined based on a baseline of 55%.

[0019] The polysilicon height of the first-direction density improvement module is set to be the same as the polysilicon height of the circuit devices in the target circuit device cluster. Based on the density of the density improvement module, the polysilicon height, the minimum width of the isolation ring, and the pitch in the second direction, the width of the first-direction density improvement module is calculated using the following formula:

[0020] ;

[0021] Where H represents the pitch in the second direction; h represents the height of the polysilicon; and a represents the minimum width of the isolation ring.

[0022] The polysilicon width of the second-direction density improvement module is set to be the same as the polysilicon width of the circuit devices in the target circuit device cluster. Based on the density of the density improvement module, the polysilicon width, the minimum width of the isolation ring, and the pitch in the first direction, the width of the second-direction density improvement module is calculated using the following formula:

[0023] ;

[0024] Where w represents the width of the polysilicon; V represents the pitch in the first direction.

[0025] In some embodiments, the closing module is used to fill the gaps between the density improvement modules, in order to close the area where the density improvement modules are located, while meeting design rule requirements.

[0026] In some embodiments, the closure module includes: a module for improving the physical verification spacing between density modules and a module for improving the corner closure of density modules.

[0027] The physical verification spacing module between the density improvement modules is set along a first direction and a second direction to fill the gap between the density improvement modules, wherein the first direction is perpendicular to the second direction.

[0028] The improved density module corner closure module is located at the corner of the improved density module and the physical verification spacing module between the improved density module, and is used to surround and close the target circuit device cluster.

[0029] In some embodiments, the polysilicon filling module includes a void filling module for filling the void area with polysilicon, wherein the polysilicon density of the void filling module is 55%.

[0030] In some embodiments, if there is an error in the layout design to be verified, the cluster of circuit devices is fine-tuned. Specifically, if the polysilicon density of the density improvement module and the polysilicon density of the blank area are greater than a first threshold, the polysilicon density of the empty filling module in the blank area is increased or decreased to perform gradient buffering.

[0031] Secondly, a system for solving polysilicon flatness in digital layout design is provided, the system comprising:

[0032] The circuit device area density checking unit is used to: check the circuit device area density after placing the circuit devices in the early stage of layout design and before routing, and partition the layout based on the cluster density and type of the circuit devices.

[0033] A polysilicon flatness adjustment unit is used to: call an adjustment module in the database to adjust the flatness of the polysilicon in the layout, wherein the adjustment module includes: a density improvement module, a closure module, and a polysilicon filling module;

[0034] The signal line and power connection unit is used to: connect the signal lines and power to the adjusted layout, supplement virtual metal to meet the metal layer density requirements, and obtain the layout design to be verified.

[0035] The design rule verification unit is used to: perform design rule verification on the layout design drawing to be verified.

[0036] Thirdly, a device is provided for solving polysilicon flatness in digital layout design, the device comprising:

[0037] At least one processor;

[0038] At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions implementing the method described in any of the above when executed by the at least one processor.

[0039] Compared with the prior art, the present invention has the following advantages and beneficial effects: the flat and uniform polycrystalline silicon layer makes it possible to...

[0040] 1) Consistent transistor electrical performance on the chip is achieved: The threshold voltage (Vt) of a transistor is the critical voltage at which it turns on, and Vt is mainly determined by the gate oxide thickness and channel doping.

[0041] 2) Improved product yield: ensured photolithography imaging accuracy and achieved uniform etching;

[0042] 3) Enhanced device reliability: The flat and uniform polysilicon layer enables the gate oxide to withstand a uniform electric field, significantly improving the long-term reliability and long-term operational stability of the product.

[0043] 4) Laying a perfect foundation for subsequent metal layer interconnects: By maintaining uniform density, the CMP polishing pad can contact the entire wafer surface with a uniform pressure, making it easier to achieve global planarization in subsequent chemical mechanical polishing.

[0044] 5) Optimize chip performance and power consumption: The drive current of all transistors is highly matched, the performance of the entire chip is uniform, there is no distinction between "fast and slow cores", the clock and signal synchronization is extremely high, when all transistors are working in the optimal design state, the signal transmission is synchronized, and the circuit can reach the highest operating speed; the uniform gate oxide (insulating oxide layer between the gate and the channel) avoids the increase of gate leakage caused by local excessive thinness, and the consistent transistor size and threshold voltage make the power consumption of circuit switching more controllable, without unexpected "power hogs". Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a traditional digital model layout design process.

[0047] Figure 2 This is a flowchart illustrating a method for solving polysilicon flatness in digital layout design according to an embodiment of the present invention.

[0048] Figure 3 This invention provides a process for solving polysilicon flatness in digital layout design.

[0049] Figure 4 The diagram shows a layout where the density of electrical appliance clusters ranges from 30% to 80%.

[0050] Figure 5 The P-injection isolation ring type is shown.

[0051] Figure 6 The N-injection isolation ring type is shown.

[0052] Figure 7 The configuration results of the P-injection type X-direction improvement module are shown.

[0053] Figure 8 The P-injection isolation ring type is shown.

[0054] Figure 9 The N-injection isolation ring type is shown.

[0055] Figure 10 The configuration results of the P-injection type Y-direction improvement module are shown.

[0056] Figure 11 The layout after the addition of the improved density module is shown.

[0057] Figure 12 The P-injection isolation ring type is shown.

[0058] Figure 13 The N-injection isolation ring type is shown.

[0059] Figure 14 The result of the X-direction fill configuration is shown.

[0060] Figure 15 The result of the Y-direction fill configuration is shown.

[0061] Figure 16 The P-injection isolation ring type is shown.

[0062] Figure 17 The N-injection isolation ring type is shown.

[0063] Figure 18 The results of the improved circuit device density configuration are shown.

[0064] Figure 19 The closed layout of the isolation ring is shown.

[0065] Figure 20 The P-substrate type is shown.

[0066] Figure 21 The N-substrate type is shown.

[0067] Figure 22 The polycrystalline silicon planar design layout is shown.

[0068] Figure 23 The image shows the effect of filling the blank area.

[0069] Figure 24 This is a structural block diagram of a system for solving polysilicon flatness in digital layout design according to an embodiment of the present invention.

[0070] Figure 25 This is a schematic diagram of a device for solving polysilicon flatness in digital layout design according to an embodiment of the present invention. Detailed Implementation

[0071] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments and accompanying drawings. The illustrative embodiments and descriptions of this invention are for illustrative purposes only and are not intended to limit the invention.

[0072] Poor polycrystalline silicon (poly) layer density design has a fatal impact on semiconductor manufacturing because it directly affects the "cells" of the chip—transistors. The consequences are far more serious and fundamental than problems with the density of subsequent metal layers. In this invention, after the layout design is completed and circuit devices are placed, suitable CMP (Chemical Mechanical Polishing) density data is retrieved from the database for that node design. The blank areas outside the circuit device placement area are configured to form a comfortable CMP density zone. Furthermore, a transition zone is configured between the ultra-high density and ultra-low density areas and the blank areas, ensuring that the overall chip density is within the required CMP density range. Simultaneously, the density gradient in each region is minimized, resulting in a smooth and uniform polycrystalline silicon layer.

[0073] Non-uniform polysilicon gates, with high-density areas (dense poly pattern) and low-density areas (sparse poly pattern), exhibit different responses to polishing pad wear and chemical slurry, leading to inconsistent polishing rates. This results in dish-shaped depressions and erosion, causing uneven poly gate thickness and morphological changes after CMP, and a highly uneven wafer surface.

[0074] 1) Uneven thickness of the poly gate alters its morphology, which has a devastating impact on transistor performance.

[0075] Threshold voltage (Vt) fluctuations: The threshold voltage of a transistor is closely related to the thickness (and doping) of the gate polysilicon. After CMP, the polysilicon thickness varies in different regions, causing Vt shifts in different transistors on the same chip. This leads to the following problems:

[0076] Slower speed: The switching speed of transistors increases with Vt, resulting in slower switching speed;

[0077] Increased leakage current: Transistors with reduced Vt do not shut off properly, resulting in a surge in static power consumption;

[0078] Circuit mismatch: This can cause functional failure in analog circuits (such as differential pairs) and SRAM (Static Random-Access Memory) storage cells.

[0079] Transconductance and drive current variations: The resistance and capacitance of the poly gate change due to variations in its thickness, affecting the transistor's charge / discharge speed and drive capability. This leads to a decrease in overall chip performance (maximum frequency) and inconsistent performance across different regions.

[0080] 2) The entire wafer surface is highly uneven: the uneven surface of the poly after CMP will become a "problematic foundation" for all subsequent process layers.

[0081] Lithography defocusing: Modern lithography machines have extremely shallow depth of field. Uneven surfaces mean that the entire chip cannot be in optimal focus. This leads to blurred patterns, bridging, or breakage, resulting in a significant drop in yield.

[0082] Thin film deposition and etching issues: Depositing subsequent dielectric and metal layers on uneven surfaces can lead to poor film coverage and excessive thinning at steps. This can cause increased contact resistance and even open or short circuits.

[0083] To address the issue of unevenness in FEOL manufacturing affecting the overall three-dimensional structure of the chip, this invention provides a technical solution for improving polysilicon flatness in mixed-signal layout design. This solution provides a database containing various customized modules that enable simultaneous placement of circuit devices during the initial layout design phase. This ensures uniform polysilicon (front-end layer) arrangement throughout the chip, creating a more favorable manufacturing environment for CMP processes. It guarantees that each layer of the manufactured chip possesses excellent geometry and physical properties, thereby achieving the desired circuit performance, high yield, and long-term reliability.

[0084] To address these issues, a more favorable manufacturing environment for CMP processes needs to be created to ensure that each layer of the manufactured chip has good geometry and physical properties, thereby achieving the expected circuit performance, high yield, and long-term reliability.

[0085] Ideally, the density of every region on the entire chip should be exactly the same, which is most advantageous for CMP. However, in actual design, factors such as design difficulty, cost, and process deviations must be considered, making it impossible to achieve this ideal state. Foundry CMP simulation tools deliver products with two density requirements (industry-standard conditions): global density: 30% - 80%; local gradient: ensuring density variation <10% within any process-defined inspection window (e.g., 50x50μm). This invention provides a technical solution involving a database that can be invoked after circuit device placement to quickly fulfill the above two conditions.

[0086] On the one hand, the present invention provides a method for solving the problem of polysilicon flatness in digital model layout design. Figure 2 This is a flowchart illustrating a method for solving polysilicon flatness in digital layout design according to an embodiment of the present invention. (Reference) Figure 2 The method includes steps S10 to S40.

[0087] Figure 3 This is a process for solving polysilicon flatness in digital layout design according to an embodiment of the present invention. The following references... Figure 2 and Figure 3The method of the present invention will be described in detail.

[0088] In S10, after placing circuit devices in the early stages of layout design and before routing, a circuit device area density check is performed, and the layout is partitioned based on the cluster density and type of the circuit devices.

[0089] For example, firstly, based on the circuit design diagram, the device layout is designed and the circuit devices are placed; then, the density of the circuit device clusters in the layout after placement is checked to ensure that the polysilicon density of all circuit device clusters meets the industry density requirements (i.e., between 30% and 80%), resulting in... Figure 4 The layout design diagram is shown; finally, the layout is analyzed and marked, and the type and density of each device cluster are extracted, resulting in the following extraction results: a) Density differentiation: high density area, low density area, blank area; b) Type differentiation: N-type transistor, P-type transistor, resistor, capacitor.

[0090] In S20, the adjustment module in the database is called to adjust the flatness of the polysilicon in the layout. The adjustment module includes: density improvement module, closure module, and polysilicon filling module.

[0091] 1. Improved density module

[0092] The density improvement module is used to adjust the density around the circuit devices to form a buffer between the cluster of circuit devices and the final filler of the blank area (the polysilicon density of the filler is set to the median value of 55%), preventing the density gradient from exceeding 10%.

[0093] Density improvement modules utilize the isolation ring space of circuit device clusters to improve the polysilicon density around the circuit device clusters, reducing the density around high-density circuit device clusters and increasing the density around low-density circuit device clusters. Density improvement modules include two types: X (first) direction density improvement modules and Y (second) direction density improvement modules, where the first direction is perpendicular to the second direction.

[0094] a) Circuit device X-direction density improvement module

[0095] The circuit device X-direction density improvement module is used to improve the density on the left and right sides of the circuit device cluster, and its type is determined according to the target device cluster type.

[0096] Figure 5 The image shows the P-injection isolation ring type. Figure 6The image shows an N-shaped implanted isolation ring type. When calling the density improvement module, the width and length of the polysilicon are set to generate a module of the corresponding size. Here, Met1 represents the metal layer, PSD represents the P-type heavily doped region, NSD represents the N-type heavily doped region, DIFF represents the diffusion region, Ploy represents polysilicon, and CONT represents the contact hole. Figure 7 The image shows the configuration result of the first direction improvement module for P injection type.

[0097] Configuration method: Taking the P injection type as an example.

[0098] 1) Determine the target cluster density value as a benchmark of 55%, which is the midpoint between the industry density standard of 30% and 80%;

[0099] 2) Set the density of the improved density module as: m = (M - 55) / 2 + 55;

[0100] 3) Reduce process errors and maintain the array arrangement of the target cluster. Set the polysilicon height of the first direction density improvement module to be the same as the polysilicon height of the target cluster device.

[0101] 4) Based on the density of the improved density module, the polysilicon height, the minimum width of the isolation ring, and the pitch in the second direction, the width of the improved density module in the first direction is calculated using the following formula:

[0102] ;

[0103] Where M represents the polysilicon integration density, H represents the pitch in the second direction, h represents the polysilicon height, and a represents the minimum width of the isolation ring (which can be obtained according to the foundry's design rules; the minimum width varies for different processes).

[0104] b) Circuit device Y-direction density improvement module

[0105] The circuit device Y-direction density improvement module is used to improve the density on the top and bottom sides of the circuit device cluster, and its type is determined according to the target device cluster type.

[0106] Figure 8 The image shows the P-injection isolation ring type. When calling it, the width and length of the polysilicon can be set to generate a module of the corresponding size. Figure 9 The image shows the N-type injection isolation ring. When calling the function, the width and length of the polysilicon can be set to generate modules of the corresponding size. Figure 10 The image shows the configuration result of the second direction improvement module for P injection type.

[0107] Configuration method: Taking the P injection type as an example.

[0108] 1) Determine the target cluster density value as a benchmark of 55%, which is the midpoint between the industry density standard of 30% and 80%;

[0109] 2) Set the density of the improved density module as: m = (M - 55) / 2 + 55;

[0110] 3) Reduce process errors and maintain the array arrangement of the target cluster by keeping the polysilicon width of the second-direction density improvement module consistent with the polysilicon width of the target cluster device;

[0111] 4) Based on the density of the improved density module, the polysilicon width, the minimum width of the isolation ring, and the pitch in the first direction, the width of the improved density module in the second direction is calculated using the following formula:

[0112] ;

[0113] Where w represents the width of the polysilicon; V represents the pitch in the first direction.

[0114] Figure 11 The diagram shown represents the layout after density improvement has been completed.

[0115] 2. Closed module

[0116] Closure modules are used to fill the gaps between density improvement modules while meeting design requirements, thereby closing the area where the density improvement modules are located. Closure modules include the following types: physical verification spacing modules between density improvement modules and corner closure modules for density improvement modules.

[0117] a) Improve the physical verification spacing between density modules

[0118] The physical verification spacing module for improving density modules is used to fill the gaps between density improvement modules while meeting design requirements.

[0119] Figure 12 The image shows the P injection isolation ring type, with width and length set during the call. Figure 13 The image shows the N-type injection isolation ring, where the width and length are set during the call.

[0120] The configuration method is illustrated using the P-injection type as an example, which fills the gaps in the density improvement module. Figure 14 The image shows the filling result in the first direction. Figure 15 The result shown is the filling result in the second direction.

[0121] b) Improved density module corner closure module

[0122] The density improvement module corner closure module is used to fill the (corner) gaps between density improvement modules while meeting design requirements.

[0123] Figure 16 The diagram shows the P-injection isolation ring type, which is used in conjunction with the improvement module to set the width and length of the polysilicon for invocation. Figure 17 The diagram shows the N-type injection isolation ring, which is used in conjunction with the improvement module to set the width and length of the polysilicon.

[0124] The configuration method is illustrated using the P-type injection method as an example. After placing the density improvement modules and gap modules in the X and Y directions, a corner closure module is placed at the corner to surround and close the target electrical assembly, forming an isolation ring. Figure 18 As shown.

[0125] Figure 19 The diagram shown is a layout with added density improvement module gap module and corner closure module.

[0126] 3. Polycrystalline silicon filling module

[0127] Figure 20 The image shows a P-type substrate chip. When calling it, set the polysilicon density (selectable range 50%-60%) and select the required filling module. Figure 21 The image shows an N-type substrate chip. When calling it, set the polysilicon density (selectable range 50%-60%) and select the required filling module.

[0128] For example, to ensure the polysilicon layer of the entire chip is flat and meets the requirement of a density gradient of less than 10%, a polysilicon filling module is used to fill blank areas with polysilicon. The polysilicon filling module includes a blank filling module with a polysilicon density of 55%, ensuring that the polysilicon layer in blank areas of the chip, excluding circuit devices, is completely flat, resulting in... Figure 22 and Figure 23 The polycrystalline silicon planar design layout is shown.

[0129] In S30, signal lines and power connections are made to the adjusted layout, and virtual metals are added to meet the metal layer density requirements, resulting in the layout design to be verified.

[0130] In S40, design rule verification is performed on the layout design to be verified. If errors exist in the layout design to be verified, the circuit device cluster is fine-tuned for the following two cases:

[0131] a) The density of the circuit device cluster module is extremely high (greater than 75%). According to the formula in the configuration introduction above, the polysilicon density of the improved module will be greater than 65%, and the polysilicon density of the central blank area will be 55%. The gradient difference will exceed 10% (first threshold).

[0132] b) The density of the circuit device cluster module is extremely high (less than 35%). According to the formula in the previous configuration introduction, the polysilicon density of the improved module will be less than 45%, and the polysilicon density of the central blank area will be 55%, with a gradient difference of more than 10%.

[0133] For cases a) and b) above, the blank area filling modules that do not meet the requirement of adjacent regions are replaced, and the polysilicon density of these filling modules is increased (selected as 60%) and decreased (selected as 50%) respectively to perform gradient buffering.

[0134] To address the density issue, this invention introduces a virtual polysilicon filler. If the virtual polysilicon filler is improperly placed, partially covering or too close to the active region, it can form an unintended parasitic transistor with the substrate. The gate (virtual polysilicon) of this parasitic transistor is floating, with an uncertain potential, and may randomly turn on, creating a large leakage current path or interfering with the function of nearby sensitive circuits (such as SRAM). Therefore, the polysilicon layers in the modules used in this invention need to be at a fixed potential to ensure that the transistor remains off even when a parasitic transistor forms. All modules in this invention are either P-type or N-type. For P-type modules, the polysilicon is connected to a high potential. For N-type modules, the polysilicon is connected to a low potential.

[0135] By using the aforementioned potential connection, the problem of parasitic transistor conduction is suppressed. The introduction of the database in this invention improves the density uniformity of the polysilicon gate (poly), providing a better manufacturing environment for CMP. This ensures that each layer of the manufactured chip has good geometry and physical properties, and also avoids the filling of floating polysilicon, suppressing parasitic transistor conduction. As a result, high-quality chips with expected circuit performance, high yield, and long-term reliability can be achieved more stably.

[0136] Compared with the prior art, the present invention has the following technical effects.

[0137] 1) Consistent transistor electrical performance on the chip is achieved: The threshold voltage (Vt) of a transistor is the critical voltage at which it turns on. Vt is mainly determined by the gate oxide thickness and channel doping.

[0138] The flatness of the polysilicon layer ensures the uniformity of the gate oxide layer thickness beneath it. If the surface is uneven, the gate oxide growth rate will differ at higher and lower elevations, resulting in uneven thickness. Even a difference of only a few angstroms (Å) in gate oxide thickness can cause significant fluctuations in voltage threshold voltage (Vt). A flat and uniform polysilicon layer ensures that all transistors have a uniform gate oxide thickness, thereby achieving a consistent and stable threshold voltage. This is the cornerstone for the proper functioning of the chip circuit as designed.

[0139] a) Achieved uniform gate height: After CMP, the polysilicon gate has a consistent height, meaning that the gates of all transistors undergo the same processing conditions in subsequent processes.

[0140] b) Achieved stable threshold voltage: Planarization ensures the uniformity of the channel region below the gate, so that millions of transistors on the same chip have almost the same switching threshold, predictable circuit behavior, and stable performance.

[0141] 2) Improved product yield

[0142] Ensuring high precision in photolithography imaging and achieving uniform etching: This allows subsequent processes such as photolithography, etching, and thin film deposition to be carried out under ideal and stable conditions, virtually eliminating failures caused by dish-shaped depressions, erosion, etc., reducing process difficulty and alignment errors, making production more stable, and improving product yield.

[0143] a) Ensure the accuracy of photolithography imaging:

[0144] Modern lithography machines have extremely shallow depths of focus (only at the nanometer level). Photoresist needs to be spin-coated onto the wafer surface, and its thickness uniformity depends entirely on the flatness of the underlying layer.

[0145] If the polysilicon layer is uneven, the photoresist surface will also be uneven. During exposure, the light source is projected onto the uneven surface, and some areas will be out of focus due to exceeding the depth of focus, resulting in blurred patterns and linewidth variations. A smooth surface ensures that photolithography can accurately focus across the entire chip, avoiding pattern blurring, short circuits, or open circuits caused by insufficient depth of focus.

[0146] b) Achieve uniform etching:

[0147] Plasma etching exhibits a "micro-loading effect," meaning the etching rate is influenced by the local pattern density. The rates of reactant consumption and byproduct generation differ between densely patterned and sparsely patterned regions.

[0148] If the surface is uneven and the density is inconsistent, during etching, some areas may be completely etched while others may have residual polysilicon (leading to short circuits), or some areas may be over-etched and damage the underlying material. A smooth and uniform surface provides uniform initial conditions for etching, ensuring that all gates are etched synchronously and in equal amounts.

[0149] 3) Enhance device reliability

[0150] The strength of the electric field is inversely proportional to the thickness of the dielectric layer (E = V / d, where E represents the electric field strength, V represents the voltage, and d represents the dielectric thickness).

[0151] If the gate oxide thickness is uneven, the electric field strength will be abnormally high in the thinner areas, becoming weak points for gate oxide breakdown and greatly reducing chip lifespan. A flat and uniform polysilicon layer eliminates these weaknesses, allowing the gate oxide to withstand a uniform electric field and significantly improving the long-term reliability of the product. At the same time, transistors with consistent performance reduce the generation of localized hot spots, also improving the long-term operational stability of the product.

[0152] 4) Lays a perfect foundation for subsequent metal layer interconnects

[0153] After the polysilicon gate is fabricated, an insulating dielectric layer needs to be deposited on it and planarized using CMP (Chemical Motion Processing) before the first metal layer can be fabricated for interconnection. However, CMP is a process that combines mechanical polishing with chemical reactions. If the polysilicon pattern density is uneven, the pressure of the polishing pad on the wafer surface will vary. In high-density areas, the pattern is dense and the structure is robust, requiring less polishing; in low-density areas, the pattern is sparse and the structure is "soft," requiring more polishing.

[0154] Uneven density can lead to severe "dish-shaped depressions" and "erosion." Therefore, by maintaining uniform density, CMP polishing pads can contact the entire wafer surface with a uniform pressure, making subsequent chemical mechanical polishing easier to achieve global planarization. The benefits are as follows:

[0155] To prevent the metal wire from breaking due to an excessively high step;

[0156] To prevent the insulation layer from being worn through, which could lead to a short circuit between the metal and polysilicon;

[0157] This makes it possible to build complex interconnect structures with a dozen or even dozens of layers.

[0158] 5) Optimize chip performance and power consumption

[0159] a) Optimize chip performance:

[0160] The drive current (Id) of a transistor determines its switching speed. Id is directly related to parameters such as gate width and gate oxide capacitance.

[0161] The flat surface ensures consistent depth of focus during photolithography, allowing for precise etching of the gate to the designed width. Combined with uniform gate oxide thickness, this results in highly consistent gate oxide capacitance and channel mobility across millions of transistors. The end result is highly matched drive currents for all transistors, uniform performance across the entire chip, no distinction between "fast" and "slow" cores, and extremely high clock and signal synchronization. When all transistors operate at their optimal design, signal transmission is synchronized, allowing the circuit to reach its maximum operating speed.

[0162] b) Power consumption:

[0163] Static power consumption: Uniform gate oxide avoids increased gate leakage caused by localized excessive thinning.

[0164] Dynamic power consumption: Consistent transistor size and threshold voltage make circuit switching power consumption more controllable, eliminating unexpected "power hogs".

[0165] On the other hand, the present invention provides a system for solving polysilicon flatness in digital layout design. Figure 24 This is a structural block diagram of a system for solving polysilicon flatness in digital layout design according to an embodiment of the present invention. (Reference) Figure 24 The system includes: a circuit device area density inspection unit, a polysilicon flatness adjustment unit, a signal line and power supply connection unit, and a design rule verification unit.

[0166] The circuit device area density checking unit is used to: check the circuit device area density after placing the circuit devices in the early stage of layout design and before routing, and partition the layout based on the cluster density and type of the circuit devices.

[0167] The polysilicon flatness adjustment unit is used to: call the adjustment module in the database to adjust the flatness of the polysilicon in the layout. The adjustment module includes: density improvement module, closure module, and polysilicon filling module.

[0168] The signal line and power connection unit is used to: connect the signal lines and power to the adjusted layout, supplement virtual metal to meet the metal layer density requirements, and obtain the layout design to be verified.

[0169] The design rule verification unit is used to verify the design rules of the layout design drawing to be verified.

[0170] For further details regarding the system for addressing polysilicon flatness in digital layout design, please refer to the previous description of methods for addressing polysilicon flatness in digital layout design; these details will not be repeated here.

[0171] In implementing the functions of the integrated modules described above in hardware, this embodiment of the invention provides a structure for a device for solving polysilicon flatness in digital module layout design, as described in the above embodiments. Figure 25 This is a schematic diagram of a device for solving polysilicon flatness in digital layout design according to an embodiment of the present invention. (Reference) Figure 25 The device for solving polysilicon flatness in digital layout design includes: at least one processor; and at least one memory. The at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, which, when executed by the at least one processor, implement the methods described above.

[0172] A processor can be a set of logic blocks, modules, and circuits that implement or execute the various exemplary logic blocks, modules, and circuits described in connection with embodiments of the present invention. The processor can be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in connection with embodiments of the present invention. A processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc.

[0173] The memory may be read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, electrically erasable programmable read-only memory (EEPROM), disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

[0174] In one implementation, the memory can exist independently of the processor. The memory can be connected to the processor via a bus and used to store instructions or program code. When the processor calls and executes the instructions or program code stored in the memory, it can implement the method provided in the embodiments of the present invention. In another implementation, the memory can also be integrated with the processor.

[0175] On the other hand, the present invention also provides a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) storing computer program instructions that, when executed on a computer, cause the computer to perform the method as described in any of the above embodiments.

[0176] Exemplary examples show that the aforementioned computer-readable storage media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical discs (e.g., compact disks (CDs), digital versatile disks (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). The various computer-readable storage media described in this invention may represent one or more devices and / or other machine-readable storage media for storing information. The term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0177] This invention provides a computer program that, when run on a computer, causes the computer to perform the method of any of the above embodiments.

[0178] This invention provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the method of any of the above embodiments.

[0179] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for solving polysilicon flatness in digital model layout design, characterized in that, The method includes: After placing circuit devices in the early stages of layout design and before routing, a circuit device area density check is performed, and the layout is partitioned based on the cluster density and type of the circuit devices. The adjustment module in the database is invoked to adjust the flatness of the polysilicon in the layout. The adjustment module includes: a density improvement module, a closure module, and a polysilicon filling module. The density improvement module is an isolation ring space set between the clusters of circuit devices and blank areas to adjust the density around the clusters of circuit devices. The closure module is used to fill the gaps between the density improvement modules, closing the area where the density improvement modules are located, while meeting design requirements. The polysilicon filling module includes a void filling module for filling the blank areas with polysilicon. Connect signal lines and power supplies to the adjusted layout, add virtual metals to meet the metal layer density requirements, and obtain the layout design to be verified. The design rules of the layout design to be verified are verified.

2. The method according to claim 1, characterized in that, After placing circuit components in the initial layout design phase and before routing, a circuit component area density check is performed, and the layout is partitioned based on the cluster density and type of the circuit components, including: The density of the circuit device clusters in the layout after the circuit devices are placed is checked to ensure that the polysilicon density of all circuit device clusters is within the industry density requirement range. Extract the type and density of each circuit device cluster to obtain density differentiation and type differentiation. The density differentiation includes: high-density area, low-density area, and blank area. The type differentiation includes: N-type transistor, P-type transistor, resistor, and capacitor.

3. The method according to claim 2, characterized in that, The density improvement module includes a first-direction density improvement module and a second-direction density improvement module. The first direction is perpendicular to the second direction. The first-direction density improvement module is used to configure the density in the first direction, and the second-direction density improvement module is used to configure the density in the second direction. The configuration of the first directional density or the second directional density includes: Determine 55%, the midpoint of the industry density requirement range, as a benchmark; The density of the improved density module is set as: m = (M-55) / 2 + 55, where M represents the polysilicon integration density and 55 is determined based on a baseline of 55%. The polysilicon height of the first-direction density improvement module is set to be the same as the polysilicon height of the circuit devices in the target circuit device cluster. Based on the density of the density improvement module, the polysilicon height, the minimum width of the isolation ring, and the pitch in the second direction, the width of the first-direction density improvement module is calculated using the following formula: ; Where H represents the pitch in the second direction; h represents the height of the polysilicon; and a represents the minimum width of the isolation ring. The polysilicon width of the second-direction density improvement module is set to be the same as the polysilicon width of the circuit devices in the target circuit device cluster. Based on the density of the density improvement module, the polysilicon width, the minimum width of the isolation ring, and the pitch in the first direction, the width of the second-direction density improvement module is calculated using the following formula: ; Where w represents the width of the polysilicon; V represents the pitch in the first direction.

4. The method according to claim 2, characterized in that, The closing module includes: a module for improving the physical verification spacing between density modules and a corner closing module for improving density modules. The physical verification spacing module between the density improvement modules is set along a first direction and a second direction to fill the gap between the density improvement modules, wherein the first direction is perpendicular to the second direction. The improved density module corner closure module is located at the corner of the physical verification spacing module between the improved density module and the improved density module, and is used to surround and close the target circuit device cluster.

5. The method according to claim 2, characterized in that, The polysilicon density of the void filling module is 55%.

6. The method according to claim 5, characterized in that, If there are errors in the layout design to be verified, the cluster of circuit devices is fine-tuned. Specifically, if the polysilicon density of the density improvement module and the polysilicon density of the blank area are greater than a first threshold, the polysilicon density of the empty filling module in the blank area is increased or decreased to perform gradient buffering.

7. A system for solving polysilicon flatness in digital model layout design, characterized in that, The system includes: The circuit device area density checking unit is used to: check the circuit device area density after placing the circuit devices in the early stage of layout design and before routing, and partition the layout based on the cluster density and type of the circuit devices. A polysilicon flatness adjustment unit is used to: call an adjustment module from a database to adjust the flatness of the polysilicon in the layout, wherein the adjustment module includes: a density improvement module, a closure module, and a polysilicon filling module; wherein the density improvement module is an isolation ring space set between the cluster of circuit devices and the blank area to adjust the density around the cluster of circuit devices; the closure module is used to fill the gaps between the density improvement modules under the condition of meeting the design rules, so as to close the area where the density improvement module is located; the polysilicon filling module includes a void filling module for filling the blank area with polysilicon. The signal line and power connection unit is used to: connect the signal lines and power to the adjusted layout, supplement virtual metal to meet the metal layer density requirements, and obtain the layout design to be verified. The design rule verification unit is used to: perform design rule verification on the layout design drawing to be verified.

8. A device for solving the problem of polysilicon flatness in digital model layout design, characterized in that, The device includes: At least one processor; At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions implementing the method of any one of claims 1 to 6 when executed by the at least one processor.

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