A method and system for alignment of differential links

Abstract

The application discloses a differential link alignment method and system, and relates to the field of data processing. The method comprises the following steps: judging whether the sampling edge of a clock signal is in a stable region of a differential link based on a training code at different delay times; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, recording the judgment result as a first flag; otherwise, recording the judgment result as a second flag; arranging the first flag and the second flag according to the order of the delay times to obtain a flag set; screening out a middle flag of any first interval or second interval in the flag set; and delaying the clock signal or the differential link based on the delay amount corresponding to the middle flag, so as to realize data alignment of the differential link. Based on the above processing, the sampling edge of the clock signal after data alignment can be prevented from being in a jump region.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of data processing, and particularly relates to a method and system for aligning a differential link. BACKGROUND

[0002] A differential link based on differential signals for data transmission has an actual waveform as shown in the figure, and there are stable regions and transition regions in one signal period. For a differential link (for example, LVDS, Low Voltage Differential Signaling) triggered by an external clock signal for sampling, when the rising edge or falling edge of the clock signal is in the transition region, it is easy to cause errors in the collected data. Therefore, in the process of data transmission of the differential link, it is required that the sampling point of the clock signal falls in the stable region of the transmitted data. Figure 1

[0003] Due to certain delay of the data transmission line and the data receiving end, it is easy to cause phase deviation between the clock signal and the differential link. In order to correct the phase deviation, at the initial power-on, the differential link is trained by delay scanning to realize data alignment between the clock signal and the differential link. At the same time, in order to improve the anti-interference ability of the differential link after alignment, it is required to align the sampling edge of the clock signal to the center of the stable time window.

[0004] However, in the process of link training, when the delay step for adjusting the delay time exceeds the transition region, it is easy to fail to detect the transition region in the delay scanning process, so that the transition region exists in the stable time window, resulting in errors in the data alignment result of the differential link. SUMMARY

[0005] The method and system for aligning a differential link provided in the present application are used to avoid errors in the data alignment result when the delay step exceeds the transition region of the differential link.

[0006] To achieve the above object, the present application provides the following technical solutions:

[0007] In the first aspect of the present application, a method for aligning a differential link is provided, comprising:

[0008] At different delay times, it is judged whether the sampling edge of the clock signal is in the stable region of the differential link based on a training code; if yes, and the latched value obtained based on the sampling edge under the current delay time belongs to a first set, a first flag is recorded as the judgment result; otherwise, a second flag is recorded as the judgment result; wherein the numbers of each bit in the training code are not completely consistent; and the first set includes the values generated after the training code is cyclically shifted.

[0009] ​The first flag and the second flag are arranged according to the order of the delay time to obtain a flag set;

[0010] In the flag set, a middle flag of any one of a first interval or a second interval is screened out; the first interval is composed of continuous first flags, the adjacent flags on the outer sides of the first interval are second flags, and the interval of the delay time corresponding to the two end points in the first interval is not more than a single signal period of the differential link; the second interval is composed of continuous second flags, the adjacent flags on the outer sides of the second interval are first flags, and the interval of the delay time corresponding to the adjacent first flags on the outer sides of the second interval is higher than a single signal period and lower than two signal periods;

[0011] The clock signal or the differential link is delayed based on the delay amount corresponding to the middle flag, so as to realize data alignment of the differential link.

[0012] Optionally, under different delay times, whether the sampling edge of the clock signal is in the stable region of the differential link is judged based on the training code, including:

[0013] Under different delay times, the same training code is input to the differential link;

[0014] Based on the sampling edge of the clock signal, the training code is sampled multiple times at the receiving end of the differential link to obtain multiple latch values; wherein the sampling edge is the rising edge or the falling edge of the clock signal;

[0015] Whether the multiple latch values are consistent is judged; if yes, it indicates that the sampling edge of the clock signal is in the stable region of the differential link; if not, it indicates that the sampling edge of the clock signal is not in the stable region of the differential link.

[0016] Optionally, each delay time is obtained based on a fixed delay step, and the highest delay time exceeds n signal periods; wherein n represents the bit number of the training code.

[0017] Optionally, if the first set only includes one value generated by cyclic shift of the training code, the middle flag of any one of the first interval or the second interval is screened out as follows:

[0018] The middle flag in any one interval composed of continuous first flags is screened out.

[0019] Optionally, if the first set only includes two values generated by cyclic shift of the training code, the shift amount interval of the two values is not less than one bit compared with the training code;

[0020] When the shift amount interval of the two values is one bit, the middle flag of any one of the first interval or the second interval is screened out as follows:

[0021] The intermediate mark of any one interval formed by consecutive first marks or second marks is screened out.

[0022] When the shift amount interval of two values exceeds one bit, the intermediate mark of any one first interval or second interval is screened out.

[0023] The intermediate mark of any one interval formed by consecutive first marks is screened out.

[0024] Optionally, if the first set includes m values generated by cyclic shift of the training code, at least two adjacent shift values in the m values have a shift amount interval of one bit, or the shift amount interval between at least three adjacent shift values in the m values is not less than one bit, compared with the training code; wherein, 3≤m≤n-1.

[0025] When the maximum shift amount interval of adjacent shift values in the m values is one bit, the intermediate mark of any one first interval or second interval is screened out.

[0026] The intermediate mark of any one second interval is screened out.

[0027] Optionally, before the first marks and the second marks are arranged according to the order of the delay times to obtain the mark set, the alignment method further comprises:

[0028] At different delay times, it is judged whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to the second set, the judgment result is recorded as the first mark; otherwise, the judgment result is recorded as the second mark.

[0029] The second set includes values generated by cyclic shift of the calibration value; the calibration value represents the latched value obtained when the sampling edge of the clock signal is first in the stable region of the differential link.

[0030] Optionally, if the second set only includes one value generated by cyclic left shift of the calibration value by q bits, the highest delay time exceeds q signal periods.

[0031] Optionally, if n is even, the second set includes n / 2 values generated by cyclic shift of the latched value, and the shift amount interval between adjacent values in the n / 2 values is one bit, the intermediate mark of any one first interval or second interval in the mark set comprises:

[0032] In the mark set, for all intervals formed by consecutive first marks or second marks, after removing the first and last intervals, the intermediate mark of any one remaining interval is screened out.

[0033] In a second aspect of the present application, a system for aligning a differential link is provided, comprising:

[0034] a flag recording module configured to determine whether a sampling edge of a clock signal is in a stable region of the differential link based on a training code at different delay times, and record a first flag if the determination is positive and a latch value obtained based on the sampling edge at a current delay time belongs to a first set, or record a second flag if the determination is negative; wherein each bit of the training code is not completely identical; and the first set comprises values generated by cyclically shifting the training code;

[0035] a set generating module configured to arrange the first flag and the second flag according to a sequence of the delay times to obtain a flag set;

[0036] a flag screening module configured to screen a middle flag of any one of a first interval or a second interval from the flag set; wherein the first interval is composed of consecutive first flags, the first flags at both sides of the first interval are second flags, and a difference between the delay times corresponding to the two ends of the first interval is not more than a single signal period of the differential link; and the second interval is composed of consecutive second flags, the second flags at both sides of the second interval are first flags, and a difference between the delay times corresponding to the two first flags at both sides of the second interval is higher than the single signal period and lower than two signal periods;

[0037] a data aligning module configured to delay the clock signal or the differential link based on a delay amount corresponding to the middle flag to achieve data alignment of the differential link.

[0038] The present application has the following advantages:

[0039] The present application provides a method for aligning a differential link, comprising: determining whether a sampling edge of a clock signal is in a stable region of the differential link based on a training code at different delay times; recording a first flag if the determination is positive and a latch value obtained based on the sampling edge at a current delay time belongs to a first set, or recording a second flag if the determination is negative; wherein each bit of the training code is not completely identical; and the first set comprises values generated by cyclically shifting the training code; and arranging the first flag and the second flag according to a sequence of the delay times to obtain a flag set.

[0040] In the mark set, a middle mark of any one of the first interval or the second interval is screened out; wherein, the first interval is composed of continuous first marks, the marks adjacent to the outside of the first interval are second marks, and the interval of the delay time corresponding to the two end points in the first interval does not exceed a single signal period of the differential link; the second interval is composed of continuous second marks, the marks adjacent to the outside of the second interval are first marks, and the interval of the delay time corresponding to the two adjacent first marks outside the second interval is higher than a single signal period and lower than two signal periods; the clock signal or the differential link is delayed based on the delay amount corresponding to the middle mark, so as to realize the data alignment of the differential link.

[0041] Based on the above processing, in the alignment method provided by the application, the corresponding determination result under each delay time is obtained by using two kinds of combination determination methods. Compared with the prior art, the application sets a judgment means for whether the latch value belongs to the first set, which can make the determination result marks corresponding to the stable regions in the adjacent two signal periods different, and at least the first interval and the second interval exist in the formed mark set.

[0042] Meanwhile, according to the limitation condition of the first interval and the data latch characteristic of the differential link, it can be known that the stable time window corresponding to the first interval completely falls in the stable region of the differential link and does not contain the transition region; according to the limitation condition of the second interval and the data latch characteristic of the differential link, it can be known that although the two end parts of the stable time window corresponding to the second interval belong to the transition region of the differential link, the middle mark located at the center of the second interval can be determined to fall in the stable region. Therefore, after completing the data alignment based on the delay amount corresponding to the middle mark, the sampling edge of the clock signal can be avoided to be in the transition region. BRIEF DESCRIPTION OF DRAWINGS

[0043] The drawings described herein are used to provide further understanding of the application, and form a part of the application. The illustrative embodiments of the application and their descriptions are used to explain the application, and do not constitute an improper limitation on the application. In the drawings:

[0044] Figure 1 is a differential link diagram provided by the application;

[0045] Figure 2 is a data sampling diagram of a differential link provided by the application;

[0046] Figure 3 is a data sampling diagram of a differential link under different delay times provided by the application;

[0047] Figure 4 is another data sampling diagram of a differential link under different delay times provided by the application;

[0048] Figure 5 is a flowchart of a method for aligning a differential link provided by the present application;

[0049] Figure 6 is a flowchart of another method for aligning a differential link provided by the present application;

[0050] Figure 7 is a schematic diagram of a latching result of a differential link at different delay times provided by the present application;

[0051] Figure 8 is a structural diagram of an alignment system of a differential link provided by the present application;

[0052] Figure 9 is a structural diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments of the present application.

[0054] The voltage change process on the two lines of the differential signal needs a certain time, resulting in that in one period of the differential signal, there are voltage change regions at both ends respectively, and a voltage constant region in the middle, which are respectively a jump region and a stable region, as shown in Figure 1 Correspondingly, using the rising edge or falling edge of the clock signal, the signal receiving end can stably collect the logic "1" and logic "0" states from the voltage constant region.

[0055] In the field of machine vision, most image sensors use differential links for high-speed data transmission, and data and clock signals are transmitted through different channels. Due to factors such as wiring delay and process deviation, there may be differences in skew (i.e., there is a phase difference) between different data channels and clock channels at the receiving end of the differential link, so that the sampling edge of the clock signal is in the jump region of the differential signal in the differential link, resulting in a risk of data latching error.

[0056] Among them, the differential link provided by the present application represents a communication link for data transmission based on a differential signal, such as LVDS. In the prior art, differential links are used in most cases of image sensor data acquisition, long-distance transmission of image data, etc. The level standards range from LVDS to sub-LVDS to SLVS, and the interface types range from the commonly used CameraLink interface of industrial cameras, the commonly used MIPI interface of mobile phones, and the commonly used PCIE interface of computers, etc.

[0057] In order to avoid that the sampling edge of the clock signal is in the transition region of the differential signal in the differential link, the receiving end of the differential link needs to align the skew of the differential link of the data channel before the effective data is latched, that is, link training.

[0058] A common link training method is to input a fixed training pattern to the differential link, and the receiving end (for example, FPGA) adjusts the delay time (idelay) of the link channel or the clock channel and judges whether the data is stable, thereby performing window scanning. The delay time window interval of the stable data obtained after scanning is the stable time window. Finally, considering that the stable time window is offset due to changes in temperature, voltage and other factors, the delay time of the differential link or the clock signal needs to be fixedly configured to the center of the aforementioned stable time window interval. On the basis of obtaining a stable latched value, the anti-interference ability of the differential link after training is improved.

[0059] With the continuous development of signal transmission technology, the width of the transition region of the differential link in the existing signal transmission system is relatively narrow (that is, the data transition time is shortened). However, the delay time setting of the receiving end of the differential link has a certain precision limit, that is, there is a minimum delay step in the adjustment of the delay time. As shown in FIG. 1, in the link training process, there is a case that the delay step exceeds the transition region. Figure 2

[0060] However, when the delay step used to adjust the delay time exceeds the transition region, there may be a problem that the transition region cannot be scanned in the stable time window scanning process, resulting in that the stable time window scanned by the delay time contains the transition region, as shown in FIG. 2. Figure 3 Figure 4 Specifically, Figure 3 It belongs to the link training mode of delaying the differential link, delay=1 indicates that the current delay amount is 1 delay step, data corresponds to the differential link, bit0, bit1 and bit2 correspond to the numbers of the corresponding bit positions in the training code, and the latched result indicates the judgment result under the current delay amount. In the latched result, 1 corresponds to the flag when the data can be stably sampled based on the clock signal under the current delay time (that is, the sampling edge falls in the stable region of the differential link), and 0 corresponds to the flag when the data cannot be stably sampled based on the clock signal under the current delay time (that is, the sampling edge falls in the transition region of the differential link). Figure 4 It belongs to the link training mode of delaying the clock signal, the arrow corresponds to the sampling edge of the clock signal under different delay times, and the stable time window is a time window composed of multiple delay times under which the data can be stably sampled.

[0061] ​​Thus, in the foregoing case, when aligned to the center of the data stable window, the sampling edge of the clock signal is likely to be in the transition region, resulting in a failure of the differential link training, and the result of the data alignment is erroneous.

[0062] To avoid the existence of the above error, the application provides an alignment method of a differential link, as shown in the figure, the method comprises the following steps: Figure 5

[0063] S1, under different delay times, judging whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code; if yes, and the latched value obtained based on the sampling edge under the current delay time belongs to the first set, recording the judgment result as the first flag; otherwise, recording the judgment result as the second flag.

[0064] Wherein, the numbers of each bit in the training code are not completely consistent; the first set includes the values generated after the cyclic shift of the training code.

[0065] S2, arranging the first flag and the second flag according to the order of the delay times to obtain a flag set.

[0066] S3, screening out the middle flag of any first interval or second interval in the flag set.

[0067] Wherein, the first interval is composed of consecutive first flags, the adjacent flags on the outside of the first interval are both second flags, and the interval of the delay times corresponding to the two end points in the first interval does not exceed a single signal period of the differential link; the second interval is composed of consecutive second flags, the adjacent flags on the outside of the second interval are both first flags, and the interval of the delay times corresponding to the adjacent first flags on the outside of the second interval is higher than a single signal period and lower than two signal periods.

[0068] S4, delaying the clock signal or the differential link based on the delay amount corresponding to the middle flag to realize the data alignment of the differential link.

[0069] Based on the above processing, in the alignment method provided by the application, the corresponding determination result under each delay time is obtained by using two kinds of combined judgment methods. Compared with the prior art, the application sets a judgment means of whether the latched value belongs to the first set, which can make the determination result flags corresponding to the stable region in the adjacent two signal periods different, and at least the first interval and the second interval exist in the formed flag set.

[0070] ​Meanwhile, according to the limiting condition of the first interval and the data latching characteristic of the differential link, it can be known that the stable time window corresponding to the first interval completely falls in the stable region of the differential link and does not contain the transition region; according to the limiting condition of the second interval and the data latching characteristic of the differential link, it can be known that the two ends of the stable time window corresponding to the second interval belong to the transition region of the differential link, but the middle mark located at the center of the second interval can be determined to fall in the stable region. Thus, after the clock signal or the differential link is delayed based on the delay amount corresponding to the middle mark and the data alignment is completed, the sampling edge of the clock signal can be avoided from being in the transition region.

[0071] For step S1, different delay times can be obtained by using fixed delay steps to increase successively, or non-fixed delay steps can be used to increase to form delay amounts, that is, the delay time of the present application can be represented as the delay amount. In actual work, in order to ensure the accuracy of the delay scanning result, a fixed delay step is usually used to form a plurality of delay times. In addition, the maximum value of the delay time in step S1 needs to exceed n signal periods. The signal period represents the period of a single differential signal in the differential link and can be calculated by the transmission rate of the differential link.

[0072] The training code belongs to a binary number of multiple bits. Taking 12 bits as an example, the training code can be 101110101101, and taking 4 bits as an example, the training code can be 1010. It should be noted that the digits of each bit in the training code in the present application are not completely consistent, that is, the digits of each bit in the training code are not all 0 or all 1.

[0073] In step S1, the step of judging whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code under different delay times can include:

[0074] Step a, under different delay times, the same training code is input into the differential link respectively.

[0075] Step b, based on the sampling edge of the clock signal, the training code is sampled at the receiving end of the differential link for multiple times to obtain a plurality of latched values. The sampling edge is the rising edge or the falling edge of the clock signal.

[0076] Step c, judging whether the plurality of latched values are consistent; if yes, it indicates that the sampling edge of the clock signal is in the stable region of the differential link; if not, it indicates that the sampling edge of the clock signal is not in the stable region of the differential link.

[0077] Taking the training code 101110101101 as an example, in the case of different delay time composed of fixed delay step, when the delay step is 0, the training code is input from the input end of the differential link. Then, at the receiving end of the differential link, the training code is sampled multiple times in succession based on the clock signal, and multiple latch values corresponding to the training code can be obtained. The number of latch values is higher than a preset threshold, which can be 1000 or 2000, and the specific number is not limited in the present application. Then, it is determined whether the multiple latch values are completely consistent. If yes, it indicates that the clock signal can be stably sampled, belonging to a stable state. If not, it indicates that the clock signal cannot be stably sampled, and the sampling edge is in a transition region.

[0078] According to the basic concept in the process of differential link transmission, in one signal period, the clock signal is sampled only once, and only one bit of number is obtained. Correspondingly, in the process of obtaining 2000 12-bit latch values at the receiving end, the sampling edge of the clock signal is triggered and sampled 24000 times.

[0079] In addition, for two different delay times, if the clock signal can be stably sampled, and the delay time falls in two adjacent signal periods, then the difference between the latch values obtained under the latter delay time and the latch values obtained under the former delay time is that the former is cyclically left shifted by 1 bit. Specifically, taking the aforementioned 12-bit training code as an example, the latch value stably sampled under the former delay time is 101101110101, and the latch value stably sampled under the latter delay time is 110110111010. Similarly, it can be extended that for two different delay times, if the data latch state is stable, and the order difference of the signal periods corresponding to the delay times is a, then the difference between the latch values obtained under the latter delay time and the latch values obtained under the former delay time is that the former is cyclically left shifted by a bits.

[0080] In some embodiments, the first set provided by the present application can be composed of values generated by cyclic shift of the training code, or can include other values in addition to the cyclic shift of the training code. In actual work, considering that the latch values in the stable state in the present application are all values generated by cyclic shift of the training code, the difference between the latch values obtained under different signal period orders is that the number of bits cyclically shifted by the training code is different, therefore, the values generated by cyclic shift of the training code are usually used to form the first set.

[0081] In the present application, the first set can only include 1 value generated by cyclic shift of the training code; or only include 2 values generated by cyclic shift of the training code, and the shift interval of the 2 values is not less than 1 bit compared with the training code; or include 2 values generated by cyclic shift of the training code, and the shift interval of the 2 values is not less than 1 bit compared with the training code; or include m values generated by cyclic shift of the training code, and among the m values, at least 2 adjacent shift values have a shift interval of 1 bit compared with the training code, or among the m values, at least 3 adjacent shift values have a shift interval not less than 1 bit compared with the training code. Wherein, 3≤m≤n-1. Based on the above setting, it can be ensured that there is a first interval or a second interval in the flag set obtained in step S2.

[0082] In some embodiments, step S1 can include the following contents:

[0083] S101, based on the training code, judge whether the sampling edge of the clock signal is in the stable region of the differential link at different delay times, if not, record the judgment result as a second flag; if not, go to step S102.

[0084] S102, judge whether the latch value obtained based on the sampling edge at the current delay time belongs to the first set, if yes, record the judgment result as a first flag; if not, record the judgment result as a second flag.

[0085] For step S1, the judgment result represents the mark of the data latch state at the current delay time. The first mark and the second mark can be represented by two different numbers or high and low levels, etc. In the present application, the number 1 is used to represent the first mark, and the number 0 is used to represent the second mark.

[0086] Based on the foregoing contents of step S1, compared with the mark of the latch state in the prior art, the present application adds the judgment of whether the latch value belongs to the first set, combined with the setting of the elements in the first set, it can make the time window corresponding to the first interval in the subsequent flag set not contain the transition region, and the time window center corresponding to the second interval not be in the transition region, thereby avoiding the error of the data alignment result of the differential link.

[0087] For step S2, according to the number of delay steps contained in the delay time, arrange the flags corresponding to each delay time in order from small to large. Wherein, the flag includes the first flag and the second flag.

[0088] For step S3, if the total number of flags in the first interval or the second interval is odd, then directly select the flag at the middle point as the middle flag. If the total number of flags in the first interval or the second interval is even, then select any one of the two flags at the middle as the middle flag.

[0089] It is considered that in the data alignment process of the differential link, only the clock signal or the differential link needs to be delayed based on one delay time, so that the sampling edge of the delayed clock signal is in the stable region. Therefore, in the present application, the middle flag of any one of the first interval or the second interval is selected, and the data alignment is performed by using the delay time corresponding to the middle flag.

[0090] In some embodiments, if the first set only includes one value generated by cyclic shift of the training code, then the middle flag of any one of the first interval or the second interval is selected as follows:

[0091] The middle flag in any one interval composed of consecutive first flags is selected.

[0092] Taking 8-bit training code 10111001 as an example, if the first set only includes one value 01101110 generated by cyclic shift of the training code. When the delay step is 0, if the clock signal can be stably sampled, but the latched value is 11011100, which does not belong to the first set, then the corresponding judgment result is 0. The delay time is increased by one delay step, and it is continued to judge whether the clock signal can be stably sampled and whether the latched value belongs to the first set. With the increase of the delay time, when the sampling edge of the clock signal is in the stable region of the next signal period, it can be known that the clock signal can be stably sampled, the latched value is 01101110, which belongs to the first set, and the corresponding judgment result is 1.

[0093] With the continuous increase of the delay step, when the sampling edge of the clock signal is not in the stable region of the next signal period, there are two possibilities. The first is that when the sampling edge is in the transition region, the judgment result of the delay time is 0. The second is that the delay step exceeds the transition region, and the sampling edge is directly in the stable region of the next signal period. Since the latched value is 00110111, which does not belong to the first set, the judgment result under this delay time is 0.

[0094] It can be seen that by setting the judgment step of whether the latched value belongs to the first set, the characteristics of the cyclic shift of the latched value under different signal periods are used, so that even if the clock signal can be stably sampled under adjacent clock periods, the corresponding judgment result basis is different, which ensures that the time window corresponding to the first interval composed of consecutive 1s is completely in the stable region, that is, the time window does not contain the transition region.

[0095] It can be understood that, for the n-bit training code, when the first set only includes 1 value generated by cyclic shift of the training code, only when the latched value is the same as the 1 value in the first set, the current delay time corresponds to the first flag 1, and the rest of the delay times correspond to the second flag 0. The flag set can be "00000111111100000000...00".

[0096] Since the time window corresponding to the continuous 0 includes multiple signal periods, there is a transition region inside, and the time window corresponding to the continuous 1 (that is, the interval composed of continuous first flags in the present application) is only in the stable region of a signal period, so the middle flag in any interval composed of continuous first flags can be screened out for subsequent data alignment of the differential link.

[0097] It can be seen from the foregoing description that, in the judgment step of whether the latched value belongs to the first set, the present application can distinguish the stable regions in different signal periods. In order to avoid that the time window corresponding to the continuous 1 includes a transition region, for the multiple values in the first set generated by cyclic shift of the training code, the shift amount interval of adjacent shift values is set to be at least 1 bit. Taking the 8-bit training code 10111001 as an example, the two values with a shift amount interval of at least 1 bit can be 01101110 and 10011011. However, 01101110 and 00110111 do not meet the foregoing requirement.

[0098] For the multiple values in the first set generated by cyclic shift of the training code, when the shift amount interval of adjacent shift values is 1 bit, the continuous 0 (interval composed of continuous second flags) between the two continuous 1s meets the requirement of the second interval, and the time window corresponding to the continuous 0 is at both ends of the transition region, but the middle part is the stable region. Therefore, after data alignment using the middle flag of the continuous 0 under the current condition, the sampling edge after delay can also be ensured not to be in the transition region.

[0099] In some embodiments, if the first set only includes 2 values generated by cyclic shift of the training code, the shift amount interval of the 2 values is not less than 1 bit compared with the training code.

[0100] When the shift amount interval of the 2 values is 1 bit, the middle flag of any first interval or second interval screened out is:

[0101] The middle flag of any interval composed of continuous first flags or second flags is screened out. The process corresponds to: selecting the center point of any one of the two time windows composed of continuous 1s, and the center point of the time window composed of the continuous 0 between the two continuous 1s.

[0102] When the shift interval between two values exceeds 1 bit, the intermediate mark of any one of the first interval or the second interval is:

[0103] The intermediate mark of any one interval formed by consecutive first marks is screened out. The process corresponds to: selecting the center point of any one of the two time windows formed by consecutive 1s.

[0104] If the first set includes m values generated by cyclic shift of the training code, at least two adjacent shift values in the m values have a shift interval of 1 bit compared with the training code, or at least three adjacent shift values in the m values have a shift interval of no less than 1 bit. Wherein, 3≤m≤n-1.

[0105] If the maximum shift interval between adjacent shift values in the m values is 1 bit, it means that the consecutive 0 between the two consecutive 1s in the mark set belongs to the second interval, so the intermediate mark of any one of the first interval or the second interval is:

[0106] The intermediate mark of any one of the second interval is screened out. The process corresponds to: selecting the center point of any one of the two time windows formed by consecutive 1s.

[0107] If the total number of bits n of the training code is even, the first includes n / 2 values generated by cyclic shift of the latch value, and the shift interval between adjacent values in the n / 2 values is 1 bit, the intermediate mark of any one of the first interval or the second interval in the mark set includes:

[0108] In the mark set, for all intervals formed by consecutive first marks or second marks, after removing the first and last, the intermediate mark of any one of the remaining intervals is screened out.

[0109] Taking a 12-bit training code 101110101101 as an example, the values of the training code cyclically right shifted by 2 bits (011011101011), cyclically right shifted by 4 bits (110110111010), cyclically right shifted by 6 bits (101101101110), cyclically right shifted by 8 bits (101011011011), cyclically right shifted by 10 bits (111010110110), and cyclically right shifted by 12 bits (101110101101) form the first set. After obtaining the mark set, the first consecutive interval (consecutive 1 or consecutive 0) and the last consecutive interval are removed in the mark set, and then the middle value of the remaining consecutive 1 or consecutive 0 corresponding to the time window is selected as the delay time of the differential link or the clock signal, which is used to realize data alignment.

[0110] In some embodiments, before step S2, the alignment method provided in the present application further comprises step S5, which is used to replace step S1.

[0111] S5, judging whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code at different delay times; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to the second set, recording the judgment result as the first flag; otherwise, recording the judgment result as the second flag.

[0112] The second set comprises a value generated by cyclically shifting a calibration value; the calibration value represents a latched value obtained when the sampling edge of the clock signal is first in the stable region of the differential link.

[0113] Compared with step S1, the elements in the second set in step S5 are obtained by cyclically shifting the latched value obtained when the sampling edge of the clock signal is first in the stable region of the differential link.

[0114] In some embodiments, step S5 provided in the present application comprises the following contents:

[0115] S501, judging whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code at different delay times; if no, recording the judgment result at the current delay time as the second flag; if yes, turning to step S502.

[0116] S502, judging whether the latched value obtained based on the sampling edge at the current delay time belongs to the second set; if yes, recording the judgment result as the first flag; if no, recording the judgment result as the second flag.

[0117] In some embodiments, if the second set only comprises one value generated by cyclically shifting the calibration value to the left by q bits, the highest delay time exceeds q signal periods. Based on the above setting, when the highest delay time exceeds q signal periods, there must be a first interval (i.e., a continuous 1 with a time window length less than 1 signal period) in the flag set obtained based on step S2, and the data alignment scheme provided in the present application can be implemented.

[0118] In some embodiments, if n is even, the second set comprises n / 2 values generated by cyclically shifting the latched value, and the shift amount interval between adjacent values in the n / 2 values is 1 bit, the middle flag of any one of the first interval or the second interval in the flag set comprises:

[0119] In the flag set, for all intervals formed by continuous first flags or second flags, after removing the first and last ones, the middle flag of any one of the remaining intervals is selected.

[0120] In the image data transmission process, the transmitting end of the differential link is the image sensor, and the receiving end is the FPPGA. The alignment process provided by the application is as follows:

[0121] Step one, configure the sensor in a fixed training code output mode, such as 101110101101 (for example, 12 bits). Reset the delay amount to 0, continuously sample 2000 times of latched values at the FPGA, and determine whether the 2000 times of latched values are consistent. If yes, it is a stable state under the delay amount, and if no, it is not a stable state. When the data latching is in a stable state, record the window latching result (i.e., the judgment result of the application) corresponding to the current delay amount as "1" (i.e., the first flag), and when the data latching is not in a stable state, record the window latching result corresponding to the current delay amount as "0" (i.e., the second flag).

[0122] Step two, if the window latching result recorded in step one is 1, then the latched values are circularly moved by an even number of bits to obtain n / 2 values, which are marked as valid training codes to form a second set. If the window latching result recorded in step (1) is "0", do not mark the valid training codes.

[0123] Suppose the latched value is 101110101101, then circularly right shift the latched value by 2 bits (011011101011), circularly right shift by 4 bits (110110111010), circularly right shift by 6 bits (101101101110), circularly right shift by 8 bits (101011011011), and circularly right shift by 10 bits (111010110110). Mark the above six data as valid training codes to form the second set.

[0124] Step three, increase the delay amount of the delay time configuration by 1 delay step, and then determine whether the current delay time is in a stable state. When the data latching is stable and the valid training codes have been marked, determine whether the latched data and the valid training codes are consistent. When the data is stable and consistent with the valid training codes, record the window latching result value as "1". Otherwise, record the window latching result value as "0". When the data latching is stable and no valid training codes have been marked before, mark the valid training codes according to the latching result of this time.

[0125] Step four, repeat steps two and three until the delay time configuration reaches the maximum value. Remove the first continuous 1 and the tail continuous 0 or continuous 1 in the flag set, and select the delay time corresponding to the center value of the remaining continuous "1" (or continuous "0") to set as the delay time of the clock signal or the differential link, which is used to realize the data alignment of the differential link. That is, after obtaining the window stable state corresponding to the entire delay range, the final delay time is fixedly set as the center value of the continuous "1" (or continuous "0"), and the data alignment of the differential link can be completed. The actual alignment process is as followsFigure 6 As shown, the latching results under different delay values ​​are as follows: Figure 7 As shown.

[0126] Based on the above processing, the alignment scheme provided in this application can obtain an accurate stable time window even when the delay time accuracy is greater than the transition region of the differential link, thus avoiding the sampling edge of the clock signal after alignment being in the transition region and improving the reliability of data window scanning.

[0127] In some embodiments, such as Figure 8 As shown, this application also provides an alignment system for differential links, including:

[0128] The flag recording module 801 is used to determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code under different delay times. If so, and the latch value obtained based on the sampling edge at the current delay time belongs to the first set, the judgment result is recorded as the first flag; otherwise, the judgment result is recorded as the second flag. The bits in the training code are not completely identical; the first set includes the values ​​generated after cyclic shifting of the training code.

[0129] The set generation module 802 is used to arrange the first and second flags according to the order of their delay times to obtain a set of flags.

[0130] The flag filtering module 803 is used to filter out any intermediate flag of a first interval or a second interval from the flag set; wherein, the first interval consists of consecutive first flags, and the flags adjacent to each other on both sides of the first interval are second flags, and the interval between the corresponding delay times of the two endpoints in the first interval does not exceed a single signal cycle of the differential link; the second interval consists of consecutive second flags, and the flags adjacent to each other on both sides of the second interval are first flags, and the interval between the corresponding delay times of the adjacent first flags on both sides of the second interval is higher than a single signal cycle and lower than two signal cycles.

[0131] The data alignment module 804 is used to delay the clock signal or differential link based on the delay amount corresponding to the intermediate flag, so as to achieve data alignment of the differential link.

[0132] This application also provides an electronic device, such as... Figure 9 As shown, it includes a processor 901, a communication interface 902, a memory 903, and a communication bus 904, wherein the processor 901, the communication interface 902, and the memory 903 communicate with each other through the communication bus 904.

[0133] Memory 903 is used to store computer programs;

[0134] The processor 901 is configured to implement the alignment method of any of the differential links by executing the program stored in the memory 903.

[0135] The communication bus mentioned in the electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0136] The communication interface is configured to communicate between the electronic device and other devices.

[0137] The memory can include a Random Access Memory (RAM) and can also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory can also be at least one storage device located away from the aforementioned processor.

[0138] The processor mentioned above can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0139] In another embodiment provided in the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the alignment method of any of the differential links.

[0140] In another embodiment provided in the present application, a computer program product containing instructions is also provided, and when the computer program product is executed on a computer, the computer is caused to execute the alignment method of any of the differential links in the above embodiments.

[0141] The above examples are only used to illustrate the technical solutions of the present application, but not to limit the same; although the present application has been described in detail with reference to the foregoing examples, it should be understood by those of ordinary skill in the art that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for aligning differential links, characterized in that, include: Under different delay times, the sampling edge of the clock signal is determined based on the training code to determine whether it is in the stable region of the differential link; If yes, and the latch value obtained based on the sampling edge under the current delay time belongs to the first set, the judgment result is recorded as the first flag; otherwise, the judgment result is recorded as the second flag; wherein, the bits in the training code are not completely consistent; the first set includes the values ​​generated after the training code is cyclically shifted; Arrange the first and second flags according to the order of their delay times to obtain the flag set; In the set of flags, select any intermediate flag of either the first interval or the second interval; wherein, the first interval consists of consecutive first flags, and the flags adjacent to each other on both sides of the first interval are second flags, and the interval between the delay times corresponding to the two endpoints of the first interval does not exceed a single signal cycle of the differential link; the second interval consists of consecutive second flags, and the flags adjacent to each other on both sides of the second interval are first flags, and the interval between the delay times corresponding to the adjacent first flags on both sides of the second interval is higher than a single signal cycle but lower than two signal cycles. Delay the clock signal or differential link based on the delay amount corresponding to the intermediate flag to achieve data alignment of the differential link.

2. The alignment method according to claim 1, characterized in that, At different delay times, determining whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code includes: The same training code is input to the differential link at different delay times; Based on the sampling edge of the clock signal, the training code is sampled multiple times at the receiving end of the differential link to obtain multiple latch values; wherein the sampling edge is the upper edge or the lower edge of the clock signal. Determine whether the multiple latch values ​​are consistent; if yes, it indicates that the sampling edge of the clock signal is in the stable region of the differential link; if no, it indicates that the sampling edge of the clock signal is not in the stable region of the differential link.

3. The alignment method according to claim 1, characterized in that, Each delay time is obtained based on a fixed delay step size, and the highest delay time exceeds n signal cycles; where n represents the number of bits in the training code.

4. The alignment method according to claim 1, characterized in that, If the first set contains only one value generated by cyclic shifting of the training code, then the step of selecting the middle marker of any first interval or second interval is: Filter out any intermediate marker within an interval consisting of consecutive first markers.

5. The alignment method according to claim 1, characterized in that, If the first set includes only two values ​​generated by cyclic shifting the training code, then the shift interval between the two values ​​is not less than 1 bit compared to the training code; When the shift interval between two values ​​is 1 bit, the method for selecting the middle flag of any first or second interval is as follows: Filter out any intermediate marker in an interval or a second interval consisting of consecutive first markers; When the shift interval between two values ​​exceeds 1 bit, the intermediate flag for selecting any one of the first or second intervals is: Filter out any intermediate marker of an interval consisting of consecutive first markers.

6. The alignment method according to claim 1, characterized in that, If the first set includes m values ​​generated by cyclic shifting of the training code, then compared to the training code, among the m values, there are at least two adjacent shifted values ​​with a shift interval of 1 bit, or among the m values, there are at least three adjacent shifted values ​​with a shift interval of not less than 1 bit; where 3≤m≤n-1; Among the m values, if the maximum shift interval between adjacent shift values ​​is 1 bit, the intermediate flag for selecting any one of the first or second intervals is: Filter out the middle marker of any second interval.

7. The alignment method according to claim 1, characterized in that, Before arranging the first and second flags according to their delay times to obtain the flag set, the alignment method further includes: Under different delay times, determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code; if so, and the latch value obtained based on the sampling edge under the current delay time belongs to the second set, record the judgment result as the first flag; otherwise, record the judgment result as the second flag. The second set includes values ​​generated by cyclically shifting calibration values; the calibration values ​​represent latch values ​​obtained when the sampling edge of the clock signal is first in the stable region of the differential link.

8. The alignment method according to claim 7, characterized in that, If the second set contains only one value generated by cyclically shifting the calibration value left by q bits, then the highest delay time exceeds q signal cycles.

9. The alignment method according to claim 7, characterized in that, If n is even, and the second set includes n / 2 values ​​generated by cyclic shifting the latched values, and the shift interval between adjacent values ​​in these n / 2 values ​​is 1 bit, then selecting any intermediate flag of the first or second interval from the flag set includes: In the set of markers, for all intervals formed by consecutive first or second markers, after removing the first and last markers, filter the middle markers of any remaining interval.

10. An alignment system for differential links, characterized in that, include: The flag recording module is used to determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code under different delay times; If yes, and the latch value obtained based on the sampling edge under the current delay time belongs to the first set, the judgment result is recorded as the first flag; otherwise, the judgment result is recorded as the second flag; wherein, the bits in the training code are not completely consistent; the first set includes the values ​​generated after the training code is cyclically shifted; The set generation module is used to arrange the first and second flags according to the order of their delay times to obtain a set of flags; The flag filtering module is used to filter out any intermediate flag in a first interval or a second interval from the flag set. The first interval consists of consecutive first flags, and the flags adjacent to each other on both sides of the first interval are second flags. The interval between the delay times of the two endpoints in the first interval does not exceed a single signal cycle of the differential link. The second interval consists of consecutive second flags, and the flags adjacent to each other on both sides of the second interval are first flags. The interval between the delay times of the adjacent first flags on both sides of the second interval is higher than a single signal cycle but lower than two signal cycles. The data alignment module is used to delay the clock signal or differential link based on the delay amount corresponding to the intermediate flag, so as to achieve data alignment of the differential link.

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